INA826S [TI]
具有关断模式的 200μA、36V 轨到轨输出仪表放大器;
| 型号： | INA826S |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有关断模式的 200μA、36V 轨到轨输出仪表放大器 放大器 仪表 仪表放大器 |
| 文件： | 总41页 (文件大小：2473K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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INA826S
ZHCSGB6A –MAY 2017–REVISED JUNE 2017
具有轨至轨输出和关断的 INA826S 精密 200µA 电源电流，3V 至 36V 电源
仪表放大器
1 特性
3 说明
1
•
•
输入共模范围：包括 V–
共模抑制：
INA826S 器件是一款低成本仪表放大器，此放大器提
供极低功耗及关断，并可在极宽的单电源或双电源电压
范围内工作。可通过单个外部电阻在 1 到 1000 范围内
设置增益。该器件在过热条件下具有很好的稳定性，即
使在 G > 1 时，也可实现只有 35ppm/°C（最大值）的
低增益漂移。
–
–
104dB（最小值，G = 10）
100dB（5kHz 下的最小值，G = 10）
•
•
•
•
•
•
•
•
电源抑制：（最小值，G = 1）
低失调电压：150µV，最大值
增益漂移：1ppm/°C (G = 1)，35ppm/°C (G > 1)
噪声：18nV/√Hz，G ≥ 100
带宽：1MHz (G = 1)，60kHz (G = 100)
输入保护电压高达 ±40V
INA826S 经优化可在频率高达 5kHz 时提供超过
100dB (G = 10) 的出色共模抑制比。G = 1 时，在从
负电源直至 1V 正电源的整个输入共模范围内共模抑制
比将超过 84dB。INA826S 采用轨到轨输出，非常适合
通过 3V 单电源和高达 ±18V 的双电源供电的低电压运
行器件。
轨到轨输出
电源电流：200µA
–
关断电流：2µA
提供关断引脚，可将电源电流降至 2µA 以下。附加电
路可通过将输入电流限制在 8mA 以下来防止输入出现
超出电源电压的过压情况（高达 ±40V）。
•
电源电压范围：
–
–
单电源：3V 至 36V
双电源：±1.5V 至 ±18V
INA826S 可提供 10 引脚、3mm ×
•
•
特定温度范围：
–40°C 至 +125°C
3mm VSON 表面贴装式封装。INA826S 的额定工作温
度范围为 –40°C 至 +125°C。
封装：3mm × 3mm VSON
器件信息(1)
2 应用
器件型号
INA826S
封装
VSON (10)
封装尺寸（标称值）
•
•
•
•
•
•
•
工业过程控制
3.00mm × 3.00mm
断路器
(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。
电池检测仪
心电图 (ECG) 放大器
电力自动化
医疗仪表
INA826S 简化内部原理图
V+
0.1 mF
便携式仪表
8
(1)
RS
1
RFI Filter
-IN
50 kW
50 kW
A1
VO = G ´ (VIN+ - VIN-
)
2
49.4 kW
24.7 kW
G = 1 +
RG
7
6
RG
A3
24.7 kW
+
3
4
VO
Load
-
50 kW
50 kW
(1)
RS
A2
REF
RFI Filter
+IN
TI Device
5
0.1 mF
Copyright © 2017, Texas Instruments Incorporated
V-
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SBOS770
INA826S
ZHCSGB6A –MAY 2017–REVISED JUNE 2017
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 8
Detailed Description ............................................ 19
7.1 Overview ................................................................. 19
7.2 Functional Block Diagram ....................................... 19
7.3 Feature Description................................................. 20
7.4 Device Functional Modes........................................ 27
8
9
Application and Implementation ........................ 27
8.1 Application Information............................................ 27
8.2 Typical Application ................................................. 28
Power Supply Recommendations...................... 30
9.1 Low-Voltage Operation ........................................... 30
10 Layout................................................................... 31
10.1 Layout Guidelines ................................................. 31
10.2 Layout Example .................................................... 31
11 器件和文档支持 ..................................................... 32
11.1 文档支持................................................................ 32
11.2 接收文档更新通知 ................................................. 32
11.3 社区资源................................................................ 32
11.4 商标....................................................................... 32
11.5 静电放电警告......................................................... 32
11.6 Glossary................................................................ 32
12 机械、封装和可订购信息....................................... 32
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (May 2017) to Revision A
Page
•
Changed output stage offset voltage from 700 µV to 1000 µV .............................................................................................. 5
2
Copyright © 2017, Texas Instruments Incorporated
INA826S
www.ti.com.cn
ZHCSGB6A –MAY 2017–REVISED JUNE 2017
5 Pin Configuration and Functions
DRC Package
10-Pin VSON
Top View
œIN
RG
RG
+IN
EN
1
2
3
4
5
10
+VS
9
8
7
6
OUT
REF
Thermal pad
œVS
ENREF
Not to scale
Pin Functions
NAME
NO.
5
I/O
I
DESCRIPTION
EN
Enable pin; active low with respect to ENREF
Enable pin reference
ENREF
–IN
6
I
1
I
Negative (inverting) input
+IN
4
I
Positive (noninverting) input
OUT
REF
RG
9
O
I
Output
8
Reference input. This pin must be driven by low impedance.
Gain setting pins. Place a gain resistor between pin 2 and pin 3.
Negative supply
2, 3
7
—
—
—
–VS
+VS
10
Positive supply
Exposed thermal die pad on underside; connect thermal die pad to V–.
Soldering the thermal pad improves heat dissipation and provides specified performance.
Thermal pad
Pad
—
Copyright © 2017, Texas Instruments Incorporated
3
INA826S
ZHCSGB6A –MAY 2017–REVISED JUNE 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–20
MAX
UNIT
Supply voltage
20
V
Signal input pins
(–VS) – 40
–20
(+VS) + 40
REF pin
+20
Voltage
V
ENREF pin
(–VS) – 0.3
(–VS) – 0.3
–10
(+VS) + 0.3
EN pin
VENREF + 0.3
Signal input pins
10
10
1
REF pin
–10
Current
mA
ENREF pin
–1
EN pin
Output short-circuit(2)
–1
1
Continuous
Operating, TA
–50
–65
150
175
150
Temperature
Junction, TJ
Storage, Tstg
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to VS / 2.
6.2 ESD Ratings
VALUE
±2500
±1500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3
NOM
MAX
36
UNIT
Single-supply
Dual-supply
Supply voltage
V
±1.5
–40
±18
125
Specified temperature
°C
6.4 Thermal Information
INA826S
THERMAL METRIC(1)
VSON (DRC)
10 PINS
51.9
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
58.2
25.8
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.0
ψJB
25.8
RθJC(bot)
8.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2017, Texas Instruments Incorporated
INA826S
www.ti.com.cn
ZHCSGB6A –MAY 2017–REVISED JUNE 2017
6.5 Electrical Characteristics
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT
RTI
40
0.4
150
2
µV
µV/°C
µV
VOSI
Input stage offset voltage(1)
vs temperature, TA = –40°C to +125°C
RTI
200
2
1000
5
Output stage offset
voltage(1)
VOSO
vs temperature, TA = –40°C to +125°C
G = 1, RTI
µV/°C
90
100
110
120
124
130
140
140
20 || 1
10 || 5
20
G = 10, RTI
PSRR
Power-supply rejection ratio
dB
G = 100, RTI
G = 1000, RTI
zid
zic
Differential impedance
GΩ || pF
GΩ || pF
MHz
Common-mode impedance
RFI filter, –3-dB frequency
V–
(V+) – 1
±40
VCM
Operating input range(2)
Input overvoltage range
V
V
VS = ±3 V to ±18 V, TA = –40°C to +125°C
TA = –40°C to 125°C
See 图 12 to 图 19
G = 1, VCM = (V–) to (V+) – 1 V
G = 10, VCM = (V–) to (V+) – 1 V
82
95
115
130
130
104
120
120
At dc to
60 Hz, RTI
G = 100, VCM = (V–) to (V+) – 1 V
G = 1000, VCM = (V–) to (V+) – 1 V
Common-mode rejection
ratio
G = 1, VCM = (V–) to (V+) – 1 V,
TA = –40°C to +125°C
CMRR
80
dB
G = 1, VCM = (V–) to (V+) – 1 V
G = 10, VCM = (V–) to (V+) – 1 V
G = 100, VCM = (V–) to (V+) – 1 V
G = 1000, VCM = (V–) to (V+) – 1 V
84
100
105
105
At 5 kHz,
RTI
BIAS CURRENT
VCM = VS / 2
35
65
95
5
IB
Input bias current
nA
nA
TA = –40°C to +125°C
VCM = VS / 2
0.7
IOS
Input offset current
TA = –40°C to +125°C
10
NOISE VOLTAGE
f = 1 kHz, G = 100, RS = 0 Ω
fB = 0.1 Hz to 10 Hz, G = 100, RS = 0 Ω
f = 1 kHz, G = 1, RS = 0 Ω
fB = 0.1 Hz to 10 Hz, G = 1, RS = 0 Ω
f = 1 kHz
18
0.52
110
3.3
nV/√Hz
µVPP
eNI
eNO
In
Input stage voltage noise(3)
nV/√Hz
µVPP
Output stage voltage noise(3)
Noise current
100
5
fA/√Hz
pAPP
fB = 0.1 Hz to 10 Hz
(1) Total offset, referred-to-input (RTI): VOS = (VOSI) + (VOSO / G).
(2) Input voltage range of the INA826S input stage. The input range depends on the common-mode voltage, differential voltage, gain, and
reference voltage.
2
eNO
2
(eNI
)
+
G
(3) Total RTI voltage noise is equal to:
.
Copyright © 2017, Texas Instruments Incorporated
5
INA826S
ZHCSGB6A –MAY 2017–REVISED JUNE 2017
www.ti.com.cn
Electrical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GAIN
G
Gain equation
Range of gain
1 + (49.4 kΩ / RG)
V/V
V/V
G
1
1000
±0.020%
±0.15%
±0.15%
±0.15%
±1
G = 1, VO = ±10 V
G = 10, VO = ±10 V
±0.003%
±0.03%
±0.04%
±0.04%
±0.1
Gain error
GE
G = 100, VO = ±10 V
G = 1000, VO = ±10 V
G = 1, TA = –40°C to +125°C
G > 1, TA = –40°C to +125°C
G = 1 to 100, VO = –10 V to 10 V
G = 1000, VO = –10 V to 10 V
Gain vs temperature(4)
Gain nonlinearity
ppm/°C
ppm
±10
±35
1
5
5
20
OUTPUT
Voltage swing
RL = 10 kΩ
(V–) + 0.1
(V+) – 0.15
V
Load capacitance stability
Open-loop output impedance
Short-circuit current
1000
See 图 59
pF
ZO
ISC
Continuous to VS / 2
±16
mA
MHz
kHz
FREQUENCY RESPONSE
G = 1
1
500
60
6
G = 10
BW
SR
Bandwidth, –3 dB
Slew rate
G = 100
G = 1000
G = 1, VSTEP = 10 V
G = 100, VSTEP = 10 V
G = 1, VSTEP = 10 V
1
V/µs
1
12
12
24
224
14
14
31
278
G = 10, VSTEP = 10 V
0.01%
G = 100, VSTEP = 10 V
G = 1000, VSTEP = 10 V
G = 1, VSTEP = 10 V
tS
Settling time
µs
G = 10, VSTEP = 10 V
0.001%
G = 100, VSTEP = 10 V
G = 1000, VSTEP = 10 V
REFERENCE INPUT
RIN Input impedance
100
kΩ
V
Voltage range
(V–)
(V+)
–1.0
Gain to output
1
V/V
Reference gain error
0.01%
ENABLE INPUT
Referenced to ENREF pin
TA = –40°C to +125°C
–0.75
–0.7
Enable threshold voltage
V
V
Referenced to ENREF pin
TA = –40°C to +125°C
Disable threshold voltage
–0.40
EN pin input current
ENREF pin input current
EN pin voltage range
ENREF voltage range
Enable delay
VENREF = 1.5 V, VEN = 0 V
VENREF = 1.5 V, VEN = 0 V
3
µA
µA
V
–3
V–
VENREF
V+
(V–) + 1.5 V
V
100
µs
(4) The values specified for G > 1 do not include the effects of the external gain-setting resistor, RG.
6
Copyright © 2017, Texas Instruments Incorporated
INA826S
www.ti.com.cn
ZHCSGB6A –MAY 2017–REVISED JUNE 2017
Electrical Characteristics (continued)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
Single
Dual
3
36
±18
250
320
5
VS
Power-supply voltage
Quiescent current
Shutdown current
V
±1.5
VIN = 0 V
200
2
IQ
µA
µA
TA = –40°C to +125°C
VS = 3 V to 36 V, VIN = 0 V
TA = –40°C to +125°C
IQSD
6
TEMPERATURE RANGE
Specified
–40
–50
125
150
°C
°C
Operating
版权 © 2017, Texas Instruments Incorporated
7
INA826S
ZHCSGB6A –MAY 2017–REVISED JUNE 2017
www.ti.com.cn
6.6 Typical Characteristics
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
25
20
15
10
5
30
25
20
15
10
5
0
0
Input Offset Voltage Drift (ꢀV/°C)
Input Offset Voltage (ꢀV)
C001
C001
C001
C001
C001
C001
1024 units
5977 units
图 1. Typical Distribution of
图 2. Typical Distribution of
Input Offset Voltage Drift
Input Offset Voltage
35
30
25
20
15
10
5
30
25
20
15
10
5
0
0
Output Offset Voltage Drift (ꢀV/°C)
Output Offset Voltage (ꢀV)
1024 units
5977 units
图 3. Typical Distribution of
图 4. Typical Distribution of
Output Offset Voltage Drift
Output Offset Voltage
30
25
20
15
10
5
60
50
40
30
20
10
0
0
Input Bias Current (nA)
Input Offset Current (nA)
1024 units
1024 units
图 5. Typical Distribution of
图 6. Typical Distribution of
Input Bias Current
Input Offset Current
8
版权 © 2017, Texas Instruments Incorporated
INA826S
www.ti.com.cn
ZHCSGB6A –MAY 2017–REVISED JUNE 2017
Typical Characteristics (接下页)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
45
40
35
30
25
20
15
10
5
30
25
20
15
10
5
0
0
Common-Mode Rejection Ratio (ꢀV/V)
Common-Mode Rejection Ratio (ꢀV/V)
C001
C001
C001
C001
1024 units
1024 units
图 7. Typical Distribution of CMRR (G = 1)
图 8. Typical Distribution of CMRR (G = 100)
35
30
25
20
15
10
5
20
18
16
14
12
10
8
6
4
2
0
0
Gain Error (m%)
Gain Error (m%)
C001
1024 units
1024 units
图 9. Typical Distribution of Gain Error (G = 1)
图 10. Gain Error (G = 10)
45
40
35
30
25
20
15
10
5
3
VREF = 0 V
VREF = 1.35 V
2.5
2
1.5
1
0.5
0
-0.5
-1
0
0
0.5
1
1.5
2
2.5
3
Gain Error Drift (ppm/°C)
Output Voltage (V)
D035
Single supply, VS = 3 V, G = 1
图 12. Input Common-Mode Voltage vs Output Voltage
5977 units
图 11. Typical Gain Error Drift Distribution
(G = 1)
版权 © 2017, Texas Instruments Incorporated
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INA826S
ZHCSGB6A –MAY 2017–REVISED JUNE 2017
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
3
2.5
2
5
4.5
4
VREF = 0 V
VREF = 1.35 V
VREF = 0 V
VREF = 2.5 V
3.5
3
1.5
1
2.5
2
1.5
1
0.5
0
0.5
0
-0.5
-1
-0.5
-1
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Output Voltage (V)
Output Voltage (V)
D036
D034
Single supply, VS = 3 V, G = 100
Single supply, VS = 5 V, G = 1
图 13. Input Common-Mode Voltage vs Output Voltage
图 14. Input Common-Mode Voltage vs Output Voltage
5
3
VREF = 0 V
VREF = 2.5 V
G = 1
G = 100
4.5
2
1
4
3.5
3
2.5
2
0
-1
-2
-3
-4
1.5
1
0.5
0
-0.5
-1
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-4
-3
-2
-1
0
1
2
3
4
Output Voltage (V)
Output Voltage (V)
D037
D039
Single supply, VS = 5 V, G = 100
Dual supply, VS = ±3.3 V, VREF = 0 V
图 15. Input Common-Mode Voltage vs Output Voltage
图 16. Input Common-Mode Voltage vs Output Voltage
16
14
12
10
8
5
VS
VS
=
=
ê
ê
15 V
12 V
G = 1
G = 100
4
3
2
6
4
1
2
0
0
-1
-2
-3
-4
-5
-6
-2
-4
-6
-8
-10
-12
-14
-16
-6 -5 -4 -3 -2 -1
0
1
2
3
4
5
6
-16
-12
-8
-4
0
4
8
12
16
Output Voltage (V)
Output Voltage (V)
D038
D040
Dual supply, VS = ±5 V, VREF = 0 V
Dual supply, VS = ±15 V and ±12 V, G = 1, VREF = 0 V
图 17. Input Common-Mode Voltage vs Output Voltage
图 18. Input Common-Mode Voltage vs Output Voltage
10
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INA826S
www.ti.com.cn
ZHCSGB6A –MAY 2017–REVISED JUNE 2017
Typical Characteristics (接下页)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
16
14
12
10
8
12
16
12
8
VS
VS
=
=
ê
ê
15 V
12 V
9
6
6
4
3
4
2
0
0
0
-2
-4
-6
-8
-10
-12
-14
-16
-3
-6
-9
-12
-4
-8
-12
-16
IIN
VOUT
-16
-12
-8
-4
0
4
8
12
16
-40 -32 -24 -16
-8
0
8
16
24
32
40
Output Voltage (V)
Input Voltage (V)
D040
D065
Dual supply, VS = ±15 V and ±12 V, G = 100, VREF = 0 V
G = 1, VS = ±15 V, RS = 0 Ω
图 20. Input Current vs Input Voltage
图 19. Input Common-Mode Voltage vs Output Voltage
8
16
12
8
160
6
4
140
120
100
80
2
4
0
0
-2
-4
-6
-8
-4
-8
-12
-16
60
40
G = 1
G = 10
G = 100
G = 1000
20
IIN
VOUT
0
-40 -32 -24 -16
-8
0
8
16
24
32
40
10
100
1k
10k
100k
Input Voltage (V)
Frequency (Hz)
D064
D001
G = 1, VS = ±15 V, RS = 10 kΩ
图 21. Input Current vs Input Voltage
with 10-kΩ Resistance
图 22. CMRR vs Frequency (RTI)
140
160
140
120
100
80
G = 1
G = 10
G = 100
G = 1000
G = 1
G = 10
G = 100
G = 1000
120
100
80
60
40
20
0
60
40
20
0
10
100
1k
10k
100k
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
D002
D003
图 23. CMRR vs Frequency
(RTI, 1-kΩ Source Imbalance)
图 24. Positive PSRR vs Frequency (RTI)
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
160
140
120
100
80
70
60
50
40
30
20
10
0
G = 1
G = 10
G = 100
G = 1000
60
40
G = 1
-10
-20
-30
G = 10
G = 100
G = 1000
20
0
10
100
1k
10k
100k
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
D004
D005
图 25. Negative PSRR vs Frequency (RTI)
图 26. Gain vs Frequency
1k
100
10
1k
100
10
G = 1
G = 10
G = 100
G = 1
G = 1000
1
10
100
1k
10k
100k
1
10
100
1k
10k
Frequency (Hz)
Frequency (Hz)
D019
D020
图 27. Voltage Noise Spectral Density
图 28. Current Noise Spectral Density vs Frequency (RTI)
vs Frequency (RTI)
400
300
200
100
0
3
2
1
0
-100
-200
-300
-400
-1
-2
-3
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
Time (s/div)
Time (s/div)
D007
D006
图 29. 0.1-Hz to 10-Hz RTI Voltage Noise (G = 1)
图 30. 0.1-Hz to 10-Hz RTI Voltage Noise (G = 1000)
12
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
15
10
5
0
-10
-20
-30
-40
-50
-60
-70
-80
-40
25
125
èC
è
C
èC
0
-5
-10
-15
0
1
2
3
4
5
6
7
8
9
10
-1
-0.5
0
0.5
1
1.5
2
2.5
3
Time (s/div)
Common-Mode Voltage (V)
D008
D056
VS = 3 V
图 31. 0.1-Hz to 10-Hz RTI Current Noise
图 32. Input Bias Current vs Common-Mode Voltage
0
-10
-20
-30
-40
-50
-60
-70
-80
100
90
80
70
60
50
40
30
20
10
0
-40
25
125
èC
è
C
èC
-16
-12
-8
-4
0
4
8
12
16
-50
-25
0
25
50
75
100
125
150
Common-Mode Voltage (V)
Temperature (èC)
D055
D033
VS = ±15 V
图 33. Input Bias Current vs Common-Mode Voltage
图 34. Input Bias Current vs Temperature
10
8
40
30
Max Data
Min Data
Unit 1
6
20
Unit 2
Unit 3
4
10
2
0
0
-10
-20
-30
-40
-50
-60
-2
-4
-6
-8
-10
-50
-25
0
25
50
75
C)
100
125
150
-50
-25
0
25
50
75
C)
100
125
150
Temperature (
è
Temperature (
è
D053
D031
图 35. Input Offset Current vs Temperature
图 36. Gain Error vs Temperature
(G = 1)
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
10
2000
1500
1000
500
DUT11
DUT23
8
6
4
2
0
0
-2
-4
-6
-8
-10
-500
-1000
-1500
-2000
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
C)
100
125
150
Temperature (èC)
Temperature (
è
D054
D032
图 37. Gain Error vs Temperature
图 38. CMRR vs Temperature (G = 1)
(G > 1)
300
250
200
150
100
50
4
3
2
1
0
VS = 2.7 V
VS = ê15 V
0
-50
-25
0
25
50
75
100
125
150
-10
-8
-6
-4
-2
0
2
4
6
8
10
Temperature (èC)
Output Voltage (V)
D043
D021
图 39. Supply Current vs Temperature
图 40. Gain Nonlinearity (G = 1)
-10
-11
-12
-13
-14
-15
-16
-17
-18
-19
-20
4
3
2
1
0
-10
-8
-6
-4
-2
0
2
4
6
8
10
-10
-8
-6
-4
-2
0
2
4
6
8
10
Output Voltage (V)
Output Voltage (V)
D022
D023
图 41. Gain Nonlinearity (G = 10)
图 42. Gain Nonlinearity (G = 100)
14
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
0
400
350
300
250
200
150
100
50
-50èC
-40èC
25èC
85èC
125èC
150èC
-2
-4
-6
-8
-10
-12
-14
-16
-18
-20
0
-50
-100
-10
-8
-6
-4
-2
0
2
4
6
8
10
-15.5
-15.3
-15.1
-14.9
-14.7
-14.5
Output Voltage (V)
Common-Mode Voltage (V)
D024
D057
VS = ±15 V
图 43. Gain Nonlinearity (G = 1000)
图 44. Offset Voltage vs
Negative Common-Mode Voltage
100
50
300
250
200
150
100
50
-50èC
-40èC
25èC
85èC
125èC
150èC
-50èC
-40èC
25èC
85èC
125èC
150èC
0
-50
-100
-150
-200
-250
-300
-350
-400
0
-50
-100
13.8
13.9
14
14.1
14.2
14.3
14.4
-0.5 -0.4 -0.3 -0.2 -0.1
0
0.1 0.2 0.3 0.4 0.5
Common-Mode Voltage (V)
Common-Mode Voltage (V)
D058
D059
VS = ±15 V
VS = 3 V
图 45. Offset Voltage vs
图 46. Offset Voltage vs
Positive Common-Mode Voltage
Negative Common-Mode Voltage
200
150
100
50
15
14.8
14.6
14.4
14.2
14
-50èC
-40èC
25èC
85èC
125èC
150èC
0
-50
-50èC
-40èC
25èC
85èC
125èC
150èC
-100
-150
-200
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
0
2
4
6
8
10
12
14
16
Common-Mode Voltage (V)
Output Current (mA)
D060
D045
VS = 3 V
VS = ±15 V
图 47. Offset Voltage vs
图 48. Positive Output Voltage Swing
Positive Common-Mode Voltage
vs Output Current
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
-14
-14.2
-14.4
-14.6
-14.8
-15
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
-50èC
-40èC
25èC
25èC
85èC
125èC
150èC
1.9
1.8
1.7
0
2
4
6
8
10
12
14
16
0
2
4
6
8
10
12
14
16
Output Current (mA)
Output Current (mA)
D046
D048
VS = ±15 V
VS = 3 V
图 49. Negative Output Voltage Swing
图 50. Positive Output Voltage Swing
vs Output Current
vs Output Current
30
27
24
21
18
15
12
9
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VS = ê15 V
VS = +5 V
25èC
6
3
0
0
2
4
6
8
10
12
14
16
1k
10k
100k
Frequency (Hz)
1M
Output Current (mA)
D049
D014
VS = 3 V
图 51. Negative Output Voltage Swing
图 52. Large-Signal Frequency Response
vs Output Current
25
21
17
13
9
100
0.01%
0.001%
1 nF
0 pF
100 pF
220 pF
500 pF
80
60
40
20
0
-20
-40
-60
-80
-100
5
2
4
6
8
10
12
14
16
18
20
0
4
8
12 16 20 24 28 32 36 40 44 48
Time (ps)
Step Size (V)
D061
D013
图 53. Settling Time vs Step Size
图 54. Small-Signal Response vs
(VS = ±15 V)
Capacitive Loads (G = 1)
16
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
100
100
80
80
60
60
40
40
20
20
0
0
-20
-40
-60
-80
-100
-20
-40
-60
-80
-100
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
Time (ms)
Time (ms)
D009
D010
G = 1, RL = 1 kΩ, CL = 100 pF
G = 10, RL = 10 kΩ, CL = 100 pF
图 55. Small-Signal Response
图 56. Small-Signal Response
100
80
100
80
60
60
40
40
20
20
0
0
-20
-40
-60
-80
-100
-20
-40
-60
-80
-100
0
20
40
60
80 100 120 140 160 180 200
0
100 200 300 400 500 600 700 800 900 1000
Time (ms)
Time (ms)
D011
D012
G = 100, RL = 10 kΩ, CL = 100 pF
G = 1000, RL = 10 kΩ, CL = 100 pF
图 57. Small-Signal Response
图 58. Small-Signal Response
100k
10k
1k
15
10
5
0
-5
-10
-15
100
1
10
100
1k
10k
100k
1M
10M
0
2
4
6
8
10
12
14
16
Frequency (Hz)
Warm-Up Time (s)
D062
D063
图 59. Open-Loop Output Impedance vs Frequency
图 60. Change in Input Offset Voltage vs Warm-Up Time
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Typical Characteristics (接下页)
at TA = 25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1 (unless otherwise noted)
6
0.8
0.4
0
6
0.8
0.4
0
EN
ENREF
Input
4
4
Output
2
2
0
0
-2
-4
-6
-2
-4
-6
EN
-0.4
-0.4
ENREF
Input
Output
-0.8
C001
-0.8
C001
Time (50 ꢀS/div)
Time (50 ꢀS/div)
ENREF pin tied to 5 V
ENREF pin tied to 5 V
图 61. Enable Output Response
图 62. Disable Output Response
18
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ZHCSGB6A –MAY 2017–REVISED JUNE 2017
7 Detailed Description
7.1 Overview
A simplified schematic of the INA826S is shown in as well as the basic connections required for proper
functionality. The INA826S consists of a 4-resistor difference amplifier, composed of amplifier A3 and 50-kΩ
resistors, as well as buffer amplifiers A1 and A2. The gain of the circuit is set by a single external resistor placed
across pins 2 and 3. Further information on the internal topology and setting the gain can be found in the Feature
Description section. High-precision thin-film resistors integrated on-chip allow for excellent rejection of common-
mode interference signals and high gain accuracy. The INA826S also integrates radio frequency interference
(RFI) filters on the signal inputs to provide improved performance in the presence of high-frequency interference.
7.2 Functional Block Diagram
V+
0.1 mF
8
(1)
RS
1
RFI Filter
-IN
50 kW
50 kW
A1
VO = G ´ (VIN+ - VIN-
)
2
49.4 kW
24.7 kW
G = 1 +
RG
7
6
RG
A3
24.7 kW
+
3
4
VO
Load
-
50 kW
50 kW
(1)
RS
A2
REF
RFI Filter
+IN
TI Device
5
0.1 mF
Copyright © 2017, Texas Instruments Incorporated
V-
(1) This resistor is optional if the input voltage stays above [(V–) – 2 V] or the signal source current drive capability is
limited to less than 3.5 mA. See the Input Protection section for more details.
图 63. Simplified Block Diagram
-IN
RG
VO
TI Device
REF
+IN
Copyright © 2017, Texas Instruments Incorporated
图 64. INA826S Basic Connections
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7.3 Feature Description
7.3.1 Inside the INA826S
See the Functional Block Diagram section for a simplified representation of the INA826S. A more detailed
diagram (shown in 图 65) provides additional details of the INA826S operation.
Each input is protected by two field-effect transistors (FETs) that provide a low series resistance under normal
signal conditions, and preserve excellent noise performance. When excessive voltage is applied, these
transistors limit input current to approximately 8 mA.
The differential input voltage is buffered by Q1 and Q2 and is impressed across RG, causing a signal current to
flow through RG, R1, and R2. The output difference amplifier, A3, removes the common-mode component of the
input signal and refers the output signal to the REF pin.
The equations shown in 图 65 describe the output voltages of A1 and A2. The VBE and voltage drop across R1
and R2 produce output voltages on A1 and A2 that are approximately 0.8 V higher than the input voltages.
V+
V+
RG
(External)
50 kW
R1
R2
A1 Out = VCM + VBE + 0.125 V - VD/2 ´ G
V+
24.7 kW
24.7 kW
V-
V-
A2 Out = VCM + VBE + 0.125 V + VD/2 ´ G
50 kW
50 kW
Output Swing Range A1, A2, (V+) - 0.1 V to (V-) + 0.1 V
VOUT
A3
V+
VO = G ´ (VIN+ - VIN-) + VREF
V-
50 kW
Linear Input Range A3 = (V+) - 0.9 V to (V-) + 0.1 V
REF
V-
V+
V+
-IN
Q1
Q2
C1
C2
VD/2
V-
V-
A1
A2
Overvoltage
Protection
Overvoltage
Protection
RB
VB
RB
VCM
VD/2
V-
+IN
Copyright © 2016, Texas Instruments Incorporated
图 65. INA826S Simplified Circuit Diagram
20
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Feature Description (接下页)
7.3.2 Setting the Gain
Gain of the INA826S is set by a single external resistor, RG, connected between pins 2 and 3. Use 公式 1 to
select the value of RG:
49.4 kW
G = 1 +
RG
(1)
表 1 lists several commonly-used gains and resistor values. The 49.4-kΩ term in 公式 1 comes from the sum of
the two internal 24.7-kΩ feedback resistors. These on-chip resistors are laser-trimmed to accurate absolute
values. The accuracy and temperature coefficients of these resistors are included in the gain accuracy and drift
specifications of the INA826S.
表 1. Commonly-Used Gains and Resistor Values
DESIRED GAIN (V/V)
RG (Ω)
—
NEAREST 1% RG (Ω)
1
2
—
49.4 k
12.35 k
5.489 k
2.600 k
1.008 k
499
49.9 k
12.4 k
5.49 k
2.61 k
1 k
5
10
20
50
100
200
500
1000
499
248
249
99
100
49.5
49.9
7.3.2.1 Gain Drift
The stability and temperature drift of the external gain setting resistor, RG, also affects gain. The contribution of
RG to gain accuracy and drift can be directly inferred from the gain of 公式 1.
The best gain drift of 1 ppm/℃ can be achieved when the INA826S uses G = 1 without RG connected. In this
case, the gain drift is limited only by the slight mismatch of the temperature coefficient of the integrated 50-kΩ
resistors in the differential amplifier (A3). At G greater than 1, the gain drift increases as a result of the individual
drift of the 24.7-kΩ resistors in the feedback of A1 and A2, relative to the drift of the external gain resistor RG.
Process improvements of the temperature coefficient of the feedback resistors now make possible specifying a
maximum gain drift of the feedback resistors of 35 ppm/℃, thus significantly improving the overall temperature
stability of applications using gains greater than 1.
Low resistor values required for high gain can make wiring resistance important. Sockets add to the wiring
resistance and contribute additional gain error (such as a possible unstable gain error) at gains of approximately
100 or greater. To ensure stability, avoid parasitic capacitance of more than a few picofarads at RG connections.
Careful matching of any parasitics on both RG pins maintains optimal CMRR over frequency; see typical
characteristic curves 图 22 and 图 23.
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7.3.3 Offset Trimming
Most applications require no external offset adjustment; however, if necessary, adjustments can be made by
applying a voltage to the REF pin. 图 66 shows an optional circuit for trimming the output offset voltage. The
voltage applied to the REF pin is summed at the output. The op amp buffer provides low impedance at the REF
pin to preserve good common-mode rejection.
mINꢀ
m+
RG
mO
INA826S
REF
100 -A
1/2 REF200
mIN+
100 Ω
OPA333
10ꢀ-m
Adjust-ent Range
10 kΩ
100 Ω
100 -A
1/2 REF200
mꢀ
Copyright © 2017, Texas Instru-ents Incorporated
图 66. Optional Trimming of Output Offset Voltage
7.3.4 Input Common-Mode Range
The linear input voltage range of the INA826S input circuitry extends from the negative supply voltage to 1 V
below the positive supply, and maintains 84-dB (minimum) common-mode rejection throughout this range. The
common-mode range for most common operating conditions is described in 图 12 through 图 18 and 图 44
through 图 46. The INA826S can operate over a wide range of power supplies and VREF configurations, making a
comprehensive guide to common-mode range limits impractical to be provided for all possible conditions.
The most commonly overlooked overload condition occurs when a circuit exceeds the output swing of A1 and A2,
which are internal circuit nodes that cannot be measured. Calculating the expected voltages at the output of A1
and A2 (see 图 65) provides a check for the most common overload conditions. The designs of A1 and A2 are
identical and the outputs can swing to within approximately 100 mV of the power-supply rails. For example, when
the A2 output is saturated, A1 may continue to be in linear operation, responding to changes in the noninverting
input voltage. This difference can give the appearance of linear operation but the output voltage is invalid.
A single-supply instrumentation amplifier has special design considerations. To achieve a common-mode range
that extends to single-supply ground, the INA826S employs a current-feedback topology with PNP input
transistors; see 图 65. The matched PNP transistors Q1 and Q2 shift the input voltages of both inputs up by a
diode drop, and through the feedback network, shift the output of A1 and A2 by approximately 0.8 V. With both
inputs and VREF at single-supply ground (negative power supply), the output of A1 and A2 is well within the linear
range, allowing differential measurements to be made at the GND level. As a result of this input level-shifting, the
voltages at pin 2 and pin 3 are not equal to the respective input pin voltages (pin 1 and pin 4). For most
applications, this inequality is not important because only the gain-setting resistor connects to these pins.
22
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7.3.5 Input Protection
The inputs of the INA826S are individually protected for voltages up to ±40 V. For example, a condition of –40 V
on one input and 40 V on the other input does not cause damage. However, if the input voltage exceeds (V–) –
2 V and the signal source current drive capability exceeds 3.5 mA, the output voltage switches to the opposite
polarity; see 图 20. This polarity reversal can easily be avoided by adding resistance of 10 kΩ in series with both
inputs.
Internal circuitry on each input provides low series impedance under normal signal conditions. If the input is
overloaded, the protection circuitry limits the input current to a safe value of approximately 8 mA. 图 20 and 图 21
illustrate this input current limit behavior. The inputs are protected even if the power supplies are disconnected or
turned off.
7.3.6 Input Bias Current Return Path
The input impedance of the INA826S is extremely high—approximately 20 GΩ. However, a path must be
provided for the input bias current of both inputs. This input bias current is typically 35 nA. High input impedance
means that this input bias current changes very little with varying input voltage.
Input circuitry must provide a path for this input bias current for proper operation. 图 67 shows various provisions
for an input bias current path. Without a bias current path, the inputs float to a potential that exceeds the
common-mode range of the INA826S, and the input amplifiers saturate. If the differential source resistance is
low, as shown in the thermocouple example in 图 67, the bias current return path can be connected to one input.
With higher source impedance, using two equal resistors provides a balanced input with possible advantages of
lower input offset voltage as a result of bias current and better high-frequency common-mode rejection.
Microphone,
Hydrophone,
and So Forth
TI Device
47 kW
47 kW
Thermocouple
TI Device
10 kW
TI Device
Center tap provides
bias current return.
Copyright © 2017, Texas Instruments Incorporated
图 67. Providing an Input Common-Mode Current Path
版权 © 2017, Texas Instruments Incorporated
23
INA826S
ZHCSGB6A –MAY 2017–REVISED JUNE 2017
www.ti.com.cn
7.3.7 Reference Pin (REF)
The output voltage of the INA826S is developed with respect to the voltage on the reference terminal. Often, in
dual-supply operation, the reference pin (pin 6) is connected to the low-impedance system ground. In single-
supply operation, offsetting the output signal to a precise mid-supply level can be useful (for example, 2.5 V in a
5-V supply environment). To accomplish this offset, a voltage source can be tied to the REF pin to level-shift the
output so that the INA826S can drive a single-supply ADC, for example.
For the best performance, keep the source impedance to the REF pin below 5 Ω. As shown in , the reference
resistor is at one end of a 50-kΩ resistor. Additional impedance at the REF pin adds to this 50-kΩ resistor. The
imbalance in the resistor ratios results in degraded common-mode rejection ratio (CMRR).
图 68 shows two different methods of driving the reference pin with low impedance. The OPA330 is a low-power,
chopper-stabilized amplifier, and therefore offers excellent stability over temperature. The OPA330 is available in
the space-saving SC70 and even smaller chip-scale package. The REF3225 is a precision reference in the small
SOT23-6 package.
+5 V
VIN-
+5 V
RG
VOUT
INA826S
VIN-
REF
VIN+
RG
VOUT
INA826S
+5 V
REF
+5 V
VIN+
+2.5 V
OPA330
REF3225
+5 V
a) Level shifting using the OPA330 as a low-impedance buffer
b) Level shifting using the low-impedance output of the REF3225
Copyright © 2017, Texas Instruments Incorporated
图 68. Options for Low-Impedance Level Shifting
24
版权 © 2017, Texas Instruments Incorporated
INA826S
www.ti.com.cn
ZHCSGB6A –MAY 2017–REVISED JUNE 2017
7.3.8 Shutdown (EN and ENREF) Pins
The INA826S provides two pins to shut the device down: EN (enable) and ENREF (enable reference). 图 69
shows a basic schematic of the shutdown logic circuitry of the INA826S. A PNP transistor forms the basis of the
internal shutdown circuitry. The ENREF pin is connected to the emitter of the PNP transistor and is meant to be
connected to a voltage reference point for the enable logic. The EN pin is connected the base of the PNP
transistor. Applying a voltage to the EN pin that is 0.8 V or more below the enable reference voltage (at the
ENREF pin) causes a small current to flow in the internal PNP transistor that powers the INA826S internal bias
circuitry and powers-up the instrumentation amplifier. The shutdown circuitry functions properly with ENREF
connected to a voltage between (V–) + 1.5 V up to V+. The voltage on the EN pin can be as low as the negative
supply voltage (VS–) but cannot go above the voltage applied to the ENREF pin.
VS+
INA826S
ENREF
VS-
VS+
EN
VS-
To amplifier internal
bias circuitry
Copyright © 2017, Texas Instruments Incorporated
图 69. Shutdown Pin Simplified Schematic
To better understand the functionality of these pins, consider the low-voltage, single-supply application shown in
图 70 with V+ = 3.3 V. ENREF is connected to the 3.3-V power supply of the microcontroller (labeled µC) and the
EN pin is toggled by a general-purpose input/output (GPIO) pin of the microcontroller. When the GPIO pin is
asserted low, such that the voltage at the GPIO pin output is at or near 0 V, the INA826S is enabled. Conversely,
if the GPIO pin is asserted high, with an output voltage at or near 3.3 V, the INA826S is disabled.
3.3 V
VDD
INA826S
RG
GPIO
IN+
IN-
+
ADC IN
œ
ꢀC
ADC REF
Copyright © 2017, Texas Instruments Incorporated
图 70. Example Configuration in a Single-Supply System
(Pulling EN low enables the INA826S.)
版权 © 2017, Texas Instruments Incorporated
25
INA826S
ZHCSGB6A –MAY 2017–REVISED JUNE 2017
www.ti.com.cn
图 71 shows an alternate configuration of the enable logic pins. By grounding the enable pin, and toggling the
ENREF pin with the GPIO of the microcontroller, the enable logic is reversed. Now asserting high at the GPIO
output enables the INA826S, and pulling the GPIO pin low disables the INA826S.
3.3 V
VDD
GPIO
INA826S
IN+
IN-
+
ADC IN
RG
œ
ꢀC
REF
Copyright © 2017, Texas Instruments Incorporated
图 71. Alternate Configuration for the Enable Logic Pins
(Pulling ENREF high enables the INA826S.)
The majority of INA826S applications benefit greatly from the reduction of quiescent current from the typical
200 µA to values at or below 6 µA. Achieving the lowest possible system-level current in a system requires
attention to other system voltages applied to the INA826S. When shutdown, voltages applied to the reference or
input pins of the INA826S can find paths for currents to flow up into the several microamps region. In many
systems these voltages are shut down when the INA826S is shutdown, simplifying the problem. Otherwise,
additional switching may be added to reduce currents to a minimum.
26
版权 © 2017, Texas Instruments Incorporated
INA826S
www.ti.com.cn
ZHCSGB6A –MAY 2017–REVISED JUNE 2017
7.4 Device Functional Modes
The INA826S features a shutdown mode that reduces the typical power-supply current consumption from 200 µA
to less than 6 µA. Disabling the INA826S turns off the bias circuitry that powers the internal amplifiers of the
INA826S. 图 72 and 图 73 show the output behavior of the INA826S when the shutdown state is toggled. For
these plots, the ENREF pin was connected to a 5-V potential and the EN pin was pulled low to enable the
INA826S. 图 72 shows how quickly the INA826S output responds when transitioning from a shutdown state to an
enabled state. When the EN pin is pulled low, the INA826S output begins to track the input signal approximately
60 µs later. When transitioning from enabled to shutdown, as shown in 图 73, the output of the INA826S stops
tracking the input waveform in approximately 10 µs.
6
4
0.8
0.4
0
6
4
0.8
0.4
0
EN
ENREF
Input
Output
2
2
0
0
-2
-4
-6
-2
-4
-6
EN
-0.4
-0.4
ENREF
Input
Output
-0.8
C001
-0.8
C001
Time (50 ꢀS/div)
Time (50 ꢀS/div)
图 72. Enable Output Response
图 73. Disable Output Response
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The low power consumption and high performance of the INA826S make the device an excellent instrumentation
amplifier for many applications. The INA826S can be used in many low-power, portable applications because the
device has a low quiescent current (200 µA, typical) and comes in a small 10-pin VSON package. The input
protection circuitry, low maximum gain drift, low offset voltage, and 36-V maximum supply voltage also make the
INA826S an ideal choice for industrial applications as well.
版权 © 2017, Texas Instruments Incorporated
27
INA826S
ZHCSGB6A –MAY 2017–REVISED JUNE 2017
www.ti.com.cn
8.2 Typical Application
图 74 shows a three-terminal, programmable-logic controller (PLC) design for the INA826S. This PLC reference
design accepts inputs of ±10 V or ±20 mA. The output is a single-ended voltage of 2.5 V ± 2.3 V (or 200 mV to
4.8 V). Many PLCs typically have these input and output ranges.
±10 V
R
= 100 kΩ
= 4.12 kΩ
1
5 V
15 V
V+
R
2
REF3225
±20 mA
v
R
O
= 100 Ω
V
V
REF
OUT
R
=
INA826S
3
R
= 10.4 kΩ
G
2.5 V ± 2.3 V
20 Ω
V-
R
= 10 kΩ
L
+
C
O
= 1.59 nF
-15 V
Copyright © 2017, Texas Instruments Incorporated
图 74. Three-Terminal Analog Input for PLCs
8.2.1 Design Requirements
This design has the following requirements:
•
•
•
Supply voltage: ±15 V, 5 V
Inputs: ±10 V, ±20 mA
Output: 2.5 V, ±2.3 V
8.2.2 Detailed Design Procedure
There are two modes of operation for the circuit shown in 图 74: current input and voltage input. This design
requires R1 >> R2 >> R3. Given this relationship, 公式 2 calculates the current input mode transfer function.
VOUT-I = VD ´ G + VREF = -(IIN ´ R3) ´ G + VREF
where
•
G represents the gain of the instrumentation amplifier
(2)
公式 3 shows the transfer function for the voltage input mode.
R2
VOUT-V = VD ´ G + VREF = - VIN
´
´ G + VREF
R1 + R2
(3)
R1 sets the input impedance of the voltage input mode. The minimum typical input impedance is 100 kΩ. 100 kΩ
is selected for R1 because increasing the R1 value also increases noise. The value of R3 must be extremely
small compared to R1 and R2. 20 Ω for R3 is selected because that resistance value is much smaller than R1 and
yields an input voltage of ±400 mV when operated in current mode (±20 mA).
公式 4 can be used to calculate R2 given VD = ±400 mV, VIN = ±10 V, and R1 = 100 kΩ.
R2
R1 ´ VD
VD = VIN ´
® R2 =
= 4.167 kW
R1 + R2
VIN - VD
(4)
28
版权 © 2017, Texas Instruments Incorporated
INA826S
www.ti.com.cn
ZHCSGB6A –MAY 2017–REVISED JUNE 2017
Typical Application (接下页)
The value obtained from 公式 4 is not a standard 0.1% value, so 4.12 kΩ is selected. R1 and R2 also use 0.1%
tolerance resistors to minimize error.
Use 公式 5 to calculate the ideal gain of the instrumentation amplifier.
V
OUT - VREF
V
4.8 V - 2.5 V
G =
=
= 5.75
V
VD
400 mV
(5)
(6)
公式 6 calculates the gain-setting resistor value using the INA826S gain equation, 公式 1.
49.4 kW 49.4 kW 49.4 kW
GINA826 = 1 +
® RG =
=
INA826 - 1 5.75 - 1
= 10.4 kW
RG
G
10.4 kΩ is a standard 0.1% resistor value that can be used in this design. Finally, the output RC filter
components are selected to have a –3-dB cutoff frequency of 1 MHz.
8.2.3 Application Curves
图 75 and 图 76 show typical characteristic curves for 图 74.
5
4
3
2
1
0
5
4
3
2
1
0
-10
-5
0
5
10
-0.02
-0.01
0
0.01
0.02
Input Voltage (V)
Input Current (A)
D071
D070
图 75. PLC Output Voltage vs Input Voltage
图 76. PLC Output Voltage vs Input Current
版权 © 2017, Texas Instruments Incorporated
29
INA826S
ZHCSGB6A –MAY 2017–REVISED JUNE 2017
www.ti.com.cn
9 Power Supply Recommendations
The INA826S operates over a power-supply range of 3 V to 36 V (±3 V to ±18 V). Supply voltages higher than
40 V (±20 V) can permanently damage the device. Parameters that vary over supply voltage or temperature are
illustrated in the Typical Characteristics section.
9.1 Low-Voltage Operation
The INA826S can operate on power supplies as low as 3 V. Most parameters vary only slightly throughout this
supply voltage range; see the Typical Characteristics section. Operation at very low supply voltage requires
careful attention to assure that the input voltages remain within the linear range. Voltage swing requirements of
internal nodes limit the input common-mode range with low power-supply voltage. The typical characteristic
curves 图 12 through 图 18 and 图 44 through 图 46 describe the range of linear operation for various supply
voltages, reference connections, and gains.
30
版权 © 2017, Texas Instruments Incorporated
INA826S
www.ti.com.cn
ZHCSGB6A –MAY 2017–REVISED JUNE 2017
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
•
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as close
to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply
applications. The bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry, because noise can propagate into analog circuitry through the power
pins of the circuit as a whole and the op amp specifically.
•
•
Connect the device reference pin to a low-impedance, low-noise, system reference point, such as an analog
ground. If a potential other than ground is used as a reference, a low output impedance (such as a voltage
divider with an op amp buffer) must be included.
Minimize the parasitic capacitance and inductance present at the gain resistor connections. Place the gain
resistor as close to the device as possible, and remove the ground plane around the gain resistor to minimize
parasitic capacitances at these nodes.
•
•
For best performance, route the input traces adjacent to each other as a differential pair.
For proper amplifier function, connect the package thermal pad to the most negative supply voltage (VEE).
10.2 Layout Example
Copyright © 2017, Texas Instruments Incorporated
GND
Place bypass
capacitors as close to
IC as possible
GND
VS-
VS+
-IN
RG
RG
+IN
EN
OUT
REF
Input traces routed
adjacent to each other
REF pin connected to
low-impedance
INA826S
reference potential
VSœ
ENREF
GND
VS-
GND
GND
GND
Ground plane
removed at gain
resistor to minimize
parasitic capacitance
Copper pour for thermal
pad must be connected to
negative supply (VS-)
图 77. INA826S PCB Layout Example
版权 © 2017, Texas Instruments Incorporated
31
INA826S
ZHCSGB6A –MAY 2017–REVISED JUNE 2017
www.ti.com.cn
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
请参阅如下相关文档：
•
•
•
•
《OPAx330 50μV VOS、0.25μV/°C、35μA CMOS 运算放大器零漂移系列》
《REF32xx 4ppm/°C、100μA、SOT23-6 系列电压基准》
《REF50xx 低噪声、极低漂移、高精度电压基准》
《基于 SPICE 的模拟仿真程序》
11.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。请单击右上角的通知我 进行注册，即可收到任意产
品信息更改每周摘要。有关更改的详细信息，请查看任意已修订文档中包含的修订历史记录。
11.3 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包括机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据发生变化时，我们可能不
会另行通知或修订此文档。如欲获取此产品说明书的浏览器版本，请参见左侧的导航栏。
32
版权 © 2017, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
INA826SIDRCR
INA826SIDRCT
ACTIVE
ACTIVE
VSON
VSON
DRC
DRC
10
10
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
IN826S
IN826S
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jun-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
INA826SIDRCR
INA826SIDRCT
VSON
VSON
DRC
DRC
10
10
3000
250
330.0
180.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jun-2017
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
INA826SIDRCR
INA826SIDRCT
VSON
VSON
DRC
DRC
10
10
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRC 10
3 x 3, 0.5 mm pitch
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226193/A
www.ti.com
PACKAGE OUTLINE
DRC0010J
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.65 0.1
2X (0.5)
(0.2) TYP
EXPOSED
THERMAL PAD
4X (0.25)
5
6
2X
2
11
SYMM
2.4 0.1
10
1
8X 0.5
0.30
0.18
10X
SYMM
PIN 1 ID
0.1
C A B
C
(OPTIONAL)
0.05
0.5
0.3
10X
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
(2.4)
(3.4)
SYMM
(0.95)
8X (0.5)
6
5
(R0.05) TYP
(
0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218878/B 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.24)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
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