ISO224BDWVR [TI]
±12V 输入、精密电压检测增强型隔离式放大器 | DWV | 8 | -55 to 125;
| 型号： | ISO224BDWVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ±12V 输入、精密电压检测增强型隔离式放大器 | DWV | 8 | -55 to 125 放大器 PC 分离技术 隔离技术 光电二极管 |
| 文件： | 总37页 (文件大小：1711K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ISO224
ZHCSIE0A –JUNE 2018–REVISED OCTOBER 2018
具有 ±12V 单端输入和 ±4V 差分输出的
ISO224 增强型隔离放大器
3 说明
1 特性
1
•
•
提供高级 (ISO224B) 与低级 (ISO224A) 两个版本
ISO224 是一款精密的隔离放大器，此放大器的输出与
输入电路由抗电磁干扰性能极强的隔离栅隔开。该隔离
栅经认证，可提供高达 5kVRMS 的增强型电隔离，使用
寿命极长，功率耗散较低。与隔离式电源结合使用时，
该器件可将以不同共模电压电平运行的系统的各器件隔
开，并防止较低电压器件损坏。
±12V 输入电压范围针对工业应用中的隔离式电压
测量进行了 优化
•
•
•
9kV 静电放电 (ESD) 过压输入钳位
±4V 差分输出电压范围，共模电压为 VDD2/2
低直流误差运行 (ISO224B)：
–
–
–
输入失调电压：25°C 时为 ±5mV，±15µV/°C
（最大值）
ISO224 的输入专门针对精确检测 ±10V 信号进行了优
化，该信号在工业应用当中十分 普遍。该器件由高侧
单电源供电运行。此独有的特性可简化隔离式电源的设
计，降低系统成本。集成的高侧电源电压检测功能可简
化系统级诊断。ISO224 的 ±4V 输出可支持使用更低
成本的模数转换器 (ADC)。输出的差分结构具有更强
的抗噪性能。
增益误差：25°C 时为 ±0.3%，±35ppm/°C（最
大值）
非线性度：±0.01%（最大值），±0.1ppm/°C
（典型值）
•
•
•
4.5V 至 18V 高侧单电源
4.5V 至 5.5V 低侧运行
安全相关认证：
ISO224 可在 –55°C 至 +125°C 的扩展工业温度范围
内正常运行，并采用宽体 8 引脚 SOIC (DWV) 封装。
–
7071 VPEAK 增强型隔离，符合 DIN VDE V
0884-11: 2017-01 标准
器件信息(1)
–
5000 VRMS 隔离，符合 UL1577 标准且持续时
长为 1 分钟
器件名称
ISO224
封装
SOIC (8)
封装尺寸
5.85mm × 7.5mm
•
高 CMTI (ISO224B)：80kV/µs（典型值）
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
•
在以下领域进行隔离模拟信号采集：
–
–
–
–
–
–
电网自动化
保护继电器
工厂自动化与控制
铁路运输
电机驱动器
功率分析仪
简化原理图
ISO224
OUTP
OUTN
optional
IN
ADS7945
14-Bit ADC
Up to ±12 V
Clamp
optional
Isolated
4.5 V to 18 V
VDD1
GND1
VCAP
VDD2
GND2
4.5 V to 5.5 V
GND1
GND2
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBAS738
ISO224
ZHCSIE0A –JUNE 2018–REVISED OCTOBER 2018
www.ti.com.cn
目录
8.1 Overview ................................................................. 17
8.2 Functional Block Diagram ....................................... 17
8.3 Feature Description................................................. 18
8.4 Device Functional Modes........................................ 21
Application and Implementation ........................ 22
9.1 Application Information............................................ 22
9.2 Typical Application .................................................. 22
9.3 What to Do and What Not to Do ............................. 24
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
器件比较表............................................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 5
7.5 Power Ratings........................................................... 5
7.6 Insulation Specifications............................................ 6
7.7 Safety-Related Certifications..................................... 7
7.8 Safety Limiting Values .............................................. 7
7.9 Electrical Characteristics........................................... 7
7.10 Switching Characteristics........................................ 9
7.11 Insulation Characteristics Curves ......................... 10
7.12 Typical Characteristics.......................................... 11
Detailed Description ............................................ 17
9
10 Power Supply Recommendations ..................... 25
11 Layout................................................................... 26
11.1 Layout Guidelines ................................................. 26
11.2 Layout Example .................................................... 26
12 器件和文档支持 ..................................................... 27
12.1 文档支持................................................................ 27
12.2 接收文档更新通知 ................................................. 27
12.3 社区资源................................................................ 27
12.4 商标....................................................................... 27
12.5 静电放电警告......................................................... 27
12.6 术语表 ................................................................... 27
13 机械、封装和可订购信息....................................... 28
8
4 修订历史记录
Changes from Original (June 2018) to Revision A
Page
•
已更改 将文档状态从“预告信息”更改成了“生产数据” .............................................................................................................. 1
2
版权 © 2018, Texas Instruments Incorporated
ISO224
www.ti.com.cn
ZHCSIE0A –JUNE 2018–REVISED OCTOBER 2018
5 器件比较表
参数
ISO224B
ISO224A
输入失调电压，VOS
输入失调电压温漂，TCVOS
输入参考噪声
±5mV（最大值）
±15µV/°C（最大值）
3µV/√Hz（典型值）
±0.3%(最大值)
±50mV（最大值）
±60µV/°C（最大值）
4µV/√Hz（典型值）
±1%（最大值）
增益误差，EG
增益误差漂移，TCEG
非线性度
±35ppm/°C（最大值）
±0.01%（最大值）
275kHz（典型值）
80kV/µs（典型值）
2.2µs（典型值）
±60ppm/°C（最大值）
±0.02%（最大值）
185kHz（典型值）
30kV/µs（典型值）
2.8µs（典型值）
输出带宽，BW
共模瞬态抗扰度，CMTI
输入到输出，OUTN 信号延迟 (50% – 50%)
6 Pin Configuration and Functions
DWV Package
8-Pin SOIC
Top View
VCAP
IN
1
2
3
4
8
7
6
5
VDD2
OUTP
OUTN
GND2
VDD1
GND1
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
VCAP
IN
Supply decoupling capacitor.
1
—
I
Connect a 0.22-µF capacitor between this pin and the high-side analog ground.
2
3
Analog input
High-side power supply, 4.5 V to 18 V.
See the Power Supply Recommendations section for decoupling recommendations.
VDD1
—
4
5
6
7
GND1
GND2
OUTN
OUTP
—
—
O
High-side analog ground
Low-side analog ground
Inverting analog output
Noninverting analog output
O
Low-side power supply, 4.5 V to 5.5 V.
See the Power Supply Recommendations section for decoupling recommendations.
8
VDD2
—
Copyright © 2018, Texas Instruments Incorporated
3
ISO224
ZHCSIE0A –JUNE 2018–REVISED OCTOBER 2018
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
(1)
see
MIN
–0.3
MAX
26
UNIT
VDD1 to GND1
Power-supply voltage
V
VDD2 to GND2
–0.3
6.5
15
Input voltage
Input current
Output voltage
IN to GND1(2)
Continuous, at IN pin(3)
OUTP, OUTN
Junction, TJ
–15
V
–10
10
mA
GND2 – 0.3
VDD2 + 0.3
150
V
Temperature
°C
Storage, Tstg
–65
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Exposure to absolute-maximum-rated condition for extended periods may increase input leakage current.
(3) Limit the input current at IN pin to prevent permanent damage to the device. The IN pin is internally protected by a voltage clamp. See
图 42 for a typical current versus voltage characteristic curve of the input clamp.
7.2 ESD Ratings
VALUE
±9000
±3000
±1000
UNIT
IN pin only
Human-body model (HBM),
per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic
discharge
V(ESD)
All pins except IN
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX UNIT
POWER SUPPLY
High-side power supply
Low-side power supply
ANALOG INPUT
VClipping Input voltage before clipping output(1)
VFSR
Specified linear input full-scale voltage(1)
TEMPERATURE RANGE
VDD1 to GND1
VDD2 to GND2
4.5
4.5
5
5
18
V
V
5.5
IN to GND1
IN to GND1
±13.8
25
V
V
–12
–55
12
TA
Specified ambient temperature
125
°C
(1) See the Analog Input section for more details.
4
Copyright © 2018, Texas Instruments Incorporated
ISO224
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ZHCSIE0A –JUNE 2018–REVISED OCTOBER 2018
7.4 Thermal Information
ISO224x
(1)
THERMAL METRIC
DWV (SOIC)
8 PINS
96.3
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
36.9
Junction-to-board thermal resistance
60.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
16.9
ψJB
58.2
RθJC(bot)
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Power Ratings(1)
PARAMETER
TEST CONDITIONS
VDD1 = 18 V, VDD2 = 5.5 V
VDD1 = VDD2 = 5.5 V
VDD1 = 18 V
VALUE
194.9
97.4
UNIT
PD
Maximum power dissipation (both sides)
mW
140.4
42.9
PD1
PD2
Maximum power dissipation (high-side supply)
Maximum power dissipation (low-side supply)
mW
mW
VDD1 = 5.5 V
VDD2 = 5.5 V
54.5
(1) See the Electrical Characteristics table for maximum supply current specifications.
Copyright © 2018, Texas Instruments Incorporated
5
ISO224
ZHCSIE0A –JUNE 2018–REVISED OCTOBER 2018
www.ti.com.cn
7.6 Insulation Specifications
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VALUE
UNIT
GENERAL
CLR
CPG
DTI
External clearance(1)
External creepage(1)
Distance through insulation
Comparative tracking index
Material group
Shortest pin-to-pin distance through air
Shortest pin-to-pin distance across the package surface
Minimum internal gap (internal clearance) of the double insulation
DIN EN 60112 (VDE 0303-11); IEC 60112
According to IEC 60664-1
≥ 8.5
≥ 8.5
≥ 0.021
≥ 600
I
mm
mm
mm
V
CTI
Rated mains voltage ≤ 600 VRMS
I-IV
Overvoltage category per
IEC 60664-1
Rated mains voltage ≤ 1000 VRMS
I-III
DIN VDE V 0884-11 (VDE V 0884-11): 2017-01(2)
Maximum repetitive peak
isolation voltage
VIORM
At AC voltage (bipolar or unipolar)
2121
1500
VPK
At AC voltage (sine wave); time dependent dielectric breakdown (TDDB) test;
see 图 4
VRMS
VDC
Maximum-rated
isolation working voltage
VIOWM
At DC voltage
2121
7071
8485
VTEST = VIOTM, t = 60 s (qualification test)
VTEST = 1.2 × VIOTM, t = 1 s (100% production test)
Maximum transient
isolation voltage
VIOTM
VIOSM
VPK
VPK
Maximum surge
Test method per IEC 60065, 1.2/50-µs waveform,
VTEST = 1.6 × VIOSM = 12800 VPK (qualification)
8000
≤ 5
≤ 5
≤ 5
~1
isolation voltage(3)
Method A, after input/output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.2 × VIORM = 2545 VPK, tm = 10 s
Method A, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s, Vpd(m) = 1.6 × VIORM = 3394 VPK, tm = 10 s
qpd
Apparent charge(4)
pC
Method B1, at routine test (100% production) and preconditioning (type test),
Vini = VIOTM, tini = 1 s, Vpd(m) = 1.875 × VIORM = 3977 VPK, tm = 1 s
Barrier capacitance,
input to output(5)
CIO
RIO
VIO = 0.5 VPP at 1 MHz
pF
VIO = 500 V at TA = 25°C
> 1012
> 1011
> 109
Insulation resistance,
input to output(5)
VIO = 500 V at 100°C ≤ TA ≤ 125°C
VIO = 500 V at TS = 150°C
Ω
Pollution degree
Climatic category
2
55/125/21
UL1577
VTEST = VISO = 5000 VRMS or 7071 VDC, t = 60 s (qualification),
VTEST = 1.2 × VISO = 6000 VRMS, t = 1 s (100% production test)
VISO
Withstand isolation voltage
5000
VRMS
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be
taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed
circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as
inserting grooves and ribs on the PCB are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier are tied together, creating a two-pin device.
6
Copyright © 2018, Texas Instruments Incorporated
ISO224
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ZHCSIE0A –JUNE 2018–REVISED OCTOBER 2018
7.7 Safety-Related Certifications
VDE
UL
Certified according to DIN VDE V 0884-11 (VDE V 0884-11): 2017-01,
DIN EN 60950-1 (VDE 0805 Teil 1): 2014-08,
Recognized under 1577 component recognition and
CSA component acceptance NO 5 programs
and DIN EN 60065 (VDE 0860): 2005-11
Reinforced insulation
Single protection
File number: 40040142
File number: E181974
7.8 Safety Limiting Values
Safety limiting intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
R
θJA = 96.3°C/W, TJ = 150°C, TA = 25°C,
55
mA
236
VDD1 = 18 V, VDD2 = 5.5 V, see 图 2
θJA = 96.3°C/W, TJ = 150°C, TA = 25°C,
VDD1 = VDD2 = 5.5 V, see 图 2
θJA = 96.3°C/W, TJ = 150°C, TA = 25°C,
see 图 3
Safety input, output, or supply
current
IS
R
R
Safety input, output, or total
power
PS
1298(1)
150
mW
°C
TS Maximum safety temperature
(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of IS and PS. These
limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum junction temperature.
PS = IS × VDD1max + IS × VDD2max, where VDD1max is the maximum high-side supply voltage and VDD2max is the maximum low-side
supply voltage.
7.9 Electrical Characteristics
minimum and maximum specifications apply from TA = –55°C to +125°C, VDD1 = 4.5 V to 18 V, VDD2 = 4.5 V to 5.5 V, VIN
=
–12 V to 12 V, and RLOAD = 10 kΩ; typical specifications are at TA = 25°C, and VDD1 = VDD2 = 5 V (unless otherwise noted)
PARAMETER
ANALOG INPUT
TEST CONDITIONS
MIN
TYP
MAX UNIT
Initial, at TA = 25°C, IN = GND1, ISO224B
–5
–50
–15
–60
±1
±1
5
VOS
Input offset voltage(1)
mV
50
Initial, at TA = 25°C, IN = GND1, ISO224A
ISO224B
±3
15
TCVOS
Input offset voltage drift(1)
µV/°C
60
ISO224A
±12
2
CIN
RIN
IIB
Input capacitance
Input resistance
IN to GND1
IN to GND1
IN = GND1
IN = GND1
ISO224B
pF
MΩ
1
1.25
±15
±30
3
Input bias current
Input bias current drift
nA
TCIIB
pA/°C
Input-referred noise
density
en
µV/√Hz
ISO224A
4
(1) The typical value includes one sigma statistical variation.
Copyright © 2018, Texas Instruments Incorporated
7
ISO224
ZHCSIE0A –JUNE 2018–REVISED OCTOBER 2018
www.ti.com.cn
Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –55°C to +125°C, VDD1 = 4.5 V to 18 V, VDD2 = 4.5 V to 5.5 V, VIN
=
–12 V to 12 V, and RLOAD = 10 kΩ; typical specifications are at TA = 25°C, and VDD1 = VDD2 = 5 V (unless otherwise noted)
PARAMETER
ANALOG OUTPUTS
TEST CONDITIONS
MIN
TYP
MAX UNIT
Nominal gain
Gain error(1)
(VOUTP – VOUTN) / VIN
1/3
±0.05%
0.4%
±10
V/V
0.3%
Initial, at TA = 25°C, ISO224B
Initial, at TA = 25°C, ISO224A
ISO224B
–0.3%
–1%
EG
1%
–35
35
TCEG
Gain error drift(1)
ppm/°C
60
ISO224A
–60
±20
ISO224B
–0.01%
–0.02%
±0.003%
±0.003%
±0.1
0.01%
0.02%
ppm/°C
dB
Nonlinearity
ISO224A
Nonlinearity drift
THD
Total harmonic distortion fIN = 10 kHz
–84
IN = GND1, fIN = 0 Hz, BW = 10 kHz
300
Output noise
µVRMS
IN = GND1, fIN = 0 Hz, BW = 100 kHz
vs VDD1, at DC
360
–107
–101
–71
vs VDD1, 100-mV and 10-kHz ripple
vs VDD2, at DC
Power-supply rejection
ratio(2)
PSRR
dB
vs VDD2, 100-mV and 10-kHz ripple
OUTP or OUTN to GND2
–56
VOUT
Output voltage
GND2 + 0.2
0.48 × VDD2
VDD2 – 0.2
V
V
Common-mode output
voltage
VCMout
(VOUTP + VOUTN) / 2
VDD2 / 2 0.52 × VDD2
GND2 + 0.1
VDD1 missing, OUTP and OUTN forced to
GND2
VFAILSAFE Failsafe output voltage
V
Output short-circuit
current
ISC
On OUTP or OUTN to GND2
±18
mA
Overload recovery time
5
< 0.5
100
50
µs
ROUT
CLOAD
RLOAD
BW
Output resistance
Capacitive load drive(3)
Resistive load
On OUTP or OUTN to GND2
On OUTP or OUTN to GND2
OUTP to OUTN
Ω
pF
kΩ
On OUTP or OUTN
10
ISO224B
220
150
55
275
185
80
Small signal output
bandwidth
kHz
ISO224A
|GND1 – GND2| = 1 kV, ISO224B
|GND1 – GND2| = 1 kV, ISO224A
Common-mode transient
immunity
CMTI
kV/µs
15
30
POWER SUPPLY
IDD1 High-side supply current
IDD2 Low-side supply current
(2) This parameter is output referred.
(3) Use series resistor to decouple higher capacilive load.
6.1
7.8
7.8
9.9
mA
mA
8
Copyright © 2018, Texas Instruments Incorporated
ISO224
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ZHCSIE0A –JUNE 2018–REVISED OCTOBER 2018
7.10 Switching Characteristics
over operating ambient temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
1.5
2
MAX UNIT
ISO224B on OUTP, OUTN
µs
µs
tr, tf
Rise time, fall time
ISO224A on OUTP, OUTN
ISO224B, unfiltered output, see 图 1
ISO224A, unfiltered output, see 图 1
ISO224B, unfiltered output, see 图 1
ISO224A, unfiltered output, see 图 1
ISO224B, unfiltered output, see 图 1
ISO224A, unfiltered output, see 图 1
1.5
1.9
2.2
2.8
3
2
µs
IN to OUTP, OUTN signal delay
(50% – 10%)
2.9
2.7
µs
IN to OUTP, OUTN signal delay
(50% – 50%)
3.8
3.5
µs
IN to OUTP, OUTN signal delay
(50% – 90%)
3.8
4.8
VDD1 step to 4.5 V with VDD2 ≥ 4.5 V,
to OUTP, OUTN valid, 0.1% settling
tAS
Analog startup time
250
µs
12 V
50%
0 V
IN
-12 V
50% - 90%
50% - 50%
50% - 10%
OUTN
90%
50%
VCMout
10%
OUTP
tr
tf
图 1. Delay Time Test Waveforms
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7.11 Insulation Characteristics Curves
250
1600
1400
1200
1000
800
600
400
200
0
VDD1 = VDD2 = 5.5 V
VDD1 = 18 V, VDD2 = 5.5 V
225
200
175
150
125
100
75
50
25
0
0
25
50
75
100
125
150
0
25
50
75
100
125
150
TA (°C)
TA (°C)
D001
D002
图 2. Thermal Derating Curve for Safety-Limiting Current per
图 3. Thermal Derating Curve for Safety-Limiting
VDE
Power per VDE
1.E+11
Safety Margin Zone: 1800 VRMS, 254 Years
Operating Zone: 1500 VRMS, 135 Years
TDDB Line (<1 PPM Fail Rate)
1.E+10
1.E+9
1.E+8
1.E+7
1.E+6
1.E+5
1.E+4
1.E+3
1.E+2
1.E+1
87.5%
20%
500 1500 2500 3500 4500 5500 6500 7500 8500 9500
Stress Voltage (VRMS
)
TA up to 150°C, stress-voltage frequency = 60 Hz,
isolation working voltage = 1500 VRMS, operating lifetime = 135 years
图 4. Reinforced Isolation Capacitor Lifetime Projection
10
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7.12 Typical Characteristics
at TA = 25°C, VDD1 = VDD2 = 5 V, and VINP = –12 V to 12 V, unless otherwise noted.
60
50
40
30
20
10
0
5
4
3
2
1
0
-1
-2
-3
-4
-5
4.5
6
7.5
9
10.5
VDD1 (V)
12
13.5
15
16.5
18
D003
VOS (mV)
D004
ISO224B
图 5. Input Offset Voltage Histogram
图 6. Input Offset Voltage vs High-Side Supply Voltage
5
4
3
2
1
0
5
4
3
2
1
0
-1
-1
-2
-3
-4
-5
-2
-3
-4
-5
Device 1
Device 2
Device 3
4.5 4.6 4.7 4.8 4.9
5
5.1 5.2 5.3 5.4 5.5
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
VDD2 (V)
D005
D006
ISO224B
图 8. Input Offset Voltage vs Temperature
图 7. Input Offset Voltage vs Low-Side Supply Voltage
60
-13
-13.5
-14
50
40
30
20
10
0
-14.5
-15
-15.5
-16
-16.5
-17
4.5
6
7.5
9
10.5
12
13.5
15
16.5
18
VDD1 (V)
D007
D008
TCVOS (mV/èC)
ISO224B
图 10. Input Bias Current vs High-Side Supply Voltage
图 9. Input Offset Drift Histogram
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Typical Characteristics (接下页)
at TA = 25°C, VDD1 = VDD2 = 5 V, and VINP = –12 V to 12 V, unless otherwise noted.
1000
100
10
-13
-13.5
-14
-14.5
-15
-15.5
-16
1
-16.5
-17
0.1
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
0.01
0.1
1
10
100
1000
Frequency (kHz)
D009
D010
ISO224B
图 11. Input Bias Current vs Temperature
图 12. Input-Referred Noise Density vs Frequency
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
D011
D012
EG (%)
EG (%)
ISO224B
ISO224A
图 13. Gain Error Histogram
图 14. Gain Error Histogram
1
0.8
0.6
0.4
0.2
0
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.2
-0.4
-0.6
-0.8
-1
ISO224A
ISO224B
ISO224A
ISO224B
4.5
6
7.5
9
10.5
12
13.5
15
16.5
18
4.5 4.6 4.7 4.8 4.9
5
5.1 5.2 5.3 5.4 5.5
VDD1 (V)
VDD2 (V)
D013
D014
图 15. Gain Error vs High-Side Supply Voltage
图 16. Gain Error vs Low-Side Supply Voltage
12
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ZHCSIE0A –JUNE 2018–REVISED OCTOBER 2018
Typical Characteristics (接下页)
at TA = 25°C, VDD1 = VDD2 = 5 V, and VINP = –12 V to 12 V, unless otherwise noted.
70
60
50
40
30
20
10
0
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
Device 1
Device 2
Device 3
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D016
TCEG (ppm/èC)
D015
ISO224B
ISO224B
图 17. Gain Error vs Temperature
图 18. Gain Error Drift Histogram
5
0
0°
-45°
-90°
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
-135°
-180°
-225°
-270°
-315°
-360°
ISO224A
ISO224B
ISO224A
ISO224B
0.1
1
10
100
1000
0.1
1
10
100
1000
fIN (kHz)
fIN (kHz)
D017
D018
图 19. Normalized Gain vs Input Frequency
图 20. Output Phase vs Input Frequency
0.01
0.008
0.006
0.004
0.002
0
7
6
5
4
3
2
1
0
VOUTP
VOUTN
-0.002
-0.004
-0.006
-0.008
-0.01
-16
-12
-8
-4
0
4
8
12
16
-12 -10 -8 -6 -4 -2
0
2
4
6
8
10 12
VIN (V)
VIN (V)
D019
D020
图 21. Output Voltage vs Input Voltage
图 22. Nonlinearity vs Input Voltage
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Typical Characteristics (接下页)
at TA = 25°C, VDD1 = VDD2 = 5 V, and VINP = –12 V to 12 V, unless otherwise noted.
0.02
0.015
0.01
0.02
0.015
0.01
0.005
0
0.005
0
-0.005
-0.01
-0.015
-0.02
-0.005
-0.01
-0.015
-0.02
4.5
6
7.5
9
10.5 12 13.5 15 16.5 18
VDD1 (V)
4.5 4.6 4.7 4.8 4.9
5
5.1 5.2 5.3 5.4 5.5
VDD2 (V)
D021
D022
图 23. Nonlinearity vs High-Side Supply Voltage
图 24. Nonlinearity vs Low-Side Supply Voltage
0.02
0.015
0.01
-74
-76
-78
-80
-82
-84
-86
-88
-90
-92
-94
0.005
0
-0.005
-0.01
-0.015
-0.02
Device 1
Device 2
Device 3
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
4.5
6
7.5
9
10.5 12
VDD1 (V)
13.5
15
16.5
18
D023
D024
图 25. Nonlinearity vs Temperature
图 26. Total Harmonic Distortion
vs High-Side Supply Voltage
-74
-76
-78
-80
-82
-84
-86
-88
-90
-92
-94
-74
-76
-78
-80
-82
-84
-86
-88
-90
-92
-94
Device 1
Device 2
Device 3
4.5 4.6 4.7 4.8 4.9
5
5.1 5.2 5.3 5.4 5.5
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
VDD2 (V)
D025
D026
图 27. Total Harmonic Distortion
图 28. Total Harmonic Distortion vs Temperature
vs Low-Side Supply Voltage
14
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Typical Characteristics (接下页)
at TA = 25°C, VDD1 = VDD2 = 5 V, and VINP = –12 V to 12 V, unless otherwise noted.
0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
-20
-40
-60
-80
-100
vs VDD2
vs VDD1
-120
0.1
1
10
100
1000
4.5 4.6 4.7 4.8 4.9
5
5.1 5.2 5.3 5.4 5.5
Ripple Frequency (kHz)
VDD2 (V)
D027
D028
图 29. Power-Supply Rejection Ratio
图 30. Output Common-Mode Voltage
vs Ripple Frequency
vs Low-Side Supply Voltage
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
8
7.5
7
6.5
6
5.5
5
4.5
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
4.5
6
7.5
9
10.5 12
VDD1 (V)
13.5
15 16.5
18
D029
D030
图 31. Output Common-Mode Voltage vs Temperature
图 32. High-Side Supply Current
vs High-Side Supply Voltage
10
10
9.5
9
IDD2
IDD1
9.5
9
8.5
8
8.5
8
7.5
7
7.5
7
6.5
6
6.5
6
5.5
5.5
4.5 4.6 4.7 4.8 4.9
5
5.1 5.2 5.3 5.4 5.5
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
VDD2 (V)
D031
D032
图 33. Low-Side Supply Current
图 34. Supply Current vs Temperature
vs Low-Side Supply Voltage
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Typical Characteristics (接下页)
at TA = 25°C, VDD1 = VDD2 = 5 V, and VINP = –12 V to 12 V, unless otherwise noted.
2.1
2.1
2
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.9
1.8
1.7
1.6
1.5
1.4
1.3
ISO224A
ISO224B
ISO224A
ISO224B
4.5 4.6 4.7 4.8 4.9
5
5.1 5.2 5.3 5.4 5.5
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
VDD2 (V)
D033
D034
图 35. Output Rise and Fall Time
图 36. Output Rise and Fall Time vs Temperature
vs Low-Side Supply Voltage
3.5
3
5
4.5
4
2.5
2
3.5
3
2.5
2
1.5
1
1.5
1
50% - 90%
50% - 50%
50% - 10%
50% - 90%
50% - 50%
50% - 10%
0.5
0.5
4.5 4.6 4.7 4.8 4.9
5
5.1 5.2 5.3 5.4 5.5
4.5 4.6 4.7 4.8 4.9
5
5.1 5.2 5.3 5.4 5.5
VDD2 (V)
VDD2 (V)
D035
D036
ISO224B
ISO224A
图 37. VIN to VOUT Signal Delay
图 38. VIN to VOUT Signal Delay
vs Low-Side Supply Voltage
vs Low-Side Supply Voltage
3.5
3
5
4.5
4
2.5
2
3.5
3
2.5
2
1.5
1
1.5
1
50% - 90%
50% - 50%
50% - 10%
50% - 90%
50% - 50%
50% - 10%
0.5
0.5
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
D037
D038
ISO224B
图 39. VIN to VOUT Signal Delay vs Temperature
ISO224A
图 40. VIN to VOUT Signal Delay vs Temperature
16
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8 Detailed Description
8.1 Overview
The ISO224 is a precision, isolated amplifier with a high input impedance and wide input voltage range suitable
for wide range of industrial applications. The input stage of the device drives a delta-sigma (ΔΣ) modulator. The
modulator uses the internal voltage reference and clock generator to convert the analog input signal to a digital
bitstream. The drivers (called TX in the Functional Block Diagram section) transfer the output of the modulator
across the isolation barrier that separates the high-side and low-side voltage domains. The received bitstream
and clock are synchronized and processed by a digital-to-analog conversion stage on the low-side and presented
as a differential analog output.
The SiO2-based, double-capacitive isolation barrier supports a high level of magnetic field immunity, as described
in ISO72x Digital Isolator Magnetic-Field Immunity. The digital modulation used in the ISO224 and the isolation
barrier characteristics result in high reliability and high common-mode transient immunity.
8.2 Functional Block Diagram
VDD1
VDD2
Reinforced
Isolation
Barrier
Voltage Regulator
(LDO)
VDD1
Detection
Bandgap
Reference
VCAP
IN
OUTP
OUTN
Data
CLK
ûꢀ
Modulator
Clamp
TX
RX
RX
TX
Bandgap
Reference
Oscillator
GND2
ISO224
GND1
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8.3 Feature Description
8.3.1 Analog Input
The input stage of the ISO224 feeds a switched capacitor, feed-forward ΔΣ modulator. The modulator converts
the analog signal into a bitstream that is transferred over the isolation barrier, as described in the Isolation
Channel Signal Transmission section. The high-impedance and low bias-current input of the ISO224 makes the
device suitable for isolated voltage sensing applications.
图 41 visualizes the difference in the transfer function of the ISO224 depending on the input signal VIN, as
specified in the Recommended Operating Conditions table. With the input voltage within the specified full-scale
range VFSR, the output of the device changes in a linear way with small error as specified by the nonlinearity
parameter in the Electrical Characteristics table. If the input signal exceeds the VFSR range, the nonlinearity of
the output signals increases and the amplitude clips at VIN = VCLIPPING
.
6
VOUTP
VOUTN
5
VCLIPPING
VFSR
4
3
VCMout
2
1
0
-15
-10
-5
0
5
10
15
VIN (V)
图 41. Transfer Function of the ISO224
There are two restrictions on the analog input signal at the IN pin. First, if the input voltage VIN exceeds the
range of –15 V to 15 V, the current must be limited to 10 mA to prevent damage to the input clamp, see the Input
Clamp Protection Circuit section for further information. In addition, the linearity and noise performance of the
ISO224 are ensured only when the analog input voltage remains within the specified linear full-scale range
(VFSR).
18
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Feature Description (接下页)
8.3.2 Input Clamp Protection Circuit
As illustrated in the Functional Block Diagram, the ISO224 features an internal clamp protection circuit on the
analog input IN. Using external protection circuits is recommended as a secondary protection scheme to protect
the device against surges, ESD events, and electrical fast transient (EFT) conditions.
图 42 shows a typical current versus voltage characteristic curve for the input clamp. Limit either the voltage VIN
at the input pin IN to the voltage range as defined in the Recommended Operating Conditions table or the input
current to the limits as defined in the Absolute Maximum Ratings table.
50
40
30
20
10
0
-10
-20
-30
-40
-50
-20
-15
-10
-5
0
5
10
15
20
Input Voltage (V)
D007
图 42. I-V Curve of the Input Clamp Protection Circuit
图 43 shows a simple method to limit the input current with an external series resistor that is also used as part of
the input low-pass filter.
ISO224
RFLT
IN
Clamp
CFLT
Input
Signal
GND1
GND1
图 43. Series Resistor-Based Input Current Limitation on the Analog Inputs of ISO224
The input overvoltage protection clamp on the ISO224 is intended to control transient excursions on the input
pins. Leaving the device in a state such that the clamp circuit is activated for extended periods of time in normal
or power-down mode is not recommended because this fault condition can degrade device performance and
reliability.
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Feature Description (接下页)
8.3.3 Isolation Channel Signal Transmission
The ISO224 uses an on-off keying (OOK) modulation scheme to transmit the modulator output bitstream across
the SiO2-based isolation barrier. As shown in 图 44, the transmitter modulates the bitstream at TX IN with an
internally-generated, high-frequency carrier across the isolation barrier to represent a digital one and does not
send a signal to represent the digital zero. The nominal frequency of the carrier used inside the ISO224 is
480 MHz.
The receiver demodulates the signal after advanced signal conditioning and produces the output. The ISO224
also incorporates advanced circuit techniques to maximize the CMTI performance and minimize the radiated
emissions caused by the high-frequency carrier and IO buffer switching.
Transmitter
Receiver
OOK
Modulation
SiO2-Based
Capacitive
Reinforced
Isolation
TX IN
TX Signal
Conditioning
RX Signal
Conditioning
Envelope
Detection
RX OUT
Barrier
Oscillator
图 44. Block Diagram of an Isolation Channel
图 45 shows the concept of the OOK scheme.
TX IN
Carrier Signal Across
the Isolation Barrier
RX OUT
图 45. OOK-Based Modulation Scheme
20
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Feature Description (接下页)
8.3.4 Fail-Safe Output
The ISO224 offers a fail-safe output that simplifies diagnostics on system level. The fail-safe output is active
when the high-side power supply VDD1 of the device is missing, independent of the input signal at the IN pin. 图
46 shows that in that case both outputs, OUTP and OUTN, of the device are actively driven close to GND2 (see
the VFAILSAFE specification in the Electrical Characteristics table for details). For easy visualization, an example
with the input signal VIN = 0 V is shown for the valid VDD1 range of 4.5 V to 5.5 V.
3.5
3
2.5
2
Outputs are not specified
in this VDD1 range
1.5
1
0.5
VFAILSAFEmax
0
0
0.5
1
1.5
2
3
3.5
4
4.5
5
5.5
2.5
VDD1 (V)
图 46. ISO224 Failsafe Output Behavior With VIN = 0 V
The ISO224 Fail-Safe Output Feature application report describes an example of a comparator-based circuit that
detects the missing high-side supply in a system.
8.4 Device Functional Modes
The ISO224 is operational when the power supplies VDD1 and VDD2 are applied, as specified in the
Recommended Operating Conditions table.
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ISO224 enables high-precision measurement of ±10-V signals that are used in a harsh environment in a
wide range of industrial applications. The high input resistance of the device simplifies the connection of its input
to different sensors or other signal sources. The very low nonlinearity, AC and DC errors, and temperature drift
make the ISO224 a robust, high-performance, isolated amplifier for applications where high voltage isolation is
required. The differential output with a full-scale voltage of 4 V offers high immunity to noise and allows
connection to a wide range of analog-to-digital converters (ADCs) powered on a 5-V nominal supply.
9.2 Typical Application
Isolated amplifiers are often used for data acquisition in industrial applications to safely separate the low-voltage
portion of the system from the high common-mode voltage input of the system. The input structure of the ISO224
is optimized for isolated voltage sensing in this kind of application.
图 47 shows a typical operation of the device for voltage sensing as used in power line monitoring systems. The
phase voltage amplitude is reduced with a resistive divider to match the input voltage range of the ISO224. The
high input voltage range and the high common-mode transient immunity of the device ensure reliable and
accurate operation even in high-noise environments.
5 V
5 V
ISO224
VDD1
VDD2
RFLTout
R1
R2
RFLTin
AC
Voltage
Source
VAC
IAC
CFLTout
ADC
CFLTin
RFLTout
VIN
GND1
GND2
GND2
GND1
图 47. Using the ISO224 for AC Voltage Sensing
9.2.1 Design Requirements
表 1 summarizes the typical design requirements for an AC power line voltage sensing application.
表 1. Design Requirements
PARAMETER
AC voltage range, VAC
VALUE
50 V to 750 V
Bandwidth
600 Hz (minimum)
1 mA (maximum)
Current through the resistive divider, IAC
22
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ZHCSIE0A –JUNE 2018–REVISED OCTOBER 2018
9.2.2 Detailed Design Procedure
The high-side power supply (VDD1) for the device is generated with a suitable isolated power source. An
example of such a circuit is provided in the Power Supply Recommendations section.
The floating ground reference (GND1) is derived from one of the ends of the shunt resistor that is connected to
the negative input of the device (VINN). If a four-pin shunt is used, the inputs of the device are connected to the
inner leads and GND1 is connected to one of the outer shunt leads.
Use Ohm's Law to calculate the minimum total resistance of the resistive divider to limit the cross current IAC to
the desired value: R1 + R2 = VAC / IAC. The input voltage at the ISO224 results from the resistance ratio of R1 and
R2 and the actual AC voltage: VIN = VAC x R2 / (R1 + R2).
Consider the following two restrictions to choose the proper value of the R1 and R2 resistors:
•
The voltage drop on R2 caused by the nominal AC voltage range of the system must not exceed the
recommended input voltage range VIN of the ISO224
•
The voltage drop on R2 caused by the maximum allowed system overvoltage must not exceed the input
voltage that causes a clipping output: VIN ≤ VClipping
表 2 lists examples of nominal E96-series (1% accuracy) resistor values for AC systems using 120 V, 240 V, and
400 V as nominal voltages.
表 2. Resistor Value Examples
PARAMETER
Resistive divider resistor R1
120-VAC SYSTEM
115 kΩ
240-VAC SYSTEM
237 kΩ
400-VAC SYSTEM
392 kΩ
Resistive divider resistor R2
12.7 kΩ
12.4 kΩ
12.1 kΩ
Resulting current through resistive divider IAC
Resulting input voltage VIN
0.93 mA
0.93 mA
0.98 mA
±11.934 V
±11.933 V
±11.977 V
For systems using single-ended input ADCs with a 5-V supply, 图 48 shows an example of a TLV6001-based
signal conversion and filter circuit. Tailor the bandwidth of this filter stage to the bandwidth requirement of the
system and use NP0-type capacitors for best performance.
ISO224
VCMADC
VDD1
VIN
VDD2
TLV6001
VOUTP
+
To ADC
VCAP
GND1
VOUTN
GND2
œ
GND2
图 48. Connecting the ISO224 Output to a Single-Ended Input 5-V ADC
For systems using single-ended, ±10-V input ADCs, the ISO224EVM offers a signal path based on an OPA277
that converts the differential output of the ISO224 and limits the signal bandwidth to 50 kHz.
For more information on the general procedure to design the filtering and driving stages of SAR ADCs, consult
the 18-Bit, 1MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise and 18-Bit Data
Acquisition Block (DAQ) Optimized for Lowest Power TI Precision Designs, available for download at
www.ti.com.
版权 © 2018, Texas Instruments Incorporated
23
ISO224
ZHCSIE0A –JUNE 2018–REVISED OCTOBER 2018
www.ti.com.cn
9.2.3 Application Curves
In some applications the system must be protected in case of an overvoltage condition. To allow for fast
powering off of the system, a low delay caused by the isolated amplifier is required. 图 49 shows the typical full-
scale step response of the device. Consider the delay of the required window comparator and the MCU to
calculate the overall response time of the system.
VIN
VOUTN
VOUTP
图 49. Step Response of the ISO224
图 50 shows the typical AC response of the device with a full-scale sine wave with a frequency of 20 kHz applied
at the input.
VIN
VOUTP
VOUTN
图 50. AC Response of the ISO224 at fIN = 20 kHz
9.3 What to Do and What Not to Do
Do not leave the input of the ISO224 unconnected (floating) when the device is powered up. If the device input is
left floating, both outputs are at the common-mode output voltage level VCMout as specified in the Switching
Characteristics table. See the ISO224 Fail-Safe Output Feature application report for more details.
24
版权 © 2018, Texas Instruments Incorporated
ISO224
www.ti.com.cn
ZHCSIE0A –JUNE 2018–REVISED OCTOBER 2018
10 Power Supply Recommendations
In a typical application, the high-side power supply (VDD1) for the ISO224 is generated from the low-side supply
(VDD2) of the device by an isolated DC/DC converter circuit. A low-cost solution is based on the push-pull driver
SN6501 and a transformer that supports the desired isolation voltage ratings. TI recommends using a low-ESR
decoupling capacitor of 0.1 µF and an additional capacitor of a minimum 1 µF for both supplies of the ISO224. 图
51 shows the recommended placement of these decoupling capacitors as close as possible to the ISO224
power-supply pins to minimize supply current loops and electromagnetic emissions.
To decouple the output of the integrated LDO, use a 0.22-µF capacitor placed as close to the VCAP pin of the
ISO224 as possible.
The ISO224 does not require any specific power up sequencing. Consider the analog settling time tAS as
specified in the Switching Characteristics table after ramp up of the VDD1 high-side supply.
ISO224
VDD1
Detection
OUTP
IN
VDD1
OUTN
VDD2
VDD1
VCAP
1 …F
0.1 …F
VDD2
GND2
0.1 …F
1 …F
0.22 µF
GND1
GND1
GND2
VDD2
TLV70450
OUT
VDD2
SN6501
IN
D1
VCC
20 V
20 V
0.1 …F 10 …F
10 …F
0.1 …F
GND
GND2
D2
GND1
10 …F
GND2
GND1
GND2
图 51. SN6501-Based, High-Side Power Supply
版权 © 2018, Texas Instruments Incorporated
25
ISO224
ZHCSIE0A –JUNE 2018–REVISED OCTOBER 2018
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
For best performance, place the 0.22-µF capacitor (C7, as shown in 图 52) required for decoupling of the internal
LDO output as close as possible to the ISO224 VCAP pin. The 0.1-µF ceramic decoupling capacitors for both
power supplies (C8 and C9) are located as close as possible to the corresponding VDDx pins followed by the
additional 1-µF ceramic capacitors for lower-frequency decoupling (C3 and C12). The resistor and capacitor used
for the analog input (R1 and C2) are placed next to the decoupling capacitors. For best performance, use 0603-
size or 1206-size, SMD-type, ceramic capacitors with low ESR. Connect the supply voltage sources in a way that
allows the supply current to flow through the pads of the decoupling capacitors before powering the device.
图 52 shows this approach as implemented on the ISO224EVM. Capacitors C3 and C8 decouple the high-side
supply VDD1 and capacitors C9 and C12 are used to support the low-side supply VDD2 of the ISO224.
11.2 Layout Example
Clearance area,
to be kept free of any
conductive materials
To VDD2 Power
Supply Source
To Input
Signal
Source
To Filter
or ADC
ISO224
To Isolated
VDD1 Power
Supply Source
LEGEND
Top-Layer Traces
Bottom-Layer (or Inner-Layer) GND1 and GND2 Copper Pour
Clearance Area to be kept free of conductive materials on all layers
图 52. Recommended Layout of the ISO224
26
版权 © 2018, Texas Instruments Incorporated
ISO224
www.ti.com.cn
ZHCSIE0A –JUNE 2018–REVISED OCTOBER 2018
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档：
•
•
•
•
•
•
•
•
•
•
•
•
德州仪器 (TI)，《隔离相关术语》应用报告
德州仪器 (TI)，《ADS794x 14 位、2MSPS、双通道、差分/单端、超低功耗模数转换器》数据表
德州仪器 (TI)，《半导体和 IC 封装热指标》应用报告
德州仪器 (TI)，《ISO72x 数字隔离器磁场抗扰度》应用报告
德州仪器 (TI)，《ISO224 失效防护输出功能》应用报告
德州仪器 (TI)，《适用于成本敏感型系统的 TLV600x 低功耗、轨至轨输入/输出、1MHz 运算放大器》数据表
德州仪器 (TI)，《OPAx277 高精度运算放大器》数据表
德州仪器 (TI)，《经优化可实现最低失真和噪声的 18 位、1MSPS 数据采集块 (DAQ)》TI 设计
德州仪器 (TI)，《经优化可实现最低功耗的 18 位数据采集块 (DAQ)》TI 设计
德州仪器 (TI)，《SN6501 用于隔离式电源的变压器驱动器》数据表
德州仪器 (TI)，《TLV704 24V 输入电压、150mA 超低 IQ 低压降稳压器》数据表
德州仪器 (TI)，《ISO224EVM 评估模块》用户指南
12.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
版权 © 2018, Texas Instruments Incorporated
27
ISO224
ZHCSIE0A –JUNE 2018–REVISED OCTOBER 2018
www.ti.com.cn
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
28
版权 © 2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
ISO224ADWV
ISO224ADWVR
ISO224BDWV
ISO224BDWVR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
DWV
DWV
DWV
DWV
8
8
8
8
64
RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-55 to 125
-55 to 125
-55 to 125
-55 to 125
ISO224A
1000 RoHS & Green
64 RoHS & Green
1000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
ISO224A
ISO224B
ISO224B
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO224ADWVR
ISO224BDWVR
SOIC
SOIC
DWV
DWV
8
8
1000
1000
330.0
330.0
16.4
16.4
12.05 6.15
12.05 6.15
3.3
3.3
16.0
16.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ISO224ADWVR
ISO224BDWVR
SOIC
SOIC
DWV
DWV
8
8
1000
1000
350.0
350.0
350.0
350.0
43.0
43.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
ISO224ADWV
ISO224BDWV
DWV
DWV
SOIC
SOIC
8
8
64
64
505.46
505.46
13.94
13.94
4826
4826
6.6
6.6
Pack Materials-Page 3
PACKAGE OUTLINE
DWV0008A
SOIC - 2.8 mm max height
S
C
A
L
E
2
.
0
0
0
SOIC
C
SEATING PLANE
11.5 0.25
TYP
PIN 1 ID
AREA
0.1 C
6X 1.27
8
1
2X
5.95
5.75
NOTE 3
3.81
4
5
0.51
0.31
8X
7.6
7.4
0.25
C A
B
A
B
2.8 MAX
NOTE 4
0.33
0.13
TYP
SEE DETAIL A
(2.286)
0.25
GAGE PLANE
0.46
0.36
0 -8
1.0
0.5
DETAIL A
TYPICAL
(2)
4218796/A 09/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DWV0008A
SOIC - 2.8 mm max height
SOIC
8X (1.8)
SEE DETAILS
SYMM
SYMM
8X (0.6)
6X (1.27)
(10.9)
LAND PATTERN EXAMPLE
9.1 mm NOMINAL CLEARANCE/CREEPAGE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218796/A 09/2013
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DWV0008A
SOIC - 2.8 mm max height
SOIC
SYMM
8X (1.8)
8X (0.6)
SYMM
6X (1.27)
(10.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4218796/A 09/2013
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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