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ISO5851-Q1

ZHCSFJ4 –SEPTEMBER 2016

ISO5851-Q1 具有有源安全特性的高 CMTI 2.5A/5A 隔离式 IGBT、

MOSFET 栅极

驱动器

1 特性

2 应用

1

•

适用于汽车电子标准

•

隔离式绝缘栅双极型晶体管 (IGBT) 和金属氧化物

半导体场效应晶体管 (MOSFET) 驱动器：

•

具有符合 AEC-Q100 标准的下列结果:

–

混合动力汽车 (HEV) 和电动车 (EV) 电源模块

–

器件温度 1 级：-40°C 至 125°C 的环境运行温

度范围

工业电机控制驱动

工业电源

–

器件人体模型 (HBM) 分类等级 3A

器件充电器件模型 (CDM) 分类等级 C6

太阳能逆变器

感应加热

•

在 V_CM= 1500V 时，共模瞬态抗扰度 (CMTI) 的最

小值为 100kV/μs

3 说明

•

2.5A 峰值拉电流和 5A 峰值灌电流

短暂传播延迟：76ns（典型值），

110ns（最大值）

ISO5851-Q1 是一款用于 IGBT 和 MOSFET 的 5.7

kV_RMS增强型隔离栅极驱动器，具有 2.5A 的拉电流能

力和 5A 的灌电流能力。输入端由 3V 至 5.5V 的单电

源供电运行。输出端允许的电源范围为 15V 至 30V。

两个互补 CMOS 输入控制栅极驱动器的输出状态。

76ns 的短暂传播时间保证了对于输出级的精确控制。

•

2A 有源米勒钳位

输出短路钳位

在检测到去饱和故障时通过 FLT 发出故障报警，并

通过 RST 复位

•

具有就绪 (RDY) 引脚指示的输入和输出欠压锁定

(UVLO)

内置的去饱和 (DESAT) 故障检测功能可识别 IGBT 何

时处于过载状态。当检测到 DESAT 时，栅极驱动器输

出会被拉低为 V_EE2电势，从而将 IGBT 立即关断。

有源输出下拉特性，在低电源或输入悬空的情况下

默认输出低电平

•

3V 至 5.5V 输入电源电压

当发生去饱和故障时，器件会通过隔离隔栅发送故障信

号，以将输入端的 FLT 输出拉为低电平并阻断隔离器

的输入。FLT 的输出状态将被锁存，可通过 RST 输入

上的低电平有效脉冲复位。

15V 至 30V 输出驱动器电源电压

互补金属氧化物半导体 (CMOS) 兼容输入

抑制短于 20ns 的输入脉冲和瞬态噪声

可承受的浪涌隔离电压达 12800V_PK

”

器件信息⁽¹⁾

安全及管理认证：

器件型号

封装

封装尺寸（标称值）

–

符合 DIN V VDE V 0884-10 (VDE V 0884-

10):2006-12 标准的 8000 V_PKV_IOTM和 2121

V_{PK IORM}增强型隔离

ISO5851-Q1

SOIC (16)

10.30mm x 7.50mm

V

(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。

–

符合 UL 1577 标准且长达 1 分钟的 5700 V_RMS

隔离

功能方框图

V_CC1

V_CC2

CSA 组件验收通知 5A、IEC 60950-1 和 IEC

60601-1 终端设备标准

V_CC1

UVLO1

UVLO2

500 µA

DESAT

GND2

INœ

符合 EN 61010-1 和 EN 60950-1 标准的 TUV

认证

Mute

9 V

IN+

–

GB4943.1-2011 CQC 认证

V_CC1

V_CC2

RDY

已通过 UL、VDE、CQC、TUV 认证并规划进

行 CSA 认证

Gate Drive

and

Encoder

Logic

Ready

OUT

V_CC1

FLT

Decoder

Q

S

2 V

Fault

CLAMP

V_CC1

R

RST

GND1

V_EE2

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLLSEQ1

ISO5851-Q1

ZHCSFJ4 –SEPTEMBER 2016

www.ti.com.cn

1

2

3

4

5

6

7

特性.......................................................................... 1

9

Detailed Description ............................................ 19

9.1 Overview ................................................................. 19

9.2 Functional Block Diagram ....................................... 19

9.3 Feature Description................................................. 20

9.4 Device Functional Modes........................................ 21

应用.......................................................................... 1

说明.......................................................................... 1

修订历史................................................................... 2

说明（续）.............................................................. 3

Pin Configuration and Function........................... 4

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings ............................................................ 5

7.3 Recommended Operating Conditions....................... 5

7.4 Thermal Information.................................................. 5

7.5 Power Rating............................................................. 6

7.6 Insulation Characteristics.......................................... 6

7.7 Safety Limiting Values .............................................. 7

7.8 Safety-Related Certifications..................................... 7

7.9 Electrical Characteristics........................................... 8

7.10 Switching Characteristics........................................ 9

7.11 Safety and Insulation Characteristics Curves ....... 10

7.12 Typical Characteristics.......................................... 11

Parameter Measurement Information ................ 17

10 Application and Implementation........................ 22

10.1 Application Information.......................................... 22

10.2 Typical Applications .............................................. 22

11 Power Supply Recommendations ..................... 31

12 Layout................................................................... 31

12.1 Layout Guidelines ................................................. 31

12.2 PCB Material......................................................... 31

12.3 Layout Example .................................................... 31

13 器件和文档支持 ..................................................... 32

13.1 文档支持................................................................ 32

13.2 接收文档更新通知 ................................................. 32

13.3 社区资源................................................................ 32

13.4 商标....................................................................... 32

13.5 静电放电警告......................................................... 32

13.6 Glossary................................................................ 32

14 机械、封装和可订购信息....................................... 33

8

4 修订历史

注：之前版本的页码可能与当前版本有所不同。

日期

修订版本

注释

2015 年 9 月

*

最初发布版本

2

ISO5851-Q1

www.ti.com.cn

ZHCSFJ4 –SEPTEMBER 2016

5 说明（续）

如果在由双极输出电源供电的正常运行期间关断 IGBT，输出电压会被硬钳位为 V_EE2。如果输出电源为单极，那么

可采用有源米勒钳位，这种钳位会在一条低阻抗路径上灌入米勒电流，从而防止 IGBT 在高电压瞬态条件下发生动

态导通。

当发生去饱和故障时，器件会通过隔离隔栅发送故障信号，以将输入端的 FLT 输出拉为低电平并阻断隔离器的输

入。FLT 的输出状态将被锁存，可通过 RST 输入上的低电平有效脉冲复位。

如果在由双极输出电源供电的正常运行期间关断 IGBT，输出电压会被硬钳位为 V_EE2。如果输出电源为单极，那么

可采用有源米勒钳位，这种钳位会在一条低阻抗路径上灌入米勒电流，从而防止 IGBT 在高电压瞬态条件下发生动

态导通。

栅极驱动器是否准备就绪待运行由两个欠压锁定电路控制，这两个电路会监视输入端和输出端的电源。如果任意一

端电源不足，RDY 输出会变为低电平；否则，该输出为高电平。

ISO5851-Q1 采用 16 引脚小外形尺寸集成电路 (SOIC) 封装。此器件的额定工作环境温度范围为 -40°C 至 125°

C。

3

ISO5851-Q1

ZHCSFJ4 –SEPTEMBER 2016

www.ti.com.cn

6 Pin Configuration and Function

DW Package

16-Pin SOIC

Top View

V_EE2

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

GND1

V_CC1

DESAT

GND2

NC

RST

FLT

RDY

IN-

V_CC2

OUT

CLAMP

V_EE2

IN+

GND1

Pin Functions

I/O

DESCRIPTION

NAME

V_EE2

DESAT

GND2

NC

NO.

1, 8

2

-

I

Output negative supply. Connect to GND2 for Unipolar supply application.

Desaturation voltage input

3

-

Gate drive common. Connect to IGBT emitter.

Not connected

4

-

V_CC2

OUT

CLAMP

GND1

IN+

5

-

Most positive output supply potential.

Gate drive voltage output

6

O

-

7

Miller clamp output

9, 16

10

11

12

13

14

15

Input ground

I

Non-inverting gate drive voltage control input

Inverting gate drive voltage control input

Power-good output, active high when both supplies are good.

Fault output, low-active during DESAT condition

Reset input, apply a low pulse to reset fault latch.

Positive input supply (3 V to 5.5 V)

IN-

I

RDY

FLT

O

I

RST

V_CC1

-

4

ISO5851-Q1

www.ti.com.cn

ZHCSFJ4 –SEPTEMBER 2016

7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾

Over operating free-air temperature range (unless otherwise noted)

MIN

GND1 - 0.3

–0.3

MAX

UNIT

V

V_CC1

Supply voltage input side

6

35

V_CC2

Positive supply voltage output side

Negative supply voltage output side

Total supply output voltage

(V_CC2– GND2)

(V_EE2– GND2)

V

V_EE2

–17.5

0.3

V

V_(SUP2)

V_OUT

I_(OUTH)

(V_CC2- V_EE2

)

–0.3

35

V

Gate driver output voltage

V_EE2- 0.3

V_CC2+ 0.3

2.7

V

Gate driver high output current

(max pulse width = 10 μs, max duty

cycle = 0.2%)

A

I_(OUTL)

Gate driver low output current

5.5

A

V_(LIP)

I_(LOP)

Voltage at IN+, IN-,FLT, RDY, RST

Output current of FLT, RDY

GND1 - 0.3

V_CC1+ 0.3

10

V

mA

V

V_(DESAT)Voltage at DESAT

V_(CLAMP)Clamp voltage

GND2 - 0.3

V_EE2- 0.3

–40

V_CC2+ 0.3

150

V

T_J

Junction temperature

Storage temperature

°C

T_STG

–65

150

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions

is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability

7.2 ESD Ratings

VALUE

±4000

±1500

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

V_(ESD)

Electrostatic discharge

V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

V_CC1

V_CC2

V_EE2

V_(SUP2)

V_IH

Supply voltage input side

3

5.5

V

Positive supply voltage output side (V_CC2– GND2)

Negative supply voltage output side (V_EE2– GND2)

15

30

–15

0

30

V

Total supply voltage output side (V_CC2– V_EE2

High-level input voltage (IN+, IN-, RST)

Low-level input voltage (IN+, IN-, RST)

)

15

V

0.7 x V_CC1

V_CC1

V

V_IL

0

40

0.3 x V_CC1

V

t_UI

Pulse width at IN+, IN- for full output (C_LOAD= 1nF)

Pulse width at RST for resetting fault latch

Ambient temperature

ns

°C

t_RST

T_A

800

-40

25

125

7.4 Thermal Information

DW (SOIC)

16 PINS

99.6

THERMAL METRIC⁽¹⁾

UNIT

θ_JA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

θ_JCtop

θ_JB

48.5

Junction-to-board thermal resistance

56.5

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

29.2

ψ_JB

56.5

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

5

ISO5851-Q1

ZHCSFJ4 –SEPTEMBER 2016

www.ti.com.cn

7.5 Power Rating

VALUE

1255

175

UNIT

P_D

Maximum power dissipation⁽¹⁾

P_ID

P_OD

Maximum input power dissipation

Maximum output power dissipation

mW

1080

(1) Full chip power dissipation is de-rated 10.04 mW/°C beyond 25°C ambient temperature. At 125°C ambient temperature, a maximum of

251 mW total power dissipation is allowed. Power dissipation can be optimized depending on ambient temperature and board design,

while ensuring that Junction temperature does not exceed 150°C.

7.6 Insulation Characteristics

PARAMETER

TEST CONDITIONS

SPECIFICATION

UNIT

CLR

CPG

External clearance⁽¹⁾

Shortest terminal-to-terminal distance through air

8

mm

Shortest terminal-to-terminal distance across the package

surface

External creepage⁽¹⁾

8

mm

DTI

CTI

Distance through the insulation

Comparative tracking index

Material group

Minimum internal gap (internal clearance)

DIN EN 60112 (VDE 0303-11); IEC 60112

According to IEC 60664-1

21

>600

I

μm

V

Rated mains voltage ≤ 600 V_RMS

Rated mains voltage ≤ 1000 V_RMS

I-IV

I-III

Overvoltage category per IEC 60664-1

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12⁽²⁾

V_IORM

Maximum repetitive peak isolation voltage

AC voltage (bipolar)

2121

1500

2121

8000

V_PK

V_RMS

V_DC

AC voltage. Time dependent dielectric breakdown (TDDB)

Test, see Figure 1

V_IOWM

Maximum isolation working voltage

DC voltage

V_TEST= V_IOTM, t = 60 sec (qualification), t = 1 sec (100%

production)

V_IOTM

V_IOSM

Maximum Transient isolation voltage

Maximum surge isolation voltage⁽³⁾

V_PK

Test method per IEC 60065, 1.2/50 μs waveform,

V_TEST= 1.6 x V_IOSM= 12800 V_PK(qualification)

8000

Method a: After I/O safety test subgroup 2/3,

V_ini= V_IOTM, t_ini= 60 s;

≤5

V_pd(m)= 1.2 × V_IORM= 2545 V_PK

,

t_m= 10 s

Method a: After environmental tests subgroup 1,

V_ini= V_IOTM, t_ini= 60 s;

≤5

q_pd

Apparent charge⁽⁴⁾

V_pd(m)= 1.6 × V_IORM= 3394 V_PK

,

pC

t_m= 10 s

Method b1: At routine test (100% production) and

preconditioning (type test)

V_ini= V_IOTM, t_ini= 60 s;

V_pd(m)= 1.875× V_IORM= 3977 V_PK

,

t_m= 10 s

> 10⁹

>10¹²

>10¹¹

1

V_IO= 500 V at T_S

Ω

R_IO

C_IO

Isolation resistance, input to output⁽⁵⁾

V_IO= 500 V, T_A= 25°C

V_IO= 500 V, 100°C ≤ T_A≤ 125°C

V_IO= 0.4 x sin (2πft), f = 1 MHz

Ω

Barrier capacitance, input to output⁽⁵⁾

Pollution degree

pF

2

UL 1577

V_TEST= V_ISO, t = 60 sec (qualification),

V_TEST= 1.2 × V_ISO= 6840 V_RMS, t = 1 sec (100%

production)

V_ISO

Withstanding Isolation voltage

5700

V_RMS

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care

should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on

the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.

Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.

(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by

means of suitable protective circuits.

(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(4) Apparent charge is electrical discharge caused by a partial discharge (pd).

(5) All pins on each side of the barrier tied together creating a two-terminal device.

6

ISO5851-Q1

www.ti.com.cn

ZHCSFJ4 –SEPTEMBER 2016

7.7 Safety Limiting Values

Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of

the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat

the die and damage the isolation barrier, potentially leading to secondary system failures.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

349

UNIT

θ_JA= 99.6°C/W, V_I= 3.6 V, T_J= 150°C, T_A= 25°C

θ_JA= 99.6°C/W, V_I= 5.5 V, T_J= 150°C, T_A= 25°C

θ_JA= 99.6°C/W, V_I= 15 V, T_J= 150°C, T_A= 25°C

θ_JA= 99.6°C/W, V_I= 30 V, T_J= 150°C, T_A= 25°C

228

Safety input, output or supply

current

I_S

mA

84

42

P_S

T_S

Safety input, output, or total power θ_JA= 99.6°C/W, T_J= 150°C, T_A= 25°C

1255⁽¹⁾

Maximum ambient safety

temperature

150

°C

(1) Input, output, or the sum of input and output power should not exceed this value

7.8 Safety-Related Certifications

VDE

CSA

UL

CQC

Certified according to GB

TUV

Plan to certify under CSA

Component Acceptance

Notice 5A, IEC 60950-1, and

IEC 60601-1

Certified according to UL

1577 Component Recognition 4943.1-2011

Program

Certified according to

EN 61010-1:2010 (3rd Ed)

and

Certified according to

DIN V VDE V 0884-10 (VDE

V 0884-10):2006-12 and DIN

EN 60950-1 (VDE 0805 Teil

1):2011-01

EN 60950-

1:2006/A11:2009/A1:2010/

A12:2011/A2:2013

Isolation Rating of 5700 V_RMS

;

5700 V_RMSReinforced

insulation per

EN 61010-1:2010 (3rd Ed) up

to working voltage of 600

V_RMS

5700 V_RMSReinforced

insulation per

EN 60950-

Reinforced insulation per CSA

60950-1- 07+A1+A2 and IEC

60950-1 (2nd Ed.), 800 V_RMS

max working voltage (pollution

degree 2, material group I) ;

2 MOPP (Means of Patient

Protection) per CSA 60601-

1:14 and IEC 60601-1 Ed.

3.1, 250 V_RMS(354 V_PK) max

working voltage

Reinforced Insulation

Maximum Transient isolation

Reinforced Insulation, Altitude

Single Protection, 5700 V_RMS≤ 5000m, Tropical climate,

voltage, 8000 V_PK

Maximum surge isolation

voltage, 8000 V_PK

;

(1)

400 V_RMSmaximum working

voltage

,

Maximum repetitive peak

isolation voltage, 2121 V_PK

1:2006/A11:2009/A1:2010/

A12:2011/A2:2013 up to

working voltage of 800 V_RMS

Certification completed

Certificate number: 40040142 Certification planned

Certification completed

File number: E181974

Certification completed

Certificate number:

CQC16001141761

Certification completed

Client ID number: 77311

(1) Production tested ≥6840 V_RMSfor 1 second in accordance with UL 1577.

The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum

Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the

application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the

Thermal Information table is that of a device installed in the High-K Test Board for Leaded Surface-Mount

Packages. The power is the recommended maximum input voltage times the current. The junction temperature is

then the ambient temperature plus the power times the junction-to-air thermal resistance.

7

ISO5851-Q1

ZHCSFJ4 –SEPTEMBER 2016

www.ti.com.cn

7.9 Electrical Characteristics

Over recommended operating conditions unless otherwise noted. All typical values are at T_A= 25°C, V_CC1= 5 V,

V_CC2– GND2 = 15 V, GND2 – V_EE2= 8 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOLTAGE SUPPLY

Positive-going UVLO1 threshold voltage

input side (V_CC1– GND1)

V_IT+(UVLO1)

V_IT-(UVLO1)

V_HYS(UVLO1)

V_IT+(UVLO2)

V_IT-(UVLO2)

V_HYS(UVLO2)

2.25

V

Negative-going UVLO1 threshold voltage

input side (V_CC1– GND1)

1.7

UVLO1 Hysteresis voltage (V_IT+– V_IT–

input side

)

0.24

12

11

1

Positive-going UVLO2 threshold voltage

output side (V_CC2– GND2)

13

Negative-going UVLO2 threshold voltage

output side (V_CC2– GND2)

9.5

UVLO2 Hysteresis voltage (V_IT+– V_IT–

output side

)

I_Q1

Input supply quiescent current

Output supply quiescent current

2.8

3.6

4.5

6

mA

I_Q2

LOGIC I/O

Positive-going input threshold voltage (IN+,

IN-, RST)

V_IT+(IN,RST)

V_IT-(IN,RST)

0.7 x V_CC1

V

Negative-going input threshold voltage

(IN+, IN-, RST)

0.3 x V_CC1

V_HYS(IN,RST)

Input hysteresis voltage (IN+, IN-, RST)

High-level input leakage at (IN+)

Low-level input leakage at (IN-, RST)

Pull-up current of FLT, RDY

0.15 x V_CC1

100

V

I_IH

IN+ = V_CC1

µA

V

I_IL

IN- = GND1, RST = GND1

V_(RDY)= GND1, V_(FLT)= GND1

I_(FLT)= 5 mA

-100

I_PU

V_OL

100

Low-level output voltage at FLT, RDY

0.2

2

GATE DRIVER STAGE

V_(OUTPD)

V_(OUTH)

V_(OUTL)

Active output pull-down voltage

I_OUT= 200 mA, V_CC2= open

I_OUT= –20 mA

V

High-level output voltage

Low-level output voltage

V_CC2- 0.5

V_CC2- 0.24

V_EE2+ 13

I_OUT= 20 mA

V_EE2+ 50

mV

IN+ = high, IN- = low,

V_OUT= V_CC2- 15 V

I_(OUTH)

I_(OUTL)

High-level output peak current

Low-level output peak current

1.5

3.4

2.5

5

A

IN+ = low, IN- = high,

V_OUT= V_EE2+ 15 V

ACTIVE MILLER CLAMP

V_(CLP)Low-level clamp voltage

I_(CLP)

I_(CLP)= 20 mA

V_EE2+ 0.015

V_EE2+ 0.08

2.5

V

A

V

Low-level clamp current

Clamp threshold voltage

V_(CLAMP)= V_EE2+ 2.5 V

1.6

2.5

2.1

V_(CLTH)

SHORT CIRCUIT CLAMPING

Clamping voltage

V_{(CLP_OUT)}

IN+ = high, IN- = low, t_CLP= 10 µs,

I_(OUTH)= 500 mA

0.8

1.3

V

(V_OUT- V_CC2

)

Clamping voltage

(V_CLP- V_CC2

IN+ = high, IN- = low, t_CLP= 10 µs,

I_(CLP)= 500 mA

V_{(CLP_CLAMP)}

1.3

0.7

V

)

V_{(CLP_CLAMP)}

Clamping voltage at CLAMP

IN+ = High, IN- = Low, I_(CLP)= 20 mA

1.1

DESAT PROTECTION

I_(CHG)

Blanking capacitor charge current

V_(DESAT)- GND2 = 2 V

V_(DESAT)- GND2 = 6 V

0.42

9

0.5

14

0.58

mA

I_(DCHG)

Blanking capacitor discharge current

DESAT threshold voltage with respect to

GND2

V_(DSTH)

V_(DSL)

8.3

0.4

9

9.5

1

V

DESAT voltage with respect to GND2,

when OUT is driven low

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7.10 Switching Characteristics

Over recommended operating conditions unless otherwise noted. All typical values are at T_A= 25°C, V_CC1= 5 V,

V_CC2– GND2 = 15 V, GND2 – V_EE2= 8 V

PARAMETER

Output signal rise time

Output signal fall time

Propagation Delay

TEST CONDITIONS

MIN

12

TYP

20

MAX UNIT

t_r

35

37

ns

t_f

12

20

t_PLH, t_PHL

t_sk-p

76

110

20

C_LOAD= 1 nF, see Figure 38,

Figure 39, and Figure 40

Pulse Skew |t_PHL– t_PLH

|

t_sk-pp

Part-to-part skew

30⁽¹⁾

t_GF

Glitch filter on IN+, IN-, RST

DESAT sense to 10% OUT delay

DESAT glitch filter delay

20

30

415

40

t_{DESAT (10%)}

t_{DESAT (GF)}

t_{DESAT (FLT)}

t_LEB

300

500

330

DESAT sense to FLT-low delay

Leading edge blanking time

Glitch filter on RST for resetting FLT

see Figure 40

2000

400

2420

500

see Figure 38 and Figure 39

330

300

t_GF(RSTFLT)

800

V_I= V_CC1/2 + 0.4 x sin (2πft), f = 1

MHz, V_CC1= 5 V

C_I

Input capacitance⁽²⁾

2

pF

CMTI

Common-mode transient immunity

V_CM= 1500 V, see Figure 41

100

120

kV/μs

(1) Measured at same supply voltage and temperature condition

(2) Measured from input pin to ground.

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7.11 Safety and Insulation Characteristics Curves

1.E+11

Safety Margin Zone: 1800 V_RMS, 254 Years

Operating Zone: 1500 V_RMS, 135 Years

TDDB Line (<1 PPM Fail Rate)

1.E+10

1.E+9

1.E+8

1.E+7

1.E+6

1.E+5

1.E+4

1.E+3

1.E+2

1.E+1

87.5%

20%

500 1500 2500 3500 4500 5500 6500 7500 8500 9500

Stress Voltage (V_RMS

)

T_Aupto 150°C

Stress-voltage frequency = 60 Hz

Figure 1. Reinforced High-Voltage Capacitor Life Time Projection

400

350

300

250

200

150

100

50

1400

V_CC1= 3.6 V

V_CC1= 5.5 V

V_CC2= 15 V

V_CC2= 30 V

Power

1200

1000

800

600

400

200

0

50

100

150

200

0

50

100

150

200

Ambient Temperature (èC)

Figure 2. Thermal Derating Curve for Safety Limiting

Current per VDE

Figure 3. Thermal Derating Curve for Safety Limiting Power

per VDE

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7.12 Typical Characteristics

0.5

7.0

6.0

5.0

4.0

3.0

2.0

1.0

0.0

V_CC2- V_OUT= 2.5 V

V_CC2- V_OUT= 5 V

V_CC2- V_OUT= 10 V

V_CC2- V_OUT= 15 V

V_CC2- V_OUT= 20 V

0.0

-0.5

-1.0

-1.5

-2.0

-2.5

-3.0

V_OUT- V_EE2= 2.5 V

V_OUT- V_EE2= 5 V

V_OUT- V_EE2= 10 V

V_OUT- V_EE2= 15 V

V_OUT- V_EE2= 20 V

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Ambient Temperature (èC)

D001

D002

V_CC2= 30 V

Figure 4. Output High Drive Current vs Temperature

Figure 5. Output Low Drive Current vs Temperature

7

6

5

4

3

2

1

0

0.0

T_A= -40èC

T_A= 25èC

T_A= 125èC

-0.5

-1.0

-1.5

-2.0

-2.5

-3.0

-3.5

T_A= -40èC

T_A= 25èC

T_A= 125èC

0

5

10

15

20

25

30

0

5

10

15

20

25

30

(V_CC2- V_OUT) Voltage (V)

(V_OUT- V_EE2) Voltage (V)

D003

D004

Figure 6. Output High Drive Current vs Output Voltage

Figure 7. Output Low Drive Current vs Output Voltage

9.5

9.4

9.3

9.2

9.1

9

15 V Unipolar

30 V Unipolar

8.9

8.8

8.7

8.6

8.5

-40

-20

0

20

40

60

80

100 120 140

Ambient Temperature (èC)

D005

Unipolar: V_CC2- V_EE2= V_CC2- GND2

Figure 8. DESAT Threshold Voltage vs Temperature

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Typical Characteristics (continued)

CH1: OUT

CH2: DESAT

CH3: /FLT

Time - 50 ns/div

C_L= 1 nF

R_G= 10 Ω

C_L= 1 nF

R_G= 0 Ω

V_CC2- V_EE2= V_CC2- GND2 = 20 V

Figure 10. OUT Transient Waveform

Figure 9. OUT Transient Waveform

Time - 500 ns/div

C_L= 10 nF

R_G= 0 Ω

C_L= 10 nF

R_G= 10 Ω

V_CC2- V_EE2= V_CC2- GND2 = 20 V

Figure 11. OUT Transient Waveform

Figure 12. OUT Transient Waveform

Time - 2 ms/div

Time - 1 ms/div

C_L= 100 nF

R_G= 10 Ω

C_L= 100 nF

R_G= 0 Ω

V_CC2- V_EE2= V_CC2- GND2 = 20 V

Figure 14. OUT Transient Waveform

Figure 13. OUT Transient Waveform

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ZHCSFJ4 –SEPTEMBER 2016

Typical Characteristics (continued)

3.5

3

CH1: OUT

2.5

2

CH2: DESAT

CH3: FLT

1.5

1

V_CC1= 3 V

V_CC1= 3.3 V

V_CC1= 5 V

V_CC1= 5.5 V

0.5

0

Time - 1 ms/div

C_L= 100 nF

R_G= 10 Ω

-40

-20

0

20

40

60

80

100 120 140

V_CC2- V_EE2= V_CC2- GND2 = 20 V

Ambient Temperature (èC)

D006

IN+ = High

IN- = Low

Figure 15. OUT Transient Waveform DESAT and FLT

Figure 16. I_CC1Supply Current vs Temperature

2

1.8

1.6

1.4

1.2

1

5

4.5

4

3.5

3

2.5

2

0.8

0.6

0.4

0.2

0

1.5

1

V_CC1= 3 V

V_CC1= 3.3 V

V_CC1= 5 V

V_CC1= 5.5 V

V_CC2= 15 V

V_CC2= 20 V

V_CC2= 30 V

0.5

0

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Ambient Temperature (èC)

D007

D008

IN+ = Low

IN- = Low

Input Frequency = 1 kHz

Figure 17. I_CC1Supply Current vs Temperature

Figure 18. I_CC2Supply Current vs Temperature

3

2.5

2

5

4.5

4

V_CC1= 3 V

V_CC1= 5.5 V

3.5

3

1.5

1

2.5

2

1.5

1

V_CC2= 15 V

V_CC2= 20 V

V_CC2= 30 V

0.5

0

0.5

0

50

100

150

200

250

300

0

50

100

150

200

250

300

Input Frequency (kHz)

D009

D010

no C_L

Figure 19. I_CC1Supply Current vs. Input Frequency

Figure 20. I_CC2Supply Current vs Input Frequency

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ZHCSFJ4 –SEPTEMBER 2016

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Typical Characteristics (continued)

100

90

80

70

60

50

40

30

20

10

0

70

V_CC2= 15 V

V_CC2= 30 V

60

50

40

30

20

10

0

tpLH at V_CC2= 15 V

tpHL at V_CC2= 15 V

tpLH at V_CC2= 30 V

tpHL at V_CC2= 30 V

0

10

20

30

40

50

60

70

80

90 100

-40

-20

0

20

40

60

80

100 120 140

Load Capacitance (nF)

Ambient Temperature (èC)

D025

D012

R_G= 10 Ω, 20kHz

C_L= 1nF

R_G= 0 Ω

V_CC1= 5 V

Figure 21. I_CC2Supply Current vs Load Capacitance

Figure 22. V_CC1Propagation Delay vs Temperature

100

90

80

70

60

50

40

30

20

10

0

1200

1000

800

600

400

200

0

tpLH at V_CC2= 15 V

tpLH at V_CC2= 30 V

tpHL at V_CC2= 15 V

tpHL at V_CC2= 30 V

tpLH at V_CC1= 3.3 V

tpHL at V_CC1= 3.3 V

tpLH at V_CC1= 5 V

tpHL at V_CC1= 5 V

-40

-20

0

20

40

60

80

100 120 140

0

10

20

30

40

50

60

70

80

90 100

Ambient Temperature (èC)

Load Capacitance (nF)

D013

D024

C_L= 1nF

R_G= 0 Ω

V_CC2= 15 V

R_G= 10 Ω

V_CC1= 5 V

Figure 23. V_CC2Propagation Delay vs Temperature

Figure 24. Propagation Delay vs Load Capacitance

800

700

600

500

400

300

200

100

0

500

450

400

350

300

250

200

150

100

50

V_CC2= 15 V

V_CC2= 30 V

V_CC2= 15 V

V_CC2= 30 V

0

10

20

30

40

50

60

70

80

90 100

0

10

20

30

40

50

60

70

80

90 100

Load Capacitance (nF)

D022

D026

R_G= 0 Ω

V_CC1= 5 V

R_G= 0 Ω

V_CC1= 5 V

Figure 25. t_rRise Time vs Load Capacitance

Figure 26. t_fFall Time v. Load Capacitance

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ZHCSFJ4 –SEPTEMBER 2016

Typical Characteristics (continued)

4000

3500

3000

2500

2000

1500

1000

500

2500

2000

1500

1000

500

V_CC2= 15 V

V_CC2= 30 V

V_CC2= 15 V

V_CC2= 30 V

0

10

20

30

40

50

60

70

80

90 100

0

10

20

30

40

50

60

70

80

90 100

Load Capacitance (nF)

D023

D027

R_G= 10 Ω

V_CC1= 5 V

R_G= 10 Ω

V_CC1= 5 V

Figure 27. t_rRise Time vs Load Capacitance

Figure 28. t_fFall Time vs Load Capacitance

500

480

460

440

420

400

380

360

340

320

300

450

445

440

435

430

425

420

415

410

405

400

V_CC2= 15 V

V_CC2= 30 V

V_CC2= 15 V

V_CC2= 30 V

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Ambient Temperature (èC)

D015

D014

C_L= 10 nF

Figure 30. DESAT Sense to V_OUT10% Delay vs Temperature

Figure 29. Leading Edge Blanking Time With Temperature

120

2.1

V_CC2= 15 V

V_CC2= 30 V

100

80

2.05

2

1.95

1.9

60

40

V_CC1= 3 V

V_CC1= 3.3 V

V_CC1= 5 V

1.85

20

V_CC1= 5.5 V

1.8

-40

0

-40

-20

0

20

40

60

80

100 120 140

-20

0

20

40

60

80

100 120 140

Ambient Temperature (èC)

D016

D017

C_L= 1 nF

Figure 31. DESAT Sense to FLT Low Delay vs Temperature

Figure 32. Reset to Fault Delay Across Temperature

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ZHCSFJ4 –SEPTEMBER 2016

www.ti.com.cn

Typical Characteristics (continued)

5

2

1.8

1.6

1.4

1.2

1

V_(CLAMP)= 2 V

V_(CLAMP)= 4 V

V_(CLAMP)= 6 V

4.5

4

3.5

3

2.5

2

0.8

0.6

0.4

0.2

0

1.5

1

I_OUT= 100 mA

I_OUT= 200 mA

0.5

0

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Ambient Temperature (èC)

D018

D019

Figure 33. Miller Clamp Current vs Temperature

Figure 34. Active Pull Down Voltage vs Temperature

1400.0

1200.0

1000.0

800.0

600.0

400.0

200.0

0.0

1200

1000

800

600

400

200

0

20mA at VCC2 = 15V

20mA at VCC2 = 30V

250mA at VCC2 = 15V

250mA at VCC2 = 30V

500mA at VCC2 = 15V

500mA at VCC2 = 30V

20mA at VCC2 = 15V

20mA at VCC2 = 30V

250mA at VCC2 = 15V

250mA at VCC2 = 30V

500mA at VCC2 = 15V

500mA at VCC2 = 30V

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Ambient Temperature (Cè)

D020

D021

Figure 36. V_{CLP_CLAMP}- Short Circuit Clamp Voltage on OUT

Across Temperature

Figure 35. V_{CLP_CLAMP}- Short Circuit Clamp Voltage on

Clamp Across Temperature

-400

-420

-440

-460

-480

-500

-520

-540

-560

-580

-600

-40

-20

0

20

40

60

80

100 120 140

Ambient Temperature (èC)

D011

V_CC2= 15 V

DESAT = 6 V

Figure 37. Blanking Capacitor Charging Current vs Temperature

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ZHCSFJ4 –SEPTEMBER 2016

8 Parameter Measurement Information

IN-

0V

V

CC1

50 %

IN+

0V

t

f

r

90%

50%

10%

OUT

t_PLH

t

PHL

DESAT

t

LEB

Figure 38. OUT Propagation Delay, Non-Inverting Configuration

V

IN-

CC1

0V

50 %

V

IN+

CC1

t

f

r

90%

50%

10%

OUT

t

PLH

PHL

DESAT

t

LEB

Figure 39. OUT Propagation Delay, Inverting Configuration

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ZHCSFJ4 –SEPTEMBER 2016

www.ti.com.cn

Parameter Measurement Information (continued)

t_{DESAT (10%)}

t_{DESAT (FLT)}

9V

t_RST

V_DESAT

OUT

10%

FLT

50 %

RST

Figure 40. DESAT, OUT, FLT, RST Delay

ISO 5851 œ Q1

15

5

V_CC2

V_CC1

15 V

1 µF

0. 1 µF

3 V - 5.5 V

9, 16

3

GND 1

GND 2

V_EE2

1, 8

6

14

10

RST

IN +

+

-

+

OUT

S1

:

Pass - Fail Criterion

OUT must remain stable

11

13

C_L

1 nF

IN -

2

-

FLT

DESAT

12

7

4

CLAMP

NC

RDY

-

+

V_CM

Figure 41. Common-Mode Transient Immunity Test Circuit

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9 Detailed Description

9.1 Overview

The ISO5851-Q1 is an isolated gate driver for IGBTs and MOSFETs. Input CMOS logic and output power stage

are separated by a capacitive, silicon dioxide (SiO₂), isolation barrier.

The IO circuitry on the input side interfaces with a micro controller and consists of gate drive control and RESET

(RST) inputs, READY (RDY) and FAULT (FLT) alarm outputs. The power stage consists of power transistors to

supply 2.5-A pull-up and 5-A pull-down currents to drive the capacitive load of the external power transistors, as

well as DESAT detection circuitry to monitor IGBT collector-emitter overvoltage under short circuit events. The

capacitive isolation core consists of transmit circuitry to couple signals across the capacitive isolation barrier, and

receive circuitry to convert the resulting low-swing signals into CMOS levels. The ISO5851-Q1 also contains

under voltage lockout circuitry to prevent insufficient gate drive to the external IGBT, and active output pull-down

feature which ensures that the gate-driver output is held low, if the output supply voltage is absent. TheISO5851-

Q1 also has an active Miller clamp function which can be used to prevent parasitic turn-on of the external power

transistor, due to Miller effect, for unipolar supply operation.

9.2 Functional Block Diagram

V_CC2

V_CC1

UVLO1

UVLO2

500 µA

DESAT

GND2

INœ

Mute

9 V

IN+

V_CC1

V_CC2

RDY

Gate Drive

and

Encoder

Logic

Ready

OUT

V_CC1

FLT

Decoder

Q

S

2 V

Fault

CLAMP

V_CC1

R

RST

GND1

V_EE2

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9.3 Feature Description

9.3.1 Supply and active Miller clamp

The ISO5851-Q1 supports both bipolar and unipolar power supply with active Miller clamp.

For operation with bipolar supplies, the IGBT is turned off with a negative voltage on its gate with respect to its

emitter. This prevents the IGBT from unintentionally turning on because of current induced from its collector to its

gate due to Miller effect. In this condition it is not necessary to connect CLAMP output of the gate driver to the

IGBT gate, but connecting CLAMP output of the gate driver to the IGBT gate is also not an issue. Typical values

of V_CC2and V_EE2for bipolar operation are 15-V and -8-V with respect to GND2.

For operation with unipolar supply, typically, V_CC2is connected to 15-V with respect to GND2, and V_EE2is

connected to GND2. In this use case, the IGBT can turn-on due to additional charge from IGBT Miller

capacitance caused by a high voltage slew rate transition on the IGBT collector. To prevent IGBT to turn on, the

CLAMP pin is connected to IGBT gate and Miller current is sinked through a low impedance CLAMP transistor.

Miller CLAMP is designed for Miller current up to 2-A. When the IGBT is turned-off and the gate voltage

transitions below 2-V the CLAMP current output is activated.

9.3.2 Active Output Pull-down

The Active output pull-down feature ensures that the IGBT gate OUT is clamped to V_EE2to ensure safe IGBT off-

state when the output side is not connected to the power supply.

9.3.3 Undervoltage Lockout (UVLO) with Ready (RDY) Pin Indication Output

Undervoltage Lockout (UVLO) ensures correct switching of IGBT. The IGBT is turned-off, if the supply V_CC1

drops below V_IT-(UVLO1), irrespective of IN+, IN- and RST input till V_CC1goes above V_IT+(UVLO1)

.

In similar manner, the IGBT is turned-off, if the supply V_CC2drops below V_IT-(UVLO2), irrespective of IN+, IN- and

RST input till V_CC2goes above V_IT+(UVLO2)

.

Ready (RDY) pin indicates status of input and output side Under Voltage Lock-Out (UVLO) internal protection

feature. If either side of device have insufficient supply (V_CC1or V_CC2), the RDY pin output goes low; otherwise,

RDY pin output is high. RDY pin also serves as an indication to the micro-controller that the device is ready for

operation.

9.3.4 Fault (FLT) and Reset (RST)

During IGBT overload condition, to report desaturation error FLT goes low. If RST is held low for the specified

duration, FLT is cleared at rising edge of RST. RST has an internal filter to reject noise and glitches. By asserting

RST for at-least the specified minimum duration, device input logic can be enabled or disabled.

9.3.5 Short Circuit Clamp

Under short circuit events it is possible that currents are induced back into the gate-driver OUT and CLAMP pins

due to parasitic Miller capacitance between the IGBT collector and gate terminals. Internal protection diodes on

OUT and CLAMP help to sink these currents while clamping the voltages on these pins to values slightly higher

than the output side supply.

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9.4 Device Functional Modes

Table 1 lists the functional modes for the ISO5851-Q1 device.

InISO5851-Q1 OUT to follow IN+ in normal functional mode, FLT needs to be in high state.

Table 1. Function Table⁽¹⁾

V_CC1

PU

PD

PU

V_CC2

PD

IN+

X

IN-

X

RST

X

RDY

Low

High

Low

High

OUT

Low

High

PU

X

PU

X

Low

X

Open

PU

X

Low

X

PU

High

Low

X

PU

High

(1) PU: Power Up (V_CC1≥ 2.25-V, V_CC2≥ 13-V), PD: Power Down (V_CC1≤ 1.7-V, V_CC2≤ 9.5-V), X: Irrelevant

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10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

10.1 Application Information

The ISO5851-Q1 is an isolated gate driver for power semiconductor devices such as IGBTs and MOSFETs. It is

intended for use in applications such as motor control, industrial inverters and switched mode power supplies. In

these applications, sophisticated PWM control signals are required to turn the power devices on and off, which at

the system level eventually may determine, for example, the speed, position, and torque of the motor or the

output voltage, frequency and phase of the inverter. These control signals are usually the outputs of a micro

controller, and are at low voltage levels such as 3.3-V or 5-V. The gate controls required by the MOSFETs and

IGBTs, on the other hand, are in the range of 30-V (using Unipolar Output Supply) to 15-V (using Bipolar Output

Supply), and need high current capability to be able to drive the large capacitive loads offered by those power

transistors. Not only that, the gate drive needs to be applied with reference to the Emitter of the IGBT (Source for

MOSFET), and by construction, the Emitter node in a gate drive system may swing between 0 to the DC bus

voltage, that can be several 100s of volts in magnitude.

The ISO5851-Q1 is thus used to level shift the incoming 3.3-V and 5-V control signals from the microcontroller to

the 30-V (using Unipolar Output Supply) to 15-V (using Bipolar Output Supply) drive required by the power

transistors while ensuring high-voltage isolation between the driver side and the microcontroller side.

10.2 Typical Applications

Figure 42 shows the typical application of a three-phase inverter using six ISO5851-Q1 isolated gate drivers.

Three-phase inverters are used for variable-frequency drives to control the operating speed and torque of AC

motors and for high power applications such as High-Voltage DC (HVDC) power transmission.

The basic three-phase inverter consists of six power switches, and each switch is driven by one ISO5851-Q1.

The switches are driven on and off at high switching frequency with specific patterns that to converter dc bus

voltage to three-phase AC voltages.

Figure 42. Typical Motor Drive Application

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ISO5851-Q1

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ZHCSFJ4 –SEPTEMBER 2016

Typical Applications (continued)

10.2.1 Design Requirements

Unlike optocoupler based gate drivers which need external current drivers and biasing circuitry to provide the

input control signals, the input control to the ISO5851-Q1 is CMOS and can be directly driven by the

microcontroller. Other design requirements include decoupling capacitors on the input and output supplies, a

pullup resistor on the common drain FLT output signal and RST input signal, and a high-voltage protection diode

between the IGBT collector and the DESAT input. Further details are explained in the subsequent sections.

Table 2 shows the allowed range for Input and Output supply voltage, and the typical current output available

from the gate-driver.

Table 2. Design Parameters

PARAMETER

Input supply voltage

VALUE

3-V to 5.5-V

15-V to 30-V

0-V to 15-V

2.5-A

Unipolar output supply voltage (V_CC2- GND2 = V_CC2- V_EE2

)

Bipolar output supply voltage (V_CC2- V_EE2

)

Bipolar output supply voltage (GND2 - V_EE2

Output current

)

10.2.2 Detailed Design Procedure

10.2.2.1 Recommended ISO5851-Q1 Application Circuit

The ISO5851-Q1 has both, inverting and non-inverting gate control inputs, an active low reset input, and an open

drain fault output suitable for wired-OR applications. The recommended application circuit in Figure 43 illustrates

a typical gate driver implementation with Unipolar Output Supply and Figure 44 illustrates a typical gate driver

implementation with Bipolar Output Supply using the ISO5851-Q1.

A 0.1-μF bypass capacitor, recommended at input supply pin V_CC1and 1-μF bypass capacitor, recommended at

output supply pin V_CC2, provide the large transient currents necessary during a switching transition to ensure

reliable operation. The 220 pF blanking capacitor disables DESAT detection during the off-to-on transition of the

power device. The DESAT diode (D_DST) and its 1-kΩ series resistor are external protection components. The R_G

gate resistor limits the gate charge current and indirectly controls the IGBT collector voltage rise and fall times.

The open-drain FLT output and RDY output has a passive 10-kΩ pull-up resistor. In this application, the IGBT

gate driver is disabled when a fault is detected and will not resume switching until the micro-controller applies a

reset signal.

10 R

10

R

15

9, 16

10

5

15

9, 16

10

V_CC1

V_CC2

GND 2

V_EE2

ISO 5851 œ Q1

V_CC2

GND 2

V_EE2

ISO 5851 œ Q1

1 µF

3

V - 5.5 V

0.1 µF

3 V - 5.5 V

15 V

3

GND 1

IN +

GND 1

IN +

1 µF

1

,

8

,

1

8

D_DST

1 kΩ

10 k

11

12

13

14

2

7

6

4

2

7

6

4

11

12

13

14

IN -

DESAT

CLAMP

OUT

IN -

DESAT

CLAMP

OUT

RDY

FLT

RST

RDY

R_G

FLT

NC

RST

220

pf

220

pf

Figure 43. Unipolar Output Supply

Figure 44. Bipolar Output Supply

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ISO5851-Q1

ZHCSFJ4 –SEPTEMBER 2016

www.ti.com.cn

10.2.2.2 FLT and RDY Pin Circuitry

There is 50k pull-up resistor internally on FLT and RDY pins. The FLT and RDY pin is an open-drain output. A

10-kΩ pull-up resistor can be used to make it faster rise and to provide logic high when FLT and RDY is inactive,

as shown in Figure 45

Fast common mode transients can inject noise and glitches on FLT and RDY pins due to parasitic coupling. This

is dependent on board layout. If required, additional capacitance (100 pF to 300 pF) can be included on the FLT

and RDY pins.

ISO 5851 œ Q1

10 R

15

V_CC1

0. 1 µF

3V œ 5 V

9, 16

GND 1

10 k

12

13

RDY

FLT

µC

14

10

RST

IN +

11

IN -

Figure 45. FLT and RDY Pin Circuitry for High CMTI

10.2.2.3 Driving the Control Inputs

The amount of common-mode transient immunity (CMTI) can be curtailed by the capacitive coupling from the

high-voltage output circuit to the low-voltage input side of the ISO5851-Q1. For maximum CMTI performance, the

digital control inputs, IN+ and IN-, must be actively driven by standard CMOS, push-pull drive circuits. This type

of low-impedance signal source provides active drive signals that prevent unwanted switching of the ISO5851-Q1

output under extreme common-mode transient conditions. Passive drive circuits, such as open-drain

configurations using pull-up resistors, must be avoided. There is a 20 ns glitch filter which can filter a glitch up to

20 ns on IN+ or IN-.

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ZHCSFJ4 –SEPTEMBER 2016

10.2.2.4 Local Shutdown and Reset

In applications with local shutdown and reset, the FLT output of each gate driver is polled separately, and the

individual reset lines are asserted low independently to reset the motor controller after a fault condition.

10 R

ISO 5851 œ Q1

15

ISO 5851 œ Q1

10 R

V_CC1

15

V_CC1

0.1 µF

3 V - 5 V

0. 1 µF

3 V œ 5 V

9, 16

GND 1

10 k

12

13

12

13

RDY

FLT

RDY

FLT

µC

14

10

14

10

RST

IN +

RST

IN +

11

IN -

11

IN -

Figure 46. Local Shutdown and Reset for Noninverting (left) and Inverting Input Configuration (right)

10.2.2.5 Global-Shutdown and Reset

When configured for inverting operation, the ISO5851-Q1 can be configured to shutdown automatically in the

event of a fault condition by tying the FLT output to IN+. For high reliability drives, the open drain FLT outputs of

multiple ISO5851-Q1 devices can be wired together forming a single, common fault bus for interfacing directly to

the micro-controller. When any of the six gate drivers of a three-phase inverter detects a fault, the active low FLT

output disables all six gate drivers simultaneously.

10 R

ISO 5851 - Q1

15

V_CC1

0. 1 µF

3V œ 5V

9, 16

GND 1

10 k

12

13

RDY

FLT

µC

14

10

RST

IN +

11

IN -

to other

RSTs

to other

FLTs

Figure 47. Global Shutdown with Inverting Input Configuration

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ISO5851-Q1

ZHCSFJ4 –SEPTEMBER 2016

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10.2.2.6 Auto-Reset

In this case, the gate control signal at IN+ is also applied to the RST input to reset the fault latch every switching

cycle. Incorrect RST makes output go low. A fault condition, however, the gate driver remains in the latched fault

state until the gate control signal changes to the 'gate low' state and resets the fault latch.

If the gate control signal is a continuous PWM signal, the fault latch will always be reset before IN+ goes high

again. This configuration protects the IGBT on a cycle by cycle basis and automatically resets before the next

'on' cycle.

ISO 5851 œ Q1

10 R

15

V_CC1

0. 1 µF

3 V - 5 V

0.1 µF

3 V - 5 V

9, 16

GND 1

10 k

12

13

12

13

RDY

FLT

RDY

FLT

µC

14

10

14

10

RST

IN +

RST

IN +

11

IN -

Figure 48. Auto Reset for Non-inverting and Inverting Input Configuration

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ISO5851-Q1

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ZHCSFJ4 –SEPTEMBER 2016

10.2.2.7 DESAT Pin Protection

Switching inductive loads causes large instantaneous forward voltage transients across the freewheeling diodes

of IGBTs. These transients result in large negative voltage spikes on the DESAT pin which draw substantial

current out of the device. To limit this current below damaging levels, a 100-Ω to 1-kΩ resistor is connected in

series with the DESAT diode.

Further protection is possible through an optional Schottky diode, whose low forward voltage assures clamping of

the DESAT input to GND2 potential at low voltage levels.

ISO 5851 -Q1

5

V_CC2

1 µF

15 V

3

GND 2

1 µF

15 V

1, 8

V_EE2

D_DST

R_S

2

DESAT

7

CLAMP

R_G

6

OUT

NC

V_FW-Inst

4

220 pF

V_FW

Figure 49. DESAT Pin Protection with Series Resistor and Schottky Diode

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ISO5851-Q1

ZHCSFJ4 –SEPTEMBER 2016

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10.2.2.8 DESAT Diode and DESAT Threshold

The DESAT diode’s function is to conduct forward current, allowing sensing of the IGBT’s saturated collector-to-

emitter voltage, V_(CESAT), (when the IGBT is "on") and to block high voltages (when the IGBT is "off"). During the

short transition time when the IGBT is switching, there is commonly a high dV_CE/dt voltage ramp rate across the

IGBT. This results in a charging current I_(CHARGE)= C_(D-DESAT)x d_VCE/dt, charging the blanking capacitor. C_(D-DESAT)

is the diode capacitance at DESAT.

To minimize this current and avoid false DESAT triggering, fast switching diodes with low capacitance are

recommended. As the diode capacitance builds a voltage divider with the blanking capacitor, large collector

voltage transients appear at DESAT attenuated by the ratio of 1+ C_(BLANK)/ C_(D-DESAT)

.

Because the sum of the DESAT diode forward-voltage and the IGBT collector-emitter voltage make up the

voltage at the DESAT-pin, V_F+ V_CE= V_(DESAT), the V_CElevel, which triggers a fault condition, can be modified by

adding multiple DESAT diodes in series: V_CE-FAULT(TH)= 9 V – n x VF (where n is the number of DESAT diodes).

When using two diodes instead of one, diodes with half the required maximum reverse-voltage rating may be

chosen.

10.2.2.9 Determining the Maximum Available, Dynamic Output Power, P_OD-max

The ISO5851-Q1 maximum allowed total power consumption of P_D= 251 mW consists of the total input power,

P_ID, the total output power, P_OD, and the output power under load, P_OL

:

P_D= P_ID+ P_OD+ P_OL

(1)

(2)

(3)

(4)

With:

P_ID= V_CC1-max× I_CC1-max= 5.5 V × 4.5 mA = 24.75 mW

and:

P_OD= (V_CC2– V_EE2) x I_CC2-max= (15 V – ( –8 V )) × 6 mA = 138 mW

then:

P_OL= P_D– P_ID– P_OD= 251 mW – 24.75 mW – 138 mW = 88.25 mW

In comparison to P_OL, the actual dynamic output power under worst case condition, P_OL-WC, depends on a variety

of parameters:

æ

ç

è

ö

÷

ø

r_on-max

r_off-max

P_OL-WC= 0.5 ´ f

´ Q_G

´

V

- V_EE2

´

+

(

)

INP

CC2

r_on-max+ R_G

r_off-max+ R_G

where

•

f_INP= signal frequency at the control input IN+

Q_G= power device gate charge

V_CC2= positive output supply with respect to GND2

V_EE2= negative output supply with respect to GND2

r_on-max= worst case output resistance in the on-state: 4Ω

r_off-max= worst case output resistance in the off-state: 2.5Ω

R_G= gate resistor

(5)

Once R_Gis determined, Equation 5 is to be used to verify whether P_OL-WC< P_OL. Figure 50 shows a simplified

output stage model for calculating P_OL-WC

.

28

ISO5851-Q1

www.ti.com.cn

ZHCSFJ4 –SEPTEMBER 2016

ISO 5851 œ Q1

V_CC2

15 V

r_on-max

R_G

OUT

Q_G

r_off-max

8 V

V_EE2

Figure 50. Simplified Output Model for Calculating P_OL-WC

10.2.2.10 Example

This examples considers an IGBT drive with the following parameters:

I_ON-PK= 2 A, Q_G= 650 nC, f_INP= 20 kHz, V_CC2= 15V, V_EE2= –8 V

(6)

Applying the value of the gate resistor R_G= 10 Ω.

Then, calculating the worst-case output power consumption as a function of R_G, using Equation 5 r_on-max= worst

case output resistance in the on-state: 4 Ω, r_off-max= worst case output resistance in the off-state: 2.5 Ω, R_G

=

gate resistor yields

4 Ω

2.5 Ω

æ

ö

P_OL-WC= 0.5´20 kHz´650 nC´ 15 V -( -8 V) ´

+

4 Ω + 10 Ω 2.5 Ω + 10 Ω

= 72.61 mW

(

)

ç

è

÷

ø

(7)

Because P_OL-WC= 72.61 mW is below the calculated maximum of P_OL= 88.25 mW, the resistor value of R_G= 10

Ω is suitable for this application.

29

ISO5851-Q1

ZHCSFJ4 –SEPTEMBER 2016

www.ti.com.cn

10.2.2.11 Higher Output Current Using an External Current Buffer

To increase the IGBT gate drive current, a non-inverting current buffer (such as the npn/pnp buffer shown in

Figure 51) may be used. Inverting types are not compatible with the desaturation fault protection circuitry and

must be avoided. The MJD44H11/MJD45H11 pair is appropriate for currents up to 8 A, the D44VH10/ D45VH10

pair for up to 15 A maximum.

ISO 5851 - Q1

5

V_CC2

1 µF

15 V

3

GND 2

1 µF

15 V

1, 8

V_EE2

D_DST

1 kΩ

10 Ω

2

7

6

4

DESAT

CLAMP

OUT

r_G

NC

220

pf

Figure 51. Current Buffer for Increased Drive Current

10.2.3 Application Curve

C_L= 1 nF

R_G= 10 Ω

C_L= 1 nF

R_G= 10 Ω

GND2 - V_EE2= 8 V

V_CC2- V_EE2= V_CC2- GND2 = 20 V

V_CC2- GND2 = 15 V

(V_CC2- V_EE2= 23 V)

Figure 53. Normal Operation - Unipolar Supply

Figure 52. Normal Operation - Bipolar Supply

30

ISO5851-Q1

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ZHCSFJ4 –SEPTEMBER 2016

11 Power Supply Recommendations

To ensure reliable operation at all data rates and supply voltages, a 0.1-μF bypass capacitor is recommended at

input supply pin V_CC1and 1-μF bypass capacitor is recommended at output supply pin V_CC2. The capacitors

should be placed as close to the supply pins as possible. Recommended placement of capacitors needs to be

2-mm maximum from input and output power supply pin (V_CC1and V_CC2).

12 Layout

12.1 Layout Guidelines

A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 54). Layer stacking should

be in the following order (top-to-bottom): high-current or sensitive signal layer, ground plane, power plane and

low-frequency signal layer.

•

Routing the high-current or sensitive traces on the top layer avoids the use of vias (and the introduction of

their inductances) and allows for clean interconnects between the gate driver and the microcontroller and

power transistors. Gate driver control input, Gate driver output OUT and DESAT should be routed in the top

layer.

•

Placing a solid ground plane next to the sensitive signal layer provides an excellent low-inductance path for

the return current flow. On the driver side, use GND2 as the ground plane.

Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of

approximately 100 pF/inch². On the gate-driver V_EE2and V_CC2can be used as power planes. They can share

the same layer on the PCB as long as they are not connected together.

•

Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links

usually have margin to tolerate discontinuities such as vias.

For more detailed layout recommendations, including placement of capacitors, impact of vias, reference planes,

routing etc. see Application Note SLLA284, Digital Isolator Design Guide.

12.2 PCB Material

For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace

lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper

alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength and

stiffness, and the self-extinguishing flammability-characteristics.

12.3 Layout Example

High-speed traces

10 mils

Ground plane

Yeep this

FR-4

0 ~ 4.5

space free

from planes,

traces, pads,

and vias

40 mils

10 mils

r

Power plane

Low-speed traces

Figure 54. Recommended Layer Stack

31

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13 器件和文档支持

13.1 文档支持

13.1.1 相关文档ꢀ


型号：	ISO5851QDWQ1
厂家：	TEXAS INSTRUMENTS
描述：	具有有源保护功能的汽车类 5.7kVrms、2.5A/5A 单通道隔离式栅极驱动器 \| DW \| 16 \| -40 to 125 栅极驱动双极性晶体管光电二极管接口集成电路驱动器
文件：	总40页 (文件大小：1133K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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