ISO7021 [TI]

经 ATEX/IECEx 认证的超低功耗两通道数字隔离器;


型号：	ISO7021
厂家：	TEXAS INSTRUMENTS
描述：	经 ATEX/IECEx 认证的超低功耗两通道数字隔离器
文件：	总34页 (文件大小：1566K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ISO7021

ZHCSK04B –JULY 2019 –REVISED AUGUST 2020

ISO7021 超低功耗双通道数字隔离器

• 工厂自动化和过程控制

• 低功耗GPIO、UART 隔离

1 特性

• 超低功耗

3 说明

– 每通道静态电流为4.8μA (3.3V)

ISO7021 器件是一种可用于隔离 CMOS 或 LVCMOS

数字 I/O 的超低功耗多通道数字隔离器。每条隔离通

道的逻辑输入和输出缓冲器均由双电容二氧化硅(SiO₂)

绝缘栅相隔离。基于边缘的创新架构与开关键控调制方

案相结合，使这些隔离器具有非常低的功耗，同时符合

UL1577 规定的 3000V_RMS隔离额定值。该器件的每通

道动态电流消耗低于 120μA/Mbps ，并且 3.3V 时每

通道静态电流消耗为 4.8μA ，从而允许在功耗和热性

能受限的系统设计中使用ISO7021。

– 100kbps 时的每通道电流为15μA (3.3V)

– 1Mbps 时的每通道电流为120μA (3.3V)

• 稳健可靠的隔离栅

– 预计寿命超过100 年

– 隔离额定值为3000V_RMS

– CMTI 典型值为±100kV/μs

• 宽电源电压范围：1.71V 到1.89V 和2.25V 到5.5V

• 宽温度范围：–55°C 至+125°C

• 小型8-SOIC 封装(8-D)

• 信令速率：高达4Mbps

• 默认输出高电平(ISO7021) 和低电平(ISO7021F)

选项

该器件可在低至 1.71V 和高达 5.5V 的电压下工作，并

可在隔离栅的每一侧采用不同电源电压的情况下实现完

整功能。双通道隔离器采用窄体8-SOIC 封装，具有一

个正向通道和一个反向通道。该器件具有默认输出高电

平和低电平选项。如果输入功率或信号出现损失，不具

有 F 后缀的 ISO7021 器件默认输出高电平，具有 F

后缀的 ISO7021F 器件默认输出低电平。请参阅器件

功能模式部分以了解详情。

• 优异的电磁兼容性(EMC)

– 系统级ESD、EFT 和浪涌抗扰性

– 在整个隔离栅具有±8kV IEC 61000-4-2 接触放

电保护

– 超低干扰(EMI)

• 安全相关认证（计划）：

器件信息

– DIN V VDE 0884-11:2017-01

– UL 1577 组件认证计划

器件型号⁽¹⁾

ISO7021

封装尺寸（标称值）

封装

SOIC (8-D)

4.90mm × 3.91mm

– IEC 60950-1、IEC 62368-1、IEC 61010-1、

IEC60601-1 和GB 4943.1-2011 认证

– IECEx（IEC 60079-0 和IEC 60079-11）和

ATEX（EN IEC60079-0 和EN 60079-11）

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

2 应用

• 4mA 至20mA 环路供电式现场变送器

400

100

V_CC2

V_CC1

V_CC2

V_DD

ISO7021

MCU

ADC

DGND

GND2

GND1

Galvanic

Isolation Barrier

Digital

Ground

ISO

Ground

简化版应用原理图

100

Data Rate (kbps)

1000

4000

SLLS

电压为3.3V 时的数据速率与功耗间的关系

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLLSFA0

ISO7021

www.ti.com.cn

ZHCSK04B –JULY 2019 –REVISED AUGUST 2020

Table of Contents

6.17 Switching Characteristics .......................................13

7 Parameter Measurement Information..........................14

8 Detailed Description......................................................15

8.1 Overview...................................................................15

8.2 Functional Block Diagram.........................................15

8.3 Feature Description...................................................16

8.4 Device Functional Modes..........................................17

9 Application and Implementation..................................18

9.1 Application Information............................................. 18

9.2 Typical Application.................................................... 20

10 Power Supply Recommendations..............................23

11 Layout...........................................................................24

11.1 Layout Guidelines................................................... 24

11.2 Layout Example...................................................... 24

12 Device and Documentation Support..........................25

12.1 Documentation Support.......................................... 25

12.2 Receiving Notification of Documentation Updates..25

12.3 支持资源..................................................................25

12.4 Trademarks.............................................................25

12.5 静电放电警告.......................................................... 25

12.6 术语表..................................................................... 25

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

Pin Functions.................................................................... 3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings ....................................... 4

6.2 ESD Ratings .............................................................. 4

6.3 Recommended Operating Conditions ........................5

6.4 Thermal Information ...................................................6

6.5 Power Ratings ............................................................6

6.6 Insulation Specifications ............................................ 7

6.7 Safety-Related Certifications ..................................... 8

6.8 Safety Limiting Values ................................................8

6.9 Electrical Characteristics 5V Supply .......................... 9

6.10 Supply Current Characteristics 5V Supply ...............9

6.11 Electrical Characteristics 3.3V Supply ................... 10

6.12 Supply Current Characteristics 3.3V Supply ..........10

6.13 Electrical Characteristics 2.5V Supply ................... 11

6.14 Supply Current Characteristics 2.5V Supply ..........11

6.15 Electrical Characteristics 1.8V Supply ................... 12

6.16 Supply Current Characteristics 1.8V Supply ..........12

Information.................................................................... 25

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision * (July 2019) to Revision A (October 2019)

Page

• RTM 发布............................................................................................................................................................1

Changes from Revision A (October 2019) to Revision B (August 2020)

Page

• 通过重命名认证、添加“（计划）”并包括已完成的 ATEX 认证，更新了首页。............................................. 1

• Added IECEx and ATEX to Safety-Related Certifications...................................................................................8

• Added 节9.1.2 section..................................................................................................................................... 20

• Updated pin numbers to reflect 8D package ................................................................................................... 21

English Data Sheet: SLLSFA0

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Device Comparison Table

表5-1. Device Features

MAXIMUM DATA

RATE

DEFAULT

OUTPUT

PART NUMBER

ISO7021

CHANNEL DIRECTION

PACKAGE

SOIC-8

RATED ISOLATION

3000 V_RMS/ 4242 V_PK

1 Forward,

1 Reverse

4 Mbps

High

1 Forward,

1 Reverse

ISO7021 with F suffix

Low

SOIC-8

5 Pin Configuration and Functions

Pin Functions

VCC1

OUTA

INB

VCC2

INA

OUTB

GND2

GND1

Not to scale

图5-1. D Package 8-Pin SOIC Top View

I/O

DESCRIPTION

NAME

GND1

GND2

INA

NO.

Ground connection for V_CC1

Ground connection for V_CC2

Input, channel A

—

INB

Input, channel B

OUTA

OUTB

V_CC1

Output, channel A

Output, channel B

Power supply, side 1

Power supply, side 2

—

V_CC2

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)^{(1) (2) (3)}

MIN

-0.5

-15

MAX

UNIT

V_CC1to GND1

Supply Voltage

V_CC2to GND2

INx to GNDx

V_CCX+ 0.5

Input/Output

Voltage

OUTx to GNDx

Output Current

Temperature

°C

Operating junction temperature, T_J

Storage temperature, T_stg

150

-65

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak

voltage values

(3) Maximum voltage must not exceed 6 V.

6.2 ESD Ratings

(1) (2)

VALUE

UNIT

Human body model (HBM), per ANSI/

ESDA/JEDEC JS-001, all pins⁽¹⁾

±6000

Charged device model (CDM), per

JEDEC specification JESD22-C101, all

pins⁽²⁾

V_(ESD)

Electrostatic discharge

±1500

±8000

Contact discharge per IEC 61000-4-2;

Isolation barrier withstand test^{(3) (4)}

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

(3) IEC ESD strike is applied across the barrier with all pins on each side tied together creating a two-terminal device.

(4) Testing is carried out in air or oil to determine the intrinsic contact discharge capability of the device.

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

1.89

UNIT

(1)

V_CC1

V_CC2

V_IH

Supply Voltage Side 1

Supply Voltage Side 2

High level Input voltage

Low level Input voltage

V_CCO⁽²⁾= 1.8 V

1.71

(1)

V_CCO= 2.5 V to 5 V

V_CCO= 1.8 V

2.25

5.5

1.71

1.89

V_CCO= 2.5 V to 5 V

2.25

5.5

0.7 x V_CCI

V_CCI

V_IL

-4

-2

-1

0.3 x V_CCI

V_CCO= 5 V

Mbps

°C

V_CCO= 3.3 V

V_CCO= 2.5 V

V_CCO= 1.8 V

V_CCO= 5 V

I_OH

High level output current

Low level output current

V_CCO= 3.3 V

V_CCO= 2.5 V

V_CCO= 1.8 V

I_OL

T_A

Data Rate

Ambient temperature

-55

125

(1) V_CC1and V_CC2can be set independent of one another

(2) V_CCI= Input-side V_CC; V_CCO= Output-side V_CC

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UNIT

ZHCSK04B –JULY 2019 –REVISED AUGUST 2020

6.4 Thermal Information

ISO7021

D (SOIC)

8 PINS

94.3

THERMAL METRIC⁽¹⁾

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

28.6

43.6

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

2.3

ψ_JT

42.9

ψ_JB

R_θJC(bot)

—

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Power Ratings

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

8.4

UNIT

P_D

Maximum power dissipation (both sides)

Maximum power dissipation (side-1)

Maximum power dissipation (side-2)

V_CC1= V_CC2= 5.5 V, T_J= 150°C, C_L= 15

pF, Input a 2-MHz 50% duty cycle square

wave

P_D1

P_D2

4.2

English Data Sheet: SLLSFA0

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6.6 Insulation Specifications

SPECIFIC

ATIONS

PARAMETER

TEST CONDITIONS

UNIT

8-D

IEC 60664-1

CLR

CPG

DTI

External clearance⁽¹⁾

Side 1 to side 2 distance through air

Side 1 to side 2 distance across package surface

Minimum internal gap (internal clearance)

IEC 60112; UL 746A

µm

External creepage⁽¹⁾

Distance through the insulation

Comparative tracking index

Material Group

>17

>600

CTI

According to IEC 60664-1

I-IV

I-III

Rated mains voltage ≤150 V_RMS

Rated mains voltage ≤300 V_RMS

Overvoltage category

DIN V VDE V 0884-11:2017-01

V_IORMMaximum repetitive peak isolation voltage

AC voltage (bipolar)

566

400

566

4242

V_PK

V_RMS

V_DC

AC voltage (sine wave); time-dependent dielectric

breakdown (TDDB) test;

V_IOWM

Maximum isolation working voltage

DC voltage

V_TEST= V_IOTM, t = 60 s (qualification); V_TEST

1.2 × V_IOTM, t = 1 s (100% production)

V_IOTM

Maximum transient isolation voltage

Maximum surge isolation voltage⁽²⁾

V_PK

Test method per IEC 62368-1, 1.2/50 µs

waveform, V_TEST= 1.6 × V_IOSM= TBD V_PK

(qualification)

V_IOSM

4000

≤5

V_PK

Method a: After I/O safety test subgroup 2/3, V_ini

= V_IOTM, t_ini= 60 s; V_pd(m)= 1.2 × V_IORM, t_m= 10

Method a: After environmental tests subgroup 1,

V_ini= V_IOTM, t_ini= 60 s;

V_pd(m)= 1.6 × V_IORM, t_m= 10 s

q_pd

Apparent charge⁽³⁾

Method b1: At routine test (100% production) and

preconditioning (type test), V_ini= V_IOTM, t_ini= 1 s;

V_pd(m)= 1.875 × V_IORM, t_m= 1 s

C_IO

R_IO

Barrier capacitance, input to output⁽⁴⁾

Insulation resistance, input to output⁽⁴⁾

V_IO= 0.4 × sin (2 πft), f = 1 MHz

V_IO= 500 V, T_A= 25°C

> 10¹²

> 10¹¹

> 10⁹

V_IO= 500 V, 100°C ≤T_A≤150°C

V_IO= 500 V at T_S= 150°C

Pollution degree

Climatic category

55/125/

UL 1577

V_TEST= V_ISO, t = 60 s (qualification); V_TEST= 1.2

× V_ISO, t = 1 s (100% production)

V_ISO

Withstand isolation voltage

3000

V_RMS

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application.

Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the

isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in

certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these

specifications.

(2) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.

(3) Apparent charge is electrical discharge caused by a partial discharge (pd).

(4) All pins on each side of the barrier tied together creating a two-pin device.

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6.7 Safety-Related Certifications

VDE

CSA

CQC

TUV

IECEx / ATEX

Plan to certify

according to DIN V

VDE V 0884-11:2017-

Plan to certify

according to UL 1577

Component

Certified for use in

intrinsic safety (IS) to

IS applications under

ATEX and IECEx.

Certified according to

IEC 60950-1 and IEC

62368-1

Plan to certify

according to

GB4943.1-2011

according to EN

61010-1:2010 (3rd

Ed) and EN 60950-

1:2006/A2:2013

Recognition Program

3000 V_RMSinsulation

per CSA

ATEX: EN

IEC60079-0:2018 and

EN 60079-11:2012

IECEx:IEC

60079-0:2017 (7th

Ed) and

IEC60079-11:2011

(6th Ed)

Markings: II 1G Ex ia

IIC Ga

Maximum transient

isolation voltage,

60950-1-07+A1+A2,

IEC 60950-1 2nd

Ed.+A1+A2, CSA

62368-1- 14 and IEC

62368-1:2014 370

V_RMS(DBQ-16)

maximum working

voltage (pollution

degree 2, material

group I)

3000 V_RMSinsulation

per EN 61010-1:2010

(3rd Ed) up to working

voltage of 300 V_RMS

3000 V_RMSinsulation

per EN 60950-

1:2006/A2:2013 up to

working voltage of

370 V_RMS

Basic insulation,

Altitude ≤5000 m,

Tropical Climate,

250 V_RMSmaximum

working voltage

4242 V_PK

;

Maximum repetitive

peak isolation

Single protection,

3000 V_RMS

voltage, 566 V_PK

Maximum surge

;

isolation voltage,

4000 V_PK

See the 节9.1.2

IECEx certificate:

IECEx CSA 20.012U

ATEX certificate:

CSANe

Certificate planned

20ATEX2090U

6.8 Safety Limiting Values

Safety limiting⁽¹⁾intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

D-8 PACKAGE

_θJA= 94.3°C/W, V_I= 5.5 V, T_J= 150°C,

241

368

482

701

T_A= 25°C

_θJA= 94.3°C/W, V_I= 3.6 V, T_J= 150°C,

T_A= 25°C

_θJA= 94.3°C/W, V_I= 2.75 V, T_J=

150°C, T_A= 25°C

_θJA= 94.3°C/W, V_I= 1.89 V, T_J=

150°C, T_A= 25°C

_θJA= 94.3°C/W, T_J= 150°C, T_A= 25°C

I_S

Safety input, output, or supply current

P_S

T_S

Safety input, output, or total power

Maximum safety temperature

1325

150

°C

(1) The maximum safety temperature, T_S, has the same value as the maximum junction temperature, T_J, specified for the device. The I_S

and P_Sparameters represent the safety current and safety power respectively. The maximum limits of I_Sand P_Sshould not be

exceeded. These limits vary with the ambient temperature, T_A.

The junction-to-air thermal resistance, R_θJA, in the table is that of a device installed on a high-K test board for leaded surface-mount

packages. Use these equations to calculate the value for each parameter:

T_J= T_A+ R_θJA× P, where P is the power dissipated in the device.

T_J(max)= T_S= T_A+ R_θJA× P_S, where T_J(max)is the maximum allowed junction temperature.

P_S= I_S× V_I, where V_Iis the maximum input voltage.

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6.9 Electrical Characteristics 5V Supply

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

(1)

V_IT+(IN)

V_IT-(IN)

V_OH

Rising input switching threshold

Falling input switching threshold

High-level output voltage

Low-level output voltage

0.7 x V_CCI

0.3 x V_CCI

V_CCO- 0.4

I_OH= -4 mA

I_OL= 4 mA

V_OL

0.4

V_I(HYS)

I_IH

Input threshold voltage hysteresis

High-level input current

0.1 x V_CCI

V_IH= V_CCI⁽¹⁾at INx

µA

kV/us

I_IL

Low-level input current

V_IL= 0 V at INx

-1

CMTI

Common mode transient immunity

V_I= V_CCor 0 V, V_CM= 1200 V

100

V_I= V_CC/ 2 + 0.4×sin(2πft), f =

2 MHz, V_CC= 5 V

C_i

Input Capacitance ⁽²⁾

(1) V_CCI= Input-side V_CC; V_CCO= Output-side V_CC

(2) Measured from input pin to same side ground.

6.10 Supply Current Characteristics 5V Supply

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

SUPPLY CURRENT

MIN

TYP

MAX

UNIT

ISO7021

I_CC1

I_CC2

I_CC1

I_CC2

I_CC1

I_CC2

I_CC1

I_CC2

I_CC1

I_CC2

5.9

11.8

µA

V_I= V_CC1(ISO7021); V_I= 0 V (ISO7021

with F suffix)

Supply current - DC

signal

6.5

11.9

V_I= 0 V (ISO7021); V_I= V_CC1(ISO7021

with F suffix)

6.5

11.9

7.2

12.2

27.7

175.0

10 kbps, No Load

100 kbps, No Load

1 Mbps, No Load

7.2

15.9

129.0

Supply current - AC

signal

V_I= V_CC1(ISO7021); V_I= 0 V (ISO7021

with F suffix)

I_CC1(ch)+ I_CC2(ch)

5.9

6.5

11.4

11.8

µA

V_I= 0 V (ISO7021); V_I= V_CC1(ISO7021

with F suffix)

Total Supply Current

Per Channel

10 kbps, No Load

100 kbps, No Load

1 Mbps, No Load

I_CC1(ch)+ I_CC2(ch)

7.2

15.9

12.2

27.8

µA

129.0

175.0

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6.11 Electrical Characteristics 3.3V Supply

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

(1)

V_IT+(IN)

V_IT-(IN)

V_OH

Rising input switching threshold

Falling input switching threshold

High-level output voltage

Low-level output voltage

0.7 x V_CCI

0.3 x V_CCI

V_CCO- 0.3

I_OH= -2mA

V_OL

I_OL= 2mA

0.3

Input threshold voltage

hysteresis

V_I(HYS)

0.1 x V_CCI

I_IH

I_IL

High-level input current

Low-level input current

V_IH= V_CCI⁽¹⁾at INx

V_IL= 0 V at INx

µA

-1

Common mode transient

immunity

CMTI

C_i

V_I= V_CCor 0 V, V_CM= 1200 V

100

kV/us

V_I= V_CC/ 2 + 0.4×sin(2πft), f =

2 MHz, V_CC= 3.3 V

Input Capacitance⁽²⁾

(1) V_CCI= Input-side V_CC; V_CCO= Output-side V_CC

(2) Measured from input pin to same side ground.

6.12 Supply Current Characteristics 3.3V Supply

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

SUPPLY CURRENT

MIN

TYP

MAX

UNIT

ISO7021

I_CC1

I_CC2

I_CC1

I_CC2

I_CC1

I_CC2

I_CC1

I_CC2

I_CC1

I_CC2

4.8

7.8

µA

V_I= V_CC1(ISO7021); V_I= 0 V (ISO7021

with F suffix)

Supply current - DC

signal

5.2

8.4

V_I= 0 V (ISO7021); V_I= V_CC1(ISO7021

with F suffix)

5.2

8.4

5.7

8.8

10 kbps, No Load

100 kbps, No Load

1 Mbps, No Load

5.7

8.8

15.0

120.0

23.0

153.0

155.0

Supply current - AC

signal

V_I= V_CC1(ISO7021); V_I= 0 V (ISO7021

with F suffix)

I_CC1(ch)+ I_CC2(ch)

4.8

5.2

7.8

8.4

µA

V_I= 0 V (ISO7021); V_I= V_CC1(ISO7021

with F suffix)

Total Supply Current

Per Channel

10 kbps, No Load

100 kbps, No Load

1 Mbps, No Load

I_CC1(ch)+ I_CC2(ch)

5.7

15.0

8.8

23.0

µA

120.0

153.0

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6.13 Electrical Characteristics 2.5V Supply

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

(1)

V_IT+(IN)

V_IT-(IN)

V_OH

Rising input switching threshold

Falling input switching threshold

High-level output voltage

Low-level output voltage

0.7 x V_CCI

0.3 x V_CCI

V_CCO- 0.2

I_OH= -1mA

V_OL

I_OL= 1mA

0.2

Input threshold voltage

hysteresis

V_I(HYS)

0.1 x V_CCI

I_IH

I_IL

High-level input current

Low-level input current

V_IH= V_CCI⁽¹⁾at INx

V_IL= 0 V at INx

µA

-1

Common mode transient

immunity

CMTI

C_i

V_I= V_CCor 0 V, V_CM= 1200 V

100

kV/us

V_I= V_CC/ 2 + 0.4×sin(2πft), f =

2 MHz, V_CC= 2.5 V

Input Capacitance⁽²⁾

(1) V_CCI= Input-side V_CC; V_CCO= Output-side V_CC

(2) Measured from input pin to same side ground.

6.14 Supply Current Characteristics 2.5V Supply

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

SUPPLY CURRENT

MIN

TYP

MAX

UNIT

ISO7021

I_CC1

I_CC2

I_CC1

I_CC2

I_CC1

I_CC2

I_CC1

I_CC2

I_CC1

I_CC2

4.4

4.3

6.9

µA

V_I= V_CC1(ISO7021); V_I= 0 V (ISO7021

with F suffix)

Supply current - DC

signal

4.8

7.4

V_I= 0 V (ISO7021); V_I= V_CC1(ISO7021

with F suffix)

4.8

7.4

5.0

7.8

10 kbps, No Load

100 kbps, No Load

1 Mbps, No Load

5.0

7.8

12.4

112.0

113.0

21.2

144.0

Supply current - AC

signal

V_I= V_CC1(ISO7021); V_I= 0 V (ISO7021

with F suffix)

I_CC1(ch)+ I_CC2(ch)

4.4

4.8

6.9

7.4

µA

V_I= 0 V (ISO7021); V_I= V_CC1(ISO7021

with F suffix)

Total Supply Current

Per Channel

10 kbps, No Load

100 kbps, No Load

1 Mbps, No Load

I_CC1(ch)+ I_CC2(ch)

5.0

12.4

7.8

21.2

µA

113.0

144.0

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6.15 Electrical Characteristics 1.8V Supply

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

(1)

V_IT+(IN)

V_IT-(IN)

V_OH

Rising input switching threshold

Falling input switching threshold

High-level output voltage

Low-level output voltage

0.7 x V_CCI

0.3 x V_CCI

V_CCO- 0.2

I_OH= -1mA

I_OL= 1mA

V_OL

0.2

V_I(HYS)

I_IH

Input threshold voltage hysteresis

High-level input current

0.1 x V_CCI

V_IH= V_CCI⁽¹⁾at INx

µA

kV/us

I_IL

Low-level input current

V_IL= 0 V at INx

-1

CMTI

Common mode transient immunity

V_I= V_CCor 0 V, V_CM= 1200 V

100

V_I= V_CC/ 2 + 0.4×sin(2πft), f =

2 MHz, V_CC= 1.8 V

C_i

Input Capacitance⁽²⁾

(1) V_CCI= Input-side V_CC; V_CCO= Output-side V_CC

(2) Measured from input pin to same side ground.

6.16 Supply Current Characteristics 1.8V Supply

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

SUPPLY CURRENT

MIN

TYP

MAX

UNIT

ISO7021

I_CC1

I_CC2

I_CC1

I_CC2

I_CC1

I_CC2

I_CC1

I_CC2

I_CC1

I_CC2

3.4

5.7

µA

V_I= V_CC1(ISO7021); V_I= 0 V (ISO7021

with F suffix)

Supply current - DC

signal

3.8

6.2

V_I= 0 V (ISO7021); V_I= V_CC1(ISO7021

with F suffix)

3.8

6.2

4.1

6.7

10 kbps, No Load

100 kbps, No Load

1 Mbps, No Load

4.1

6.7

9.9

19.3

134.0

Supply current - AC

signal

9.9

90.0

V_I= V_CC1(ISO7021); V_I= 0 V (ISO7021

with F suffix)

I_CC1(ch)+ I_CC2(ch)

3.4

3.8

5.7

6.2

µA

V_I= 0 V (ISO7021); V_I= V_CC1(ISO7021

with F suffix)

Total Supply Current

Per Channel

10 kbps, No Load

100 kbps, No Load

1 Mbps, No Load

I_CC1(ch)+ I_CC2(ch)

3.9

9.9

6.7

19.3

µA

90.0

134.0

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6.17 Switching Characteristics

V_CC1, V_CC2= 1.71 V to 1.89 V or 2.25 V to 5.5 V (over recommended operating conditions unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

140

MAX

UNIT

t_PLH, t_PHL

t_P(dft)

Propagation delay time

Propagation delay drift

Minimum pulse width

165

See 图7-1

ps/℃

t_UI

250

See 图7-1

PWD

t_sk(o)

Pulse width distortion

Channel to channel output skew time

Part to part skew time

t_sk(p-p)

V_CC= 1.71 V to 1.9 V, See 图7-1

V_CC= 2.25 V to 5.5 V, See 图7-1

V_CC= 1.71 V to 1.9 V, See 图7-1

V_CC= 2.25 V to 5.5 V, See 图7-1

t_r

Output signal rise time

Output signal fall time

t_f

Default output delay time from input

power loss

t_DO

400

750

See 图7-2

t_PU

F_R

Time from UVLO to valid output data

Refresh rate

kbps

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7 Parameter Measurement Information

CCI

50%

OUT

0 V

PHL

PLH

Input

Generator

(See Note A)

See Note B

90%

10%

50%

A. The input pulse is supplied by a generator having the following characteristics: PRR ≤50 kHz, 50% duty cycle, t_r≤3 ns, t_f≤3ns, Z_O

= 50 Ω. At the input, 50 Ωresistor is required to terminate Input Generator signal. It is not needed in actual application.

B. C_L= 15 pF and includes instrumentation and fixture capacitance within ±20%.

图7-1. Switching Characteristics Test Circuit and Voltage Waveforms

1.7 V

0 V

default high

OUT

IN = 0 V (Devices without suffix F)

IN = V (Devices with suffix F)

50%

See Note A

default low

A. C_L= 15 pF and includes instrumentation and fixture capacitance within ±20%.

B. Power Supply Ramp Rate = 10 mV/ns

图7-2. Default Output Delay Time Test Circuit and Voltage Waveforms

CCO

CCI

C = 0.1 µF 1%

Pass-fail criteria:

The output must

remain stable.

OUT

or V

See Note A

GNDI

GNDO

A. C_L= 15 pF and includes instrumentation and fixture capacitance within ±20%.

图7-3. Common-Mode Transient Immunity Test Circuit

English Data Sheet: SLLSFA0

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8 Detailed Description

8.1 Overview

The ISO7021 device uses edge encoding of data with an ON-OFF keying (OOK) modulation scheme to transmit

the digital data across a silicon dioxide isolation barrier. The transmitter uses a high frequency carrier signal to

pass data across the barrier representing a signal edge transition. Using this method achieves very low power

consumption and high immunity. The receiver demodulates the carrier signal after advanced signal conditioning

and produces the output through a buffer stage. For low data rates, a refresh logic option is available to make

sure the output state matches the input state. Advanced circuit techniques are used to maximize the CMTI

performance and minimize the radiated emissions due to the high frequency carrier and IO buffer switching. The

conceptual block diagram of a digital capacitive isolator, 图 8-2, shows a functional block diagram of a typical

channel.

8.2 Functional Block Diagram

Transmitter

Receiver

OOK

Modulation

SiO based

RX OUT

TX Signal

Conditioning

RX Signal

Conditioning

Envelope

Detection

TX IN

Edge

Encoding

Capacitive

Isolation

Barrier

Refresh

Logic

Watch Dog

Timer

Oscillator

图8-1. Conceptual Block Diagram of a Digital Capacitive Isolator

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Transmitter

Receiver

OOK

Modulation

SiO based

RX OUT

TX Signal

Conditioning

RX Signal

Conditioning

Envelope

Detection

TX IN

Edge

Encoding

Capacitive

Isolation

Barrier

Refresh

Logic

Watch Dog

Timer

Oscillator

图8-2. Conceptual Block Diagram of a Digital Capacitive Isolator

8.3 Feature Description

8.3.1 Refresh

The ISO7021 uses an edge based encoding scheme to transfer an input signal change across the isolation

barrier versus sending across the DC state. The built in refresh function consistently validates that the DC output

state of each isolator channel matches the DC input state. An internal watchdog timer monitors for activity on the

individual inputs and transmits the logic state when there is no input signal transition for more than 100 µs. This

ensures that the input and output state of the isolator always match.

8.3.2 Electromagnetic Compatibility (EMC) Considerations

Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge

(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances

are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level

performance and reliability depends, to a large extent, on the application board design and layout, the ISO70xx

family of devices incorporates many chip-level design improvements for overall system robustness. Some of

these improvements include:

• Robust ESD protection cells for input and output signal pins and inter-chip bond pads.

• Low-resistance connectivity of ESD cells to supply and ground pins.

• Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.

• Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance

path.

• PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic

SCRs.

• Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.

The device has no issue being able to meet either CISPR 22 Class A and CISPR22 Class B standards in an

unshielded environment.

English Data Sheet: SLLSFA0

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8.4 Device Functional Modes

表8-1 shows the functional modes for the device.

表8-1. Function Table

INPUT

(INx)3

OUTPUT

(OUTx)

V_CCI

V_CCO

COMMENTS

Normal Operation:

A channel output assumes the logic state of its input.

Default

The channel output assumes the selected default option.

When V_CCIis unpowered, a channel output assumes the logic state based on

the selected default option. Default is High for the device without the F suffix

and Low for device with the F suffix.

Default

When V_CCItransitions from unpowered to powered-up, a channel output

assumes the logic state of the input.

When V_CCItransitions from powered-up to unpowered, channel output

assumes the selected default state.

When V_CCOis unpowered, a channel output is undetermined and tri state2.

When V_CCOtransitions from unpowered to powered-up, a channel output

assumes the selected default option.

Undetermined

1. V_CCI= Input-side V_CC; V_CCO= Output-side V_CC; PU = Powered up (V_CC≥1.54 V); PD = Powered down

(V_CC≤1.54); X = Irrelevant; H = High level; L = Low level ; Z = High Impedance.

2. The outputs are in undetermined state when 1.54 V < V_CCI, V_CCO< 1.54 V.

3. A strongly driven input signal can weakly power the floating V_CCthrough an internal protection diode and

cause undetermined output.

8.4.1 Device I/O Schematics

Output

Input

CCO

CCI

~20 ꢀ

985 ꢀ

OUTx

INx

图8-3. Device I/O Schematics

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9 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

The ISO7021 device is an ultra-low power digital isolator. The device uses single-ended CMOS-logic switching

technology. The voltage range is from 1.71 V to 1.89 V and 2.25 V to 5.5 V for both supplies, V_CC1and V_CC2

and can be set irrespective of one another. When designing with digital isolators, keep in mind that because of

the single-ended design structure, digital isolators do not conform to any specific interface standard and are only

intended for isolating single-ended CMOS or TTL digital signal lines. The isolator is typically placed between the

data controller (that is, μC or UART), and a data converter or a line transceiver, regardless of the interface type

or standard. See Isolated power and data interface for low-power applications reference design TI Design for

detailed information on designing the ISO70xx in low-power applications.

9.1.1 Insulation Lifetime

Insulation lifetime projection data is collected by using industry-standard Time Dependent Dielectric Breakdown

(TDDB) test method. In this test, all pins on each side of the barrier are tied together creating a two-terminal

device and high voltage applied between the two sides; see 图 9-1 for TDDB test setup. The insulation

breakdown data is collected at various high voltages switching at 60 Hz over temperature. For reinforced

insulation, VDE standard requires the use of TDDB projection line with failure rate of less than 1 part per million

(ppm) and a minimum insulation lifetime of 20 years. VDE standard also requires additional safety margin of

20% for working voltage and 87.5% for insulation lifetime which translates into minimum required life time of 37.5

years.

图 9-2 shows the intrinsic capability of the isolation barrier to withstand high voltage stress over its lifetime.

Based on the TDDB data, the intrinsic capability of these devices is 400 VRMS with a lifetime of >100 years.

Other factors, such as package size, pollution degree, material group, and so forth can further limit the working

voltage of the component. The working voltage of the DBQ-16 package specified up to 400 VRMS. At the lower

working voltages, the corresponding insulation barrier life time is much longer.

Vcc 1

Vcc 2

Time Counter

> 1 mA

DUT

GND

GND 2

Oven at 150 °C

图9-1. Test Setup for Insulation Lifetime Measurement

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图9-2. Insulation Lifetime Projection Data

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9.1.2 Intrinsic Safety

The ISO7021 supports Intrinsically Safe (IS) to IS applications and carry IECEx and ATEX certifications. These

devices do not currently support IS to non-IS galvanic isolation applications due to the minimum insulation

thickness requirements of IEC 60079-11.

9.1.2.1 Schedule of Limitations

These components are certified to comply with IEC 60079-0, Edition 7, IEC 60079-11, Edition 6, EN

IEC60079-0:2018 and EN 60070-11:2012. When one of these components is used in an equipment, the

component is to be soldered on a PCB inside a suitable enclosure and re-evaluated as an equipment. The

operating temperature range of these components is -55°C to +85°C. The creepage and clearance distances

across the isolating component have been evaluated, but the distance to other circuitry remain the responsibility

of the user of the final equipment.

This assembly is an isolating component between separate intrinsically safe circuits. The assembly must be

connected to suitably certified intrinsically safe circuits considering the entity parameters and temperature ratings

in the application scenario shown in 表9-1

表9-1. Entity Parameters and Temperature Ratings

ENTITY PARAMETERS

SIDE 1

ENTITY PARAMETERS

SIDE 2

AMBIENT TEMPERATURE

RANGE

MAXIMUM COMPONENT

TEMPERATURE

APPLICATION

Ui = 50 V

Ii = 300 mA

Pi = 1.3 W

Li = 0 H

Ui = 50 V

Ii = 300 mA

Pi = 1.3 W

Li = 0 H

IS to IS: Case 1

-55°C to +85°C

183°C

Ci = 4 pF

9.2 Typical Application

图9-3 shows the isolated UART.

Isolation Barrier

VCC1

VCC2

0.1 …F

0.1 ꢀF

1 MΩ

1 kΩ

10 nF

100 nF

10 nF

V_CC1

V_CC2

DVDD AVDD

ADS122U04

AVCC

DVCC

AIN0

AIN1

AIN2

AIN3

OUTA

INA

UCA0RXD

MSP430FR2355

Thermocouple

ISO7021

INB

OUTB

UCA0TXD

DVSS

1 MΩ

DGND

AVSS

GND1

GND2

图9-3. Isolated UART for a Temperature Field Transmitter

English Data Sheet: SLLSFA0

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9.2.1 Design Requirements

To design with these devices, use the parameters listed in 表9-2.

表9-2. Design Parameters

PARAMETER

VALUE

Supply voltage, V_CC1and V_CC2

1.71 V to 1.89 V or 2.25 V to 5.5 V

Decoupling capacitor between V_CC1and GND1

Decoupling capacitor from V_CC2and GND2

0.1 µF

9.2.2 Detailed Design Procedure

Unlike optocouplers, which require external components to improve performance, provide bias, or limit current,

the device only require two external bypass capacitors to operate.

2 mm maximum

from V_CC2

2 mm maximum

from V_CC1

V_CC2

V_CC1

GND1

GND2

0.1 µF

INA

OUTA

INB

OUTB

GND2

GND1

图9-4. Typical ISO7021 Circuit Hook-up

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9.2.3 Application Curves

The following typical eye diagrams of the device indicates wide open eye at the maximum data rate of 4 Mbps.

图9-5. Eye Diagram at 4 Mbps PRBS 2¹⁶–1, 1.8 V and 25°C

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图9-6. Eye Diagram at 4 Mbps PRBS 2¹⁶–1, 5 V and 25°C

10 Power Supply Recommendations

Put a 0.1-μF bypass capacitor at the input and output supply pins (V_CC1and V_CC2) to make sure that operation

is reliable at data rates and supply voltage. Put the capacitors as near to the supply pins as possible. If only one

primary-side power supply is available in an application, use a transformer driver to help generate the isolated

power for the secondary-side. Texas Instruments recommends the SN6501 device or SN6505A device. Refer to

the SN6501 Transformer Driver for Isolated Power Supplies data sheet or SN6505 Low-Noise 1-A Transformer

Drivers for Isolated Power Supplies data sheet for detailed power supply design and transformer selection

recommendations.

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11 Layout

11.1 Layout Guidelines

A minimum of four layers is required to accomplish a low EMI PCB design (see 图 11-1). Layer stacking should

be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency

signal layer.

• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their

inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits

of the data link.

• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for

transmission line interconnects and provides an excellent low-inductance path for the return current flow.

• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of

approximately 100 pF/in².

• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links

usually have margin to tolerate discontinuities such as vias.

If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to

the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also

the power and ground plane of each power system can be placed closer together, thus increasing the high-

frequency bypass capacitance significantly.

Refer to the Digital Isolator Design Guide for detailed layout recommendations,.

11.1.1 PCB Material

For digital circuit boards operating at less than 150 Mbps, (or rise and fall times greater than 1 ns), and trace

lengths of up to 10 inches, use standard FR-4 UL94V-0 printed circuit board. This PCB is preferred over cheaper

alternatives because of lower dielectric losses at high frequencies, less moisture absorption, greater strength

and stiffness, and the self-extinguishing flammability-characteristics.

11.2 Layout Example

High-speed traces

10 mils

Ground plane

Keep this space

FR-4

free from planes,

traces, pads, and

vias

40 mils

0_r~ 4.5

Power plane

10 mils

Low-speed traces

图11-1. Recommended Layer Stack

English Data Sheet: SLLSFA0

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

• Texas Instruments, Digital Isolator Design Guide

• Texas Instruments, Isolation Glossary

• Texas Instruments, ADS1220 4-Channel, 2-kSPS, Low-Power, 24-Bit ADC with Integrated PGA and

Reference data sheet

• Texas Instruments, ADS122U04 24-Bit, 4-Channel, 2-kSPS, Delta-Sigma ADC With UART Interface data

sheet

• Texas Instruments, ADS124S0x Low-Power, Low-Noise, Highly Integrated, 6- and 12-Channel, 4-kSPS, 24-

Bit, Delta-Sigma ADC with PGA and Voltage Reference data sheet

• Texas Instruments, Uniquely Efficient Isolated DC/DC Converter for Ultra-Low Power and Low-Power

Applications TI Design

• Texas Instruments, SN6501 Transformer Driver for Isolated Power Supplies data sheet

• Texas Instruments, SN6505A Low-Noise 1-A Transformer Drivers for Isolated Power Supplies data sheet

• Texas Instruments, Isolated power and data interface for low-power applications reference design TI Design

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.3 支持资源

TI E2E^™中文支持论坛是工程师的重要参考资料，可直接从专家处获得快速、经过验证的解答和设计帮助。搜索

现有解答或提出自己的问题，获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的使用条款。

12.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

12.5 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

12.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Submit Document Feedback

Product Folder Links: ISO7021

English Data Sheet: SLLSFA0

PACKAGE OPTION ADDENDUM

www.ti.com

9-May-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

ISO7021D

ISO7021DR

ISO7021FD

ISO7021FDR

ACTIVE

SOIC

RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-55 to 125

7021

Samples

2500 RoHS & Green

75 RoHS & Green

2500 RoHS & Green

NIPDAU

7021F

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

9-May-2023

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

9-May-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

ISO7021DR

SOIC

2500

330.0

12.4

6.4

5.2

2.1

8.0

12.0

ISO7021FDR

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

9-May-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

ISO7021DR

SOIC

2500

350.0

367.0

350.0

367.0

43.0

38.0

ISO7021FDR

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

9-May-2023

TUBE

T - Tube

height

L - Tube length

W - Tube

width

B - Alignment groove width

*All dimensions are nominal

Device

Package Name Package Type

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

ISO7021D

SOIC

505.46

6.76

3810

ISO7021FD

Pack Materials-Page 3

PACKAGE OUTLINE

D0008A

SOIC - 1.75 mm max height

SCALE 2.800

SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE

.228-.244 TYP

[5.80-6.19]

.004 [0.1] C

PIN 1 ID AREA

6X .050

[1.27]

.189-.197

[4.81-5.00]

NOTE 3

.150

[3.81]

4X (0 -15 )

8X .012-.020

[0.31-0.51]

.150-.157

[3.81-3.98]

NOTE 4

.069 MAX

[1.75]

.010 [0.25]

C A B

.005-.010 TYP

[0.13-0.25]

4X (0 -15 )

SEE DETAIL A

.010

[0.25]

.004-.010

[0.11-0.25]

0 - 8

.016-.050

[0.41-1.27]

DETAIL A

TYPICAL

(.041)

[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

www.ti.com

EXAMPLE BOARD LAYOUT

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

SEE

DETAILS

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

6X (.050 )

[1.27]

(.213)

[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED

METAL

EXPOSED

METAL

.0028 MAX

[0.07]

.0028 MIN

[0.07]

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

D0008A

SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )

[1.55]

SYMM

8X (.024)

[0.6]

SYMM

(R.002 ) TYP

[0.05]

6X (.050 )

[1.27]

(.213)

[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

ISO7021 [TI]

相关型号：

ISO7021D

ISO7021DR

ISO7021FD

ISO7021FDR

ISO7041

ISO7041-Q1

ISO7041DBQ

ISO7041DBQR

ISO7041FDBQ

ISO7041FDBQR

ISO7041FQDBQRQ1

ISO7041QDBQRQ1