ISO721DUBR [TI]
3.3-V / 5-V HIGH-SPEED DIGITAL ISOLATORS; 3.3 V / 5 V高速数字隔离器
| 型号： | ISO721DUBR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V / 5-V HIGH-SPEED DIGITAL ISOLATORS |
| 文件： | 总29页 (文件大小：677K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISO721, ISO721M
ISO722, ISO722M
www.ti.com
SLLS629J –JANUARY 2006–REVISED JULY 2010
3.3-V / 5-V HIGH-SPEED DIGITAL ISOLATORS
Check for Samples: ISO721, ISO721M, ISO722, ISO722M
1
FEATURES
DESCRIPTION
23
•
4000-V(peak) Isolation, 560-Vpeak VIORM
–
UL 1577, IEC 60747-5-2 (VDE 0884, Rev. 2)
IEC 61010-1, IEC 60950-1 and CSA
Approved
The ISO721, ISO721M, ISO722, and ISO722M are
digital isolators with a logic input and output buffer
separated by a silicon dioxide (SiO2) insulation
barrier. This barrier provides galvanic isolation of up
to 4000 V. Used in conjunction with isolated power
supplies, these devices prevent noise currents on a
data bus or other circuits from entering the local
ground, and interfering with or damaging sensitive
circuitry.
–
50 kV/µs Transient Immunity, Typical
•
Signaling Rate 0 Mbps to 150 Mbps
–
–
Low Propagation Delay
Low Pulse Skew (Pulse-Width Distortion)
•
•
•
•
•
Low-Power Sleep Mode
High Electromagnetic Immunity
Low Input-Current Requirement
Failsafe Output
A binary input signal is conditioned, translated to a
balanced signal, then differentiated by the capacitive
isolation barrier. Across the isolation barrier,
a
differential comparator receives the logic transition
information, then sets or resets a flip-flop and the
output circuit accordingly. A periodic update pulse is
sent across the barrier to ensure the proper dc level
of the output. If this dc-refresh pulse is not received
for more than 4 ms, the input is assumed to be
unpowered or not being actively driven, and the
failsafe circuit drives the output to a logic-high state.
Drop-In Replacement for Most Opto and
Magnetic Isolators
APPLICATIONS
•
Industrial Fieldbus
–
–
–
–
Modbus
Profibus
DeviceNet™ Data Buses
Smart Distributed Systems ( SDS™)
•
•
•
Computer Peripheral Interface
Servo Control Interface
Data Acquisition
FUNCTION DIAGRAM
Isolation Barrier
DC Channel
+
_
Filter
Pulse Width
Demodulation
OSC
+
PWM
V
ref
_
+
Carrier Detect
POR
POR
BIAS
ISO722
Only
+
_
Data MUX
AC Detect
3-State
EN
Input
+
Filter
IN
V
ref
_
+
OUT
Output Buffer
AC Channel
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
SDS is a trademark of Honeywell.
DeviceNet is a trademark of Open Devicenet Vendors Association, Inc.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2010, Texas Instruments Incorporated
ISO721, ISO721M
ISO722, ISO722M
SLLS629J –JANUARY 2006–REVISED JULY 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
The symmetry of the dielectric and capacitor within the integrated circuitry provides for close capacitive matching,
and allows fast transient voltage changes between the input and output grounds without corrupting the output.
The small capacitance and resulting time constant provide for fast operation with signaling rates(1) from 0 Mbps
(dc) to 100 Mbps for the ISO721/ISO722, and 0 Mbps to 150 Mbps with the ISO721M/ISO722M.
These devices require two supply voltages of 3.3-V, 5-V, or any combination. All inputs are 5-V tolerant when
supplied from a 3.3-V supply and all outputs are 4-mA CMOS.
The ISO722 and ISO722M devices include an active-low output enable that when driven to a high logic level,
places the output in a high-impedance state and turns off internal bias circuitry to conserve power.
Both the ISO721 and ISO722 have TTL input thresholds and a noise filter at the input that prevent transient
pulses of up to 2 ns in duration from being passed to the output of the device.
The ISO721M and ISO722M have CMOS VCC/2 input thresholds, but do not have the noise-filter and the
additional propagation delay. These features of the ISO721M also provide for reduced-jitter operation.
The ISO721, ISO721M, ISO722, and ISO722M are characterized for operation over the ambient temperature
range of –40°C to 125°C.
(1) The signaling rate of a line is the number of voltage transitions that are made per second expressed in
the units bps (bits per second).
ISO721, ISO721M
D Package
(Top View)
ISO722, ISO722M
D Package
(Top View)
ISO721
DUB Package
(Top View)
VCC1
VCC2
VCC1
VCC2
VCC1
IN
VCC2
8
7
6
5
8
7
6
5
1
2
8
7
1
2
3
4
1
2
3
4
GND2
IN
VCC1
GND2
OUT
IN
VCC1
EN
VCC1
GND1
3
4
6
5
OUT
OUT
GND2
GND1
GND2
GND1
GND2
P0106-01
P0066-09
P0066-10
AVAILABLE OPTIONS
OUTPUT
ENABLED
INPUT
THRESHOLDS
NOISE
FILTER
MARKED
AS
PRODUCT
PACKAGE(1)
ORDERING NUMBER
ISO721D (rail)
ISO721DR (reel)
ISO721DUB (rail)
ISO721DUBR (reel)
ISO721MD (rail)
ISO721MDR (reel)
ISO722D (rail)
D-8
DUB-8
D-8
ISO721
NO
TTL
YES
ISO721
ISO721M
ISO722
NO
YES
YES
CMOS
TTL
NO
YES
NO
IS721M
ISO722
IS722M
D-8
ISO722DR (reel)
ISO722MD (rail)
ISO722MDR (reel)
ISO722M
CMOS
D-8
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
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Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): ISO721 ISO721M ISO722 ISO722M
ISO721, ISO721M
ISO722, ISO722M
www.ti.com
SLLS629J –JANUARY 2006–REVISED JULY 2010
Table 1. REGULATORY INFORMATION
VDE
CSA
UL
Approved under CSA Component
Acceptance notice: CA-5A
Recognized under 1577
Certified according to IEC 60747-5-2
File number: 40016131
Component Recognition Program(1)
File number: 1698195
File number: E181974
(1) Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577.
ABSOLUTE MAXIMUM RATINGS(1)
UNIT
VCC
VI
Supply voltage(2), VCC1, VCC2
Voltage at IN, OUT, or EN terminal
Output current
–0.5 V to 6 V
–0.5 V to 6 V
±15 mA
IO
Human-body model
Charged-device model
JEDEC Standard 22, Test Method A114-C.01
±2 kV
±1 kV
170°C
Electrostatic
discharge
ESD
TJ
All pins
JEDEC Standard 22, Test Method C101
Maximum junction temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values. Vrms
values are not listed in this publication.
RECOMMENDED OPERATING CONDITIONS
MIN TYP
MAX
5.5
4
UNIT
VCC
IOH
IOL
Supply voltage(1), VCC1, VCC2
Output current
3
V
mA
ns
V
–4
10
6.67
2
ISO72x
tui
Input pulse duration
ISO72xM
VIH
VIL
VIH
VIL
TJ
High-level input voltage (IN, EN)
Low-level input voltage (IN, EN)
High-level input voltage (IN, EN)
Low-level input voltage (IN, EN)
Junction temperature
VCC
0.8
ISO72x
0
0.7 VCC
VCC
IOS72xM
V
0
0.3 VCC
150
See the Thermal Characteristics table
°C
External magnetic field intensity per IEC 61000-4-8 and IEC 61000-4-9
certification
H
1000
A/m
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V.
Copyright © 2006–2010, Texas Instruments Incorporated
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Product Folder Link(s): ISO721 ISO721M ISO722 ISO722M
ISO721, ISO721M
ISO722, ISO722M
SLLS629J –JANUARY 2006–REVISED JULY 2010
www.ti.com
INSULATION CHARACTERISTICS(1)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SPECIFICATIONS
UNIT
VIORM
Maximum working insulation voltage
560
Vpeak
After Input/Output Safety Test Subgroup 2/3
VPR = VIORM × 1.2, t = 10 s,
Partial discharge < 5 pC
672
896
Vpeak
Vpeak
Vpeak
Method a, VPR = VIORM × 1.6,
Type and sample test with t = 10 s,
Partial discharge < 5 pC
VPR
Input to output test voltage
Method b1, VPR = VIORM × 1.875,
100% production test with t = 1 s,
Partial discharge < 5 pC
1050
VIOTM
VISO
RS
Transient overvoltage
Isolation voltage per UL
t = 60 s
4000
3535 / 2500
4242 / 3000
>109
Vpeak
Vpeak/Vrms
Ω
VTEST = VISO, t = 60 s (qualification)
VTEST = 1.2 × VISO, t = 1 s (100% production)(2)
VIO = 500 V at TS
Insulation resistance
Pollution degree
2
(1) Climatic classification 40/125/21
(2) Based on lifetime curve (see the High-Voltage Lifetime of the ISO72x Family of Digital Isolators application report, SLLA197); these
devices can withstand 4242 Vpeak / 3000 Vrms for > 10,000 s at 150oC.
4
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Product Folder Link(s): ISO721 ISO721M ISO722 ISO722M
ISO721, ISO721M
ISO722, ISO722M
www.ti.com
SLLS629J –JANUARY 2006–REVISED JULY 2010
ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 5-V(1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
Quiescent
TEST CONDITIONS
MIN
TYP
0.5
2
MAX
1
UNIT
mA
ICC1
VCC1 supply current
VI = VCC or 0 V, no load
25 Mbps
4
ISO722/722M Sleep Mode
EN at VCC
200
mA
VI = VCC or 0 V,
EN at 0 V or
No load
ICC2
VCC2 supply current
Quiescent
25 Mbps
8
12
14
ISO721/721M
VI = VCC or 0 V, no load
mA
V
10
4.6
5
IOH = -4 mA, See Figure 1
IOH = –20 mA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 mA, See Figure 1
VCC – 0.8
VCC – 0.1
VOH
High-level output voltage
Low-level output voltage
0.2
0
0.4
0.1
VOL
V
VI(HYS) Input voltage hysteresis
150
mV
mA
IIH
IIL
High-level input current
Low-level input current
EN, IN at 2 V
10
1
EN, IN at 0.8 V
–10
25
High-impedance output
current
IOZ
ISO722, ISO722M
EN, IN at VCC
mA
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6pt)
1
pF
CMTI Common-mode transient immunity
VI = VCC or 0 V, See Figure 5
50
kV/ms
(1) For 5-V operation, VCC1 and VCC2 are specified from 4.5 V to 5.5 V.
SWITCHING CHARACTERISTICS: VCC1 and VCC2 5-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
tPLH
tPHL
tsk(p)
tPLH
tPHL
tsk(p)
tsk(pp)
tr
Propagation delay, low-to-high-level output
Propagation delay, high-to-low-level output
13
13
17
17
0.5
10
10
0.5
0
24
24
2
ns
ns
ns
ns
ns
ns
ns
ISO72x
Pulse skew |tPHL – tPLH
|
EN at 0 V,
See Figure 1
Propagation delay, low-to-high-level output
Propagation delay, high-to-low-level output
8
8
16
16
1
ISO72xM
Pulse skew |tPHL – tPLH
|
(1)
Part-to-part skew
3
Output signal rise time
Output signal fall time
1
EN at 0 V,
See Figure 1
ns
tf
1
Sleep-mode propagation delay,
high-level-to-high-mpedance output
tpHZ
tpZH
tpLZ
6
3.5
5.5
4
8
4
8
5
15
8
ns
ms
ns
See Figure 2
Sleep-mode propagation delay,
high-impedance-to-high-level output
ISO722
ISO722M
Sleep-mode propagation delay,
low-level-to-high-impedance output
15
8
See Figure 3
See Figure 4
Sleep-mode propagation delay,
high-impedance-to-low-level output
tpZL
tfs
ms
ms
Failsafe output delay time from input power loss
3
2
100-Mbps NRZ data input, See Figure 6
ISO72x
Peak-to-peak eye-pattern jitter
ISO72xM
100-Mbps unrestricted bit run length data
input, See Figure 6
3
1
2
tjit(PP)
ns
150-Mbps NRZ data input, See Figure 6
150-Mbps unrestricted bit run length data
input, See Figure 6
(1) tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
Copyright © 2006–2010, Texas Instruments Incorporated
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Product Folder Link(s): ISO721 ISO721M ISO722 ISO722M
ISO721, ISO721M
ISO722, ISO722M
SLLS629J –JANUARY 2006–REVISED JULY 2010
www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V(1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
Quiescent
TEST CONDITIONS
MIN TYP
MAX UNIT
0.5
2
1
ICC1
VCC1 supply current
VCC2 supply current
VI = VCC or 0 V, no load
mA
4
25 Mbps
ISO722/722M
Sleep mode
EN at VCC
150
mA
VI = VCC or 0 V,
No load
ICC2
EN at 0 V or
Quiescent
25 Mbps
4
5
6.5
7.5
ISO721/721M
mA
VI = VCC or 0 V, no load
IOH = –4 mA, See Figure 1
IOH = –20 mA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 mA, See Figure 1
VCC – 0.4
3
3.3
0.2
0
VOH
High-level output voltage
Low-level output voltage
V
V
VCC – 0.1
0.4
0.1
VOL
VI(HYS) Input voltage hysteresis
150
mV
mA
mA
IIH
IIL
High-level input current
Low-level input current
EN, IN at 2 V
10
1
EN, IN at 0.8 V
–10
25
High-impedance output
current
IOZ
ISO722, ISO722M
EN, IN at VCC
mA
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6pt)
1
pF
CMTI Common-mode transient immunity
VI = VCC or 0 V, See Figure 5
40
kV/ms
(1) For 5-V operation, VCC1 is specified from 4.5 V to 5.5 V. For 3.3-V operation, VCC2 is specified from 3 V to 3.6 V.
SWITCHING CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
15
TYP
MAX UNIT
tPLH
tPHL
tsk(p)
tPLH
tPHL
tsk(p)
tsk(pp)
tr
Propagation delay, low-to-high-level output
Propagation delay , high-to-low-level output
19
19
0.5
12
12
0.5
0
30
30
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ISO72x
15
Pulse skew |tPHL – tPLH
|
EN at 0 V,
See Figure 1
Propagation delay, low-to-high-level output
Propagation delay, high-to-low-level output
10
10
20
20
1
ISO72xM
Pulse skew |tPHL – tPLH
|
(1)
Part-to-part skew
5
Output signal rise time
Output signal fall time
2
EN at 0 V,
See Figure 1
tf
2
Sleep-mode propagation delay,
high-level-to-high-mpedance output
tpHZ
tpZH
tpLZ
7
4.5
7
11
6
25
8
ns
ms
ns
See Figure 2
Sleep-mode propagation delay,
high-impedance-to-high-level output
ISO722
ISO722M
Sleep-mode propagation delay,
low-level-to-high-impedance output
13
6
25
8
See Figure 3
See Figure 4
Sleep-mode propagation delay,
high-impedance-to-low-level output
tpZL
tfs
4.5
ms
ms
Failsafe output delay time from input power loss
3
2
100-Mbps NRZ data input, See Figure 6
ISO72x
Peak-to-peak eye-pattern jitter
ISO72xM
100-Mbps unrestricted bit run length data
input, See Figure 6
3
1
2
tjit(PP)
ns
150-Mbps NRZ data input, See Figure 6
150-Mbps unrestricted bit run length data
input, See Figure 6
(1) tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
6
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Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): ISO721 ISO721M ISO722 ISO722M
ISO721, ISO721M
ISO722, ISO722M
www.ti.com
SLLS629J –JANUARY 2006–REVISED JULY 2010
ELECTRICAL CHARACTERISTICS: VCC1 at 3.3-V, VCC2 at 5-V(1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
Quiescent
TEST CONDITIONS
MIN TYP
MAX UNIT
0.3
1
0.5
mA
2
ICC1
VCC1 supply current
VCC2 supply current
VI = VCC or 0 V, no load
25 Mbps
ISO722/722M
Sleep mode
EN at VCC
200
mA
VI = VCC or 0 V,
No load
ICC2
EN at 0 V or
Quiescent
25 Mbps
8
12
14
ISO721/721M
mA
VI = VCC or 0 V, No load
IOH = –4 mA, See Figure 1
IOH = –20 mA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 mA, See Figure 1
10
VCC – 0.8
VCC – 0.1
4.6
5
VOH
High-level output voltage
Low-level output voltage
V
V
0.2
0
0.4
0.1
VOL
VI(HYS) Input voltage hysteresis
150
mV
mA
mA
IIH
IIL
High-level input current
Low-level input current
EN, IN at 2 V
10
1
EN, IN at 0.8 V
–10
High-impedance output
current
IOZ
ISO722, ISO722M
EN, IN at VCC
mA
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6pt)
1
pF
CMTI Common-mode transient immunity
VI = VCC or 0 V, See Figure 5
25
40
kV/ms
(1) For 5-V operation, VCC2 is specified from 4.5 V to 5.5 V. For 3.3-V operation, VCC1 is specified from 3 V to 3.6 V.
SWITCHING CHARACTERISTICS: VCC1 at 3.3-V, VCC2 at 5-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
15
TYP
MAX UNIT
tPLH
tPHL
tsk(p)
tPLH
tPHL
tsk(p)
tsk(pp)
tr
Propagation delay, low-to-high-level output
Propagation delay , high-to-low-level output
17
17
0.5
12
12
0.5
0
30
30
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ISO72x
15
Pulse skew |tPHL – tPLH
|
EN at 0 V,
See Figure 1
Propagation delay, low-to-high-level output
Propagation delay, high-to-low-level output
10
10
21
21
1
ISO72xM
Pulse skew |tPHL – tPLH
|
(1)
Part-to-part skew
5
Output signal rise time
Output signal fall time
1
EN at 0 V,
See Figure 1
tf
1
Sleep-mode propagation delay,
high-level-to-high-mpedance output
tpHZ
tpZH
tpLZ
7
4.5
7
9
5
9
5
15
8
ns
ms
ns
See Figure 2
Sleep-mode propagation delay,
high-impedance-to-high-level output
ISO722
ISO722M
Sleep-mode propagation delay,
low-level-to-high-impedance output
15
8
See Figure 3
See Figure 4
Sleep-mode propagation delay,
high-impedance-to-low-level output
tpZL
tfs
4.5
ms
ms
Failsafe output delay time from input power loss
3
2
100-Mbps NRZ data input, See Figure 6
ISO72x
Peak-to-peak eye-pattern jitter
ISO72xM
100-Mbps unrestricted bit run length data
input, See Figure 6
3
1
2
tjit(PP)
ns
150-Mbps NRZ data input, See Figure 6
150-Mbps unrestricted bit run length data
input, See Figure 6
(1) tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
Copyright © 2006–2010, Texas Instruments Incorporated
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ISO721, ISO721M
ISO722, ISO722M
SLLS629J –JANUARY 2006–REVISED JULY 2010
www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3-V(1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
Quiescent
TEST CONDITIONS
MIN
TYP
0.3
1
MAX
0.5
2
UNIT
ICC1
VCC1 supply current
VCC2 supply current
VI = VCC or 0 V, no load
mA
25 Mbps
ISO722/722M
Sleep Mode
EN at VCC
150
mA
VI = VCC or 0 V,
No load
ICC2
EN at 0 V or
Quiescent
25 Mbps
4
6.5
7.5
ISO721/721M
mA
VI = VCC or 0 V, no load
IOH = –4 mA, See Figure 1
IOH = –20 mA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 mA, See Figure 1
5
3
VCC – 0.4
VCC – 0.1
VOH
High-level output voltage
Low-level output voltage
V
V
3.3
0.2
0
0.4
0.1
VOL
VI(HYS) Input voltage hysteresis
150
mV
mA
mA
IIH
IIL
High-level input current
Low-level input current
EN, IN at 2 V
10
1
EN, IN at 0.8 V
–10
25
High-impedance output
current
IOZ
ISO722, ISO722M
EN, IN at VCC
mA
CI
Input capacitance to ground
IN at VCC, VI = 0.4 sin (4E6pt)
1
pF
CMTI Common-mode transient immunity
VI = VCC or 0 V, See Figure 5
40
kV/ms
(1) For the 3.3-V operation, VCC1 and VCC2 are specified from 3 V to 3.6 V.
SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 3.3-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
tPLH
tPHL
tsk(p)
tPLH
tPHL
tsk(p)
tsk(pp)
tr
Propagation delay, low-to-high-level output
Propagation delay , high-to-low-level output
17
17
20
20
0.5
12
12
0.5
0
34
34
3
ns
ns
ns
ns
ns
ns
ns
ISO72x
Pulse skew |tPHL – tPLH
|
EN at 0 V,
See Figure 1
Propagation delay, low-to-high-level output
Propagation delay, high-to-low-level output
10
10
25
25
1
ISO72xM
Pulse skew |tPHL – tPLH
|
(1)
Part-to-part skew
5
Output signal rise time
Output signal fall time
2
EN at 0 V,
See Figure 1
ns
tf
2
Sleep-mode propagation delay,
high-level-to-high-mpedance output
tpHZ
tpZH
tpLZ
7
5
7
5
13
6
25
8
ns
µs
ns
See Figure 2
Sleep-mode propagation delay,
high-impedance-to-high-level output
ISO722
ISO722M
Sleep-mode propagation delay,
low-level-to-high-impedance output
13
6
25
8
See Figure 3
See Figure 4
Sleep-mode propagation delay,
high-impedance-to-low-level output
tpZL
tfs
ms
ms
Failsafe output delay time from input power loss
3
2
100-Mbps NRZ data input, See Figure 6
ISO72x
Peak-to-peak eye-pattern jitter
ISO72xM
100-Mbps unrestricted bit run length data
input, See Figure 6
3
1
2
tjit(PP)
ns
150-Mbps NRZ data input, See Figure 6
150-Mbps unrestricted bit run length data
input, See Figure 6
(1) tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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PARAMETER MEASUREMENT INFORMATION
V
CC1
V
/2
V
/2
CC1
I
OUT
V
CC1
O
I
IN
0 V
t
t
+
Input
PHL
V
PLH
+
C
Generator
OH
OL
V
L
Note B
V
ISO722
and
ISO722M
90%
10%
O
I
50 W
50%
50%
V
-
EN
-
O
NOTE A
V
t
t
f
r
Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms
V
O
V
CC2
IN
V
OUT
C
I
V
/2
3 V
V
/2
CC2
CC2
0 V
V
EN
t
R
= 1 kW ±1 %
PZH
L
L
OH
NOTE B
+
50%
Input
Generator
NOTE A
0.5 V
V
O
V
I
50 W
0 V
t
PHZ
-
Figure 2. ISO722 Sleep-Mode High-Level Output Test Circuit and Voltage Waveforms
V
CC2
R
= 1 kW ±1%
L
V
CC2
0 V
V
I
V
/2
V
/2
CC2
CC2
IN
OUT
V
0 V
O
t
t
PZL
PLZ
V
CC2
EN
0.5 V
V
C
L
NOTE B
O
50%
+
V
Input
Generator
NOTE A
OL
50 W
V
I
-
Figure 3. ISO722 Sleep-Mode Low-Level Output Test Circuit and Voltage Waveforms
NOTE
A: The input pulse is supplied by a generator having the following characteristics:
PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
B: CL = 15 pF ± 20% and includes instrumentation and fixture capacitance.
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PARAMETER MEASUREMENT INFORMATION (continued)
V
I
V
CC1
V
CC1
V
2.7 V
I
IN
0 V
V
OUT
V
0 V
t
fs
O
OH
50%
V
O
C
EN
ISO722
and
L
15 pF
±20%
V
OL
ISO722M
NOTE: VI transition time is 100 ns.
Figure 4. Failsafe Delay Time Test Circuit and Voltage Waveforms
V
V
CC2
CC1
OUT
C
IN
V
L
CC
or
V
15 pF
±20%
O
C = 0.1 mF,
I
GND1
GND2
0 V
±1%
V
CM
NOTE: Pass/fail criterion is no change in VO.
Figure 5. Common-Mode Transient-Immunity Test Circuit and Voltage Waveform
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PARAMETER MEASUREMENT INFORMATION (continued)
Tektronix
HFS9009
Tektronix
784D
PATTERN
GENERATOR
V
CC1
In p u t
0 V
O u tp u t
V
CC2/2
J itte r
NOTE: Bit pattern run length is 216 – 1. Transition time is 800 ps. NRZ data input has no more than five consecutive
1s or 0s.
Figure 6. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform
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DEVICE INFORMATION
PACKAGE INSULATION CHARACTERISTICS
PARAMETER
DESCRIPTIONS / TEST CONDITIONS
MIN
4.8
TYP
MAX UNIT
D-8
(1)
L(101) Minimum air gap (clearance)
Shortest terminal-to-terminal distance through air
mm
DUB-8
D-8
6.1
4.3
6.8
Minimum external tracking
(creepage)
Shortest terminal-to-terminal distance across the
package surface
L(102)
mm
DUB-8
Tracking resistance (comparative
tracking index)
CTI
DIN IEC 60112/VDE 0303 Part 1
Distance through insulation
≥ 175
V
Minimum internal gap (internal
clearance)
0.008
mm
Input to output, VIO = 500 V; all pins on each side of the
barrier tied together, creating a two-terminal device; TA
100°C
<
>1012
>1011
Ω
Ω
RIO
Isolation resistance
Input to output, VIO = 500 V,
100°C ≤ TA< TA max.
Barrier capacitance
Input-to-output
CIO
CI
VI = 0.4 sin (4E6pt)
VI = 0.4 sin (4E6pt)
1
1
pF
pF
Input capacitance to ground
(1) Creepage and clearance requirements are applied according to the specific equipment isolation standards of an application. Care should
be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the
printed circuit board do not reduce this distance.
Creepage and clearance on a printed circuit board become equal according to the measurement techniques shown in the Isolation
Glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
IEC 60664-1 RATINGS TABLE
PARAMETER
TEST CONDITIONS
SPECIFICATION
Basic isolation group
Material group
IIIa
I-IV
I-III
Rated mains voltage ≤150 VRMS
Rated mains voltage ≤300 VRMS
Installation classification
DEVICE I/O SCHEMATIC
Equivalent Input and Output Schematic Diagrams
Enable
Input
Output
V
CC2
V
V
V
CC1
CC2
V
CC1
V
CC1
CC2
8 W
750 kW
OUT
500 W
500 W
EN
IN
13 W
1 MW
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IEC SAFETY LIMITING VALUES
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.
A failure of the I/O can allow low resistance to ground or the supply, and without current limiting, dissipate
sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system
failures.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
100
153
150
UNIT
mA
qJA = 263°C/W, VI = 5.5 V, TJ = 170°C, TA = 25°C
qJA = 263°C/W, VI = 3.6 V, TJ = 170°C, TA = 25°C
IS
Safety input, output, or supply current
Maximum case temperature
TS
°C
The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum
ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The junction-to-air thermal resistance in the Thermal
Characteristics table is that of a device installed in the JESD51-3, Low Effective Thermal Conductivity Test Board
for Leaded Surface Mount Packages and is conservative. The power is the recommended maximum input
voltage times the current. The junction temperature is then the ambient temperature plus the power times the
junction-to-air thermal resistance.
Table 2. THERMAL CHARACTERISTICS for D-8 PACKAGE
(over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
Low-K thermal resistance(1)
High-K thermal resistance(1)
MIN TYP MAX
UNIT
°C/W
°C/W
°C/W
°C/W
263
125
44
RqJA
Junction-to-air
RqJB
RqJC
Junction-to-board thermal resistance
Junction-to-case thermal resistance
75
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 100-Mbps 50% duty-cycle square wave
ISO72x
Device power dissipation
ISO72xM
159
195
PD
mW
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 150-Mbps 50% duty-cycle square wave
(1) Tested in accordance with the low-K or high-K thermal metric definition of EIA/JESD51-3 for leaded surface-mount packages.
Table 3. THERMAL CHARACTERISTICS for DUB-8 PACKAGE
(over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
Low-K thermal resistance(1)
High-K thermal resistance(1)
MIN TYP MAX
UNIT
°C/W
°C/W
°C/W
°C/W
188
117
82.1
60
RqJA
Junction-to-air
RqJB
RqJC
Junction-to-board thermal resistance
Junction-to-case thermal resistance
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 100 Mbps 50% duty cycle square wave
PD
Device power dissipation
ISO721
159
mW
(1) Tested in accordance with the low-K or high-K thermal metric definition of EIA/JESD51-3 for leaded surface-mount packages.
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200
175
150
V
, V
= 3.6 V
CC1 CC2
125
100
75
50
25
0
V
, V
= 5.5 V
CC1 CC2
0
50
100
Case Temperature
150
200
−
oC
Figure 7. qJC Thermal Derating Curve per IEC 60747-5-2
FUNCTION TABLE
Table 4. ISO721(1)
VCC1
VCC2
INPUT
(IN)
OUTPUT
(OUT)
H
L
H
L
PU
PD
PU
PU
Open
X
H
H
(1) PU = Powered up (VCC ≥ 3 V); PD = Powered down (VCC ≤ 2.5 V); X = Irrelevant; H = High level;
L = Low level
Table 5. ISO722(1)
VCC1
VCC2
INPUT
(IN)
ISO722/ISO722M
OUTPUT ENABLE (EN)
OUTPUT
(OUT)
H
L
L or open
L or open
H
H
L
PU
PU
X
Z
H
H
Z
Open
X
L or open
L or open
H
PD
PD
PU
PU
X
(1) PU = Powered up (VCC ≥ 3 V); PD = Powered down (VCC ≤ 2.5 V); X = Irrelevant; Z = High impedance; H = High level; L = Low level
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TYPICAL CHARACTERISTICS
RMS SUPPLY CURRENT vs
RMS SUPPLY CURRENT vs
SIGNALING RATE
SIGNALING RATE
10
9
15
14
13
12
V
V
T
= 3.3 V,
= 3.3 V,
= 25oC,
V
V
T
= 5 V,
= 5 V,
= 25oC,
CC1
CC2
CC1
CC2
8
7
6
5
A
A
I
CC2
C
= 15 pF
C
= 15 pF
L
L
11
10
9
8
7
6
I
CC2
I
4
3
2
CC1
5
4
3
2
1
0
I
CC1
1
0
0
25
50
75
100
0
25
50
75
100
Signaling Rate (Mbps)
Signaling Rate (Mbps)
Figure 8.
Figure 9.
PROPAGATION DELAY vs
FREE-AIR TEMPERATURE
PROPAGATION DELAY vs
FREE-AIR TEMPERATURE
30
25
20
18
t
PLH
t
PLH
ISO72x
16
t
PHL
t
ISO72x
PHL
14
12
10
20
15
t
PLH
t
PLH
t
PHL
t
PHL
ISO72xM
ISO72xM
8
6
4
10
V
V
= 3.3 V,
= 3.3 V,
CC1
CC2
V
V
= 5 V,
CC1
CC2
= 5 V,
5
0
C
= 15 pF,
L
C
= 15 pF,
L
Air Flow at 7 cf/m
2
0
Air Flow at 7 cf/m
-40 -25 -10
5
20
35
50
65
80
95
110 125
-40 -25 -10
5
20
35
50
65
80
95
110 125
T
− Free-Air Temperature − o
C
T
− Free-Air Temperature − o
C
A
A
Figure 10.
Figure 11.
ISO72x INPUT THRESHOLD VOLTAGE vs
FREE-AIR TEMPERATURE
ISO72xM INPUT THRESHOLD VOLTAGE vs
FREE-AIR TEMPERATURE
1.4
1.35
1.3
2.5
5-V (V
)
IT+
2.4
2.3
5-V (V
)
IT+
2.2
2.1
5-V (V
)
3.3-V (V
)
IT-
IT+
1.25
1.2
2
Air Flow at 7 cf/m
1.9
Air Flow at 7 cf/m
1.15
1.1
1.05
1
1.8
1.7
1.6
5-V (V
)
IT-
3.3-V (V
)
IT+
3.3-V (V
)
IT-
3.3-V (V
)
1.5
1.4
IT-
-40 -25 -10
5
20
35
50
65
80
95
110 125
-40 -25 -10
5
20
35
50
65
80
95
110 125
T
− Free-Air Temperature − o
C
T
− Free-Air Temperature − o
C
A
A
Figure 12.
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
VCC1 FAILSAFE THRESHOLD VOLTAGE vs
FREE-AIR TEMPERATURE
HIGH-LEVEL OUTPUT CURRENT vs
HIGH-LEVEL OUTPUT VOLTAGE
-80
-70
-60
-50
-40
-30
-20
2.92
2.9
T
= 25oC
A
V
= 5 V
CC
2.88
2.86
V
fs+
V
= 5 V or 3.3 V,
CC
= 15 pF,
C
L
Air Flow at 7 cf/m
V
= 3.3 V
2.84
2.82
CC
V
fs-
2.8
-10
0
2.78
0
1
2
3
4
5
6
-40 -25 -10
5
20
35
50
65
80
95
110 125
− Free-Air Temperature − o
C
V
− High-Level Output Voltage − V
T
OH
A
Figure 14.
Figure 15.
LOW-LEVEL OUTPUT CURRENT vs
LOW-LEVEL OUTPUT VOLTAGE
70
60
T
= 25oC
A
V
= 5 V
CC
50
40
30
20
V
= 3.3 V
CC
10
0
0
1
2
3
4
5
V
− Low-Level Output Voltage − V
OL
Figure 16.
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APPLICATION INFORMATION
MANUFACTURER CROSS-REFERENCE DATA
The ISO72xx isolators have the same functional pinout as those of most other vendors, and they are often
pin-for-pin drop-in replacements. The notable differences in the products are propagation delay, signaling rate,
power consumption, and transient protection rating. Table 6 is used as a guide for replacing other isolators with
the ISO72x family of single channel isolators.
ISO722
or
ISO722M
ISO721
or
ISO721M
HCPL-xxxx
IL710
ADuM1100
V
V
V
V
V
V
V
DD2
1
2
3
4
1
8
7
6
5
8
7
6
5
1
2
3
4
8
7
6
5
DD1
V
V
V
V
V
V
CC2
DD1
DD2
DD2
DD1
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CC1
IN
CC2
CC1
IN
V
I
V
V
2
3
4
NC
GND2
V
I
V
I
DD1
OE
O
EN
GND2
OUT
V
O
GND2
GND1
V
O
GND2
NC
OUT
GND2
CC1
CC1
*
GND1
GND1
GND2
GND1
GND1
GND2
Figure 17. Pin Cross Reference
Table 6. CROSS REFERENCE
PIN 7
ISO721
OR
ISO722
OR
ISOLATOR
PIN 1
PIN 2
PIN 3
PIN 4
PIN 5
PIN 6
PIN 8
ISO721M
ISO722M
ISO721(1) (2)
ADuM1100(1) (2)
VCC1
VDD1
IN
VI
VCC1
VDD1
GND1
GND1
GND2
GND2
OUT
VO
GND2
EN
VCC2
VDD2
GND2
*Leave
HCPL-xxxx
IL710
VDD1
VDD1
VI
VI
GND1
GND1
GND2
GND2
VO
VO
NC(4)
V OE
VDD2
VDD2
Open(3)
NC(5)
(1) Pin 1 should be used as VCC1. Pin 3 may also be used as VCC1 or left open, as long as pin 1 is connected to VCC1
.
(2) Pin 5 should be used as GND2. Pin 7 may also be used as GND2 or left open, as long as pin 5 is connected to GND2.
(3) Pin 3 of the HCPL devices must be left open. This is not a problem when substituting an ISO72xx device, because the extra VCC1 on pin
3 may be left an open circuit as well.
(4) An HCPL device pin 7 must be left floating (open) or grounded when an ISO722 or ISO722M device is to be used as a drop-in
replacement. If pin 7 of the ISO722 or ISO722M device is placed in a high logic state, the output of the device is disabled.
(5) Pin 3 of the IL710 must not be tied to ground on the circuit board because this shorts the ISO72xx's VCC1 to ground. The IL710 pin 3
may only be tied to VCC or left open to drop in an ISO72xx.
VCC1
VCC2
ISO721
2 mm
max.
from
VCC2
2 mm
max.
from
VCC1
or ISO721M
0.1mF
0.1mF
1
8
7
6
5
2
IN
INPUT
GND1
3
4
OUT
OUTPUT
GND2
Figure 18. Basic Application Circuit
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ISOLATION GLOSSARY
Creepage Distance — The shortest path between two conductive input to output leads measured along the
surface of the insulation. The shortest distance path is found around the end of the package body.
Clearance — The shortest distance between two conductive input to output leads measured through air (line of
sight).
Input-to Output Barrier Capacitance — The total capacitance between all input terminals connected together,
and all output terminals connected together.
Input-to Output Barrier Resistance — The total resistance between all input terminals connected together, and
all output terminals connected together.
Primary Circuit — An internal circuit directly connected to an external supply main or other equivalent source
which supplies the primary circuit electric power.
Secondary Circuit — A circuit with no direct connection to primary power, which derives its power from a
separate isolated source.
Comparative Tracking Index (CTI) — CTI is an index used for electrical insulating materials that is defined as
the numerical value of the voltage which causes failure by tracking during standard testing. Tracking is the
process that produces a partially conducting path of localized deterioration on or through the surface of an
insulating material as a result of the action of electric discharges on or close to an insulation surface -- the higher
the CTI value of the insulating material, the smaller the minimum creepage distance.
Generally, insulation breakdown occurs either through the material, over its surface, or both. Surface failure may
arise from flashover or from the progressive degradation of the insulation surface by small localized sparks. Such
sparks are the result of the breaking of a surface film of conducting contaminant on the insulation. The resulting
break in the leakage current produces an overvoltage at the site of the discontinuity, and an electric spark is
generated. These sparks often cause carbonization on insulation material and lead to a carbon track between
points of different potential. This process is known as tracking.
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Insulation:
Operational insulation — Insulation needed for the correct operation of the equipment.
Basic insulation — Insulation to provide basic protection against electric shock.
Supplementary insulation — Independent insulation applied in addition to basic insulation in order to ensure
protection against electric shock in the event of a failure of the basic insulation.
Double insulation — Insulation comprising both basic and supplementary insulation.
Reinforced insulation — A single insulation system which provides a degree of protection against electric shock
equivalent to double insulation.
Pollution Degree:
Pollution Degree 1 — No pollution, or only dry, nonconductive pollution occurs. The pollution has no influence.
Pollution Degree 2 — Normally, only nonconductive pollution occurs. However, a temporary conductivity caused
by condensation must be expected.
Pollution Degree 3 — Conductive pollution occurs or dry nonconductive pollution occurs which becomes
conductive due to condensation which is to be expected.
Pollution Degree 4 – Continuous conductivity occurs due to conductive dust, rain, or other wet conditions.
Installation Category:
Overvoltage Category — This section is directed at insulation co-ordination by identifying the transient
overvoltages which may occur, and by assigning four different levels as indicated in IEC 60664.
I: Signal level — Special equipment or parts of equipment.
II: Local level — Portable equipment, etc.
III: Distribution level — Fixed installation
IV: Primary supply level — Overhead lines, cable systems
Each category should be subject to smaller transients than the category above.
A
A
A
REVISION HISTORY
Changes from Revision I (February 2010) to Revision J
Page
•
•
•
•
Changed V to Vpeak in UNIT column of IEC Insulation Characteristics table ..................................................................... 4
Added row for VISO to IEC Insulation Characteristics table .................................................................................................. 4
Changed note from " ............................................................................................................................................................. 5
Removed VCC2 from 5-V operation, changed 3-V operation to 3.3-V operation, and removed VCC1 from 3.3-V
operation in note. .................................................................................................................................................................. 6
•
Removed VCC1 from 5-V operation, changed 3-V operation to 3.3-V operation, and removed VCC2 from 3.3-V
operation in note. .................................................................................................................................................................. 7
•
•
•
Removed 5-V operation, changed 3-V operation to 3.3-V operation, and changed " .......................................................... 8
Added "INSULATION" to the title of "PACKAGE CHARACTERISTICS" table ................................................................... 12
Added "Descriptions" to header of PACKAGE INSULATION CHARACTERISTICS table ................................................. 12
Changes from Revision H (June 2009) to Revision I
Page
•
Changed 50 kV/s to 50 kV/µs ............................................................................................................................................... 1
Copyright © 2006–2010, Texas Instruments Incorporated
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Product Folder Link(s): ISO721 ISO721M ISO722 ISO722M
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jul-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
ISO721D
ISO721DG4
ISO721DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOP
D
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
75
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-4-260C-72 HR
CU NIPDAU Level-4-260C-72 HR
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
Purchase Samples
Purchase Samples
Purchase Samples
Request Free Samples
D
2500
2500
50
Green (RoHS
& no Sb/Br)
ISO721DRG4
ISO721DUB
ISO721DUBR
ISO721MD
D
Green (RoHS
& no Sb/Br)
DUB
DUB
D
Green (RoHS
& no Sb/Br)
SOP
350
75
Green (RoHS
& no Sb/Br)
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
Green (RoHS
& no Sb/Br)
Contact TI Distributor
or Sales Office
ISO721MDG4
ISO721MDR
ISO721MDRG4
ISO722D
D
75
Green (RoHS
& no Sb/Br)
Contact TI Distributor
or Sales Office
D
2500
2500
75
Green (RoHS
& no Sb/Br)
Purchase Samples
D
Green (RoHS
& no Sb/Br)
Purchase Samples
D
Green (RoHS
& no Sb/Br)
Contact TI Distributor
or Sales Office
ISO722DG4
ISO722DR
D
75
Green (RoHS
& no Sb/Br)
Contact TI Distributor
or Sales Office
D
2500
2500
75
Green (RoHS
& no Sb/Br)
Request Free Samples
ISO722DRG4
ISO722MD
D
Green (RoHS
& no Sb/Br)
Request Free Samples
D
Green (RoHS
& no Sb/Br)
Contact TI Distributor
or Sales Office
ISO722MDG4
ISO722MDR
D
75
Green (RoHS
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Contact TI Distributor
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D
2500
Green (RoHS
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Request Free Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jul-2010
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
ISO722MDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF ISO721, ISO721M :
Automotive: ISO721-Q1
•
Enhanced Product: ISO721M-EP
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jul-2010
Enhanced Product - Supports Defense, Aerospace and Medical Applications
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Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Oct-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO721DUBR
ISO722DR
SOP
SOIC
SOIC
DUB
D
8
8
8
350
2500
2500
330.0
330.0
330.0
24.4
12.4
12.4
10.9 10.01 5.85
16.0
8.0
24.0
12.0
12.0
Q1
Q1
Q1
6.4
6.4
5.2
5.2
2.1
2.1
ISO722MDR
D
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Oct-2010
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ISO721DUBR
ISO722DR
SOP
SOIC
SOIC
DUB
D
8
8
8
350
2500
2500
358.0
358.0
358.0
335.0
335.0
335.0
35.0
35.0
35.0
ISO722MDR
D
Pack Materials-Page 2
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