ISO7231MDWG4 [TI]
HIGH SPEED, TRIPLE DIGITAL ISOLATORS; 高速TRIPLE数字隔离器
| 型号： | ISO7231MDWG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH SPEED, TRIPLE DIGITAL ISOLATORS |
| 文件： | 总23页 (文件大小：745K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISO7230C, ISO7230M
ISO7231C, ISO7230M
www.ti.com.................................................................................................................................................. SLLS867F–SEPTEMBER 2007–REVISED JUNE 2008
HIGH SPEED, TRIPLE DIGITAL ISOLATORS
1
FEATURES
•
25 and 150-Mbps Signaling Rate Options
•
•
High Electromagnetic Immunity
(See Application Note SLLA181)
–
–
–
Low Channel-to-Channel Output Skew;
1 ns max
–40°C to 125°C Operating Range
Low Pulse-Width Distortion (PWD);
2 ns max
APPLICATIONS
•
•
•
•
Industrial Fieldbus
Low Jitter Content; 1 ns Typ at 150 Mbps
Computer Peripheral Interface
Servo Control Interface
Data Acquisition
•
•
Typical 25-Year Life at Rated Working Voltage
(See Application Note SLLA197 and Figure 14)
4000-Vpeak Isolation, 560-Vpeak VIORM
–
UL 1577, IEC 60747-5-2 (VDE 0884, Rev 2),
IE 61010-1 and CSA Approved
•
•
4 kV ESD Protection
Operate With 3.3-V or 5-V Supplies
DESCRIPTION
The ISO7230 and ISO7231 are triple-channel digital isolators each with multiple channel configurations and
output enable functions. These devices have logic input and output buffers separated by TI’s silicon dioxide
(SiO2) isolation barrier. Used in conjunction with isolated power supplies, these devices block high voltage,
isolate grounds, and prevent noise currents on a data bus or other circuits from entering the local ground and
interfering with or damaging sensitive circuitry.
The ISO7230 triple-channel device has all three channels in the same direction while the ISO7231 has two
channels in one direction and one channel in opposition. These devices have an active-high output enable that
when driven to a low level, places the output in a high-impedance state.
The ISO7230C and ISO7231C have TTL input thresholds and a noise-filter at the input that prevents transient
pulses of up to 2 ns in duration from being passed to the output of the device, while the ISO7230M and
ISO7231M have CMOS VCC/2 input thresholds and do not have the input noise-filter or the additional propagation
delay.
In each device, a periodic update pulse is sent across the isolation barrier to ensure the proper dc level of the
output. If this dc-refresh pulse is not received, the input is assumed to be unpowered or not being actively driven,
and the failsafe circuit drives the output to a logic high state. (Contact TI for a logic low failsafe option).
These devices require two supply voltages of 3.3-V, 5-V, or any combination. All inputs are 5-V tolerant when
supplied from a 3.3-V supply and all outputs are 4-mA CMOS. These devices are characterized for operation
over the ambient temperature range of –40°C to 125°C.
ISO7230
ISO7231
DW PACKAGE
DW PACKAGE
V
V
V
V
CC2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC1
CC2
CC1
GND1
GND2
GND1
GND2
IN
A
IN
B
IN
C
OUT
A
IN
IN
OUT
A
A
OUT
B
OUT
B
B
IN
C
OUT
C
OUT
C
NC
NC
NC
NC
NC
EN
EN
EN
2
1
GND1
GND2
GND1
GND2
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2008, Texas Instruments Incorporated
ISO7230C, ISO7230M
ISO7231C, ISO7230M
SLLS867F–SEPTEMBER 2007–REVISED JUNE 2008.................................................................................................................................................. www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTION DIAGRAM
Galvanic Isolation
Barrier
DC Channel
Filter
OSC
+
PWM
Pulse Width
Demodulation
Vref
Carrier Detect
EN
Data MUX
AC Detect
Input
+
Filter
Vref
IN
OUT
Output Buffer
AC Channel
(1)
Table 1. Device Function Table ISO723x
INPUT
(IN)
OUTPUT ENABLE
OUTPUT
(OUT)
INPUT VCC
OUTPUT VCC
(EN)
H or Open
H or Open
L
H
L
H
L
PU
PU
X
Z
H
H
Z
Open
X
H or Open
H or Open
L
PD
PD
PU
PU
X
(1) PU = Powered Up; PD = Powered Down ; X = Irrelevant; H = High Level; L = Low Level
AVAILABLE OPTIONS
SIGNALING
RATE
INPUT
THRESHOLD
CHANNEL
CONFIGURATION
MARKED
AS
ORDERING
NUMBER(1)
PRODUCT
ISO7230CDW (rail)
ISO7230CDWR (reel)
ISO7230MDW (rail)
ISO7230MDWR (reel)
ISO7231CDW (rail)
ISO7231CDWR (reel)
ISO7231MDW (rail)
ISO7231MDWR (reel)
~1.5 V (TTL)
(CMOS compatible)
ISO7230CDW
25 Mbps
150 Mbps
25 Mbps
150 Mbps
ISO7230C
ISO7230M
ISO7231C
ISO7231M
3/0
2/1
ISO7230MDW
ISO7231CDW
ISO7231MDW
Vcc/2 (CMOS)
~1.5 V (TTL)
(CMOS compatible)
Vcc/2 (CMOS)
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
2
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Product Folder Link(s): ISO7230C, ISO7230M ISO7231C, ISO7230M
ISO7230C, ISO7230M
ISO7231C, ISO7230M
www.ti.com.................................................................................................................................................. SLLS867F–SEPTEMBER 2007–REVISED JUNE 2008
ABSOLUTE MAXIMUM RATINGS(1)
VALUE
–0.5 to 6
–0.5 to 6
±15
UNIT
V
VCC Supply voltage(2), VCC1, VCC2
VI
IO
Voltage at IN, OUT, EN
Output current
V
mA
Human Body Model
Electrostatic Field-Induced-Charged Device
JEDEC Standard 22, Test Method A114-C.01
JEDEC Standard 22, Test Method C101
ANSI/ESDS5.2-1996
±4
kV
ESD
TJ
All pins
±1
discharge
Model
Machine Model
±200
170
V
Maximum junction temperature
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal and are peak voltage values.
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX UNIT
VCC Supply voltage(1), VCC1, VCC2
3.15
5.5
4
V
IOH
IOL
High-level output current
Low-level output current
mA
mA
–4
ISO723xC
ISO723xM
ISO723xC
ISO723xM
40
tui
Input pulse width
ns
Mbps
V
6.67
5
30(2)
200(2)
0
25
150
1/tui Signaling rate
0
VIH
VIL
VIH
VIL
TJ
High-level input voltage (IN)
0.7 VCC
VCC
ISO723xM
ISO723xC
Low-level input voltage (IN)
0
2
0
0.3 VCC
VCC
High-level input voltage (IN) (EN on all devices)
Low-level input voltage (IN) (EN on all devices)
Junction temperature
V
0.8
150
°C
H
External magnetic field-strength immunity per IEC 61000-4-8 and IEC 61000-4-9
certification
A/m
1000
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
(2) Typical sigalling rate under ideal conditions at 25°C.
Copyright © 2007–2008, Texas Instruments Incorporated
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Product Folder Link(s): ISO7230C, ISO7230M ISO7231C, ISO7230M
ISO7230C, ISO7230M
ISO7231C, ISO7230M
SLLS867F–SEPTEMBER 2007–REVISED JUNE 2008.................................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 5-V(1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
1
7
3
9.5
11
17
22
24
20
27
VI = VCC or 0 V, All channels, no load,
EN2 at 3 V
ISO7230C/M
mA
mA
mA
mA
ICC1
6.5
11
VI = VCC or 0 V, All channels, no load,
EN1 at 3 V, EN2 at 3 V
ISO7231C/M
ISO7230C/M
ISO7231C/M
15
VI = VCC or 0 V, All channels, no load,
EN2 at 3 V
17
ICC2
13
VI = VCC or 0 V, All channels, no load,
EN1 at 3 V, EN2 at 3 V
17.5
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
EN at 0 V, Single channel
IOH = –4 mA, See Figure 1
IOH = –20 µA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 µA, See Figure 1
0
µA
VCC – 0.8
VCC – 0.1
VOH
High-level output voltage
V
0.4
0.1
VOL
Low-level output voltage
V
VI(HYS)
IIH
Input voltage hysteresis
High-level input current
Low-level input current
Input capacitance to ground
150
mV
µA
10
IN from 0 V to VCC
IIL
–10
25
CI
IN at VCC, VI = 0.4 sin (4E6πt)
2
pF
CMTI
Common-mode transient immunity
VI = VCC or 0 V, See Figure 4
50
kV/µs
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
4
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Product Folder Link(s): ISO7230C, ISO7230M ISO7231C, ISO7230M
ISO7230C, ISO7230M
ISO7231C, ISO7230M
www.ti.com.................................................................................................................................................. SLLS867F–SEPTEMBER 2007–REVISED JUNE 2008
SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 5-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
tPLH, tPHL
PWD
Propagation delay
18
42
2.5
23
2
ISO723xC
ISO723xM
See Figure 1
ns
Pulse-width distortion(1) |tPHL – tPLH
Propagation delay
Pulse-width distortion(1) |tPHL – tPLH
|
tPLH, tPHL
PWD
10
ns
ns
ns
ns
|
1
ISO723xC
ISO723xM
ISO723xC
ISO723xM
8
(2)
tsk(pp)
Part-to-part skew
0
0
3
2
(3)
tsk(o)
Channel-to-channel output skew
0
1
tr
Output signal rise time
Output signal fall time
2
See Figure 1
tf
2
tPHZ
tPZH
tPLZ
tPZL
tfs
Propagation delay, high-level-to-high-impedance output
Propagation delay, high-impedance-to-high-level output
Propagation delay, low-level-to-high-impedance output
Propagation delay, high-impedance-to-low-level output
Failsafe output delay time from input power loss
15
15
15
15
12
20
20
20
20
See Figure 2
See Figure 3
ns
µs
150 Mbps PRBS NRZ data input,
Same polarity inputon all channels,
See Figure 5
tjit(pp)
Peak-to-peak eye-pattern jitter
ISO723xM
1
ns
(1) Also referred to as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Copyright © 2007–2008, Texas Instruments Incorporated
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5
Product Folder Link(s): ISO7230C, ISO7230M ISO7231C, ISO7230M
ISO7230C, ISO7230M
ISO7231C, ISO7230M
SLLS867F–SEPTEMBER 2007–REVISED JUNE 2008.................................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V(1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
1
7
3
9.5
11
17
15
17
12
16
ISO7230C/M
VI = VCC or 0 V, All channels, no load, EN2 at 3 V
mA
mA
mA
mA
ICC1
6.5
11
9
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
ISO7231C/M
ISO7230C/M
ISO7231C/M
VI = VCC or 0 V, All channels, no load, EN2 at 3 V
10
8
ICC2
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
10.5
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
EN at 0 V, Single channel
ISO7230
0
µA
VCC – 0.4
VCC – 0.8
IOH = –4 mA, See Figure 1
ISO7231
VOH
High-level output voltage
V
(5-V side)
IOH = –20 µA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 µA, See Figure 1
VCC – 0.1
0.4
0.1
VOL
Low-level output voltage
V
VI(HYS)
IIH
Input voltage hysteresis
High-level input current
Low-level input current
Input capacitance to ground
150
mV
µA
10
IN from 0 V to VCC
IIL
–10
25
CI
IN at VCC, VI = 0.4 sin (4E6πt)
2
pF
Common-mode transient
immunity
CMTI
VI = VCC or 0 V, See Figure 4
50
kV/µs
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
6
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Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): ISO7230C, ISO7230M ISO7231C, ISO7230M
ISO7230C, ISO7230M
ISO7231C, ISO7230M
www.ti.com.................................................................................................................................................. SLLS867F–SEPTEMBER 2007–REVISED JUNE 2008
SWITCHING CHARACTERISTICS: VCC1 at 5-V, VCC2 at 3.3-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
See Figure 1
MIN
TYP MAX
UNIT
tPLH, tPHL
PWD
Propagation delay, low-to-high-level output
20
50
3
ISO723xC
ISO723xM
ns
Pulse-width distortion(1) |tPHL – tPLH
Propagation delay, low-to-high-level output
Pulse-width distortion(1) |tPHL – tPLH
|
tPLH, tPHL
PWD
12
29
ns
ns
ns
ns
|
1
2
10
5
ISO723xC
ISO723xM
ISO723xC
ISO723xM
(2)
tsk(pp)
Part-to-part skew
0
0
2.5
1
(3)
tsk(o)
Channel-to-channel output skew
0
tr
Output signal rise time
Output signal fall time
2
See Figure 1
tf
2
tPHZ
tPZH
tPLZ
tPZL
tfs
Propagation delay, high-level-to-high-impedance output
Propagation delay, high-impedance-to-high-level output
Propagation delay, low-level-to-high-impedance output
Propagation delay, high-impedance-to-low-level output
Failsafe output delay time from input power loss
15
15
15
15
18
20
20
20
20
See Figure 2
See Figure 3
ns
µs
150 Mbps PRBS NRZ data
input, Same polarity input on
all channels, See Figure 5
tjit(pp)
Peak-to-peak eye-pattern jitter
ISO723xM
1
ns
(1) Also known as pulse skew
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Copyright © 2007–2008, Texas Instruments Incorporated
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7
Product Folder Link(s): ISO7230C, ISO7230M ISO7231C, ISO7230M
ISO7230C, ISO7230M
ISO7231C, ISO7230M
SLLS867F–SEPTEMBER 2007–REVISED JUNE 2008.................................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 at 3.3-V, VCC2 at 5-V(1) OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
0.5
3
1
5
ISO7230C/M
VI = VCC or 0 V, All channels, no load, EN2 at 3 V
mA
mA
mA
mA
ICC1
4.5
6.5
15
7
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
ISO7231C/M
ISO7230C/M
ISO7231C/M
11
22
24
20
27
VI = VCC or 0 V, All channels, no load, EN2 at 3 V
17
ICC2
13
VI = VCC or 0 V, All channels, no load, EN1 at 3 V,
EN2 at 3 V
17.5
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
EN at 0 V, Single channel
0
µA
IOH = –4 mA, See Figure 1
ISO7230
VCC – 0.4
VCC – 0.8
VCC – 0.1
ISO7231
(5-V side)
VOH
High-level output voltage
V
IOH = –20 µA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 µA, See Figure 1
0.4
0.1
VOL
Low-level output voltage
V
VI(HYS)
IIH
Input voltage hysteresis
High-level input current
Low-level input current
Input capacitance to ground
150
mV
µA
10
IN from 0 V to VCC
IIL
–10
25
CI
IN at VCC, VI = 0.4 sin (4E6πt)
2
pF
Common-mode transient
immunity
VI = VCC or 0 V, See Figure 4
CMTI
50
kV/µs
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
8
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Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): ISO7230C, ISO7230M ISO7231C, ISO7230M
ISO7230C, ISO7230M
ISO7231C, ISO7230M
www.ti.com.................................................................................................................................................. SLLS867F–SEPTEMBER 2007–REVISED JUNE 2008
SWITCHING CHARACTERISTICS: VCC1 at 3.3-V and VCC2 at 5-V OPERATION
, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
tPLH, tPHL
PWD
Propagation delay
22
51
3
ISO723xC
ISO723xM
Pulse-width distortion(1) |tPHL – tPLH
Propagation delay
|
See Figure 1
ns
tPLH, tPHL
PWD
12
30
Pulse-width distortion(1) |tPHL – tPLH
|
1
2
10
5
ISO723xC
ISO723xM
ISO723xC
ISO723xM
(2)
tsk(pp)
Part-to-part skew
ns
ns
ns
0
0
2.5
1
(3)
tsk(o)
Channel-to-channel output skew
0
tr
Output signal rise time
Output signal fall time
2
See Figure 1
tf
2
tPHZ
tPZH
tPLZ
tPZL
tfs
Propagation delay, high-level-to-high-impedance output
Propagation delay, high-impedance-to-high-level output
Propagation delay, low-level-to-high-impedance output
Propagation delay, high-impedance-to-low-level output
Failsafe output delay time from input power loss
15
15
15
15
12
20
20
20
20
See Figure 2
See Figure 3
ns
µs
150 Mbps PRBS NRZ data input, Same
polarity input on all channels, See Figure 5
tjit(pp)
Peak-to-peak eye-pattern jitter
ISO723xM
1
ns
(1) Also known as pulse skew
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
Copyright © 2007–2008, Texas Instruments Incorporated
Submit Documentation Feedback
9
Product Folder Link(s): ISO7230C, ISO7230M ISO7231C, ISO7230M
ISO7230C, ISO7230M
ISO7231C, ISO7230M
SLLS867F–SEPTEMBER 2007–REVISED JUNE 2008.................................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3 V(1) OPERATION
, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
SUPPLY CURRENT
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
Quiescent
25 Mbps
0.5
3
1
5
VI = VCC or 0 V, all channels, no load,
EN2 at 3 V
ISO7230C/M
mA
mA
mA
mA
ICC1
4.5
6.5
9
7
VI = VCC or 0 V, all channels, no load,
EN1 at 3 V, EN2 at 3 V
ISO7231C/M
11
15
17
12
16
VI = VCC or 0 V, all channels, no load,
EN2 at 3 V
ISO7230C/M
ISO7231C/M
10
8
ICC2
VI = VCC or 0 V, all channels, no load,
EN1 at 3 V, EN2 at 3 V
10.5
ELECTRICAL CHARACTERISTICS
IOFF
Sleep mode output current
EN at 0 V, single channel
IOH = –4 mA, See Figure 1
IOH = –20 µA, See Figure 1
IOL = 4 mA, See Figure 1
IOL = 20 µA, See Figure 1
0
µA
VCC – 0.4
VCC – 0.1
VOH
High-level output voltage
V
0.4
0.1
VOL
Low-level output voltage
V
VI(HYS)
IIH
Input voltage hysteresis
150
mV
µA
High-level input current
10
IN from 0 V or VCC
IIL
Low-level input current
–10
25
CI
Input capacitance to ground
Common-mode transient immunity
IN at VCC, VI = 0.4 sin (4E6πt)
2
pF
CMTI
VI = VCC or 0 V, See Figure 4
50
kV/µs
(1) For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V.
For the 3-V operation, VCC1 or VCC2 is specified from 3.15 V to 3.6 V.
10
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Product Folder Link(s): ISO7230C, ISO7230M ISO7231C, ISO7230M
ISO7230C, ISO7230M
ISO7231C, ISO7230M
www.ti.com.................................................................................................................................................. SLLS867F–SEPTEMBER 2007–REVISED JUNE 2008
SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 3.3-V OPERATION
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
tPLH, tPHL
PWD
Propagation delay
Pulse-width distortion(1) |tPHL – tPLH
25
56
4
ISO723xC
ISO723xM
See Figure 1
ns
|
|
tpLH, tpHL
PWD
Propagation delay
Pulse-width distortion(1) |tPHL – tPLH
12
34
ns
ns
ns
ns
1
2
10
5
ISO723xC
ISO723xM
ISO723xC
ISO723xM
(2)
tsk(pp)
Part-to-part skew
0
0
3
(3)
tsk(o)
Channel-to-channel output skew
0
1
tr
Output signal rise time
Output signal fall time
2
See Figure 1
tf
2
tPHZ
tPZH
tPLZ
tPZL
tfs
Propagation delay, high-level-to-high-impedance output
Propagation delay, high-impedance-to-high-level output
Propagation delay, low-level-to-high-impedance output
Propagation delay, high-impedance-to-low-level output
Failsafe output delay time from input power loss
15
15
15
15
18
20
20
20
20
See Figure 2
See Figure 3
ns
µs
150 Mbps PRBS NRZ data input, same
polarity input on all channels, See Figure 5
tjit(pp)
Peak-to-peak eye-pattern jitter
ISO723xM
1
ns
(1) Also referred to as pulse skew.
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
(3) tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
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ISO7230C, ISO7230M
ISO7231C, ISO7230M
SLLS867F–SEPTEMBER 2007–REVISED JUNE 2008.................................................................................................................................................. www.ti.com
PARAMETER MEASUREMENT INFORMATION
V
1
CC
V
V
1/2
CC
V
1/2
I
CC
IN
OUT
0 V
t
t
PHL
PLH
Input
Generator
V
C
V
V
O
50 W
OH
OL
L
NOTE B
I
90%
10%
V
O
50%
50%
NOTE A
V
t
t
f
r
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms
Vcc
Vcc
RL = 1 kW 1%
Vcc/2
50%
Vcc/2
V
I
IN
0 V
OUT
VO
tPZL
0 V
tPLZ
Vcc
0.5 V
EN
CL
V
O
NOTE
B
Input
VOL
VI
Generator
50 W
NOTE A
Vcc
Vcc/2
Vcc/2
V
V
O
IN
OUT
I
3 V
0 V
VOH
t
PZH
EN
RL = 1 kW 1%
CL
50%
0.5 V
V
O
NOTE
B
Input
0 V
tPHZ
VI
Generator
50 W
NOTE A
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 2. Enable/Disable Propagation Delay Time Test Circuit and Waveform
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ISO7230C, ISO7230M
ISO7231C, ISO7230M
www.ti.com.................................................................................................................................................. SLLS867F–SEPTEMBER 2007–REVISED JUNE 2008
PARAMETER MEASUREMENT INFORMATION (continued)
V
I
V
1
CC
V
1
CC
V
I
0 V
or
2.7 V
OUT
IN
V
0 V
V
O
V
1
t
CC
fs
OH
C
V
L
50%
O
NOTE B
V
OL
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 3. Failsafe Delay Time Test Circuit and Voltage Waveforms
V
1
V
2
CC
CC
C = 0.1 mF 1ꢀ
C = 0.1 mF 1ꢀ
Pass-fail criteria:
Output must
remain stable
OUT
IN
S1
NOTE B
V
or V
OL
OH
GND1
GND2
V
CM
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3 ns, ZO = 50Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 4. Common-Mode Transient Immunity Test Circuit and Voltage Waveform
V
1
CC
DUT
Tektronix
HFS9009
IN
0 V
V
Tektronix
784D
OUT
PATTERN
/2
GENERATOR
CC
Jitter
NOTE: PRBS bit pattern run length is 216 – 1. Transition time is 800 ps. NRZ data input has no more than five consecutive 1s
or 0s.
Figure 5. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform
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ISO7230C, ISO7230M
ISO7231C, ISO7230M
SLLS867F–SEPTEMBER 2007–REVISED JUNE 2008.................................................................................................................................................. www.ti.com
DEVICE INFORMATION
PACKAGE CHARACTERISTICS
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
L(I01) Minimum air gap (Clearance)
Shortest terminal-to-terminal distance through air
8.34
mm
Shortest terminal-to-terminal distance across the
package surface
L(I02) Minimum external tracking (Creepage)
8.1
mm
mm
Minimum Internal Gap (Internal
Clearance)
Distance through the insulation
0.008
Input to output, VIO = 500 V, all pins on each side of the
barrier tied together creating a two-terminal device,
TA < 100°C
>1012
Ω
RIO
Isolation resistance
Input to output, VIO = 500 V, 100°C ≤ TA ≤ TA max
VI = 0.4 sin (4E6πt)
>1011
Ω
CIO
CI
Barrier capacitance Input to output
Input capacitance to ground
2
2
pF
pF
VI = 0.4 sin (4E6πt)
REGULATORY INFORMATION
VDE
CSA
UL
Recognized under 1577
Certified according to IEC
60747-5-2
Approved under CSA Component
Acceptance Notice
Component Recognition
Program(1)
File Number: 40016131
File Number: 1698195
File Number: E181974
(1) Production tested ≥ 3000 VRMS for 1 second in accordance with UL 1577.
DEVICE I/O SCHEMATICS
Enable
Output
VCC2
Input
VCC1
VCC2
VCC2
VCC2
VCC1
1 MW
500 W
8 W
500 W
IN
EN
OUT
13 W
1 MW
THERMAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Low-K Thermal Resistance(1)
High-K Thermal Resistance
MIN
TYP MAX UNIT
168
°C/W
96.1
θJA
Junction-to-air
θJB
θJC
Junction-to-Board Thermal Resistance
Junction-to-Case Thermal Resistance
61
48
°C/W
°C/W
VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF,
Input a 50% duty cycle square wave
PD
Device Power Dissipation
220
mW
(1) Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages.
14
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ISO7230C, ISO7230M
ISO7231C, ISO7230M
www.ti.com.................................................................................................................................................. SLLS867F–SEPTEMBER 2007–REVISED JUNE 2008
TYPICAL CHARACTERISTIC CURVES
ISO7230 C/M RMS SUPPLY CURRENT
ISO7231 C/M RMS SUPPLY CURRENT
vs
vs
SIGNALING RATE
SIGNALING RATE
45
40
35
45
40
35
T
= 25°C,
T = 25°C,
A
A
Load = 15 pF,
All Channels
Load = 15 pF,
All Channels
5-V ICC1
30
30
5-V ICC2
3.3-V ICC2
25
20
25
20
5-V ICC2
15
15
5-V ICC1
3.3-V ICC1
10
5
10
5
3.3-V ICC2
3.3-V ICC1
0
0
0
25
50
75
100
125
150
0
25
50
75
100
125
150
Signaling Rate - Mbps
Signaling Rate - Mbps
Figure 6.
Figure 7.
PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE
INPUT THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE
45
1.4
1.35
1.3
5 V Vth+
40
35
C 3.3-V tpLH, tpHL
C 5-V tpLH, tpHL
3.3 V Vth+
30
25
20
1.25
1.2
Air Flow at 7 cf/m,
Low-K Board
M 3.3-V tpLH, tpHL
1.15
1.1
15
10
5 V Vth-
M 5-V tpLH, tpHL
T
= 25°C,
A
1.05
1
5
0
Load = 15 pF,
All Channels
3.3 V Vth-
110 125
80
-40
65
95
-25
-10
5
35
20
50
-40 -25
-10
5
20
35
50
65
80
95
110 125
TA - Free-Air Temperature - °C
TA - Free-Air Temperature - °C
Figure 8.
Figure 9.
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ISO7230C, ISO7230M
ISO7231C, ISO7230M
SLLS867F–SEPTEMBER 2007–REVISED JUNE 2008.................................................................................................................................................. www.ti.com
TYPICAL CHARACTERISTIC CURVES (continued)
VCC1 FAILSAFE THRESHOLD
vs
FREE-AIR TEMPERATURE
HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
3
2.9
2.8
50
40
30
20
VCC at 5 V or 3.3 V,
Load = 15 pF,
TA = 25°C
VCC = 5 V
Load = 15 pF,
Air Flow at 7/cf/m,
Low-K Board
VCC = 3.3 V
2.7
2.6
2.5
2.4
2.3
Vfs+
Vfs-
2.2
10
0
2.1
2
0
-40
-25
-10
5
20
35
50
65
80
95
110 125
4
6
2
VO - Output Voltage - V
TA - Free-Air Temperature - °C
Figure 10.
Figure 11.
LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
50
Load = 15 pF,
TA = 25°C
45
40
35
VCC = 3.3 V
30
25
20
VCC = 5 V
15
10
5
0
1
0
2
3
4
5
VO - Output Voltage - V
Figure 12.
16
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Product Folder Link(s): ISO7230C, ISO7230M ISO7231C, ISO7230M
ISO7230C, ISO7230M
ISO7231C, ISO7230M
www.ti.com.................................................................................................................................................. SLLS867F–SEPTEMBER 2007–REVISED JUNE 2008
APPLICATION INFORMATION
20 mm
20 mm
max. from
V
V
max. from
CC1
CC2
V
CC1
V
CC2
0.1 mF
0.1 mF
1
16
15
GND2
GND1
2
IN
IN
IN
OUT
OUT
OUT
A
B
C
A
B
C
14
13
12
11
10
3
4
5
6
7
8
NC
NC
NC
EN
GND2
GND1
9
ISO7230
Figure 13. Typical ISO7230 Application Circuit
LIFE EXPECTANCY vs WORKING VOLTAGE
100
V
at 560-V
IORM
28 Years
10
0
120
250
500
750
1000
880
WORKING VOLTAGE (VIORM) -- V
Figure 14. Time Dependant Dielectric Breakdown Testing Results
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Product Folder Link(s): ISO7230C, ISO7230M ISO7231C, ISO7230M
PACKAGE OPTION ADDENDUM
www.ti.com
2-Jun-2008
PACKAGING INFORMATION
Orderable Device
ISO7230CDW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
DW
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
ISO7230CDWG4
ISO7230CDWR
ISO7230CDWRG4
ISO7230MDW
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
DW
40 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
ISO7230MDWG4
ISO7230MDWR
ISO7230MDWRG4
ISO7231CDW
40 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
ISO7231CDWG4
ISO7231CDWR
ISO7231CDWRG4
ISO7231MDW
40 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
ISO7231MDWG4
ISO7231MDWR
ISO7231MDWRG4
40 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
2-Jun-2008
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jun-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
ISO7230CDWR
ISO7230MDWR
ISO7231CDWR
ISO7231MDWR
SOIC
SOIC
SOIC
SOIC
DW
DW
DW
DW
16
16
16
16
2000
2000
2000
2000
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
10.9
10.9
10.9
10.9
10.78
10.78
10.78
10.78
3.0
3.0
3.0
3.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Jun-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ISO7230CDWR
ISO7230MDWR
ISO7231CDWR
ISO7231MDWR
SOIC
SOIC
SOIC
SOIC
DW
DW
DW
DW
16
16
16
16
2000
2000
2000
2000
358.0
358.0
358.0
358.0
335.0
335.0
335.0
335.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
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