ISO7641FMDW [TI]
Low Power Quad Channels Digital Isolators; 低功耗四通道数字隔离器
| 型号： | ISO7641FMDW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Low Power Quad Channels Digital Isolators |
| 文件： | 总29页 (文件大小：956K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISO7640FM
ISO7641FM
www.ti.com
SLLSE89D –SEPTEMBER 2011–REVISED JULY 2012
Low Power Quad Channels Digital Isolators
Check for Samples: ISO7640FM, ISO7641FM
1
FEATURES
APPLICATIONS
•
•
Signaling Rate: 150 Mbps
•
Optocoupler Replacement in:
Low Power Consumption, Typical ICC per
Channel (3.3 V Supplies):
–
Industrial Fieldbus
–
–
–
Profibus
–
–
ISO7640FM: 2 mA at 25 Mbps
ISO7641FM: 2.4 mA at 25 Mbps
Modbus
DeviceNetTM Data Buses
•
•
•
•
•
•
Low Propagation Delay: 7 ns Typical
Output Defaults to Low-state in fail-safe mode
Wide Temperature Range: –40°C to 125°C
50 KV/µs Transient Immunity, Typical
Long Life with SiO2 Isolation barrier
–
–
–
–
Servo Control Interface
Motor Control
Power Supplies
Battery Packs
SAFETY AND REGULATORY
APPROVALS
Operates From 2.7V, 3.3 V and 5 V Supply and
Logic Levels
•
•
•
•
6000 VPK / 4243 VRMS for 1 Minute per UL 1577
(approved)
•
Wide Body SOIC-16 Package
VDE Approval for DIN EN 60747-5-2 (VDE 0884
Rev. 2), 1414 VPK Working Voltage (approved)
CSA Component Acceptance Notice 5A, IEC
60601-1 Medical Standard (approved)
5 KVRMS Reinforced Insulation per TUV for
EN/UL/CSA 60950-1 and EN/UL/CSA 61010-1
(approved)
DESCRIPTION
ISO7640FM and ISO7641FM provide galvanic isolation up to 6 KVPK for 1 minute per UL and VDE. These
devices are also certified up to 5 KVRMS Reinforced isolation at a working voltage of 400 VRMS per end equipment
standards EN/UL/CSA 60950-1 and 61010-1. ISO7640F and ISO7641F are quad channel isolators; ISO7640F
has four forward and ISO7641F has three forward and one reverse direction channels. Suffix F indicates that
output defaults to Low-state in fail-safe conditions (see Table 1). M-Grade devices are high speed isolators
capable of 150 Mbps data rate with fast propagation delays
Spacer
ISO7640
ISO7641
VCC1
VCC2
VCC1
VCC2
1
2
16
15
1
2
16
15
GND2
OUTA
OUTB
OUTC
IND
GND1
GND2
OUTA
OUTB
OUTC
OUTD
EN
GND1
INA
INA
INB
INC
3
4
5
6
7
8
14
13
12
11
10
9
3
4
5
6
7
8
14
13
12
11
10
9
INB
INC
OUTD
EN1
IND
NC
EN2
GND1
GND1
GND2
GND2
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2012, Texas Instruments Incorporated
ISO7640FM
ISO7641FM
SLLSE89D –SEPTEMBER 2011–REVISED JULY 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION CONTINUED
Each isolation channel has a logic input and output buffer separated by a silicon dioxide (SiO2) insulation barrier.
Used in conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other
circuits from entering the local ground and interfering with or damaging sensitive circuitry. The devices have TTL
input thresholds and can operate from 2.7 V, 3.3 V and 5 V supplies. All inputs are 5 V tolerant when supplied
from 3.3 V or 2.7 V supplies.
PIN DESCRIPTIONS
PIN
I/O
DESCRIPTION
NAME
INA
ISO7640
ISO7641
3
4
3
4
I
I
Input, channel A
Input, channel B
Input, channel C
Input, channel D
Output, channel A
Output, channel B
Output, channel C
Output, channel D
INB
INC
5
5
I
IND
6
11
14
13
12
6
I
OUTA
OUTB
OUTC
OUTD
14
13
12
11
O
O
O
O
Enables (when input is High or Open) or Disables (when input is Low) OUTA, OUTB, OUTC
and OUTD of ISO7640
EN
10
-
-
I
I
I
EN1
EN2
7
Enables (when input is High or Open) or Disables (when input is Low) OUTD of ISO7641
Enables (when input is High or Open) or Disables (when input is Low) OUTA, OUTB, and
OUTC of ISO7641
-
10
VCC1
VCC2
GND1
GND2
NC
1
16
1
16
2,8
9,15
-
–
–
–
–
-
Power supply, VCC1
Power supply, VCC2
2,8
9,15
7
Ground connection for VCC1
Ground connection for VCC2
No Connect pins are floating with no internal connection
Table 1. FUNCTION TABLE(1)
INPUT
VCC
OUTPUT
VCC
INPUT
(INx)
OUTPUT ENABLE
(ENx)
OUTPUT
(OUTx)
H
L
H or Open
H
L
Z
L
L
Z
Z
H or Open
PU
PU
X
L
Open
X
H or Open
PD
PD
PU
PU
PU
PD
H or Open
X
L
X
X
(1) PU = Powered Up(VCC ≥ 2.7 V); PD = Powered Down (VCC ≤ 2.1 V); X = Irrelevant; H = High Level; L
= Low Level; Z = High Impedance
2
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Product Folder Link(s): ISO7640FM ISO7641FM
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ISO7641FM
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SLLSE89D –SEPTEMBER 2011–REVISED JULY 2012
AVAILABLE OPTIONS
RATED
ISOLATION
INPUT
THRESHOLD
DATA RATE
and FILTER
CHANNEL
DIRECTION
MARKED
AS
ORDERING
NUMBER
PRODUCT
PACKAGE
ISO7640FMDW (rail)
ISO7640FMDWR (reel)
ISO7641FMDW (rail)
ISO7641FMDWR (reel)
4 Forward,
0 Reverse
ISO7640FM
ISO7640FM
ISO7641FM
1.5 V TTL
(CMOS
Compatible)
6 KVPK
5 KVRMS
/
150 Mbps,
No Noise Filter
DW-16
(1)
3 Forward,
1 Reverse
ISO7641FM
(1) See the Regulatory Information table for detailed isolation ratings.
ABSOLUTE MAXIMUM RATINGS(1)
VALUE
PARAMETER
UNIT
MIN
–0.5
–0.5
MAX
6
Supply voltage(2)
Voltage
VCC1, VCC2
V
V
INx, OUTx, ENx
6
Output Current, IO
±15
±4
mA
kV
Human Body Model
ESDA, JEDEC JS-001-2012
JEDEC JESD22-C101E
JEDEC JESD22-A115-A
Field-Induced Charged Device
Model
Electrostatic discharge
All pins
±1.5
kV
Machine Model
±200
150
V
Maximum junction temperature, TJ
Storage temperature, TSTG
°C
°C
-65
150
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GND1 or GND2) and are peak
voltage values.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
MIN
2.7
-4
TYP
MAX
UNIT
V
Supply voltage
VCC1, VCC2
5.5
High-level output current
Low-level output current
High-level input voltage
Low-level input voltage
IOH
IOL
VIH
VIL
mA
mA
V
4
VCC
0.8
2
0
V
≥3V-Operation
<3V-Operation
≥3V-Operation
<3V-Operation
6.67
10
0
Input pulse duration
Signaling rate
tui
ns
150
100
136
125
1 / tui
Mbps
0
Junction temperature
Ambient temperature
TJ
-40
-40
°C
°C
TA
25
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SLLSE89D –SEPTEMBER 2011–REVISED JULY 2012
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UNITS
THERMAL INFORMATION
ISO76xx
THERMAL METRIC(1)
DW (16 Pins)
θJA
Junction-to-ambient thermal resistance
72
38
θJC(top)
θJB
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
39
°C/W
mW
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
9.4
n/a
n/a
ψJB
θJC(bottom)
VCC1 = VCC2 = 5.5V, TJ = 150°C, CL = 15pF
PD
Maximum Device Power Dissipation
399
Input a 75 MHz 50% duty cycle square wave
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
ELECTRICAL CHARACTERISTICS
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VCCx(1) – 0.8
VCCx(1) – 0.1
TYP
4.8
5
MAX
UNIT
IOH = –4 mA; see Figure 1
VOH
High-level output voltage
V
IOH = –20 μA; see Figure 1
IOL = 4 mA; see Figure 1
IOL = 20 μA; see Figure 1
0.2
0
0.4
0.1
VOL
Low-level output voltage
V
mV
VI(HYS)
IIH
Input threshold voltage hysteresis
High-level input current
450
VIH = VCC at INx or ENx
VIL = 0 V at INx or ENx
10
μA
IIL
Low-level input current
-10
25
CMTI
Common-mode transient immunity VI = VCC or 0 V; see Figure 4
75
kV/μs
(1) VCCx is the supply voltage, VCC1 or VCC2, for the output channel that is being measured.
SWITCHING CHARACTERISTICS
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH, tPHL
PWD(1)
Propagation delay time
3.5
7
10.5
2
See Figure 1
Pulse width distortion |tPHL – tPLH
|
Same-direction Channels
2
ns
(2)
tsk(o)
Channel-to-channel output skew time
Opposite-direction Channels
3
(3)
tsk(pp)
Part-to-part skew time
Output signal rise time
Output signal fall time
4.5
tr
tf
1.6
1
See Figure 1
ns
Disable Propagation Delay, high-to-high
impedance output
tPHZ
tPLZ
tPZH
tPZL
tfs
5
5
16
16
16
16
Disable Propagation Delay, low-to-high
impedance output
See Figure 2
See Figure 3
ns
Enable Propagation Delay, high impedance-to-
high output
4
Enable Propagation Delay, high impedance-to-
low output
4
Fail-safe output delay time from input data or
power loss
9.5
μs
(1) Also known as Pulse Skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
4
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Product Folder Link(s): ISO7640FM ISO7641FM
ISO7640FM
ISO7641FM
www.ti.com
SLLSE89D –SEPTEMBER 2011–REVISED JULY 2012
SUPPLY CURRENT
VCC1 and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
ISO7640FM
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC1
0.6
4.5
0.7
4.6
1.1
6.6
1.9
9.7
8.2
35
1.2
6.6
1.3
6.7
2
Disable
EN = 0 V
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
DC to 1 Mbps
10 Mbps
mA
DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with square wave clock
input; CL = 15 pF
10.5
3
25 Mbps
14.7
14.5
58
150 Mbps
ISO7641FM
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
2.6
4.2
2.7
4.3
3.6
6
4.2
6.8
4.3
6.9
4.9
8.2
6.6
11.4
22
Disable
EN1 = EN2 = 0 V
DC to 1 Mbps
10 Mbps
mA
DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with square wave clock
input; CL = 15 pF
5.1
8.8
17
25 Mbps
150 Mbps
31
42
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ELECTRICAL CHARACTERISTICS
VCC1 at 5 V ± 10% and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VCC1 – 0.8
VCC2 - 0.4
VCC1 – 0.1
VCC2 – 0.1
TYP
4.8
3
MAX
UNIT
IOH = –4 mA; see
Figure 1
OUTx on VCC1 (5V) side
OUTx on VCC2 (3.3V) side
OUTx on VCC1 (5V) side
OUTx on VCC2 (3.3V) side
VOH
High-level output voltage
V
IOH = –20 μA; see
Figure 1
5
3.3
0.2
0
IOL = 4 mA; see Figure 1
0.4
0.1
VOL
Low-level output voltage
V
IOL = 20 μA; see Figure 1
VI(HYS)
Input threshold voltage
hysteresis
430
mV
IIH
IIL
High-level input current
Low-level input current
VIH = VCC at INx or ENx
VIL = 0 V at INx or ENx
10
μA
-10
25
Common-mode transient
immunity
CMTI
VI = VCC or 0 V; see Figure 4
50
kV/μs
SWITCHING CHARACTERISTICS
VCC1 at 5 V ± 10% and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH, tPHL
PWD(1)
Propagation delay time
4
8
13
2
See Figure 1
Pulse width distortion |tPHL – tPLH
|
Same-direction Channels
2.5
3.5
6
ns
(2)
tsk(o)
Channel-to-channel output skew time
Opposite-direction Channels
(3)
tsk(pp)
Part-to-part skew time
Output signal rise time
Output signal fall time
tr
tf
2
See Figure 1
ns
1.2
Disable Propagation Delay, high-to-high
impedance output
tPHZ
tPLZ
tPZH
tPZL
tfs
6.5
6.5
5.5
5.5
9.5
17
17
17
17
Disable Propagation Delay, low-to-high
impedance output
See Figure 2
See Figure 3
ns
Enable Propagation Delay, high impedance-to-
high output
Enable Propagation Delay, high impedance-to-
low output
Fail-safe output delay time from input data or
power loss
μs
(1) Also known as Pulse Skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
6
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Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): ISO7640FM ISO7641FM
ISO7640FM
ISO7641FM
www.ti.com
SLLSE89D –SEPTEMBER 2011–REVISED JULY 2012
SUPPLY CURRENT
VCC1 at 5 V ± 10% and VCC2 at 3.3V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISO7640FM
ICC1
0.6
3.6
0.7
3.7
1.1
5
1.2
5.1
1.3
5.2
2
Disable
EN = 0 V
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
DC to 1 Mbps
10 Mbps
mA
DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with square wave clock input; CL
= 15 pF
7.1
3
1.9
6.9
8.2
24
25 Mbps
11
14.5
40
150 Mbps
ISO7641FM
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
2.6
3.2
2.7
3.3
3.6
4.4
5.1
6.1
17
4.2
4.9
4.3
5
Disable
EN1 = EN2 = 0 V
DC to 1 Mbps
10 Mbps
4.9
5.8
6.6
7.6
22
mA
DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with square wave clock input; CL
= 15 pF
25 Mbps
150 Mbps
20.6
26.5
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ELECTRICAL CHARACTERISTICS
VCC1 at 3.3 V ± 10% and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VCC1–0.4
VCC2–0.8
VCC1–0.1
VCC2–0.1
TYP
MAX UNIT
IOH = –4 mA; see Figure 1
OUTx on VCC1 (3.3 V) side
3
OUTx on VCC2 (5 V) side
OUTx on VCC1 (3.3 V) side
OUTx on VCC2 (5 V) side
4.8
3.3
5
VOH
High-level output voltage
V
IOH = –20 μA; see Figure 1
IOL = 4 mA; see Figure 1
0.2
0
0.4
V
0.1
VOL
Low-level output voltage
IOL = 20 μA; see Figure 1
VI(HYS)
IIH
Input threshold voltage hysteresis
High-level input current
430
mV
VIH = VCC at INx or ENx
VIL = 0 V at INx or ENx
VI = VCC or 0 V; see Figure 4
10
μA
IIL
Low-level input current
-10
25
CMTI
Common-mode transient immunity
50
kV/μs
SWITCHING CHARACTERISTICS
VCC1 at 3.3 V ± 10% and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH, tPHL
PWD(1)
Propagation delay time
4
7.5
12.5
2
See Figure 1
Pulse width distortion |tPHL – tPLH
|
Same-direction Channels
2.5
3.5
6
ns
(2)
tsk(o)
Channel-to-channel output skew time
Opposite-direction Channels
(3)
tsk(pp)
Part-to-part skew time
Output signal rise time
Output signal fall time
tr
tf
1.7
1.1
See Figure 1
ns
Disable Propagation Delay, high-to-high impedance
output
tPHZ
tPLZ
tPZH
tPZL
tfs
5.5
5.5
4.5
4.5
9.5
17
17
17
17
Disable Propagation Delay, low-to-high impedance
output
See Figure 2
See Figure 3
ns
Enable Propagation Delay, high impedance-to-high
output
Enable Propagation Delay, high impedance-to-low
output
Fail-safe output delay time from input data or power
loss
μs
(1) Also known as Pulse Skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
8
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Product Folder Link(s): ISO7640FM ISO7641FM
ISO7640FM
ISO7641FM
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SLLSE89D –SEPTEMBER 2011–REVISED JULY 2012
SUPPLY CURRENT
VCC1 at 3.3 V ± 10% and VCC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISO7640FM
ICC1
0.35
4.5
0.4
4.6
0.7
6.6
1.1
9.7
5
0.7
6.6
0.8
6.7
1.2
10.5
2
Disable
EN = 0 V
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
DC to 1 Mbps
10 Mbps
mA
DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with square wave clock input; CL
15 pF
=
25 Mbps
14.7
8.5
58
150 Mbps
35
ISO7641FM
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
1.9
4.2
2
2.9
6.8
3
Disable
EN1 = EN2 = 0 V
DC to 1 Mbps
10 Mbps
4.3
2.5
6
6.9
3.5
8.2
4.5
11.4
14.5
42
mA
DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with square wave clock input; CL
15 pF
=
3.4
8.8
10.5
31
25 Mbps
150 Mbps
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ELECTRICAL CHARACTERISTICS
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VCCx(1) – 0.4
VCCx(1) – 0.1
TYP
3
MAX
UNIT
IOH = –4 mA; see Figure 1
VOH
High-level output voltage
V
IOH = –20 μA; see Figure 1
IOL = 4 mA; see Figure 1
IOL = 20 μA; see Figure 1
3.3
0.2
0
0.4
0.1
VOL
Low-level output voltage
V
VI(HYS)
Input threshold voltage
hysteresis
425
mV
IIH
IIL
High-level input current
Low-level input current
VIH = VCC at INx or ENx
VIL = 0 V at INx or ENx
10
μA
-10
25
Common-mode transient
immunity
CMTI
VI = VCC or 0 V; see Figure 4
50
kV/μs
(1) VCCx is the supply voltage, VCC1 or VCC2, for the output channel that is being measured.
SWITCHING CHARACTERISTICS
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
14
2
UNIT
tPLH, tPHL
PWD(1)
Propagation delay time
4
8.5
See Figure 1
Pulse width distortion |tPHL – tPLH
|
Same-direction Channels
3
ns
(2)
tsk(o)
Channel-to-channel output skew time
Opposite-direction Channels
4
(3)
tsk(pp)
Part-to-part skew time
Output signal rise time
Output signal fall time
6.5
tr
tf
2
See Figure 1
ns
1.3
Disable Propagation Delay, high-to-high
impedance output
tPHZ
tPLZ
tPZH
tPZL
tfs
6.5
6.5
5.5
5.5
9.2
17
17
17
17
Disable Propagation Delay, low-to-high impedance
output
See Figure 2
See Figure 3
ns
Enable Propagation Delay, high impedance-to-high
output
Enable Propagation Delay, high impedance-to-low
output
Fail-safe output delay time from input data or
power loss
μs
(1) Also known as Pulse Skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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SUPPLY CURRENT
VCC1 and VCC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISO7640FM
ICC1
0.35
3.6
0.4
3.7
0.7
5
0.7
5.1
0.8
5.2
1.2
7.1
2
Disable
EN = 0 V
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
DC to 1 Mbps
10 Mbps
mA
DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with square wave clock input; CL
15 pF
=
1.1
6.9
5
25 Mbps
11
8.5
40
150 Mbps
24
ISO7641FM
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
1.9
3.2
2
2.9
4.9
3
Disable
EN1 = EN2 = 0 V
DC to 1 Mbps
10 Mbps
3.3
2.5
4.4
3.4
6.1
10.5
20.6
5
3.5
5.8
4.5
7.6
14.5
26.5
mA
DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with square wave clock input; CL
15 pF
=
25 Mbps
150 Mbps
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ELECTRICAL CHARACTERISTICS
VCC1 and VCC2 at 2.7 V(1) (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VCC(2) – 0.5
VCC(2) – 0.1
TYP MAX
UNIT
IOH = –4 mA; see Figure 1
2.4
2.7
0.2
0
VOH
High-level output voltage
V
IOH = –20 μA; see Figure 1
IOL = 4 mA; see Figure 1
IOL = 20 μA; see Figure 1
0.4
0.1
VOL
Low-level output voltage
V
mV
VI(HYS)
IIH
Input threshold voltage hysteresis
High-level input current
350
VIH = VCC at INx or ENx
VIL = 0 V at INx or ENx
VI = VCC or 0 V; see Figure 4
10
μA
IIL
Low-level input current
-10
25
CMTI
Common-mode transient immunity
50
kV/μs
(1) For 2.7 V-operation, max data rate is 100 Mbps.
(2) VCCx is the supply voltage, VCC1 or VCC2, for the output channel that is being measured.
SWITCHING CHARACTERISTICS
VCC1 and VCC2 at 2.7 V (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
16
2.5
4
UNIT
tPLH, tPHL
PWD(1)
Propagation delay time
5
8
See Figure 1
Pulse width distortion |tPHL – tPLH
|
Same-direction Channels
ns
(2)
tsk(o)
Channel-to-channel output skew time
Opposite-direction Channels
5
(3)
tsk(pp)
Part-to-part skew time
Output signal rise time
Output signal fall time
8
tr
tf
2.3
1.8
See Figure 1
ns
Disable Propagation Delay, high-to-high
impedance output
tPHZ
tPLZ
tPZH
tPZL
tfs
8
8
18
18
18
18
Disable Propagation Delay, low-to-high
impedance output
See Figure 2
See Figure 3
ns
Enable Propagation Delay, high impedance-to-
high output
7
Enable Propagation Delay, high impedance-to-
low output
7
Fail-safe output delay time from input data or
power loss
8.5
μs
(1) Also known as Pulse Skew.
(2) tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same
direction while driving identical loads.
(3) tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same
direction while operating at identical supply voltages, temperature, input signals and loads.
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SUPPLY CURRENT
VCC1 and VCC2 at 2.7 V (over recommended operating conditions unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISO7640FM
ICC1
0.2
3.3
0.2
3.4
0.4
4.4
0.8
6
0.6
5
Disable
EN = 0 V
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
0.7
5.1
1.1
6.8
1.8
9.5
5
DC to 1 Mbps
10 Mbps
mA
DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with square wave clock input; CL
15 pF
=
25 Mbps
2.7
14.2
100 Mbps
21
ISO7641FM
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
ICC1
ICC2
1.6
2.8
1.7
2.9
2.1
3.8
2.8
5.2
6.4
11.8
2.4
4.1
2.5
4.2
3
Disable
EN1 = EN2 = 0 V
DC to 1 Mbps
10 Mbps
mA
DC Signal: VI = VCC or 0 V,
AC Signal: All channels switching with square wave clock input; CL
15 pF
5
=
3.8
6.7
7.5
15.5
25 Mbps
100 Mbps
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PARAMETER MEASUREMENT INFORMATION
V
CC1
V
I
V
/2
V
/2
CC
CC
IN
OUT
0 V
t
t
Input
Generator
NOTE A
PLH
PHL
V
O
V
50 W
V
OH
C
L
I
90%
10%
V
50%
50%
O
NOTE
B
V
OL
t
t
f
r
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3
ns, tf ≤ 3ns, ZO = 50 Ω. At the input, 50 Ω resistor is required to terminate Input Generator signal. It is not needed in
actual application.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 1. Switching Characteristics Test Circuit and Voltage Waveforms
V
CC
V
CC
R = 1 kW
L
±1%
V
/2
CC
V
/2
CC
V
V
I
0 V
IN
OUT
t
t
V
O
PLZ
PZL
0V
V
CC
0.5 V
V
50%
EN
O
C
L
OL
NOTE
B
Input
V
I
Generator
NOTE A
50 W
V
CC
V
V
/2
V
/2
O
CC
IN
CC
OUT
V
V
I
3V
0 V
V
t
EN
PZH
C
OH
L
R = 1 kW
±1%
L
NOTE
B
50%
Input
Generator
NOTE A
0.5 V
O
V
I
50 W
0 V
t
PHZ
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 10 kHz, 50% duty cycle,
tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω.
B. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 2. Enable/Disable Propagation Delay Time Test Circuit and Waveform
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PARAMETER MEASUREMENT INFORMATION (continued)
V
I
V
V
CC
CC
2.7 V
V
I
0 V
V
OUT
t
V
IN = V
fs
O
CC
OH
50%
V
O
C
fs low
L
V
OL
NOTE A
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 3. Failsafe Delay Time Test Circuit and Voltage Waveforms
V
V
CC1
CC2
C = 0.1 mF 1ꢀ
C = 0.1 mF 1ꢀ
Pass/Fail Criterion –
the output must
remain stable.
OUT
IN
S1
C
L
NOTE A
V
or V
OL
OH
GND1
GND2
V
TEST
A. CL = 15 pF and includes instrumentation and fixture capacitance within ±20%.
Figure 4. Common-Mode Transient Immunity Test Circuit
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DEVICE INFORMATION
IEC INSULATION AND SAFETY-RELATED SPECIFICATIONS FOR DW-16 PACKAGE
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
L(I01)
Minimum air gap (Clearance)
Shortest terminal to terminal distance through air
8.3
mm
Minimum external tracking
(Creepage)
Shortest terminal to terminal distance across the
package surface
L(I02)(1)
8.1
≥400
0.014
mm
V
Tracking resistance (Comparative
Tracking Index)
CTI
DIN IEC 60112 / VDE 0303 Part 1
Distance through the insulation
Minimum Internal Gap (Internal
Clearance)
mm
VIO = 500 V, TA < 100°C
>1012
>1011
Isolation resistance, Input to
Output
(2)
RIO
Ω
VIO = 500 V, 100°C ≤ TA ≤ max
VI = 0.4 sin (2πft), f = 1MHz
Barrier capacitance, Input to
Output
(2)
CIO
2
2
pF
pF
CI(3)
Input capacitance
VI = VCC/2 + 0.4 sin (2πft), f = 1MHz, VCC = 5 V
(1) Per JEDEC package dimensions.
(2) All pins on each side of the barrier tied together creating a two-terminal device.
(3) Measured from input pin to ground.
spacer
NOTE
Creepage and clearance requirements should be applied according to the specific
equipment isolation standards of an application. Care should be taken to maintain the
creepage and clearance distance of a board design to ensure that the mounting pads of
the isolator on the printed circuit board do not reduce this distance.
Creepage and clearance on a printed circuit board become equal according to the
measurement techniques shown in the Isolation Glossary. Techniques such as inserting
grooves and/or ribs on a printed circuit board are used to help increase these
specifications.
DIN EN 60747-5-2 (VDE 0884 TEIL 2) INSULATION CHARACTERISTICS(4)
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SPECIFICATION
UNIT
(1)
VIORM
Maximum working insulation voltage
1414
VPEAK
After Input/Output safety test subgroup 2/3,
VPR = VIORM x 1.2, t = 10 s,
Partial discharge < 5 pC
1697
2262
2652
6000
Method a, After environmental tests subgroup 1,
VPR = VIORM x 1.6, t = 10 s,
Partial Discharge < 5 pC
VPR
Input-to-output test voltage
VPEAK
Method b1, 100% Production test
VPR = VIORM x 1.875, t = 1 s
Partial discharge < 5 pC
VTEST = VIOTM
t = 60 sec (Qualification)
t = 1 sec (100% Production)
VIOTM
RS
Maximum transient overvoltage
VPEAK
Insulation resistance
Pollution degree
VIO = 500 V at TS
>109
2
Ω
(4) Climatic Classification 40/125/21
(1) For applications that require DC working voltages between GND1 and GND2, please contact Texas Instruments for further details.
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IEC 60664-1 RATINGS TABLE
PARAMETER
TEST CONDITIONS
SPECIFICATION
Basic Isolation Group
Material Group
II
Rated mains voltage ≤ 300 VRMS
Rated mains voltage ≤ 600 VRMS
Rated mains voltage ≤ 1000 VRMS
I–IV
I–III
I–II
Installation classification
REGULATORY INFORMATION
VDE
TUV
CSA
UL
Certified according to DIN EN Certified according to
Approved under CSA Component Recognized under 1577 Component
60747-5-2
EN/UL/CSA 60950-1 and 61010- Acceptance Notice #5A Recognition Program
1
Basic Insulation
5000 VRMS Reinforced Insulation,
400 VRMS maximum working
voltage
5000 VRMS Basic Insulation, 600
VRMS maximum working voltage
5000 VRMS Reinforced Insulation
Maximum Transient
Overvoltage, 6000 VPK
Maximum Working Voltage,
1414 VPK
2 Means of Patient Protection at
(1)
Single Protection, 4243 VRMS
125 VRMS per IEC 60601-1 (3rd
Ed.)
File Number: 40016131
Certificate Number: U8V 11 08
77311 005
File Number: 220991
File Number: E181974
(1) Production tested ≥ 5092 VRMS for 1 second in accordance with UL 1577.
IEC SAFETY LIMITING VALUES
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry.
A failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate
sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system
failures.
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
θJA = 72 °C/W, VI = 5.5V, TJ = 150°C, TA = 25°C
θJA = 72 °C/W, VI = 3.6V, TJ = 150°C, TA = 25°C
θJA = 72 °C/W, VI = 2.7V, TJ = 150°C, TA = 25°C
316
Safety input, output, or supply
current
IS
DW-16
482
643
150
mA
°C
TS Maximum case temperature
The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum
ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the
application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the
Thermal Information table is that of a device installed on a High-K Test Board for Leaded Surface Mount
Packages. The power is the recommended maximum input voltage times the current. The junction temperature is
then the ambient temperature plus the power times the junction-to-air thermal resistance.
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700
600
VCC1 = VCC2 = 2.7V
500
VCC1 = VCC2 = 3.6V
400
300
VCC1 = VCC2 = 5.5V
200
100
0
0
50
100
150
200
Case Temperature - oC
Figure 5. DW-16 θJC Thermal Derating Curve per IEC 60747-5-2
APPLICATION INFORMATION
2 mm
2 mm
V
V
CC1
max. from
max. from
CC2
V
V
CC2
CC1
ISO7640
0.1 mF
0.1 mF
1
16
15
GND1
2
3
4
5
6
7
8
GND2
OUTA
OUTB
OUTC
OUTD
14
13
12
11
10
9
INA
INB
INC
IND
EN
NC
GND 2
GND1
2 mm
2 mm
V
V
CC1
max. from
max. from
CC2
V
V
CC2
CC1
ISO7641
0.1 mF
0.1 mF
1
16
15
2
3
4
5
6
7
8
GND1
GND2
OUTA
OUTB
OUTC
IND
14
13
12
11
10
9
INA
INB
INC
OUTD
EN2
EN1
GND 2
GND1
Figure 6. Typical ISO7640FM and ISO7641FM Application Circuit
Note: For detailed layout recommendations, see Application Note SLLA284, Digital Isolator Design Guide.
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TYPICAL SUPPLY CURRENT EQUATIONS
(Calculated based on room temperature and typical Silicon process)
ISO7640FM:
At VCC1 = VCC2 = 3.3V
ICC1 = 0.388 + 0.0312 x f
ICC2 = 3.39 + 0.03561 x f + 0.006588 x f x CL
At VCC1 = VCC2 = 5V
ICC1 = 0.584 + 0.05349 x f
ICC2 = 4.184 + 0.05597 x f + 0.009771 x f x CL
ISO7641FM:
At VCC1 = VCC2 = 3.3V
ICC1 = 1.848 + 0.03233 x f + 0.001645 x f x CL
ICC2 = 3.005 + 0.03459 x f + 0.0049395 x f x CL
At VCC1 = VCC2 = 5V
ICC1 = 2.369 + 0.05385 x f + 0.002448 x f x CL
ICC2 = 3.857 + 0.05506 x f + 0.007348 x f x CL
ICC1 and ICC2 are typical supply currents measured in mA; f is data rate measured in Mbps; CL is the capacitive
load on each channel measured in pF.
Enable
Input
Output
V
CC
V
V
V
V
V
CC
CC
CC
CC
CC
1 MW
8 W
500 W
500 W
EN
IN
OUT
13 W
1 MW
Figure 7. Device I/O Schematics
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TYPICAL CHARACTERISTICS
10
40
ICC1 at 3.3 V
ICC1 at 5 V
ICC1 at 3.3 V
ICC1 at 5 V
9
35
30
25
20
15
10
5
ICC2 at 3.3 V
8
ICC2 at 5 V
ICC2 at 3.3 V
ICC2 at 3.3 V
7
6
5
4
3
2
1
0
TA = 25°C
CL = 15 pF
TA = 25°C
CL = 15 pF
0
0
25
50
75
Data Rate (Mbps)
100
125
150
0
25
50
75
Data Rate (Mbps)
100
125
150
G001
G002
Figure 8. ISO7640FM Supply Current Per Channel
vs Data Rate
Figure 9. ISO7640FM Supply Current For All Channels
vs Data Rate
9
8
7
6
5
4
3
2
1
0
40
ICC1 at 3.3 V
ICC1 at 5 V
ICC1 at 3.3 V
ICC1 at 5 V
ICC2 at 3.3 V
ICC2 at 5 V
35
30
25
20
15
10
5
ICC2 at 3.3 V
ICC2 at 3.3 V
TA = 25°C
CL = 15 pF
TA = 25°C
CL = 15 pF
0
0
25
50
75
Data Rate (Mbps)
100
125
150
0
25
50
75
Data Rate (Mbps)
100
125
150
G003
G002
Figure 10. ISO7641FM Supply Current Per Channel
vs Data Rate
Figure .
6
6
VCC = 5 V
VCC = 3.3 V
TA = 25°C
VCC = 3.3 V
VCC = 5 V
TA = 25°C
5
4
3
2
1
0
5
4
3
2
1
0
−70
−60
−50
−40
−30
−20
−10
0
0
10
20
30
40
50
60
70
High−Level Output Current (mA)
Low−Level Output Current (mA)
G005
G006
Figure 11. High-Level Output Voltage
vs High-Level Output Current
Figure 12. Low-Level Output Voltage
vs Low-Level Output Current
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TYPICAL CHARACTERISTICS (continued)
2.52
11
10
9
tPLH at 3.3 V
tPHL at 3.3 V
tPHL at 5 V
tPLH at 5 V
2.5
2.48
2.46
2.44
2.42
2.4
VCC Rising
VCC Falling
8
7
2.38
2.36
CL = 15 pF
110 135 150
6
−40
−40
−20
0
20
40
60
80
100
120
−15
10
35
60
85
Free−Air Temperature (°C)
Free−Air Temperature (°C)
G007
G008
Figure 13. VCC Undervoltage Threshold
vs Free Air Temperature
Figure 14. Propagation Delay Time
vs Free Air Temperature
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
TA = 25°C
CL = 15 pF
All Channels Switching
VCC = 5 V
VCC = 3.3 V
0.1
0
Typ Jitter on output pin shown
0
20
40
60
80 100 120 140 160 180
Data Rate (Mbps)
G009
Figure 15. Output Jitter vs Data Rate
TA = 25oC, CL = 15 pF
VCC1 = VCC2 = 5 V
Pattern: NRZ 216-1
TA = 25oC, CL = 15 pF
VCC1 = VCC2 = 3.3 V
Pattern: NRZ 216-1
Figure 16. Typical Eye Diagram at 150 Mbps,
5 V Operation
Figure 17. Typical Eye Diagram at 150 Mbps,
3.3 V Operation
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REVISION HISTORY
Changes from Original (September 2011) to Revision A
Page
•
•
Changed Figure 3 - From: 0 V or VCC To: IN = VCC ........................................................................................................... 15
Added Note (1) "Per JEDEC package dimensions" to the IEC INSULATION AND SAFETY-RELATED
SPECIFICATIONS FOR DW-16 PACKAGE table .............................................................................................................. 16
•
•
•
Changed L(I01) Min Value From: 8 mm To: 8.3 mm .......................................................................................................... 16
Changed L(I02) Min Value From: 7.8 mm To: 8.1 mm ....................................................................................................... 16
Added pinout for ISO7641 and ISO7631 to Figure 6 ......................................................................................................... 18
Changes from Revision A (October 2011) to Revision B
Page
•
•
Changed feature bullet From: ISO7641FC: 1.2 mA at 10 Mbps To: ISO7641FC: 1.3 mA at 10 Mbps ............................... 1
Changed Safety and Regulatory Approvals bullet From: 6 KVPK for 1 Minute per UL1577 and VDE (Pending) To:
6000 VPK / 4243 VRMS for 1 Minute per UL 1577 (pending) .................................................................................................. 1
•
•
Changed Safety and Regulatory Approvals bullet From: To: 6000 VPK / 4243 VRMS for 1 Minute per UL 1577
(approved) ............................................................................................................................................................................. 1
Changed Safety and Regulatory Approvals bullet From: CSA Component Acceptance Notice 5A, IEC 60601-1
Medical Standard (pending) To: CSA Component Acceptance Notice 5A, IEC 60601-1 Medical Standard (approved) ..... 1
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Changed all the ELECTRICAL CHARACTERISTICS tables ................................................................................................ 4
Changed all the SWITCHING CHARACTERISTICS tables ................................................................................................. 4
Changed the SWITCHING CHARACTERISTICS table ISO7640F and ISO7641F C-Grade values ................................... 5
Changed the SWITCHING CHARACTERISTICS table ISO7640F and ISO7641F C-Grade values ................................... 7
Changed the SWITCHING CHARACTERISTICS table ISO7640F and ISO7641F C-Grade values ................................... 9
Changed the SWITCHING CHARACTERISTICS table ISO7640F and ISO7641F C-Grade values ................................. 11
Changed the SWITCHING CHARACTERISTICS table ISO7640F and ISO7641F C-Grade values ................................. 13
Changed the IEC 60664-1 Ratings Table ........................................................................................................................... 17
Changes from Revision B (December 2011) to Revision C
Page
•
•
Changed Safety and Regulatory Approvals bullet From: 6000 VPK / 4243 VRMS for 1 Minute per UL1577 (pending)
To: 6000 VPK / 4243 VRMS for 1 Minute per UL 1577 (approved) ......................................................................................... 1
Changed Description text From: The devices have TTL input thresholds and can operate from 2.7 V, 3.3 V and 5 V
supplies. To: The devices have TTL input thresholds and can operate from 2.7 V (M-Grade), 3.3 V and 5 V
supplies. ................................................................................................................................................................................ 2
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Deleted the Product Preview Note From the Available Options Table ................................................................................. 3
Changed the ESD standards ................................................................................................................................................ 3
Changed UL in the REGULATORY INFORMATION Table From: File Number: E181974 (Approval Pending) To: File
Number: E181974 ............................................................................................................................................................... 17
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Changed the typical characteristics section ........................................................................................................................ 20
22
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Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Link(s): ISO7640FM ISO7641FM
ISO7640FM
ISO7641FM
www.ti.com
SLLSE89D –SEPTEMBER 2011–REVISED JULY 2012
Changes from Revision C (January 2012) to Revision D
Page
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Deleted devices: ISO7631FM, ISO7631FC, ISO7640FC, ISO7641FC from the data sheet ............................................... 1
Changed the Title From: Low Power Triple and Quad Channels Digital Isolators To: Low Power Quad Channels
Digital Isolators ..................................................................................................................................................................... 1
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Deleted devices from the Features List ................................................................................................................................ 1
Changed the DESCRIPTION ................................................................................................................................................ 1
Changed EN1 and EN2 Pin Descriptions ............................................................................................................................. 2
Deleted device from the Available Options Table ................................................................................................................. 3
Changed the ELECTRICAL, SWITCHING, and SUPPLY CURRENT CHARACTERISTICS tables .................................... 4
Changed the ELECTRICAL, SWITCHING, and SUPPLY CURRENT CHARACTERISTICS tables .................................... 6
Changed the ELECTRICAL, SWITCHING, and SUPPLY CURRENT CHARACTERISTICS tables .................................... 8
Changed the ELECTRICAL, SWITCHING, and SUPPLY CURRENT CHARACTERISTICS tables .................................. 10
Changed the ELECTRICAL, SWITCHING, and SUPPLY CURRENT CHARACTERISTICS tables .................................. 12
Deleted devices from the TYPICAL SUPPLY CURRENT EQUATIONS section ............................................................... 19
Changed the TYPICAL CHARACTERISTICS section ........................................................................................................ 20
Copyright © 2011–2012, Texas Instruments Incorporated
Submit Documentation Feedback
23
Product Folder Link(s): ISO7640FM ISO7641FM
PACKAGE OPTION ADDENDUM
www.ti.com
15-May-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
ISO7640FMDW
ISO7640FMDWR
ISO7641FMDW
ISO7641FMDWR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
DW
DW
DW
DW
16
16
16
16
40
2000
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
Green (RoHS
& no Sb/Br)
2000
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
ISO7640FMDWR
ISO7641FMDWR
SOIC
SOIC
DW
DW
16
16
2000
2000
330.0
330.0
16.4
16.4
10.75 10.7
10.75 10.7
2.7
2.7
12.0
12.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
ISO7640FMDWR
ISO7641FMDWR
SOIC
SOIC
DW
DW
16
16
2000
2000
367.0
533.4
367.0
186.0
38.0
36.0
Pack Materials-Page 2
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