JM54AC299BRA-RH [TI]
AC SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP20, CERAMIC, DIP-20;
| 型号： | JM54AC299BRA-RH |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | AC SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP20, CERAMIC, DIP-20 CD 输出元件 逻辑集成电路 |
| 文件： | 总10页 (文件大小：210K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 1998
54AC299 • 54ACT299
8-Input Universal Shift/Storage Register with Common
Parallel I/O Pins
n Common parallel I/O for reduced pin count
General Description
n Additional serial inputs and outputs for expansion
The ’AC/’ACT299 is an 8-bit universal shift/storage register
n Four operating modes: shift left, shift right, load and
with TRI-STATE® outputs. Four modes of operation are pos-
store
sible: hold (store), shift left, shift right and load data. The par-
allel load inputs and flip-flop outputs are multiplexed to re-
duce the total number of package pins. Additional outputs
n TRI-STATE outputs for bus-oriented applications
n Outputs source/sink 24 mA
n ’ACT299 has TTL-compatible inputs
n Standard Microcircuit Drawing (SMD)
’AC299: 5962-88754
are provided for flip-flops Q0, Q7 to allow easy serial cascad-
ing. A separate active LOW Master Reset is used to reset the
register.
’ACT299: 5962-88771
Features
n ICC and IOZ reduced by 50%
Ordering Code:
Logic Symbols
Connection Diagrams
Pin Assignment
for DIP and Flatpak
DS100252-1
IEEE/IEC
DS100252-2
Pin Assignment for LCC
DS100252-3
DS100252-4
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FACT® is a registered trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100252
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Connection Diagrams (Continued)
Pin Names
CP
Description
Clock Pulse Input
DS0
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
DS7
S0, S1
MR
Asynchronous Master Reset
TRI-STATE Output Enable Inputs
Parallel Data Inputs or
OE1, OE2
I/O0–I/O7
TRI-STATE Parallel Outputs
Serial Outputs
Q0, Q7
Functional Description
Truth Table
The ’AC/’ACT299 contains eight edge-triggered D-type
flip-flops and the interstage logic necessary to perform syn-
chronous shift left, shift right, parallel load and hold opera-
tions. The type of operation is determined by S0 and S1, as
shown in the Truth Table. All flip-flop outputs are brought out
through TRI-STATE buffers to separate I/O pins that also
serve as data inputs in the parallel load mode. Q0 and Q7 are
also brought out on other pins for expansion in serial shifting
of longer words.
Inputs
Response
MR
S1
S0
CP
L
X
X
X
Asynchronous Reset;
=
Q0–Q7 LOW
N
N
→
H
H
H
L
H
H
Parallel Load; I/On
Qn
→
Shift Right; DS0
Q0,
→
Q0
Q1, etc.
A LOW signal on MR overrides the Select and CP inputs and
resets the flip-flops. All other state changes are initiated by
the rising edge of the clock. Inputs can change when the
clock is in either state provided only that the recommended
setup and hold times, relative to the rising edge of CP, are
observed.
N
→
Q7,
H
H
L
Shift Left, DS7
→
Q7
Q6, etc.
H
L
L
X
Hold
=
=
=
H
L
X
HIGH Voltage Level
LOW Voltage Level
Immaterial
A HIGH signal on either OE1 or OE2 disables the TRI-STATE
buffers and puts the I/O pins in the high impedance state. In
this condition the shift, hold, load and reset operations can
still occur. The TRI-STATE buffers are also disabled by HIGH
signals on both S0 and S1 in preparation for a parallel load
operation.
N =
LOW-to-HIGH Transition
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2
Logic Diagram
DS100252-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Recommended Operating
Conditions
Supply Voltage (VCC
)
(Unless Otherwise Specified)
Supply Voltage (VCC
)
−0.5V to +7.0V
’AC
2.0V to 6.0V
4.5V to 5.0V
0V to VCC
DC Input Diode Current (IIK
)
’ACT
=
VI −0.5V
−20 mA
+20 mA
Input Voltage (VI)
=
VI VCC +0.5V
Output Voltage (VO
)
0V to VCC
DC Input Voltage (VI)
−0.5V to VCC +0.5V
Operating Temperature (TA)
54AC/ACT
DC Output Diode Current (IOK
)
−55˚C to +125˚C
125 mV/ns
=
VO −0.5V
−20 mA
+20 mA
Minimum Input Edge Rate (∆V/∆t)
’AC Devices
=
VO VCC +0.5V
DC Output Voltage (VO
)
−0.5V to VCC +0.5V
% to 70% of V
VIN from 30
CC
DC Output Source or Sink Current
(IO
@
VCC 3.3V, 4.5V, 5.5V
±
)
50 mA
Minimum Input Edge Rate (∆V/∆t)
’ACT Devices
DC VCC or Ground Current
Per Output Pin (ICC or IGND
±
)
50 mA
VIN from 0.8V to 2.0V
Storage Temperature (TSTG
Junction Temperature (TJ)
CDIP
)
−65˚C to +150˚C
175˚C
@
VCC 4.5V, 5.5V
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. Obviously the databook specifications should be
met, without exception, to ensure that the system design is reliable over its
power supply, temperature, and output/input loading variables. National does
not recommend operation of FACT® circuits outside databook specifications.
DC Electrical Characteristics
For ’AC Family Devices
54AC
=
Symbol
Parameter
VCC
(V)
TA
Units
Conditions
−55˚C to +125˚C
Guaranteed Limits
=
VIH
Minimum High Level
Input Voltage
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
2.1
3.15
3.85
0.9
VOUT 0.1V
V
V
V
or VCC − 0.1V
=
VIL
Maximum Low Level
Input Voltage
VOUT 0.1V
1.35
1.65
2.9
or VCC − 0.1V
=
VOH
Minimum High Level
Output Voltage
IOUT −50 µA
4.4
5.4
(Note 2)
=
VIN VIL or VIH
=
IOH −12 mA
3.0
4.5
5.5
3.0
4.5
5.5
2.4
3.7
4.7
0.1
0.1
0.1
V
V
=
IOH −24 mA
=
IOH −24 mA
=
VOL
Maximum Low Level
Output Voltage
IOUT 50 µA
(Note 2)
=
VIN VIL or VIH
=
IOH 12 mA
3.0
4.5
5.5
5.5
0.50
0.50
0.50
=
IOH 24 mA
V
=
IOH 24 mA
=
±
IIN
Maximum Input
Leakage Current
1.0
µA
VI VCC, GND
Note 2: All outputs loaded; threshold on input associated with output under test.
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4
DC Electrical Characteristics
For ’AC Family Devices
54AC
=
Symbol
Parameter
VCC
(V)
TA
Units
Conditions
−55˚C to +125˚C
Guaranteed Limits
(Note 4)
=
VOLD 1.65V Max
IOLD
IOHD
ICC
Minimum Dynamic
Output Current
5.5
5.5
5.5
50
mA
mA
µA
=
VOHD 3.85V Min
−50
80.0
=
Maximum Quiescent
Supply Current
Maximum I/O
VIN VCC
or GND
=
IOZT
VI(OE) VIL, VIH
=
±
Leakage Current
5.5
5.5
µA
VI VCC, GND
=
VO VCC, GND
Note 3: All outputs loaded; threshold on input associated with output under test.
Note 4: Maximum test duration 20 ms, one output loaded at a time.
@
@
Note 5:
I
and I
CC
3.0V are guaranteed to be less than or equal to the respective limit 5.5V V .
IN
CC
@
@
I
for 54AC 25˚C is identical to 74AC 25˚C.
CC
DC Electrical Characteristics
For ’ACT Family Devices
54ACT
=
Symbol
Parameter
VCC
(V)
TA
−55˚C to +125˚C
Units
Conditions
Guaranteed Limits
=
VIH
Minimum High Level
Input Voltage
4.5
5.5
3.0
4.5
4.5
5.5
2.0
2.0
0.8
0.8
4.4
5.4
V
VOUT 0.1V
or VCC − 0.1V
=
VIL
Maximum Low Level
Input Voltage
VOUT 0.1V
or VCC − 0.1V
=
VOH
Minimum High Level
V
IOUT −50 µA
(Note 7)
=
VIN VIL or VIH
=
IOH −24 mA
4.5
5.5
4.5
5.5
3.70
4.70
0.1
V
V
=
IOH −24 mA
=
VOL
Maximum Low Level
Output Voltage
IOUT 50 µA
0.1
(Note 7)
=
VIN VIL or VIH
=
IOL 24 mA
4.5
5.5
5.5
0.50
0.50
V
=
IOL 24 mA
=
±
IIN
Maximum Input
Leakage Current
Maximum ICC/Input
(Note 8)
1.0
µA
mA
VI VCC, GND
=
VI VCC − 2.1V
ICCT
5.5
1.6
=
VOLD 1.65V Max
IOLD
IOHD
ICC
Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
Maximum I/O
5.5
5.5
5.5
50
mA
mA
µA
=
VOHD 3.85V Min
−50
80.0
=
VIN VCC
or GND
=
IOZT
VI(OE) VIL, VIH
=
±
Leakage Current
5.5
5.0
µA
VI VCC, GND
=
VO VCC, GND
5
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DC Electrical Characteristics (Continued)
@ @
I limit for 54ACT 25˚C is identical to 74ACT 25˚C.
CC
Note 6:
Note 7: All outputs loaded; thresholds on input associated with output under test.
Note 8: Maximum test duration 2.0 ms, one output loaded at a time.
Capacitance
Symbol
Parameter
Input Capacitance
Power Dissipation
Capacitance
Typ
4.5
Units
pF
Conditions
=
VCC 5.0V
CIN
CPD
=
170
pF
VCC 5.5V
AC Electrical Characteristics
54AC
=
VCC
(V)
TA −55˚C
Fig.
No.
Symbol
Parameter
to +125˚C
Units
MHz
ns
=
(Note 9)
CL 50 pF
Max
Min
70
fmax
Maximum Input
Frequency
3.3
5.0
3.3
5.0
80
tPLH
Propagation Delay
CP to Q0 or Q7
(Shift Left or Right)
Propagation Delay
CP to Q0 or Q7
(Shift Left or Right)
Propagation Delay
CP to I/On
1.0
1.0
25.5
17.5
tPHL
3.3
5.0
1.0
1.0
26.5
18.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPLH
tPHL
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
24.5
17.0
26.5
18.5
27.0
18.5
26.5
18.0
22.0
15.0
23.5
16.0
22.5
17.0
21.5
16.0
Propagation Delay
CP to I/On
Propagation Delay
MR to Q0 or Q7
Propagation Delay
MR to I/On
Output Enable Time
OE to I/On
Output Enable Time
OE to I/On
Output Disable Time
OE to I/On
Output Disable Time
OE to I/On
±
Note 9: Voltage Range 3.3 is 3.3V 0.3V.
±
Voltage Range 5.0 is 5.0V 0.5V.
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6
AC Operating Requirements
54AC
=
VCC
(V)
TA −55˚C
Fig.
No.
Symbol
Parameter
to +125˚C
Units
=
(Note 10)
CL 50 pF
Guaranteed
Minimum
9.5
ts
Setup Time, HIGH or LOW
S0 or S1 to CP
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
7.0
th
Hold Time, HIGH or LOW
S0 or S1 to CP
2.0
2.5
ts
Setup Time, HIGH or LOW
I/On to CP
6.0
4.0
th
Hold Time, HIGH or LOW
I/On to CP
1.5
2.0
ts
Setup Time, HIGH or LOW
DS0 or DS7 to CP
7.5
5.0
th
Hold Time, HIGH or LOW
DS0 or DS7 to CP
1.5
1.5
tw
tw
trec
CP Pulse Width, LOW
5.5
5.0
MR Pulse Width, LOW
5.5
5.0
Recovery Time
MR to CP
2.5
2.5
±
Note 10: Voltage Range 3.3 is 3.3V 0.3V
±
Voltage Range 5.0 is 5.0V 0.5V
AC Electrical Characteristics
54ACT
=
VCC
TA −55˚C
Fig.
No.
Symbol
Parameter
(V)
to +125˚C
Units
=
(Note 11)
CL 50 pF
Min
Max
fmax
Maximum Input
Frequency
5.0
5.0
70
MHz
ns
tPLH
Propagation Delay
CP to Q0 or Q7
(Shift Left or Right)
Propagation Delay
CP to Q0 or Q7
(Shift Left or Right)
Propagation Delay
CP to I/On
1.0
15.5
tPHL
5.0
5.0
5.0
5.0
5.0
1.0
1.0
1.0
1.0
1.0
16.0
15.0
18.0
18.0
17.5
ns
ns
ns
ns
ns
tPLH
tPHL
tPHL
tPHL
Propagation Delay
CP to I/On
Propagation Delay
MR to Q0 or Q7
Propagation Delay
MR to I/On
7
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AC Electrical Characteristics (Continued)
54ACT
=
VCC
TA −55˚C
Fig.
No.
Symbol
Parameter
(V)
to +125˚C
Units
=
(Note 11)
CL 50 pF
Min
Max
tPZH
tPZL
tPHZ
tPLZ
Output Enable Time
OE to I/On
5.0
5.0
5.0
5.0
1.0
14.0
14.5
14.5
14.0
ns
ns
ns
ns
Output Enable Time
OE to I/On
1.0
1.0
1.0
Output Disable Time
OE to I/On
Output Disable Time
OE to I/On
±
Note 11: Voltage Range 5.0 is 5.0V 0.5V
AC Operating Requirements
54ACT
=
VCC
TA −55˚C
Fig.
No.
Symbol
Parameter
(V)
to +125˚C
Units
=
(Note 12)
CL 50 pF
Guaranteed
Minimum
6.5
ts
th
ts
th
ts
th
tw
Setup Time, HIGH or LOW
S0 or S1 to CP
5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
ns
ns
ns
ns
ns
ns
Hold Time, HIGH or LOW
S0 or S1 to CP
1.5
4.5
1.5
5.5
1.5
5.0
Setup Time, HIGH or LOW
I/On to CP
Hold Time, HIGH or LOW
I/On to CP
Setup Time, HIGH or LOW
DS0 or DS7 to CP
Hold Time, HIGH or LOW
DS0 or DS7 to CP
CP Pulse Width
HIGH or LOW
tw
MR Pulse Width, LOW
Recovery Time
5.0
5.0
5.0
1.5
ns
ns
trec
MR to CP
±
Note 12: Voltage Range 5.0 is 5.0V 0.5V.
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8
Physical Dimensions inches (millimeters) unless otherwise noted
20 Terminal Ceramic Leadless Chip Carrier (LCC)
NS Package Number E20A
20 Lead Ceramic Dual-In-Line Package (J)
NS Package Number J20A
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20 Lead Ceramic FLATPAK
NS Package Number W20A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-
VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-
CONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or sys-
tems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, and whose fail-
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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Tel: 1-800-272-9959
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