LM2775QDSGTQ1 [TI]
汽车级、2.7V 至 5.5V 输入电压、200mA 输出电流、5V 固定输出电压加倍器 | DSG | 8 | -40 to 125;
| 型号： | LM2775QDSGTQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车级、2.7V 至 5.5V 输入电压、200mA 输出电流、5V 固定输出电压加倍器 | DSG | 8 | -40 to 125 |
| 文件： | 总30页 (文件大小：2842K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM2775-Q1
ZHCSIR1C –JUNE 2018 –REVISED MAY 2021
LM2775-Q1 开关电容器5V 升压转换器
1 特性
3 说明
• 符合汽车应用要求
• 具有符合AEC-Q100 标准的下列特性
LM2775-Q1 是一款稳压开关电容器加倍器，具有低噪
声输出电压。LM2775-Q1 可在 3.1V 至 5.5V 输入电压
范围内提供高达 200mA 的输出电流，并且在输入电压
低至 2.7V 时提供高达 125mA 的输出电流。通过对
3.3V 的稳压系统轨进行升压，LM2775-Q1 可提供成本
优化的 5V、200mA 电源来为 CAN 收发器和其他负载
供电。该器件可用于对那些不使用宽输入电压进行预升
压或冷启动的汽车系统进行后升压。在低输出电流下，
LM2775-Q1 可以通过在脉冲频率调制(PFM) 模式下运
行来降低自身的静态电流。可通过将 PFM 引脚驱动为
高电平或低电平的方式来启用或禁用 PFM 模式。此
外，当该器件关断时，用户可通过将 OUTDIS 引脚设
置为高电平或低电平，选择将输出电压拉至 GND 或保
持在高阻抗状态。
– 器件温度等级1：–40°C 至+125°C 环境工作
温度范围
• 2.7V 至5.5V 的输入电压范围
• 固定5V 输出
• 200mA 输出电流
• 无电感器解决方案：仅需3 个小型陶瓷电容器
• 关断期间从VIN 断开负载
• 电流限制和过热保护
• 2MHz 开关频率
• 轻负载电流条件下支持PFM 操作（PFM 引脚连接
高电平）
2 应用
LM2775-Q1 使用了 TI 的 8 引脚 WSON 封装，该封装
具有出色的热属性，可以在几乎任何额定运行条件下防
止器件过热。
• 为CAN 收发器供电
• 毫米波雷达
• ADAS 摄像头电源
器件信息(1)
封装尺寸（标称值）
器件型号
LM2775-Q1
封装
WSON (8)
2.00mm × 2.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
5.04
5.02
5
LM2775-Q1
5 V @ up to 200 mA
VIN
EN
VOUT
2.7 V to 5.5 V
2.2 mF
2.2 mF
C1+
C1-
1 mF
4.98
4.96
PFM
OUTDIS
GND
Copyright © 2017, Texas Instruments Incorporated
4.94
TJ=-40èC
典型应用电路
TJ=+25èC
4.92
TJ=+85èC
TJ=+125èC
4.9
1E-5
0.0001
0.001
IOUT (A)
0.01
0.05
0.2 0.5
Fig3
负载调节
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVSAH6
LM2775-Q1
ZHCSIR1C –JUNE 2018 –REVISED MAY 2021
www.ti.com.cn
Table of Contents
7.4 Device Functional Modes..........................................11
8 Application and Implementation..................................12
8.1 Application Information............................................. 12
8.2 Typical Application.................................................... 12
9 Power Supply Recommendations................................17
10 Layout...........................................................................18
10.1 Layout Guidelines................................................... 18
10.2 Layout Example...................................................... 18
11 Device and Documentation Support..........................19
11.1 接收文档更新通知................................................... 19
11.2 支持资源..................................................................19
11.3 Trademarks............................................................. 19
11.4 Electrostatic Discharge Caution..............................19
11.5 Glossary..................................................................19
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics............................................5
6.7 Typical Characteristics................................................6
7 Detailed Description........................................................9
7.1 Overview.....................................................................9
7.2 Functional Block Diagram...........................................9
7.3 Feature Description.....................................................9
Information.................................................................... 20
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision B (November 2019) to Revision C (May 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式。..................................................................................... 1
• 更正了应用..........................................................................................................................................................1
Changes from Revision A (September 2018) to Revision B (November 2019)
Page
• 更改了负载稳压图...............................................................................................................................................1
• Changed Abs Max Ratings TJ-MAX 'Max' temp from 125 to 150......................................................................... 4
• Added IOUT spec to 节6.3 table..........................................................................................................................4
• Changed maximum ambient temp range from 85 to 125°C in the 'Condition statement of 节6.5 table............ 5
• Added Thermal shutdown spec to Electrical Characteristics table ....................................................................5
• Changed TA to TJ= 25°C in Conditions statement of 节6.7 section...................................................................6
• Updated Typical Characteristics graphs ............................................................................................................ 6
• Updated Application Curve 图8-4 ................................................................................................................... 16
Changes from Revision * (June 2018) to Revision A (September 2018)
Page
• 删除了“预告信息”标题。数据表内为量产数据。.............................................................................................1
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5 Pin Configuration and Functions
1
2
3
4
8
7
6
5
图5-1. 8-Pin WSON with Thermal Pad DSG Package (Top View)
表5-1. Pin Functions
PIN
I/O
DESCRIPTION
NO.
1
NAME
PFM
C1–
C1+
I
PFM mode enable. Allow or disallow PFM operation. 1 = PFM enabled, 0 = PFM disabled
2
P
P
Flying capacitor pin
Flying capacitor pin
3
Output disconnect option. 1 = Active output discharge during shutdown, 0 = High impedance
output without pull-down during shutdown.
4
OUTDIS
I
5
EN
VOUT
VIN
I
O
Chip enable. 1 = Enabled, 0 = Disabled
Charge pump output
Input voltage
6
7
P
8
GND
GND
G
Ground
Thermal Pad
GND
Connect to GND
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
MAX
UNIT
V
VIN, VOUT
6
EN, OUTDIS, PFM
VIN + 0.3 with 6 V Max
V
Continuous power dissipation
Internally Limited
°C
°C
°C
(2)
Junction temperature (TJ-MAX
Storage temperature, Tstg
)
150
150
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) High junction temperature degrade operating lifetimes. Operating lifetime is de-rated for juction temperatures greater than 125°C
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
NOM
MAX
5.5
UNIT
VIN
V
Junction temperature (TJ )
IOUT
125
°C
–40
200(1)
mA
(1) Maximum output current is specified when TJ<TTSD
.
6.4 Thermal Information
LM2775-Q1
THERMAL METRIC(1)
DSG (WSON)
8 PINS
71.6
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
95.0
41.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
3.2
ψJT
41.8
ψJB
RθJC(bot)
12.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
Typical limits tested at TJ = 25°C. Minimum and maximum limits apply over the full operating ambient temperature range
(−40°C ≤TJ ≤+125°C). VIN = 3.6 V, CIN = COUT = 2.2 µF, C1 = 1 µF
PARAMETER
TEST CONDITIONS
MIN
TYP
5
MAX
5.2
UNIT
V
VOUT
IQ
Output voltage regulation
IOUT = 180 mA
4.8
75
150
µA
mA
µA
µA
mA
V
IOUT = 0 mA, PFM = ‘1’
IOUT = 0 mA, PFM = ‘0’
EN = '0'
Quiescent current
5
ISD
Shutdown current
0.7
500
600
3
IOUTDIS
ICL
Output discharge current
Input current limit
OUTDIS = '1'
VIL
Input logic low: EN, OUTDIS, PFM
Input logic high: EN, OUTDIS, PFM
0
0.4
VIN
VIH
1.2
V
VIN falling
2.4
2.6
150
20
UVLO
TTSD
Undervoltage lockout
V
VIN rising
Thermal shutdown threshold
Thermal shutdown hysteresis
TJ rising
°C
°C
TJ falling below TTSD
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Switching frequency
1.7
2
2.3
MHz
ƒSW
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6.7 Typical Characteristics
TJ = 25°C, VIN = 3.6 V, CIN = COUT = 10 µF (10-V 0402 case), C1 = 1 µF (10-V 0402 case), VEN = VIN
.
5.2
5.1
5
5.2
5.1
5
4.9
4.8
4.7
4.6
4.5
4.4
4.9
4.8
4.7
4.6
4.5
4.4
TJ = -40èC
TJ = -40èC
TJ = +25èC
TJ = +85èC
TJ = +125èC
TJ = +25èC
TJ = +85èC
TJ = +125èC
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VIN (V)
VIN (V)
Fig1
Fig2
ILOAD = 200 mA
PFM = '0'
ILOAD = 200 mA
PFM = '1'
图6-1. PWM Output Regulation
图6-2. PFM Output Regulation
5.04
5.02
5
5.15
5.1
5.05
5
4.98
4.96
4.94
4.92
4.9
TJ=-40èC
TJ=+25èC
TJ=+85èC
TJ=+125èC
TJ = -40èC
TJ = +25èC
TJ = +85èC
TJ = +125èC
4.95
4.9
1E-5
0.0001
0.001
IOUT (A)
0.01
0.05
0.2 0.5
1E-5
0.0001
0.001
IOUT (A)
0.01
0.05
0.2 0.5
Fig3
Fig4
VIN = 3.3 V
PFM = '0'
VIN = 3.3 V
PFM = '1'
图6-3. Load Regulation
图6-4. Load Regulation
3.5E-6
3.25E-6
3E-6
5.2
5
TJ = -40èC
TJ = +25èC
TJ = +85èC
TJ = +125èC
2.75E-6
2.5E-6
2.25E-6
2E-6
4.8
4.6
4.4
1.75E-6
1.5E-6
1.25E-6
1E-6
TJ = -40èC
7.5E-7
5E-7
TJ = +25èC
TJ = +85èC
TJ = +125èC
2.5E-7
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
4.2
0.0001
VIN (V)
0.001
0.01 0.02 0.05 0.1 0.2
0.5
Fig6
IOUT (A)
Fig5
EN = '0'
VIN = 2.7 V
PFM = '0'
图6-6. Shutdown Current
图6-5. Load Regulation
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1.75E-6
1.5E-6
1.25E-6
1E-6
0.01
0.007
0.005
TJ = -40èC
TJ = +25èC
TJ = +85èC
TJ = +125èC
0.003
0.002
0.001
0.0007
0.0005
7.5E-7
5E-7
0.0003
0.0002
TJ = -40èC
TJ = +25èC
TJ = +85èC
TJ = +125èC
2.5E-7
0.0001
7E-5
5E-5
0
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VIN (V)
VIN (V)
Fig7
Fig8
EN = '0'
OUTDIS = '0'
ILOAD = 0 mA
PFM = '1'
图6-7. Output Leakage Current
图6-8. PFM Quiescent Current
0.015
0.014
0.013
0.012
0.011
0.01
2.16
2.14
2.12
2.1
TJ = -40èC
TJ = -40èC
TJ = +25èC
TJ = +85èC
TJ = +25èC
TJ = +85èC
TJ = +125èC
TJ = +125èC
0.009
0.008
0.007
0.006
0.005
0.004
0.003
0.002
0.001
0
2.08
2.06
2.04
2.02
2
2.7
2.7
3.1
3.5
3.9
VIN (V)
4.3
4.7
5.1
5.5
3.1
3.5
3.9
VIN (V)
4.3
4.7
5.1
5.5
Fig9
Fig1
ILOAD = 0 mA
PFM = '0'
图6-10. Switching Frequency
图6-9. PWM Quiescent Current
90
85
80
75
70
65
60
55
50
45
40
80
60
40
20
TJ = -40èC
TJ = +25èC
TJ = +85èC
TJ = +125èC
TJ = -40èC
TJ = +25èC
TJ = +85èC
TJ = +125èC
0
2E-5
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
0.0001
0.001
0.01
0.05
0.2 0.5
VIN (V)
IOUT (A)
Fig1
Fig1
ILOAD = 100 mA
PFM = '0'
VIN = 3.3 V
PFM = '0'
图6-11. Efficiency vs Input Voltage
图6-12. Efficiency vs Load Current
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80
60
40
20
0
VOUT (100 mV/DIV)
+5 V Offset
ILOAD (100 mA/DIV)
TJ = -40èC
TJ = +25èC
TJ = +85èC
TJ = +125èC
Time (200 ms / DIV)
2E-5
0.0001
0.001
0.01
0.05
0.2 0.5
IOUT (A)
Fig1
VIN = 3.6 V
ILOAD = 1 mA to 100 mA
PFM = '1'
VIN = 3.3 V
PFM = '1'
图6-14. PFM Load Step
图6-13. Efficiency vs Load Current
VOUT (2 V/DIV)
VOUT (100 mV/DIV)
+5 V Offset
EN
ILOAD (100 mA/DIV)
Time (200 ms / DIV)
Time (10 ms / DIV)
VIN = 3.6 V
ILOAD = 1 mA to 100 mA
PFM = '0'
VIN = 3.6 V
OUTDIS = '0'
图6-15. PWM Load Step
图6-16. Output Discharge Disabled
VIN (2 V/DIV)
EN
EN
VOUT (2 V/DIV)
VOUT (2 V/DIV)
IIN (1 A/DIV)
IOUT (100 mA/DIV)
Time (20 ms / DIV)
Time (200 ms / DIV)
VIN = 3.6 V
OUTDIS = '1'
VIN = 3.6 V
ILOAD = 100 mA
图6-17. Output Discharge Enabled
图6-18. Start-Up into a Load
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7 Detailed Description
7.1 Overview
The LM2775-Q1 is a regulated switched capacitor doubler that, by combining the principles of switched-
capacitor voltage boost and linear regulation, generates a regulated output from an extended Li-Ion input voltage
range. A two-phase non-overlapping clock generated internally controls the operation of the doubler. During the
charge phase (φ1), the flying capacitor (C1) is connected between the input and ground through internal pass
transistor switches and is charged to the input voltage. In the pump phase that follows (φ2), the flying capacitor
is connected between the input and output through similar switches. Stacked atop the input, the charge of the
flying capacitor boosts the output voltage and supplies the load current.
A traditional switched capacitor doubler operating in this manner uses switches with very low on-resistance to
generate an output voltage that is 2× the input voltage. Regulation is achieved by modulating the current of the
two switches connected to the VIN pin (one switch in each phase).
7.2 Functional Block Diagram
C1-
C1+
LM2775-Q1
S1
S3
S2
S4
f1
f2
f1
f2
VOUT
OCL =
Current Limit
VIN
OCL
OUTDIS
GND
PFM
EN
PFM EN
1.2-V
Ref.
2-MHz
Osc.
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7.3 Feature Description
7.3.1 Pre-Regulation
The very low input current ripple of the LM2775-Q1, resulting from internal pre-regulation, adds minimal noise to
the input line. The core of the device is very similar to that of a basic switched capacitor doubler: it is composed
of four switches and a flying capacitor (external). Regulation is achieved by controlling the current through the
two switches connected to the VIN pin (one switch in each phase). The regulation is done before the voltage
doubling, giving rise to the term "pre-regulation". It is pre-regulation that eliminates most of the input current
ripple that is a typical and undesirable characteristic of a many switched capacitor converters.
7.3.2 Input Current Limit
The LM2775-Q1 contains current limit circuitry that protects the device in the event of excessive input current
and/or output shorts to ground. The input current is limited to 600 mA (typical) when the output is shorted directly
to ground. When the device is current limiting, power dissipation in the device is likely to be quite high. In this
event, thermal cycling should be expected.
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7.3.3 PFM Mode
To minimize quiescent current during light load operation, the LM2775-Q1 provides a PFM operation option
(selectable via the PFM pin. '1' = PFM allowed, '0' = Fixed frequency). By allowing the charge pump to only
switch when the VOUT voltage decays to a typical 5.05 V, the quiescent current drawn from the power source is
minimized. The frequency of pulsed operation is not limited and can drop into the sub-1-kHz range when
unloaded. As the load increases, the frequency of pulsing increases.
When PFM mode is disabled, the device operates in a constant frequency mode. In this mode, the quiescent
current remains at normal levels even when the load current is decreased. The main advantages of fixed
frequency operation include a lower output voltage ripple level due to the constant switching and a predictable
switching frequency that stays at 2 MHz which can be important in noise sensitive applications.
7.3.4 Output Discharge
The LM2775-Q1 provides two different output discharge modes upon entering a shutdown state (EN pin = '0')
after running in the on state (EN = '1'). The first mode is high impendance mode (OUTDIS = '0'). In this mode,
the output remains high even when the EN pin is driven low. This enables use in applications where the
LM2775-Q1 output might be tied to a system rail that has another power source connected (USBOTG). When
OUTDIS = 0, the output of the device draws a minimal current from the output supply (1.6 µA typical).
In Discharge Mode (OUTDIS pin = '1'), the LM2775-Q1 actively pulls down on the output of the device until the
output voltage reaches GND. In this mode, the current drawn from the output is approximately 450 µA.
7.3.5 Thermal Shutdown
The LM2775-Q1 implements a thermal shutdown mechanism to protect the device from damage due to
overheating. When the junction temperature rises to 150°C (typical), the part switches into shutdown mode. The
device releases thermal shutdown when the junction temperature of the part is reduced to 130°C (typical).
Thermal shutdown is most often triggered by self-heating, which occurs when there is excessive power
dissipation in the device and/or insufficient thermal dissipation. LM2775-Q1 power dissipation increases with
increased output current and input voltage. When self-heating brings on thermal shutdown, thermal cycling is the
typical result. Thermal cycling is the repeating process where the part self-heats, enters thermal shutdown
(where internal power dissipation is practically zero), cools, turns on, and then heats up again to the thermal
shutdown threshold. Thermal cycling is recognized by a pulsing output voltage and can be stopped be reducing
the internal power dissipation (reduce input voltage and/or output current) or the ambient temperature. If thermal
cycling occurs under desired operating conditions, thermal dissipation performance must be improved to
accommodate the power dissipation of the LM2775-Q1. The WSON package is designed to have excellent
thermal properties that, when soldered to a PCB designed to aid thermal dissipation, allows the device to
operate under very demanding power dissipation conditions.
7.3.6 Undervoltage Lockout
The LM2775-Q1 has an internal comparator that monitors the voltage at VIN and forces the device into
shutdown if the input voltage drops to 2.4 V. If the input voltage rises above 2.6 V, the LM2775-Q1 resumes
normal operation
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7.4 Device Functional Modes
7.4.1 Shutdown
The LM2775-Q1 enters Shutdown Mode if one of the two conditions are met.
• If VIN is removed or allowed to sag to ground, the device enters shutdown.
• If the EN pin is driven low when VIN is within the normal operating range.
In Shutdown, the LM2775-Q1 typically draws less than 1 µA from the supply. Depending on the state of the
OUTDIS pin, the output is pulled low when entering shutdown (OUTDIS = '1'), or it remains near the final output
voltage with the output in a low leakage state (OUTDIS = '0').
7.4.2 Boost Mode
The LM2775-Q1 is in Boost Mode if VIN is within the normal operating range, and the EN pin is driven high.
Depending on the state of the PFM pin, the device either regulates the output via a PFM burst mode (PFM = '1')
or via a constant switching mode (PFM = '0').
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The LM2775-Q1 can create a 5-V system rail capable of delivering up to 200 mA of output current to the load.
The 2-MHz switched capacitor boost allows for the use of small value discrete external components.
8.2 Typical Application
LM2775-Q1
5V @ 200mA
VIN
VOUT
System
Battery
10 mF
10 mF
C1+
PFM
1 mF
C1-
OUTDIS
GND
Controller
EN
Copyright © 2017, Texas Instruments Incorporated
图8-1. Typical LM2775-Q1 Configuration
8.2.1 Design Requirements
DESIGN PARAMETER
Input voltage range
Output current range
EXAMPLE VALUE
2.7 V to 5.5 V
0 mA to 200 mA (Max. current will depend on VIN)
8.2.2 Detailed Design Procedure
8.2.2.1 Output Current Capability
The LM2775-Q1 provides 200 mA of output current when the input voltage is within 3.1 V to 5.5 V.
Note
Understanding relevant application issues is recommended and a thorough analysis of the application
circuit should be performed when using the part outside operating ratings and/or specifications to
ensure satisfactory circuit performance in the application. Special care should be paid to power
dissipation and thermal effects. These parameters can have a dramatic impact on high-current
applications, especially when the input voltage is high. (see the 节8.2.2.3 section).
The schematic of 图 8-2 is a simplified model of the LM2775-Q1 that is useful for evaluating output current
capability. The model shows a linear pre-regulation block (Reg), a voltage doubler (2×), and an output resistance
(ROUT). Output resistance models the output voltage droop that is inherent to switched capacitor converters. The
output resistance of the device is 3.5 Ω (typical) and is approximately equal to twice the resistance of the four
LM2775-Q1 switches. When the output voltage is in regulation, the regulator in the model controls the voltage V'
to keep the output voltage equal to 5 V ± 4%. With increased output current, the voltage drop across ROUT
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increases. To prevent droop in output voltage, the voltage drop across the regulator is reduced, V' increases,
and VOUT remains at 5 V. When the output current increases to the point that there is zero voltage drop across
the regulator, V' equals the input voltage, and the output voltage is near the edge of regulation. Additional output
current causes the output voltage to fall out of regulation, and the LM2775-Q1 operation is similar to a basic
open-loop doubler. As in a voltage doubler, increase in output current results in output voltage drop proportional
to the output resistance of the doubler. The out-of-regulation LM2775-Q1 output voltage can be approximated
by:
VOUT = 2 × VIN –IOUT × ROUT
(1)
Again, 方程式1 only applies at low input voltage and high output current where the LM2775-Q1 is not regulating.
See Output Current vs. Output Voltage curves in the 节6.7 section for more details.
LM2775-Q1
VIN
VOUT
V '
2×V '
ROUT
Reg
2×
Output Resistance Model
图8-2. LM2775-Q1 Output Resistance Model
A more complete calculation of output resistance takes into account the effects of switching frequency, flying
capacitance, and capacitor equivalent series resistance (ESR) (see 方程式2).
1
+ ESR
COUT
R
= 2 ∂ R
+
+ 4 ∂ ESR
C1
OUT
SW
F
ì C
1
SW
(2)
Switch resistance component (3 Ω typical) dominates the output resistance equation of the LM2775-Q1. With a
2-MHz typical switching frequency, the 1/(F×C) component of the output resistance contributes only 0.5 Ω to the
total output resistance. Increasing the flying capacitance only provides minimal improvement to the total output
current capability of the LM2775-Q1. In some applications it may be desirable to reduce the value of the flying
capacitor below 1 µF to reduce solution size and/or cost, but this should be done with care so that output
resistance does not increase to the point that undesired output voltage droop results. If ceramic capacitors are
used, ESR will be a negligible factor in the total output resistance, as the ESR of quality ceramic capacitors is
typically much less than 100 mΩ.
8.2.2.2 Efficiency
Charge-pump efficiency is derived in 方程式 3 and 方程式 4 (supply current and other losses are neglected for
simplicity):
IIN = G × IOUT E = (VOUT × IOUT) ÷ (VIN × IIN) = VOUT ÷ (G × VIN)
(3)
If one includes the quiescent current drawn by the LM2775-Q1 to operate, the following can be derived :
P
V
ìI
OUT
OUT OUT
E =
=
P
V
ì (2 ∂I
+ I )
OUT Q
IN
IN
(4)
In 方程式3, G represents the charge pump gain. Efficiency is at its highest as G × VIN approaches VOUT. For the
LM2775-Q1 device, G = 2.
8.2.2.3 Power Dissipation
LM2775-Q1 power dissipation (PD) is calculated simply by subtracting output power from input power:
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PD = PIN –POUT = [VIN × (2 × IOUT + IQ)] –[VOUT × IOUT
]
(5)
Power dissipation increases with increased input voltage and output current, up to 1.35 W at the ends of the
operating ratings (VIN = 5.5 V, IOUT = 200 mA). Internal power dissipation self-heats the device. Dissipating this
amount power/heat so the LM2775-Q1 does not overheat is a demanding thermal requirement for a small
surface-mount package. When soldered to a PCB with layout conducive to power dissipation, the excellent
thermal properties of the WSON package enable this power to be dissipated from the LM2775-Q1 with little or no
derating, even when the circuit is placed in elevated ambient temperatures.
LM2775-Q1
Ideal
Switched-
Capacitor
Doubler
VIN
V ' @ 2 × VIN
VOUT = 5 V
IOUT
Linear
Regulator
(IQ = 0)
I ' = IOUT
IIN = (2 × IOUT) + IQ
IQ
Power Model
Copyright © 2017, Texas Instruments Incorporated
图8-3. Power Model
8.2.2.4 Recommended Capacitor Types
The LM2775-Q1 requires 3 external capacitors for proper operation. Surface-mount multi-layer ceramic
capacitors are recommended. These capacitors are small, inexpensive, and have very low ESR (≤ 15 mΩ
typical). Tantalum capacitors, OS-CON capacitors, and aluminum electrolytic capacitors generally are not
recommended for use with the device due to their high ESR compared to ceramic capacitors.
For most applications, ceramic capacitors with an X7R or X5R temperature characteristic are preferred for use
with the LM2775-Q1. These capacitors have tight capacitance tolerance (as good as ±10%) and hold their value
over temperature (X7R: ±15% over –55°C to 125°C; X5R: ±15% over –55°C to 85°C).
Capacitors with a Y5V or Z5U temperature characteristic are generally not recommended for use with the
LM2775-Q1. These types of capacitors typically have wide capacitance tolerance (80% to 20%) and vary
significantly over temperature (Y5V: 22%, –82% over –30°C to 85°C range; Z5U: 22%, –56% over 10°C to
85°C range). Under some conditions, a 1-µF-rated Y5V or Z5U capacitor could have a capacitance as low as 0.1
µF. Such detrimental deviation is likely to cause Y5V and Z5U capacitors to fail to meet the minimum
capacitance requirements of the LM2775-Q1.
Net capacitance of a ceramic capacitor decreases with increased DC bias. This degradation can result in lower
capacitance than expected on the input and/or output, resulting in higher ripple voltages and currents. Using
capacitors at DC-bias voltages significantly below the capacitor voltage rating usually minimizes DC-bias effects.
Consult capacitor manufacturers for information on capacitor DC-bias characteristics.
Capacitance characteristics can vary quite dramatically with different application conditions, capacitor types, and
capacitor manufacturers. It is strongly recommended that the LM2775-Q1 circuit be thoroughly evaluated early in
the design-in process with the mass-production capacitors of choice. This helps ensure that any such variability
in capacitance does not negatively impact circuit performance.
The voltage rating of the output capacitor should be 10 V or more. All other capacitors should have a voltage
rating at or above the maximum input voltage of the application.
8.2.2.5 Output Capacitor and Output Voltage Ripple
The output capacitor in the LM2775-Q1 circuit (COUT) directly impacts the magnitude of output voltage ripple.
Other prominent factors also affecting output voltage ripple include input voltage, output current, and flying
capacitance. One important generalization can be made: increasing (decreasing) the output capacitance results
in a proportional decrease (increase) in output voltage ripple. A simple approximation of output ripple is
determined by calculating the amount of voltage droop that occurs when the output of the LM2775-Q1 is not
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being driven. This occurs during the charge phase (φ1). During this time, the load is driven solely by the charge
on the output capacitor. The magnitude of the ripple thus follows the basic discharge equation for a capacitor (I =
C × dV/dt), where discharge time is one-half the switching period, or 0.5/FSW (see 方程式6).
I
0.5
OUT
RIPPLE
=
ì
Peak -Peak
C
F
SW
OUT
(6)
A more thorough and accurate examination of factors that affect ripple requires including effects of phase non-
overlap times and output capacitor ESR. In order for the LM2775-Q1 to operate properly, the two phases of
operation must never coincide. (If this were to happen all switches would be closed simultaneously, shorting
input, output, and ground). Thus, non-overlap time is built into the clocks that control the phases. Because the
output is not being driven during the non-overlap time, this time should be accounted for in calculating ripple.
Actual output capacitor discharge time is approximately 60% of a switching period, or 0.6/FSW (see 方程式7).
≈
∆
∆
«
’
÷
÷
◊
I
0.6
OUT
RIPPLE
=
ì
+ (2 ìI
ì ESR
)
Peak-Peak
OUT
COUT
C
F
SW
OUT
(7)
Note
In typical high-current applications, a 10-µF, 10-V low-ESR ceramic output capacitor is recommended.
Different output capacitance values can be used to reduce ripple, shrink the solution size, and/or cut
the cost of the solution. But changing the output capacitor may also require changing the flying
capacitor and/or input capacitor to maintain good overall circuit performance. If a small output
capacitor is used and PFM mode is enabled, the output ripple can become large during the transition
between PFM mode and constant switching. To prevent toggling, a 2-µF capacitance is
recommended. For example, a 10-µF, 10-V output capacitor in a 0402 case size will typically only
have 2-µF capacitance when biased to 5 V.
High ESR in the output capacitor increases output voltage ripple. If a ceramic capacitor is used at the output, this
is usually not a concern because the ESR of a ceramic capacitor is typically very low and has only a minimal
impact on ripple magnitudes. If a different capacitor type with higher ESR is used (tantalum, for example), the
ESR could result in high ripple. To eliminate this effect, the net output ESR can be significantly reduced by
placing a low-ESR ceramic capacitor in parallel with the primary output capacitor. The low ESR of the ceramic
capacitor is in parallel with the higher ESR, resulting in a low net ESR based on the principles of parallel
resistance reduction.
8.2.2.6 Input Capacitor and Input Voltage Ripple
The input capacitor (CIN) is a reservoir of charge that aids a quick transfer of charge from the supply to the flying
capacitor during the charge phase of operation. The input capacitor helps to keep the input voltage from
drooping at the start of the charge phase when the flying capacitor is connected to the input. It also filters noise
on the input pin, keeping this noise out of sensitive internal analog circuitry that is biased off the input line.
Much like the relationship between the output capacitance and output voltage ripple, input capacitance has a
dominant and first-order effect on input ripple magnitude. Increasing (decreasing) the input capacitance results in
a proportional decrease (increase) in input voltage ripple. Input voltage, output current, and flying capacitance
also affect input ripple levels to some degree.
In typical high-current applications, a 10-µF low-ESR ceramic capacitor is recommended on the input. Different
input capacitance values can be used to reduce ripple, shrink the solution size, and/or cut the cost of the
solution. But changing the input capacitor may also require changing the flying capacitor and/or output capacitor
to maintain good overall circuit performance.
8.2.2.7 Flying Capacitor
The flying capacitor (C1) transfers charge from the input to the output. Flying capacitance can impact both output
current capability and ripple magnitudes. If flying capacitance is too small, the LM2775-Q1 may not be able to
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regulate the output voltage when load currents are high. On the other hand, if the flying capacitance is too large,
the flying capacitor might overwhelm the input and output capacitors, resulting in increased input and output
ripple.
In typical high-current applications, 1-µF low-ESR ceramic capacitors are recommended for the flying capacitor.
Polarized capacitors (tantalum, aluminum electrolytic, etc.) must not be used for the flying capacitor, as they
could become reverse-biased during LM2775-Q1 operation.
8.2.3 Application Curve
5.04
5.02
5
4.98
4.96
4.94
TJ=-40èC
TJ=+25èC
4.92
TJ=+85èC
TJ=+125èC
4.9
1E-5
0.0001
0.001
IOUT (A)
0.01
0.05
0.2 0.5
Fig3
VIN = 3.3 V
PFM = '0'
图8-4. Load Regulation
8.2.4 USB OTG / Mobile HDMI Power Supply
V
BAT
(System Voltage)
LM2775-Q1
(Host Mode
VBUS Power)
PFM
EN
OUTDIS
USB Connector
V
OUT
/ V
(5 V)
BUS
V
BUS
Dual Role
Application
Processor
ID
D+
D-
USB OTG
Transceiver
GND
Copyright © 2017, Texas Instruments Incorporated
图8-5. USB OTG Configuration
8.2.4.1 Design Requirements
DESIGN PARAMETER
Input voltage range
Output current range
EXAMPLE VALUE
2.7 V to 5.5 V
0 mA to 200 mA (Max. current will depend on VIN)
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8.2.4.2 Detailed Design Procedure
The 5-V output mode is normally used for the USB OTG / Mobile HDMI application. Therefore, the LM2775-Q1
can be enabled/disabled by applying a logic signal on only the EN pin while grounding the OUTDIS pin.
Depending on the USB/HDMI mode of the application, the LM2775-Q1 can be enabled to drive the power bus
line (Host), or disabled to put its output in high impedance allowing an external supply to drive the bus line
(Slave). In addition to the high impedance-backdrive protection, the output current limit protection is 250 mA
(typical), well within the USB OTG and HDMI requirements.
8.2.4.3 Application Curve
1.75E-6
1.5E-6
1.25E-6
1E-6
7.5E-7
5E-7
TJ = -40èC
TJ = +25èC
2.5E-7
TJ = +85èC
TJ = +125èC
0
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VIN (V)
Fig7
EN = '0'
OUTDIS = '0'
图8-6. Output Leakage Current High Z
9 Power Supply Recommendations
The LM2775-Q1 is designed to operate from an input voltage supply range between 2.7 V and 5.5 V. This input
supply must be well regulated and capable to supply the required input current. If the input supply is located far
from the device additional bulk capacitance may be required in addition to the ceramic bypass capacitors.
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10 Layout
10.1 Layout Guidelines
Proper board layout helps to ensure optimal performance of the LM2775-Q1 circuit. The following guidelines are
recommended:
• Place capacitors as close as possible to the LM2775-Q1, preferably on the same side of the board as the
device.
• Use short, wide traces to connect the external capacitors to the device to minimize trace resistance and
inductance.
• Use a low resistance connection between ground and the GND pin of the LM2775-Q1. Using wide traces
and/or multiple vias to connect GND to a ground plane on the board is most advantageous.
10.2 Layout Example
CONNECT TO GND PLANE
LM2775-Q1
PFM
C1-
GND
VIN
C1+
VOUT
EN
OUTDIS
CONNECT TO GND PLANE
图10-1. Example LM2775-Q1 Layout
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11 Device and Documentation Support
11.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
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证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
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提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM2775QDSGRQ1
LM2775QDSGTQ1
ACTIVE
ACTIVE
WSON
WSON
DSG
DSG
8
8
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
1R1H
1R1H
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2021
OTHER QUALIFIED VERSIONS OF LM2775-Q1 :
Catalog : LM2775
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-May-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM2775QDSGRQ1
LM2775QDSGTQ1
WSON
WSON
DSG
DSG
8
8
3000
250
180.0
180.0
8.4
8.4
2.3
2.3
2.3
2.3
1.15
1.15
4.0
4.0
8.0
8.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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7-May-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM2775QDSGRQ1
LM2775QDSGTQ1
WSON
WSON
DSG
DSG
8
8
3000
250
210.0
210.0
185.0
185.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DSG 8
2 x 2, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
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PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
0.32
0.18
PIN 1 INDEX AREA
2.1
1.9
0.4
0.2
ALTERNATIVE TERMINAL SHAPE
TYPICAL
0.8
0.7
C
SEATING PLANE
0.05
0.00
SIDE WALL
0.08 C
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
EXPOSED
THERMAL PAD
(DIM A) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
9
1.6 0.1
8
1
0.32
0.18
PIN 1 ID
(45 X 0.25)
8X
0.4
0.2
8X
0.1
C A B
C
0.05
4218900/E 08/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
(
0.2) VIA
8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(1.9)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/E 08/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
METAL
8
SYMM
1
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/E 08/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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