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LM36273

ZHCSGN8D –FEBRUARY 2016–REVISED MARCH 2018

具有集成偏置电源的 LM36273 三通道 LCD 背光驱动器

1 特性

3 说明

1

•

可驱动多达三个并联的白色发光二极管 (LED) 串

（V_OUT最大值为 29V）

LM36273 是一款集成式三通道 WLED 驱动器及 LCD

偏置电源。LM36273 拥有超紧凑外形、高效率、高集

成度和可编程性等特性，因此适用于各种应用，而且

无需更换硬件，同时还能够最大限度地减小整体解决方

案尺寸。

•

11 位指数和线性调光控制

脉宽调制 (PWM) 和 I²C 亮度控制

采用 4.7µH 到 15µH 电感的背光操作

背光和液晶显示屏 (LCD) 偏置效率高达 92%

背光升压转换器可提供电源以偏置三个并联 LED 串，

总输出电压最高可达 29V。11 位 LED 电流可通过 I²C

总线进行编程，并且/或者可通过介于 60µA 和 30mA

之间的逻辑电平 PWM 输入进行控制。每个 LED 串均

可单独使能或禁用，从而实现区域调光功能。采用

4.7µH 到 15µH 的电感即可高效操作背光升压转换器，

从而优化效率和解决方案尺寸。

可编程 LCD 偏置电压（±4V 到 ±6.5V，分辨率为

50mV），每个输出的电流高达 80mA

•

60µA 到 30mA 范围内的 LED 电流匹配度为 0.2%

60µA 到 30mA 范围内的 LED 电流精度为 1%

输入电压范围：2.7V 至 5V

2 应用

•

LED 数最多可达 24 个的 LCD 面板

LCD 偏置升压转换器为正低压降稳压器 (LDO) 和反向

电荷泵供电。正负偏置电源均提供了可编程的输出电压

（±4V 到 ±6.5V，步长为 50mV）以及高达 ±80mA 的

电流能力。自动排序功能可通过编程设定从正到负偏置

激活的延迟，并且具有附加的可编程电压转换率控制。

凭借两种唤醒模式，两个偏置输出可通过单一外部信号

进行控制，并且能够以超低的静态电流消耗保持工作状

态。

智能手机

平板电脑和游戏平板电脑

家庭自动化面板

空白

简化原理图

DSCH

L_BL

器件信息⁽¹⁾

C_{BL_OUT}

器件型号

LM36273

封装

封装尺寸（最大值）

BL_OUT

LED1

DSBGA (24)

2.44mm × 1.67mm

IN

(1) 要了解所有可用封装，请参见数据表末尾的可订购产品附录。

L_LCM

V_BATT

LCM_SW

背光效率，3P7S

LED2

SCL

95

90

85

80

75

70

65

LED3

SDA

Up to 8 LEDs / String

LM36273

C+

C-

PWM

C_FLY

HWEN

LCM_EN1

LCM_EN2

LCM_OUT

C_LCM

VPOS

VNEG

60

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

C_VPOS

55

50

C_VNEG

0

10

20

30

40

50

60

70

80

90

Load (mA)

D052

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNVSAJ8

LM36273

ZHCSGN8D –FEBRUARY 2016–REVISED MARCH 2018

www.ti.com.cn

7.5 Programming........................................................... 33

7.6 Register Maps......................................................... 37

Application and Implementation ........................ 47

8.1 Application Information............................................ 47

8.2 Typical Application .................................................. 47

Power Supply Recommendations...................... 69

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information ................................................. 5

6.5 Electrical Characteristics .......................................... 6

6.6 I²C Timing Requirements (Fast Mode) .................... 9

6.7 Typical Characteristics............................................ 10

Detailed Description ............................................ 15

7.1 Overview ................................................................. 15

7.2 Functional Block Diagram ....................................... 16

7.3 Features Description............................................... 16

7.4 Device Functional Modes........................................ 32

8

9

10 Layout................................................................... 69

10.1 Layout Guidelines ................................................ 69

10.2 Layout Example ................................................... 70

11 器件和文档支持 ..................................................... 71

11.1 器件支持................................................................ 71

11.2 文档支持................................................................ 71

11.3 接收文档更新通知 ................................................. 71

11.4 社区资源................................................................ 71

11.5 商标....................................................................... 71

11.6 静电放电警告......................................................... 71

11.7 Glossary................................................................ 71

12 机械、封装和可订购信息....................................... 71

7

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision C (June 2017) to Revision D

Page

•

已添加 added silicon rev A1 to revision register. ................................................................................................................. 37

Changes from Revision B (March 2017) to Revision C

Page

•

已更改将完整的数据表首次公开发布到网站 ......................................................................................................................... 1

Changes from Revision A (January 2017) to Revision B

Page

•

Changed row(s) in Abs Max table: BL_SW from 30 V to 35 V, BL_OUT and current sink inputs (LEDX) remain at 30 V ... 5

Changes from Original (February 2016) to Revision A

Page

•

已更改 POA 上的“可订购器件”后缀从“YFRR”更改为“YFFR” .................................................................................................. 1

2

LM36273

www.ti.com.cn

ZHCSGN8D –FEBRUARY 2016–REVISED MARCH 2018

5 Pin Configuration and Functions

YFF Package

24-Pin DSBGA

Top View

1

2

3

4

VNEG

C-

CP_GND

C+

A

LCM_

EN2

LCM_

EN1

IN

VPOS

B

LCM_

OUT

NC

SCL

SDA

C

LED3

PWM

HWEN

LCM_SW

BL_GND

D

LCM_

GND

LED2

AGND

E

LED1

BL_OUT

BL_SW

F

Pin Functions

TYPE

DESCRIPTION

NUMBER

NAME

Inverting charge pump output. Bypass VNEG with a 10-µF ceramic capacitor to

CP_GND.

A1

VNEG

O

A2

A3

A4

B1

C-

CP_GND

C+

O

—

O

I

Inverting charge-pump flying capacitor negative connection

Charge pump GND. Connect the CNEG capacitor negative terminal to this pin.

Inverting charge-pump flying capacitor positive connection

IN

Input voltage connection. Bypass IN with a 10-µF ceramic capacitor to GND.

Enable for LCD bias negative output; 300-kΩ internal pulldown resistor between

LCM_EN2 and GND.

B2

B3

LCM_EN2

LCM_EN1

I

Enable for LCD bias positive output; 300-kΩ internal pulldown resistor between

LCM_EN1 and GND.

B4

C1

C2

C3

VPOS

NC

O

—

I

Positive LCD bias output. Bypass VPOS with a 10-µF ceramic capacitor to GND.

No connect; leave this pin disconnected

Serial clock connection for I²C-compatible interface

SCL

SDA

I/O

LCD bias boost output voltage. Bypass LCM_OUT with a 10-µF ceramic capacitor to

LCM_GND.

C4

D1

D2

LCM_OUT

LED3

O

I

Current sink 3 input. Connect the cathode of LED string 3 to this pin. Leave this pin

disconnected if not used.

PWM input for duty cycle current control; 300-kΩ internal pulldown resistor between

PWM and GND.

PWM

I

D3

D4

HWEN

I

Active high chip enable; 300-kΩ internal pulldown resistor between HWEN and GND.

LCM_SW

O

LCD bias boost inductor connection

Current sink 2 input. Connect the cathode of LED string 2 to this pin. Leave this pin

disconnected if not used.

E1

LED2

I

3

LM36273

ZHCSGN8D –FEBRUARY 2016–REVISED MARCH 2018

www.ti.com.cn

Pin Functions (continued)

TYPE

DESCRIPTION

NUMBER

NAME

E2

AGND

—

I

Analog ground connection. Connect AGND directly to GND on the PCB.

LCD bias boost GND connection. Connect LCM_GND to the negative terminal of the

LCD bias output capacitor.

E3

E4

F1

LCM_GND

BL_GND

LED1

Backlight boost output capacitor GND connection

Current sink 1 input. Connect the cathode of LED string 1 to this pin. Leave this pin

disconnected if not used.

Backlight boost output voltage sense connection. Connect to the positive terminal of

backlight boost output capacitor.

F2

BL_OUT

O

F3

F4

BL_SW

O

Backlight boost inductor connection

4

LM36273

www.ti.com.cn

ZHCSGN8D –FEBRUARY 2016–REVISED MARCH 2018

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

MIN

–0.3

–7

MAX

6

UNIT

Voltage on IN, HWEN, LCM_EN1, LCM_EN2, SCL, SDA, PWM

Voltage on LCM_SW, LCM_OUT, VPOS, C+

Voltage on VNEG, C–

V

9

0.3

35

30

Voltage on BL_SW

–0.3

Voltage on BL_OUT, LED1, LED2, LED3

Continuous power dissipation

Internally limited

Maximum junction temperature, T_J(MAX)

Storage temperature, T_stg

150

°C

–45

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the potential at the AGND pin.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

Electrostatic

discharge

V_(ESD)

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

(2)

.

MIN

2.7

MAX

5

UNIT

V

Input voltage, V_IN

(3)

Operating ambient temperature, T_A

–40

85

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to the potential at the AGND pin.

(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (T_J-MAX-OP

=

125°C), the maximum power dissipation of the device in the application (P_D-MAX), and the junction-to-ambient thermal resistance of the

part/package in the application (R_θJA), as given by the following equation: T_A-MAX= T_J-MAX-OP– (R_θJA× P_D-MAX).

6.4 Thermal Information

LM36273

THERMAL METRIC⁽¹⁾

DSBGA (YFF)

(24 PINS)

63.1

UNIT

R_θJA

R_θJC

R_θJB

Ψ_JT

Junction-to-ambient thermal resistance

°C/W

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

0.4

11.6

Junction-to-top characterization parameter

Junction-to-board characterization parameter

1.6

Ψ_JB

11.6

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

5

LM36273

ZHCSGN8D –FEBRUARY 2016–REVISED MARCH 2018

www.ti.com.cn

6.5 Electrical Characteristics

Unless otherwise specified, typical limits apply at 25°C, minimum and maximum limits apply over the full operating ambient

temperature range (−40°C ≤ T_A≤ 85°C), and V_IN= 3.6 V.

PARAMETER

CURRENT CONSUMPTION

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_SD

Shutdown current

HWEN = 0

0.2

1

2.8

7

µA

Quiescent current, device not

switching

I_Q

HWEN = V_IN, LCM boost disabled

VPOS, VNEG enabled with no load,

I_{LCM_EN}

Bias power no load supply current backlight boost disabled, typical

application circuit (not ATE tested)

0.5

30

10

µA

BACKLIGHT LED CURRENT SINKS (LED1, LED2, LED3, LED4)

Maximum output current (per

string)

2.7 V ≤ V_IN≤ 5 V, linear or

exponential mode

I_{LED_MAX}

I_LED

mA

2.7 V ≤ V_IN≤ 5 V, 60 µA < I_LED< 30

mA, linear or exponential mode

LED current accuracy⁽¹⁾

–3%

–2%

3%

2%

2.7 V ≤ V_IN≤ 5 V, 60 µA ≤ I_LED≤ 30

mA, linear or exponential mode

I_MATCH

I_LEDcurrent matching⁽²⁾

0.2%

I_{LED_MIN}

Minimum LED current (per string)

Linear or exponential mode

Exponential mode⁽³⁾

Linear mode

60

0.3%

14.63

µA

LED current step size (code to

code)

I_STEP

BACKLIGHT BOOST

011 to 111

28.5

24.5

20.5

16.3

29

25

21

17

0.5

29.5

25.5

21.5

17.7

010

001

000

ON threshold, 2.7 V

≤ V_IN≤ 5 V

OVP threshold

V

OVP hysteresis

OFF threshold

V_IN= 3.6 V, I_BLED= 5 mA/string,

(P_OUT/P_IN), Typical Application Circuit

(not ATE tested)

Efficiency

V_HR

Boost efficiency

90%

I_LED= 30 mA

I_LED= 5 mA

310

120

mV

Regulated current-sink headroom

voltage (boost feedback voltage)

Current-sink minimum headroom

voltage

V_{HR_MIN}

R_DSON

I_LED= 95% of nominal, I_LED= 5 mA

30

50

mV

NMOS switch on resistance

I_SW= 250 mA

0.2

900

Ω

00

792

1056

1320

1584

450

1008

1344

1680

2016

550

mA

01

2.7 V ≤ V_IN≤ 5 V

10

1200

1500

1800

500

I_CL

NMOS switch current limit

11

500-kHz mode

2.7 V ≤ V_IN≤ 5 V

ƒ_{BL_SW}

D_MAX

Switching frequency

Maximum duty cycle

kHz

1-MHz mode

900

1000

94%

1100

V_IN= 2.7 V, ƒ_{LED_SW}= 1 MHz

93%

DEVICE PROTECTION

TSD Thermal shutdown

Not ATE tested

140

°C

(1) Output current accuracy is the difference between the actual value of the output current and programmed value of this current.

(2) LED current matching is the maximum difference between any string current and the average string current, divided by the average

string current. This is calculated as (I_LEDX– I_{LED_AVE}) / I_{LED_AVE}× 100.

(3) LED current step size from code to code in exponential mode is typically 0.304%, given as (1 – (I_LED(CODE+1) / I_LED(CODE)).

6

LM36273

www.ti.com.cn

ZHCSGN8D –FEBRUARY 2016–REVISED MARCH 2018

Electrical Characteristics (continued)

Unless otherwise specified, typical limits apply at 25°C, minimum and maximum limits apply over the full operating ambient

temperature range (−40°C ≤ T_A≤ 85°C), and V_IN= 3.6 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DISPLAY BIAS (LCM BOOST)

LCM bias boost overvoltage

protection

V_{OVP_LCM}

ƒ_{LCM_SW}

On threshold, 2.7 V ≤ V_IN≤ 5 V

7.8

V

2.7 V ≤ V_IN≤ 5 V (continuous

conduction mode)

Switching frequency⁽⁴⁾

LCM boost output voltage range

2500

kHz

V

4

7.15

V_IN= 3.6 V, V_{LCM_OUT}= 5.9 V, 6 mA

< I_{LCM_OUT}< 160mA, Typical

V_{LCM_OUT}

Efficiency

92%

Application Circuit (not ATE tested)

Output voltage step size

Valley current limit

50

1000

170

mV

mA

I_{LCM_BOOST_CL}

R_{DSON_LCM}

High-side MOSFET on resistance

V_IN= V_GS= 3.6 V

mΩ

Low-side MOSFET on Resistance V_IN= V_GS= 3.6 V

290

V_{LCM_OUT_}

RIPPLE

I_{LOAD_LCM_BOOST}= 5 mA and 50 mA,

C_BST= 20 µF

Peak-to-peak ripple voltage⁽⁴⁾

50

mVpp

V_IN+ 500 mVp-p AC square wave, Tr

= 100 mV/µs, 200 Hz, 12.5% DS at

5 mA, I_LOAD= 5 mA, C_IN= 10 µF

V_{LCM_OUT_LINE_}

TRANSIENT

LCM_OUT line transient

response⁽⁴⁾

–50

±25

50

mV

0 mA to 150 mA, t_RISE/FALL= 100

mA/µs,

C_IN= 10 µF

V_{LCM_OUT_LOAD_}LCM_OUT load transient

TRANSIENT

–150

150

mV

µs

response⁽⁴⁾

Start-up time (LCM_OUT),

t_{LCM_OUT_ST}

C_{LCM_OUT}= 20 µF

1000

V_{LCM_OUT}= 10% to 90%⁽⁴⁾

DISPLAY BIAS POSITIVE OUTPUT (VPOS)

Programmable output voltage

range

4

6.5

V

V_VPOS

Output voltage step size

50

mV

Output voltage accuracy

Output voltage = 5.4 V

–1.5%

80

1.5%

I_{VPOS_MAX}

I_{VPOS_CL}

Maximum output current

Output current limit

mA

180

V_{LCM_OUT}= 6.3 V, V_POS= 5.8 V,

C_VPOS= 10 µF (nominal)

I_{RUSH_PK_VPOS}

Peak start-up inrush current⁽⁴⁾

250

50

mA

V_IN+ 500 mVp-p AC square wave, Tr

= 100 mV/µs, 200 Hz at 25 mA, C_IN

10 µF (nominal)

V_{VPOS_}

LINE_TRANSIENT

LDO_VPOS line transient

response⁽⁴⁾

=

–50

mV

V_{VPOS_LOAD_TRA}LDO_VPOS load transient

NSIENT

Load current step 0 mA to 50 mA,

C_VPOS= 10 µF (nominal)

50

20

mV

response⁽⁴⁾

DC load regulation⁽⁴⁾

V_{VPOS_DC_REG}

V_{DO_VPOS}

0 mA ≤ I_{LOAD_VPOS}≤ I_{LOAD_VPOS_MAX}

I_{LOAD_VPOS}= I_{LOAD_VPOS_MAX}

V_VPOS= 5.7 V

VPOS dropout voltage⁽⁵⁾

160

ƒ = 10 Hz to 500 kHz at I_MAX/2

V_{LCM_OUT}– V_VPOS≥ 300 mV

Power supply rejection ratio

(LDO_VPOS)⁽⁴⁾

Start-up time (LDO_VPOS)⁽⁶⁾

V_VPOS= 10% to 90%⁽⁴⁾

PSSR_VPOS

25

30

dB

t_{ST_VPOS}

C_VPOS= 10 µF v

800

80

µs

R_{PD_VPOS}

Output pulldown resistor (VPOS)

VPOS pulldown in shutdown

270

Ω

Pulldown

resistance on

LCM_EN1

Not ATE tested

300

kΩ

(4) Limits set by characterization and/or simulation only.

(5) V_{IN_VPOS}– V_VPOSwhen V_VPOShas dropped 100 mV below target.

(6) Typical value only for information.

7

LM36273

ZHCSGN8D –FEBRUARY 2016–REVISED MARCH 2018

www.ti.com.cn

Electrical Characteristics (continued)

Unless otherwise specified, typical limits apply at 25°C, minimum and maximum limits apply over the full operating ambient

temperature range (−40°C ≤ T_A≤ 85°C), and V_IN= 3.6 V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DISPLAY BIAS NEGATIVE OUTPUT (VNEG)

V_{NEG_SHORT}

V_NEGto CP_GND, VNEG rises to %

of target

NEG output short circuit protection

84%

92%

V_{LCM_OUT}= 5.7 V, V_NEG= –5.4 V,

I_NEG> –5 mA

Efficiency⁽⁶⁾

Programmable output voltage

–6.5

–4

V

V_VNEG

range

Output voltage step size

Output accuracy

50

mV

Output voltage = –5.4 V

–1.5%

80

1.5%

I_{LOAD_VNEG_MAX}Maximum output current

V_{LCM_OUT}= 5.9 V, V_NEG= –5.4 V

mA

I_{VNEG_CL}

Output current limit

135

350

240

Q1

Q2

Q3

R_{DSON_VNEG}

CP FET ON resistance

mΩ

I_NEG= –5 mA and –50 mA,

C_VNEG= 10 µF (nominal)

V_{VNEG_RIPPLE}

Peak-to-peak ripple voltage⁽⁴⁾

VNEG line transient response⁽⁴⁾

V_VNEGload transient response⁽⁴⁾

60

50

mVpp

mV

V_IN+ 500 mVp-p AC square wave,

100 mV/µs 200 Hz,

12.5% duty at 5 mA

V_{VNEG_LINE_TRAN}

SIENT

–50

±25

V_{VNEG_LOAD_TRA}

NSIENT

0 to –50 mA step, t_RISE/FALL= 1 µs,

C_VNEG= 10 µF (nominal)

100

1

mV

ms

V_VNEGstart-up time, V_VNEG= 10% V_VNEG= –6.5 V, C_VNEG= 10 µF

t_{SU_VNEG}

R_VNEG

to 90%⁽⁴⁾

(nominal)

Output pullup resistor (VNEG to

CP_GND)⁽⁴⁾

VNEG pullup in shutdown

Not ATE tested

6

20

Ω

Pulldown

300

kΩ

resistance on

LCM_EN2

PWM INPUT

ƒ_{PWM_INPUT}

PWM input frequency⁽⁶⁾

2.7 V ≤ V_IN≤ 5 V

50

183.3

1100

4400

183.3

1100

4400

50000

Hz

ns

24-MHz sample rate

4-MHz sample rate

1-MHz sample rate

24-MHz sample rate

4-MHz sample rate

1-MHz sample rate

t_{MIN_ON}

Minimum pulse ON time⁽⁴⁾

t_{MIN_OFF}

Minimum pulse OFF timet⁽⁴⁾

ns

Turnon delay from PWM = 0 to

PWM = 50% duty cycle

t_START-UP

PWM_RES

4-MHz sample rate

3.5

ms

PWM input resolution

50 Hz < ƒ_PWM< 11 kHz

Filter = 00

11

0

bits

Filter = 01

100

150

200

t_GLITCH

PWM input glitch rejection

ns

Filter = 10

Filter = 11

LOGIC INPUTS (PWM, HWEN, EN_POS, EN_NEG, SCL, SDA, EN_BL)

V_IL

V_IH

Input logic low

Input logic high

2.7 V ≤ V_IN≤ 5 V

0

0.4

V_IN

V

1.2

LOGIC OUTPUTS (SDA)

V_OLOutput logic low

2.7 V ≤ V_IN≤ 5 V, I_OL= 3 mA

0.4

V

8

LM36273

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6.6 I²C Timing Requirements (Fast Mode)

Over operating free-air temperature range; limits apply over 2.5 V ≤ V_IN≤ 5 V (unless otherwise noted). See 图 1.

MIN

0.5

0.26

1

MAX

UNIT

µs

t_{LOW_SCL}

t_{HIGH_SCL}

ƒ_SCL

SCL low clock period

SCL high clock period

µs

SCL clock frequency

MHz

ns

t_{SU_DAT}

t_{V_DAT}

t_{HD_DAT}

t_START

Data in setup time to SCL high

Data valid time

50

0.45

µs

Data out stable after SCL low

SDA low setup time to SCL low (start)

SDA high hold time after SCL high (stop)

0

260

ns

t_STOP

V_PULLUP= 1.8 V, R_PULLUP= 1 kΩ,

C_BUS= 100 pF

t_RISE

t_FALL

SDA/SCL rise time

SDA/SCL fall time

120

ns

V_PULLUP= 1.8 V, R_PULLUP= 1 kΩ,

C_BUS= 100 pF

t_FALL

t_{SU_DAT}

t_RISE

70%

SDA

30%

t_STOP

t_FALL

t_RISE

t_HIGH

70%

t_{HD_DAT}

t_{V_DAT}

70%

SCL

30%

t_LOW

9^thClock

Pulse

t_START

1/f_SCL

Stop

Start

图 1. I²C Timing Parameters

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6.7 Typical Characteristics

Ambient temperature is 25°C and V_INis 3.7 V unless otherwise noted.

30

25

20

15

10

5

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

25

20

15

10

5

0

256

512

768 1024 1280 1536 1792 2048

0

256

512

768 1024 1280 1536 1792 2048

Brightness Code

D001

D002

图 2. Backlight LED Current, Linear Control

图 3. Backlight LED Current, Exponential Control

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

5

10

15

I_LED(mA)

20

25

30

5

10

15

20

25

30

I_LED(mA)

D003

D004

图 4. Backlight LED Current Matching

图 5. Backlight LED Current Matching

0.6

0.5

0.4

0.3

0.2

0.1

0.0

0.6

0.5

0.4

0.3

0.2

0.1

0.0

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

T_A= -40èC

T_A= 25èC

T_A= 85èC

256

512

768 1024 1280 1536 1792 2048

256

512

768 1024 1280 1536 1792 2048

Brightness Code

D005

D006

图 6. Backlight LED Current-Step Ratio

图 7. Backlight LED Current-Step Ratio

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Typical Characteristics (接下页)

Ambient temperature is 25°C and V_INis 3.7 V unless otherwise noted.

3.0

2.0

1.0

0.0

2.0

1.0

0.0

-1.0

-2.0

-3.0

-1.0

-2.0

-3.0

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

T_A= -40èC

T_A= 25èC

T_A= 85èC

0

256

512

768 1024 1280 1536 1792 2048

0

256

512

768 1024 1280 1536 1792 2048

Brightness Code

D007

D008

图 8. Backlight LED Current Accuracy

图 9. Backlight LED Current Accuracy

1100

1080

1060

1040

1020

1000

980

550

540

530

520

510

500

490

480

470

460

450

960

940

T_A= -40èC

T_A= 25èC

T_A= 85èC

T_A= -40èC

T_A= 25èC

T_A= 85èC

920

900

2.5 2.8 3.1 3.4 3.7

4

4.3 4.6 4.9 5.2 5.5

2.5 2.8 3.1 3.4 3.7

4

4.3 4.6 4.9 5.2 5.5

V_IN(V)

D009

D010

ƒ = 1 MHz

图 10. Backlight Boost Frequency

ƒ = 500 kHz

图 11. Backlight Boost Frequency

275

270

265

260

255

250

245

240

235

230

225

0.32

0.30

0.28

0.26

0.24

0.22

0.20

0.18

0.16

0.14

0.12

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

T_A= -40èC

T_A= 25èC

T_A= 85èC

0

5

10

15

I_LED(mA)

20

25

30

2.5 2.8 3.1 3.4 3.7

4

4.3 4.6 4.9 5.2 5.5

V_IN(V)

D027

D011

ƒ = 250 kHz

图 12. Backlight Boost Frequency

图 13. Backlight Regulated Headroom Voltage

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Typical Characteristics (接下页)

Ambient temperature is 25°C and V_INis 3.7 V unless otherwise noted.

0.32

0.30

0.28

0.26

0.24

0.22

0.20

0.18

0.16

0.14

0.12

4.875

4.850

4.825

4.800

4.775

4.750

4.725

T_A= -40èC

T_A= 25èC

T_A= 85èC

T_A= -40èC

T_A= 25èC

T_A= 85èC

0

20

40

60

80

100

120

140

160

0

5

10

15

I_LED(mA)

20

25

30

Load (mA)

D012

D014

D016

D028

V_{LCM_OUT}= 4.8 V

图 15. V_{LCM_OUT}Load Regulation

图 14. Backlight Regulated Headroom Voltage

5.900

5.875

5.850

5.825

5.800

5.775

5.750

5.725

5.700

5.900

5.875

5.850

5.825

5.800

5.775

5.750

5.725

5.700

T_A= -40èC

T_A= 25èC

T_A= 85èC

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

0

20

40

60

80

100

120

140

160

0

20

40

60

80

100

120

140

160

Load (mA)

D013

V_{LCM_OUT}= 5.8 V

图 16. V_{LCM_OUT}Load Regulation

图 17. V_{LCM_OUT}Load Regulation

6.900

6.875

6.850

6.825

6.800

6.775

6.750

6.725

6.700

4.06

4.04

4.02

4.00

3.98

3.96

3.94

T_A= -40èC

T_A= 25èC

T_A= 85èC

T_A= -40èC

T_A= 25èC

T_A= 85èC

0

20

40

60

80

100

120

140

160

0

10

20

30

40

50

60

70

80

Load (mA)

D015

V_{LCM_OUT}= 6.8 V

图 18. V_{LCM_OUT}Load Regulation

V_VPOS= 4 V

V_{LCM_OUT}= 4.3 V

图 19. V_VPOSLoad Regulation

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Typical Characteristics (接下页)

Ambient temperature is 25°C and V_INis 3.7 V unless otherwise noted.

5.58

5.56

5.54

5.52

5.50

5.48

5.46

5.44

5.42

5.58

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

5.56

5.54

5.52

5.50

5.48

5.46

5.44

5.42

T_A= -40èC

T_A= 25èC

T_A= 85èC

0

10

20

30

40

50

60

70

80

0

10

20

30

40

50

60

70

80

Load (mA)

D017

D018

V_VPOS= 5.5 V

V_{LCM_OUT}= 5.8 V

图 20. V_VPOSLoad Regulation

V_VPOS= 5.5 V

V_{LCM_OUT}= 5.8 V

图 21. V_VPOSLoad Regulation

6.60

-3.94

6.58

6.56

6.54

6.52

6.50

6.48

6.46

6.44

6.42

6.40

-3.96

-3.98

-4.00

-4.02

-4.04

-4.06

T_A= -40èC

T_A= 25èC

T_A= 85èC

T_A= -40èC

T_A= 25èC

T_A= 85èC

0

10

20

30

40

50

60

70

80

0

10

20

30

40

50

60

70

80

Load (mA)

D019

D020

V_VPOS= 6.5 V

V_{LCM_OUT}= 6.8 V

图 22. V_VPOSLoad Regulation

V_VNEG= –4 V

V_{LCM_OUT}= 4.3 V

图 23. V_VNEGLoad Regulation

-5.42

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

-5.44

-5.46

-5.48

-5.50

-5.52

-5.54

-5.56

-5.58

-5.44

-5.46

-5.48

-5.50

-5.52

-5.54

-5.56

-5.58

T_A= -40èC

T_A= 25èC

T_A= 85èC

0

10

20

30

40

50

60

70

80

0

10

20

30

40

50

60

70

80

Load (mA)

D021

D022

V_VNEG= –5.5 V

V_{LCM_OUT}= 5.8 V

图 24. V_VNEGLoad Regulation

V_VNEG= –5.5 V

V_{LCM_OUT}= 5.8 V

图 25. V_VNEGLoad Regulation

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Typical Characteristics (接下页)

Ambient temperature is 25°C and V_INis 3.7 V unless otherwise noted.

-6.40

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

T_A= -40èC

T_A= 25èC

T_A= 85èC

-6.42

-6.44

-6.46

-6.48

-6.50

-6.52

-6.54

-6.56

T_A= -40èC

T_A= 25èC

-6.58

T_A= 85èC

-6.60

0

10

20

30

40

50

60

70

80

2.5 2.8 3.1 3.4 3.7

4

4.3 4.6 4.9 5.2 5.5

Load (mA)

V_IN(V)

D023

D024

V_VNEG= –6.5 V

V_{LCM_OUT}= 6.8 V

图 26. V_VNEGLoad Regulation

V_HWEN= 0 V

I²C = 0 V

图 27. Iq Shutdown

2.4

10

9

8

7

6

5

4

3

2

1

0

T_A= -40èC

T_A= 25èC

T_A= 85èC

T_A= -40èC

T_A= 25èC

T_A= 85èC

2.2

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

2.5 2.8 3.1 3.4 3.7

4

4.3 4.6 4.9 5.2 5.5

2.5 2.8 3.1 3.4 3.7

4

4.3 4.6 4.9 5.2 5.5

V_IN(V)

D025

D026

V_HWEN= V_IN

I²C = V_IN

V_HWEN= 1.8 V

I²C = 1.8 V

图 28. I_QStandby

图 29. I_QStandby

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7 Detailed Description

7.1 Overview

The LM36273 is a single-chip, complete backlight and LCM power solution. The device operates over the 2.7-V

to 5-V input voltage range.

The backlight block consists of an inductive boost plus three current sink white-LED drivers designed to power

from one to three LED strings with up to eight LEDs each (up to 28 V typical), with a maximum of 30 mA per

string. A higher number of LEDs per string can be supported if the total output power requirement for the boost

does not exceed 2.5 Watts. The power for the LED strings comes from an integrated asynchronous backlight

boost converter with three selectable switching frequencies to optimize performance or solution area. LED

current is regulated by the low-headroom current sinks. The inductive backlight boost automatically adjusts its

output voltage to keep the active current sinks in regulation, while minimizing current sink headroom voltage. The

11-bit LED current is set via an I²C interface, via a logic level PWM input, or a combination of both.

The LCM bias power portion of the LM36273 consists of a synchronous LCM bias boost converter, inverting

charge pump, and an integrated LDO. The LCM positive bias voltage VPOS (up to 6.5 V) is post-regulated from

the LCM bias boost converter output voltage. The LCM negative bias voltage VNEG (down to –6.5 V) is

generated from the LCM bias boost converter output using a regulated inverting charge pump.

The LM36273 flexible control interface consists of an HWEN active low reset input, LCM_EN1 and LCM_EN2

inputs for VPOS and VNEG enable control, PWM input for content adaptive backlight control (CABC), and an

I²C-compatible interface.

Additionally, there is a flag register with flag and status bits. The user can read back this register and determine if

a fault or warning message has been generated.

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7.2 Functional Block Diagram

BL_SW

BL_OUT

Reference and

Thermal Shutdown

Programmable

Overvoltage Protection

(17 V, 21 V, 25 V, 29 V)

IN

POR

(1.8V)

Programmable

500 kHz/1 MHz

Oscillator

Backlight Boost Converter

BL_GND

Global Active-low

Reset

HWEN

PWM

LED1

LED2

LED3

Overcurrent

Protection

V

HR

Feedback

Backlight LED Control

PWM Sampler

1. 11-bit Brightness

Adjustment

2. Exponential/Linear

Dimming

3. LED Current

Ramping

4. Auto Frequency

Mode

SDA

SCL

I²C Compatible

Interface

BL LED Drivers

VPOS

(LCM Postive Bias)

VPOS

LCM_EN1

LCM_EN2

LCM Bias

Output Control

LCM Boost Converter

C+

VNEG

(LCM Negative Bias)

VNEG

Internal Logic

AGND

C-

LCM_SW

LCM_GND LCM_OUT

CP_GND

7.3 Features Description

7.3.1 Enabling the LM36273

The LM36273 has a logic level input HWEN which serves as the master enable/disable for the device. When

HWEN is low the device is disabled, the registers are reset to their default state, the I²C bus is inactive, and the

device is placed in a low-power shutdown mode. When HWEN is forced high the device is enabled, and I²C

writes are allowed to the device.

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Features Description (接下页)

7.3.2 Backlight

The high voltage required by the LED strings is generated with an asynchronous backlight boost converter. An

adaptive voltage control loop automatically adjusts the output voltage based on the voltage over the LED drivers

LED1, LED2 and LED3. The LM36273 has three switching frequency modes, 1 MHz, 500 kHz, and 250 kHz.

These are set via the BL_FREQ Select bit, register 0x03 bit[7] and by utilizing the auto-frequency feature (refer

to Auto Switching Frequency). Operation in low-frequency mode results in better efficiency at lighter load

currents due to the decreased switching losses. Operation in high-frequency mode gives better efficiency at

higher load currents due to the reduced inductor current ripple and the resulting lower conduction losses in the

MOSFET and inductor.

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Features Description (接下页)

BL_SW BL_SW

BL_GND

Overvoltage

Protection

17 V

BL_OUT

21 V

25 V

29 V

OVP

0.2 ꢀ

Boost Control

Fault Detection

OCP

Overvoltage

Current Limit

Thermal Shutdown

Boost Switching

Frequency

1 MHz

TSD

500 kHz

250 kHz

Thermal

Shutdown

140^oC

Auto Frequency

Mode

SDA

Boost Current Limit

900 mA

I²C Interface

1200 mA

1500 mA

1800 mA

Min Headroom

Select

SCL

Adaptive

Headroom

Current Sinks

LED1

LED2

LED3

PWM Sample Rate

11-Bit

Brightness

Code

1 MHz

4 MHz

24 MHz

LED Current

Mapping

Exponential

Linear

LED Current

LED String

Enables

Ramping

16 - Levels

0 to 8 s

PWM

PWM Sampler

图 30. Backlight Block Diagram

7.3.2.1 Current Sink Enable

Each current sink in the device has a separate enable input. This allows for a one-string, two-string or three-

string application. Once the correct LED string configuration is programmed and a non-zero code is written to the

brightness registers, the device can be enabled by writing the backlight enable bit high (register 0x08 bit[4]).

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Features Description (接下页)

The default settings for the device are backlight enable bit set to 0, all backlight strings disabled, PWM input

disabled, linear mapped mode, and the brightness level set to 30 mA per string.

When PWM is enabled, the LM36273 actively monitors the PWM input. After a non-zero PWM duty cycle is

detected, the LM36273 multiplies the duty cycle with the programmed I²C brightness code to give an 11-bit

brightness value between 60 µA and 30 mA. 图 31 and 图 32 describe the start-up timing for operation with I²C

controlled current and with PWM controlled current.

VIN

HWEN

I2C Registers In

Reset

I2C LED

Strings Enable

I2C Brightness

Data Sent

I2C Data Valid

I2C

ILED

t_{BRT_DAC}

t_{HWEN_I2C}

(< 50 µs)

t_{DAC_LED}

(< 800 µs)

(< 30 µs)

图 31. Enabling the LM36273 via I²C

VIN

HWEN

I2C Registers In

I2C LED

Strings Enable

I2C PWM Pin

Enable

I2C Data Valid

I2C

Reset

PWM

ILED

t_{PWM_DAC}

t_{HWEN_I2C}

(< 50 µs)

t_{DAC_LED}

(< 30 µs) (< 800 µs)

t_{DD_LED}

t_{PWM_STBY}

图 32. Enabling the LM36273 via PWM

The LM36273 backlight can be enabled or disabled in various ways. When disabled, the device is considered

shut down, and the quiescent current drops to I_SHDN. When the device is in standby, it returns to the I_STANDBY

current level retaining all programmed register values. 表 1 describes the different backlight operating states for

the LM36273.

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Features Description (接下页)

表 1. Backlight Operating Modes

I²C

CURRENT

SINK

ENABLES

0x08[2:0]

FEEDBACK

DISABLES

0x10[5:3]

BL_EN

0x08[4]

PWM EN PWM RAMP

MAPPING MODE

0x02[3]

BRIGHTNESS

0x05[7:0]

0x04[2:0]

HWEN

PWM INPUT

ACTION

0x02[0]

0x02[1]

0

1

X

0

1

X

Shutdown

Standby⁽¹⁾

0x000

000

-Backlight boost enabled

-Selected current sink(s) enabled

-I²C control only

0 = Exponential Mode

1 = Linear Mode

1

X

≥0x001

≥001

0

1

X

<111

Duty cycle = 0

X

Standby⁽¹⁾

-Backlight boost enabled

-Selected current sink(s) enabled

0 = Exponential Mode

1 = Linear Mode

-I²C × PWM (after ramper)

-No ramp between PWM duty-

cycle change

1

Duty cycle > 0

≥0x001

≥001

1

0

<111

-Backlight boost enabled

-Selected current sink(s) enabled

-I²C × PWM (before ramper)

0 = Exponential Mode

1 = Linear Mode

1

Duty cycle > 0

≥0x001

≥001

1

0

1

<111

111

-Backlight boost disabled

-Selected current sink(s) enabled

-I²C × PWM (after ramper)

0 = Exponential Mode

1 = Linear Mode

-Backlight boost disabled

-Selected current sink(s) enabled

-I²C × PWM (before ramper)

0 = Exponential Mode

1 = Linear Mode

111

(1) Standby implies the backlight boost and current sinks are shut down. Register writes are still possible. Shutdown implies that the device

is in reset and no I²C communication is possible.

7.3.2.2 Brightness Mapping

There are two different ways to map the brightness code (or PWM duty cycle) to the LED current: linear and

exponential mapping.

7.3.2.2.1 Linear Mapping

For linear mapped mode the LED current increases proportionally to the 11-bit brightness code and follows the

relationship:

I_LED= 45.37 µA + 14.63 µA × Code

(1)

This is valid from codes 1 to 2047. Code 0 programs 0 current. Code is an 11-bit code that can be the I²C

brightness code or the product of the I²C brightness code and the PWM duty cycle.

7.3.2.2.2 Exponential Mapping

In exponential mapped mode the LED current follows the relationship:

I_LED= 60 µA × 1.003040572^Code

(2)

This results in an LED current step size of approximately 0.304% per code. This is valid for codes from 1 to

2047. Code 0 programs 0 current. Code is an 11-bit code that can be the I²C brightness code or the product of

the I²C brightness code and the PWM duty cycle. 图 33 details the LED current exponential response.

The 11-bit (0.304%) per code step is small enough such that the transition from one code to the next in terms of

LED brightness is not distinguishable to the eye. This, therefore, gives a perfectly smooth brightness increase

between adjacent codes.

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100

10

1

0.1

0.01

0

256

512

768 1024 1280 1536 1792 2048

11-Bit Brightness Code

图 33. LED Current vs Brightness Code (Exponential Mapping)

7.3.2.3 Backlight Brightness Control Modes

The LM36273 has 2 brightness control modes:

1. I²C only brightness control

2. I²C × PWM brightness control

7.3.2.3.1 I²C Brightness Control (PWM Pin Disabled)

If the PWM pin is disabled the I²C brightness registers are in control of the LED current, and the PWM input is

disabled. The brightness data (BRT) is the concatenation of the two brightness registers (3 LSBs) and (8 MSBs)

(registers 0x04 and 0x05, respectively). The LED current only changes when the MSBs are written, meaning that

to do a full 11-bit current change via I²C, first the 3 LSBs are written and then the 8 MSBs are written. In this

mode the ramper only controls the time from one I²C brightness set-point to the next 图 34.

V_OUT

Boost

Digital Domain

Analog Domain

Min V_HR

RAMP_RATE Bits

I_LED3

I_LED1

I_LED2

Driver_1

BRT Code = I2C

Code

DAC_i

Driver_2

Driver_3

Ramper

Mapper

DAC

I2C Brightness Reg

MAP_MODE

图 34. I²C Only Brightness Control

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7.3.2.3.2 I²C × PWM Brightness Control (PWM Pin Enabled)

If the PWM pin is enabled both the I²C brightness code and the PWM duty-cycle control the LED current.

With linear mapping the PWM duty cycle-to-current response is approximated by 公式 3:

I_LED= 45.37 µA + 14.63 µA × I²C BRGT CODE × PWM D/C

(3)

(4)

With exponential mapping the PWM duty cycle-to-current response is approximated by 公式 4:

I_LED= 60 µA × 1.003040572^{I2C BRGT CODE × PWM D/C}

7.3.2.3.2.1 PWM Ramper

The PWM ramp option (register 0x02 bit[1]) determines whether the ramper is active or inactive during a change

in PWM duty cycle.

The ramper smooths the transition from one brightness value to another. Ramp time can be adjusted from 0 ms

to 8000 ms with LED Current Ramp [3:0] bits (register 0x03 bits [6:3]). Ramp time is used for sloping both up and

down. Ramp time always remains the same regardless of the amount of change in brightness.

In PWM mode the behavior of the ramper depends on the state of the PWM Ramp bit (register 0x02, bit [1]). If

the PWM Ramp bit is set to 0, there is no LED current ramping between PWM duty cycle changes. The PWM

duty cycle is multiplied with the I²C brightness code at the output of the ramper (see 图 35). If this bit is set to 1,

ramping is achieved between I²C × PWM currents (see 图 36).

V_OUT

Boost

Digital Domain

Analog Domain

Min V_HR

RAMP_RATE Bits

I_LED3

I_LED1

I_LED2

Driver_1

BRT Code =

I2C × Duty Cycle

DAC_i

Driver_2

Driver_3

I2C Brightness Reg

Ramper

Mapper

DAC

MAP_MODE

PWM Input

PWM Detector

图 35. (I²C + PWM) Brightness Control, PWM Ramper Disabled

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V_OUT

Boost

Digital Domain

Analog Domain

Min V_HR

I_LED3

I_LED1

I_LED2

RAMP_RATE Bits

Driver_1

Driver_2

Driver_3

BRT Code =

I2C × Duty Cycle

DAC_i

DAC

I2C Brightness Reg

Ramper

Mapper

MAP_MODE

PWM

Detector

PWM Input

图 36. (I²C + PWM) Brightness Control, PWM Ramper Enabled

7.3.2.4 Boost Switching Frequency

The LM36273 has two programmable switching frequencies: 500 kHz and 1 MHz. These are set via the Backlight

Configuration 2 register (register 0x03 bit [7]). Operation at 1 MHz is primarily beneficial when efficiency at high

load current is more important. For maximum efficiency across the entire load current range the device

incorporates an automatic frequency shift mode (see Auto Switching Frequency).

7.3.2.4.1 Minimum Inductor Select

The LM36273 can use inductors in the range of 4.7 µH to 15 µH. In order to optimize the converter response to

changes in V_INand load, the Backlight Boost L Select bits (register 0x11 bits [7:6]) must be selected depending

on the nominal value of inductance chosen.

7.3.2.5 Boost Feedback Gain Select

The Boost Integral and Proportional Feedback Gain Select bits in Option 2 register (bits [3:2] and bits[5:4] in

register 0x11) contain adjustment parameters for the LM36273 internal loop gain. The optimized settings using a

1-uF capacitor at BL_OUT are the default settings of 01 and 11 for Integral and Proportional, respectively.

7.3.2.6 Auto Switching Frequency

To take advantage of frequency vs load dependent losses, the LM36273 can automatically change the boost

switching frequency based on the programmed brightness code. In addition to the register programmable

switching frequencies of 500 kHz and 1 MHz, the auto-frequency mode also incorporates a low-frequency

selection of 250 kHz. It is important to note that the 250-kHz frequency is only accessible in auto-frequency

mode and has a maximum boost duty cycle (D_MAX) of 50%.

Auto-frequency mode operates by using two programmable registers (Backlight Auto Frequency Low Threshold

(register 0x06) and Backlight Auto Frequency High Threshold (register 0x07)). The high threshold determines the

switchover from 1 MHz to 500 kHz. The low threshold determines the switchover from 500 kHz to 250 kHz. Both

the High and Low Threshold registers take an 8-bit code which is compared against the 8 MSB of the brightness

register (register 0x05). 表 2 details the boundaries for this mode.

表 2. Auto Switching Frequency Operation

BRIGHTNESS CODE MSBs (Register 0x05 bits[7:0])

BOOST SWITCHING FREQUENCY

< Auto Frequency Low Threshold (register 06 Bits[7:0])

250 kHz (D_MAX= 50%)

> Auto Frequency Low Threshold (Register 06 Bits[7:0]) and < Auto

Frequency High Threshold (Register 07 Bits[7:0])

500 kHz

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表 2. Auto Switching Frequency Operation (接下页)

BRIGHTNESS CODE MSBs (Register 0x05 bits[7:0])

BOOST SWITCHING FREQUENCY

≥ Auto Frequency High Threshold (register 07 Bits[7:0])

1 MHz

Automatic-frequency mode is enabled whenever there is a non-zero code in either the Auto-Frequency High or

Auto-Frequency Low registers. To disable the auto-frequency shift mode, set both registers to 0x00. When

automatic-frequency select mode is disabled, the switching frequency operates at the programmed frequency

(Register 0x03 bit[7]) across the entire LED current range. 表 3 provides a guideline for selecting the auto

frequency threshold settings at V_IN= 3.7 V. The actual setting must be verified in the application and optimized

for the desired input voltage range.

表 3. Auto Frequency Threshold Settings Examples, V_IN= 3.7 V

CONDITION

(V_f= 3.35 V at I_LED

30 mA)

INDUCTOR

(µH)

RECOMMENDED AUTO FREQUENCY

HIGH THRESHOLD

RECOMMENDED AUTO FREQUENCY

LOW THRESHOLD

=

2 × 4 LEDs

2 × 5 LEDs

2 × 6 LEDs

2 × 7 LEDs

2 × 8 LEDs

3 × 4 LEDs

3 × 5 LEDs

3 × 6 LEDs

3 × 7 LEDs

3 × 8 LEDs

10

0x65 (12 mA)

0x5C (11 mA)

0x54 (10 mA)

0x4F (9.4 mA)

0x65 (12 mA)

0x4C (9 mA)

0x43 (8mA)

0x43 (8 mA)

0x42 (7.9 mA)

0x3F (7.5 mA)

0x36 (6.5 mA)

0x3F (7.5 mA)

0x2A (5.1 mA)

0x28 (4.8 mA)

0x27 (4.7 mA)

0x26 (4.6 mA)

0x25 (4.5 mA)

0x3B (7 mA)

0x35 (6.4 mA)

0x43 (8 mA)

7.3.2.7 PWM Input

The PWM input is a sampled input which converts the input duty cycle information into an 11-bit brightness code.

The use of a sampled input eliminates any noise and current ripple that traditional PWM controlled LED drivers

are susceptible to. It also allows the PWM duty cycle to LED current response to have the same high accuracy

and matching that is offered in the I²C brightness control.

The PWM input uses logic level thresholds with V_{IH_MIN}= 1.25 V and V_{IL_MAX}= 0.4 V. Because this is a sampled

input, there are limits on the maximum PWM input frequency as well as the resolution that can be achieved.

7.3.2.7.1 PWM Sample Frequency

There are three selectable sample rates for the PWM input. The choice of sample rate depends on three factors:

1. Required PWM resolution (input duty cycle to brightness code, with 11 bits maximum)

2. PWM input frequency

3. Efficiency

7.3.2.7.1.1 PWM Resolution and Input Frequency Range

The PWM input frequency range is 50 Hz to 50 kHz. To achieve the full 11-bit maximum resolution of PWM duty

cycle to the LED brightness code (BRT), the input PWM duty cycle must be ≥ 11 bits, and the PWM sample

period (1/ƒ_SAMPLE) must be smaller than the minimum PWM input pulse width. 图 37 shows the possible

brightness code resolutions based on the input PWM frequency. The minimum PWM frequency for each PWM

sample rate is described in PWM Timeout.

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12

11

10

9

8

7

6

Sample Freq = 1 MHz

Sample Freq = 4 MHz

Sample Freq = 24 MHz

5

4

100

1000

10000

100000

PWM Frequency (Hz)

图 37. PWM Sample Rate, Resolution, and PWM Input Frequency

7.3.2.7.1.2 PWM Sample Rate and Efficiency

Efficiency is maximized when the lowest ƒ_SAMPLEis chosen because this lowers the quiescent operating current

of the device. 表 4 describes the typical efficiency tradeoffs for the different sample clock settings.

表 4. PWM Sample Rate Trade-Offs

TYPICAL INPUT CURRENT, DEVICE ENABLED

PWM SAMPLE RATE (ƒ_SAMPLE

)

TYPICAL EFFICIENCY

I_LED= 10 mA/string, 3 × 6 LEDs

0x03 Bit[2]

0x12 Bit[0]

ƒ_SW= 1 MHz

V_IN= 3.7 V

87.7%

0

1

0

1

1.685 mA

1.756 mA

87.66%

87.2%

X

2.479 mA

7.3.2.7.1.2.1 PWM Sample Rate Example

The number of bits of resolution on the PWM input varies according to the PWM sample rate and PWM input

frequency (see 表 5).

表 5. PWM Resolution vs PWM Sample Rate

PWM

FREQUENCY

(kHz)

RESOLUTION

(PWM SAMPLE RATE = 1 MHz)

RESOLUTION

(PWM SAMPLE RATE = 4 MHz)

RESOLUTION

(PWM SAMPLE RATE = 24 MHz)

0.4

2

11

9

11

12

6.4

8.4

7.3.2.7.2 PWM Hysteresis

To prevent jitter at the input PWM signal from feeding through the PWM path and causing oscillations in the LED

current, the LM36273 offers 4 selectable hysteresis settings. The hysteresis options for the 1-MHz and 4-MHz

PWM sample rate settings are 1, 2, 4, and 6 bits and for the 24-MHz PWM sample rate setting 0, 1, 2, and 3 bits.

The hysteresis works by forcing a specific number of 11-bit LSB code transitions to occur in the input duty cycle

before the LED current changes. 表 6 describes the hysteresis. The hysteresis only applies during the change in

direction of brightness currents. Once a change in the direction of the LED current has taken place, the PWM

input must over come the required LSB(s) of the hysteresis setting before the brightness change takes effect.

Once the initial hysteresis has been overcome and the direction in brightness change remains the same, the

PWM to current response changes with no hysteresis.

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表 6. PWM Input Hysteresis

MIN CHANGE IN PWM

PULSE WIDTH (Δt)

MIN CHANGE IN PWM

DUTY CYCLE (ΔD)

MIN (ΔI_LED), INCREASE FOR INITIAL CODE

CHANGE

HYSTERESIS SETTING REQUIRED TO CHANGE REQUIRED TO CHANGE

(0x03 Bits[1:0])

LED CURRENT, AFTER

DIRECTION CHANGE

(for ƒ_PWM< 11.7 kHz)

LED CURRENT AFTER

DIRECTION CHANGE

EXPONENTIAL MODE

LINEAR MODE

0 LSB (24 MHz sample

rate only)

1/(ƒ_PWM× 2047)

0.05%

0.30%

0.05%

1 LSB

1/(ƒ_PWM× 1023)

1/(ƒ_PWM× 511)

1/(ƒ_PWM× 255)

0.10%

0.20%

0.39%

0.61%

1.21%

2.40%

0.10%

0.20%

0.39%

2 LSBs

3 LSBs (24-MHz sample

rate only)

4 LSBs (1-MHz and 4-

MHz sample rate only)

1/(ƒ_PWM× 127)

1/(ƒ_PWM× 31)

0.78%

3.12%

4.74%

0.78%

3.12%

6 LSBs (1-MHz and 4-

MHz sample rate only )

17.66%

t_JITTER

D/f_PWM

1/f_PWM

ñ

D is t_JITTERx f_PWMor equal to #LSB‘s = ∆D x 2048 codes.

For 11-bit resolution, #LSBs is equal to a hysteresis setting of LN(#LSB‘s)/LN(2).

For example, with a t_JITTERof 1 µs and a f_PWMof 5 kHz, the hysteresis setting should be:

LN(1 µ s x 5 kHz x 2048)/LN(2) = 3.35 (4 LSBs).

图 38. PWM Hysteresis Example

7.3.2.7.3 PWM Step Response

The LED current response due to a step change in the PWM input is approximately 2 ms to go from minimum

LED current to maximum LED current.

7.3.2.7.4 PWM Timeout

The LM36273 PWM timeout feature turns off the boost output when the PWM is enabled and there is no PWM

pulse detected. The timeout duration changes based on the PWM sample rate selected which results in a

minimum supported PWM input frequency. The sample rate, timeout, and minimum supported PWM frequency

are summarized in 表 7.

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表 7. PWM Timeout and Minimum Supported PWM Frequency vs PWM Sample Rate

SAMPLE RATE

TIMEOUT

25 msec

3 msec

MINIMUM SUPPORTED PWM FREQUENCY

1 MHz

4 MHz

24 MHz

48 Hz

400 Hz

2000 Hz

0.6 msec

7.3.2.7.5 PWM-to-Digital Code Readback

In PWM mode, registers 0x12 and 0x13 contain the PWM duty cycle to the 11-bit code conversion information.

Register 0x12 contains the 8 LSBs of the brightness code and register 0x13 the 3 MSBs. To translate this

reading to the actual LED current setting of the LM36273, convert it to the corresponding duty cycle and multiply

it by the brightness level setting in the brightness registers (0x04 and 0x05). For example, if the 11-bit brightness

code is set to 0x554 (decimal 1364) and the PWM-to-digital code readback is 0x3FF (decimal 1023) in linear

mode, the expected LED current is approximately: I_LED= 45.37 µA + ( ( 1023 / 2047 ) × 14.63 × 1364 ) µA =

10.018 mA (approximately 50% duty cycle).

7.3.2.8 Regulated Headroom Voltage

In order to optimize efficiency, current accuracy, and string-to-string matching the LED current sink regulated

headroom voltage (V_HR) varies with the target LED current. 图 39 details the typical variation of V_HRwith LED

current. This allows for increased solution efficiency as the dropout voltage of the LED driver changes.

Furthermore, in order to ensure that all current sinks remain in regulation whenever there is a mismatch in string

voltages, the minimum headroom voltage between VLED1, VLED2, VLED3 becomes the regulation point for the

boost converter. For example, if the LEDs connected to LED1 require 12 V, the LEDs connected to LED2 require

12.5 V and the LEDs connected to LED3 require 13 V at the programmed current, then the voltage at LED1 is

VHR + 1 V, the voltage at LED2 is V_HR+ 0.5 V and the voltage at LED3 is regulated at VHR. In other words, the

boost makes the cathode of the highest voltage LED string the regulation point.

0.32

0.3

0.28

0.26

0.24

0.22

0.2

0.18

0.16

0.14

0.12

0.1

1

10

50

LED Current (mA)

图 39. LM36273 Typical Exponential Regulated Headroom Voltage vs Programmed LED Current

7.3.2.9 Backlight Fault Protection and Faults

7.3.2.9.1 Backlight Overvoltage Protection (OVP)

The LM36273 provides an OVP that monitors the LED boost output voltage (V_{BL_OUT}) and protects BL_OUT and

BL_SW from exceeding safe operating voltages. The OVP threshold can be set to 17 V, 21 V, 25 V, or 29 V with

register 0x02 bits[7:5]. Once an OVP event has been detected, the BL_OVP flag is set in the Flags Register, and

the subsequent behavior depends on the state of bit OVP_Mode in the Backlight Configuration 1 Register: If

OVP_Mode is set to 0, as soon as V_{BL_OUT}falls below the backlight OVP threshold, the LM36273 begins

switching again. If OVP_Mode is set to 1 and the device detects three occurrences of V_{BL_OUT}> V_{OVP_BL}while

any of the enabled current sink headroom voltages drops below 40 mV, the Backlight Boost OVP flag is set, the

Backlight Enable bit is cleared, and the LM36273 enters standby mode. When the device is shut down due to a

Backlight Boost OVP fault, the Flags register must be read back before the device can be reenabled.

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7.3.2.9.2 Backlight Overcurrent Protection (OCP)

The LM36273 has 4 selectable OCP thresholds (900 mA, 1200 mA, 1500 mA, and 1800 mA). These are

programmable in register 0x11 bits[1:0]. The OCP threshold is a cycle-by-cycle current limit and is detected in

the internal low-side NFET. Once the threshold is hit the NFET turns off for the remainder of the switching period.

If enough overcurrent threshold events occur, the BL_OCP Flag (register 0x0F, bit[0]) is set. To avoid transient

conditions from inadvertently setting the BL_OCP Flag, a pulse density counter monitors OCP threshold events

over a 128-µs period. If 8 consecutive 128-µs periods occur where the pulse density count has found 2 or more

OCP events, then the BL_OCP Flag is set.

During device start-up and during brightness code changes, there is a 4-ms blank time where BL OCP events

are ignored. As a result, if the device starts up in an overcurrent condition there is an approximate 5-ms delay

before the BL_OCP Flag is set.

7.3.3 LCM Bias

7.3.3.1 Display Bias Boost Converter (V_VPOS, V_VNEG

)

A single high-efficiency boost converter provides a positive voltage rail, V_{LCM_OUT}, which serves as the power rail

for the LCM VPOS and VNEG outputs.

•

The V_VPOSoutput LDO has a programmable range from 4 V up to 6.5 V with 50-mV steps and can supply up

to 80 mA.

•

The V_VNEGoutput is generated from a regulated, inverting charge pump and has an adjustable range of

–6.5 V up to –4 V with 50-mV steps and a maximum load of 80 mA.

Boost voltage also has a programmable range from 4 V up to 7.15 V with 50-mV steps. Refer to 表 22, 表 23 and

表 24 for V_{LCM_OUT}, V_VPOSand V_VNEGvoltage settings. When selecting a suitable boost-output voltage, the

following estimation can be used: V_{LCM_OUT}= max(V_VPOS, |V_VNEG|) + V_HR, where V_HR≥ 200 mV for lower currents

and V_HR≥ 300 mV for higher currents. When the device input voltage (V_IN) is greater than the programmed LCM

boost output voltage, the boost voltage is regulated to V_IN+ 100 mV. V_VPOSand V_VNEGvoltage settings cannot be

changed while they are enabled. V_VPOSand V_VNEGregister setting targets take effect only after the outputs are

disabled and re-enabled. However, the V_{LCM_OUT}target changes immediately upon a register write.

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VPOS

4 V to 6.5 V

50 mV steps

LDO

VPOS

(VPOS)

ENP

SCL

SDA

Auto Sequence

ENP

ENN

Bias Registers

Slew Rate

Control

LCM_EN1

LCM_EN2

VNEG

-4 V to -6.5 V

-50 mV steps

VBST

4 V to 7.15 V

50 mV steps

Current Limit

1 A

2.5 MHz

LCM Boost

control

Inverting

Charge Pump

(VNEG)

VNEG

ENN

0.29 ꢀ

0.17 ꢀ

C-

C+

图 40. LCM Boost Block Diagram

The LCM Bias outputs can be controlled either by pins LCM_EN1 and LCM_EN2 or register bits VPOS_EN and

VNEG_EN, register 0x09 bits[2:1]. Setting bit EXT_EN, register 0x09 bit[0], to 1 allows pins LCM_EN1 and

LCM_EN2 to control VPOS and VNEG, respectively, while setting this bit to 0 yields control to bits VPOS_EN

and VNEG_EN. Refer to 表 8 for LCM bias control information.

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表 8. LCM Operating Modes

LCM_EN2

INPUT

LCM_EN1

INPUT

LCM_EN MODE

0x09[7:5]

VPOS_EN

0x09[2]

VNEG_EN

0x09[1]

EXT_EN

0x09[0]

HWEN

ACTION

Device shutdown

0

1

X

0

X

0

1

X

0

X

1

0

XXX

000

100

X

0

X

0

X

1

0

1

Standby⁽¹⁾

X

VPOS enabled via external input

VNEG enabled via external input

VPOS and VNEG enabled via external

input

1

100

X

1

VPOS enabled via I²C

1

X

100

1

0

1

0

1

0

VNEG enabled via I²C

VPOS and VNEG enabled via I²C

VPOS and VNEG enabled via I²C with

auto-sequencing

1

X

1

X

101

1

0

1

VPOS and VNEG enabled via LCM_EN2

with auto-sequencing

X

WAKE1

1

X

110

1

0

1

0

1

X

V_VPOS= V_IN

V_VNEG= GND

WAKE1

V_VPOS= GND

V_VNEG= –V_IN

WAKE1

V_VPOS= V_IN

V_VNEG= –V_IN

WAKE1

1

0

1

X

110

1

0

1

0

X

Standby⁽¹⁾

WAKE1

Standby⁽¹⁾

WAKE2

1

X

111

1

0

1

0

1

X

V_VPOS= programmed target

V_VNEG= disabled

WAKE2

V_VPOS= disabled

V_VNEG= programmed target

WAKE2

V_VPOS= programmed target

V_VNEG= programmed target

WAKE2

1

0

X

111

0

1

0

1

X

Standby⁽¹⁾

WAKE2

Standby⁽¹⁾

(1) Standby implies that VPOS and VNEG are either high impedance or being internally pulled low via the active pulldown, and that the

LCM boost is off. Shutdown implies that the device is in reset and no I²C communication is possible.

7.3.3.2 Auto Sequence Mode

If this mode is selected the LM36273 controls the turnon and turnoff of VPOS and VNEG as shown in 图 41.

VPOS

VNEG

VPOS

VNEG

T_R= 256 µs

to

T_F= 512 µs

to

≥ 1 ms

1024 µs

8192 µs

图 41. Auto Sequence Timing

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7.3.3.3 Wake-up Mode

If wake-up mode is selected the LM36273 allows on/off control of both VPOS and VNEG with only one external

pin (LCM_EN2). Any combination of VPOS or VNEG can be turned on based on the state of bits VPOS_EN and

VNEG_EN in register 0x09. In these modes the internal shutdown timing of the VPOS and VNEG blocks is

modified to allow for lower quiescent current in standby mode, therefore reducing the average current

consumption during a sequence of on/off events.

There are two wake-up modes available on the LM36273: wake1 and wake2.

7.3.3.3.1 Wake1 Mode

In wake1 mode the LM36273 passes V_INthrough to the LCM boost output and the enabled VPOS, VNEG

outputs. Due to the impedance of the LCM boost, the VPOS LDO and the VNEG charge pump, the respective

outputs are regulated close to V_INonly at very light load current and droop below V_INas the load increases.

7.3.3.3.2 Wake2 Mode

In wake2 mode the LM36273 regulates the LCM boost output as well as the enabled VPOS and VNEG outputs

to their programmed voltage.

7.3.3.4 Active Discharge

An optional active discharge is available for the VPOS and VNEG output rails. An internal switch resistance for

this discharge function is implemented on each output rail. The VPOS active discharge function is enabled with

register 0x09 bit[4] and the VNEG active discharge with register 0x09 bit[3].

7.3.3.5 LCM Bias Protection and Faults

The LCM bias block of the LM36273 provides three protection mechanisms in order to prevent damage to the

device. Note that none of these have any effect on backlight operation.

7.3.3.5.1 LCM Overvoltage (OVP) Protection

The LM36273 provides OVP that monitors the LCM bias boost output voltage (V_{LCM_OUT}) and protects LCM_OUT

and LCM_SW from exceeding safe operating voltages. The OVP threshold is set to 7.8 V (typical). If an LCM

bias overvoltage condition is detected, the LCM_OVP flag, register 0x0F bit[5], is set. Once the OVP condition is

removed, the flag can be cleared with an I²C read back of the register. An LCM OVP condition does not cause

the LCM bias to shut down; it is a report-only flag.

7.3.3.5.2 VPOS Short-Circuit Protection

If the current at VPOS exceeds 180 mA (typical), the LM36273 sets the VPOS_SHORT flag, register 0x0F bit[3].

A readback of register 0x0F is required to clear the flag. The outcome of a VPOS_SHORT detection depends on

the configuration of the bias short-circuit mode option, register 0x0A bits[7:6]. The options are report-only flag,

shutdown VPOS/VNEG, and shutdown VPOS/VNEG and backlight. To prevent narrow spikes from falsely

triggering a VPOS short-circuit condition, the LM36273 provides four programmable VPOS short-circuit filter

options: 100 µs, 500 µs, 1 ms, and 2 ms. These are selected in register 0x0B bits[3:2].

7.3.3.5.3 VNEG Short-Circuit Protection

If the voltage at VNEG rises (towards GND) to above 84% of its programmed value (typical), the LM36273 sets

the VNEG_SHORT flag, register 0x0F bit[2]. A readback of register 0x0F is required to clear the flag. The

outcome of a VNEG_SHORT detection depends on the configuration of the bias short-circuit mode option,

register 0x0A bits[7:6]. The options are report-only flag, shut down VPOS/VNEG, and shut down VPOS/VNEG

and backlight. To prevent narrow spikes from falsely triggering a VNEG short circuit condition, the LM36273

provides four programmable VNEG short circuit filter options: 100 µs, 500 µs, 1 ms, and 2 ms. These are

selected in register 0x0B bits[1:0].

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7.3.4 Software Reset

Bit[7] (SWR_RESET) of the Enable Register (0x08) is a software reset bit. Writing a 1 to this bit resets all I²C

register values to their default values. Once the LM36273 has finished resetting all registers, it auto-clears the

SWR_RESET bit.

7.3.5 HWEN Input

The HWEN pin is a global hardware enable for the LM36273. This pin must be pulled to logic HIGH to enable the

device and the I²C-compatible interface. There is a 300-kΩ internal resistor between HWEN and GND. When this

pin is at logic LOW, the LM36273 is placed in shutdown, the I²C-compatible interface is disabled, and the internal

registers are reset to their default state. TI recommends that V_INhas risen above 2.7 V before setting HWEN

HIGH.

7.3.6 Thermal Shutdown (TSD)

The LM36273 has TSD protection which shuts down the backlight boost, all backlight current sinks, LCM bias

boost, inverting charge pump, and the LDO when the die temperature reaches or exceeds 140°C (typical). The

I²C interface remains active during a TSD event. If a TSD fault occurs the TSD fault is set (register 0x0F bit[6]).

The fault is cleared by an I²C read of register 0x0F or by toggling the HWEN pin.

7.4 Device Functional Modes

7.4.1 Modes of Operation

Shutdown: The LM36273 is in shutdown when the HWEN pin is low.

Standby:

After the HWEN pin is set high the LM36273 goes into standby mode. In standby mode, I²C writes

are allowed but references, bias currents, the oscillator, LCM powers, and backlight are all disabled

to keep the quiescent supply current low (2 µA typical).

Normal mode: Both main blocks of the LM36273 are independently controlled. For enabling each of the blocks

in all available modes, see 表 1 and 表 8.

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7.5 Programming

7.5.1 I²C-Compatible Serial Bus Interface

7.5.1.1 Interface Bus Overview

The I²C-compatible synchronous serial interface provides access to the programmable functions and registers on

the device. This protocol uses a two-wire interface for bidirectional communications between the devices

connected to the bus. The two interface lines are the Serial Data Line (SDA) and the Serial Clock Line (SCL).

These lines must be connected to a positive supply via a pullup resistor and remain HIGH even when the bus is

idle.

Every device on the bus is assigned a unique address and acts as either a Master or a Slave, depending

whether it generates or receives the serial clock (SCL).

7.5.1.2 Data Transactions

One data bit is transferred during each clock pulse. Data is sampled during the high state of the SCL.

Consequently, throughout the clock’s high period, the data remains stable. Any changes on the SDA line during

the high state of the SCL and in the middle of a transaction, aborts the current transaction. New data is sent

during the low SCL state. This protocol permits a single data line to transfer both command/control information

and data using the synchronous serial clock.

SCL

SDA

data

change

allowed

data

change

allowed

data

change

allowed

data

valid

data

valid

图 42. Data Validity

Each data transaction is composed of a start condition, a number of byte transfers (set by the software), and a

stop condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is

transferred with the most significant bit first. After each byte, an acknowledge signal must follow. The following

sections provide further details of this process.

Transmitter Stays off the

Bus During the Acknowledge Clock

Acknowledge Signal from Receiver

3...6

7

9

1

8

2

S

Start

Condition

图 43. Acknowledge Signal

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Programming (接下页)

The Master device on the bus always generates the start and stop conditions (control codes). After a Start

Condition is generated, the bus is considered busy, and it retains this status until a certain time after a stop

condition is generated. A high-to-low transition of the data line (SDA) while the clock (SCL) is high indicates a

start condition. A low-to-high transition of the SDA line while the SCL is high indicates a stop condition.

SDA

SCL

S

P

START condition

STOP condition

图 44. Start and Stop Conditions

In addition to the first start condition, a repeated start condition can be generated in the middle of a transaction.

This allows another device to be accessed, or a register read cycle.

7.5.1.3 Acknowledge Cycle

The acknowledge cycle consists of two signals: the acknowledge clock pulse the master sends with each byte

transferred, and the acknowledge signal sent by the receiving device.

The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter

releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver

must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the

high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to

receive the next byte.

7.5.1.4 Acknowledge After Every Byte Rule

The master generates an acknowledge clock pulse after each byte transfer. The receiver sends an acknowledge

signal after every byte received.

There is one exception to the acknowledge after every byte rule. When the master is the receiver, it must

indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out

of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master),

but the SDA line is not pulled down.

7.5.1.5 Addressing Transfer Formats

Each device on the bus has a unique slave address. The LM36273 operates as a slave device with the 7-bit

address. If an 8-bit address is used for programming, the 8th bit is 1 for read and 0 for write. The 7-bit address

for the device is 0x11.

Before any data is transmitted, the master transmits the address of the slave being addressed. The slave device

sends an acknowledge signal on the SDA line, once it recognizes its address. The slave address is the first

seven bits after a Start Condition. The direction of the data transfer (R/W) depends on the bit sent after the slave

address — the eighth bit.

When the slave address is sent, each device in the system compares this slave address with its own. If there is a

match, the device considers itself addressed and sends an acknowledge signal. Depending upon the state of the

R/W bit (1: read, 0: write), the device acts as a transmitter or a receiver.

MSB

LSB

ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0

R/W

bit0

Bit7

bit6

bit5

bit4

bit3

bit2

bit1

I²C SLAVE address (chip address)

图 45. I²C Device Address

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Programming (接下页)

Control Register Write Cycle

•

Master device generates start condition.

Master device sends slave address (7 bits) and the data direction bit (r/w = 0).

Slave device sends acknowledge signal if the slave address is correct.

Master sends control register address (8 bits).

Slave sends acknowledge signal.

Master sends data byte to be written to the addressed register.

Slave sends acknowledge signal.

If master sends further data bytes the control register address is incremented by one after acknowledge

signal.

•

Write cycle ends when the master creates stop condition.

Control Register Read Cycle

•

Master device generates a start condition.

Master device sends slave address (7 bits) and the data direction bit (r/w = 0).

Slave device sends acknowledge signal if the slave address is correct.

Master sends control register address (8 bits).

Slave sends acknowledge signal

Master device generates repeated start condition.

Master sends the slave address (7 bits) and the data direction bit (r/w = 1).

Slave sends acknowledge signal if the slave address is correct.

Slave sends data byte from addressed register.

If the master device sends acknowledge signal, the control register address is incremented by one. Slave

device sends data byte from addressed register.

•

Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop

condition.

表 9. I²C Data Read/Write⁽¹⁾

ADDRESS MODE

<Slave Address><r/w =0>[Ack]

<Register Addr>[Ack]

<Slave Address><r/w = 1>[Ack]

Data Read

[Register Data]<Ack or NAck>

...additional reads from subsequent register address possible

<Slave Address><r/w = 0>[Ack]

<Register Addr>[Ack]

<Register Data>[Ack]

Data Write

...additional writes to subsequent register address possible

(1) < > = Data from master, [ ] = Data from slave

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ack from slave

start msb Chip Address lsb

w

ack

msb Register Addr lsb

ack

msb

Data

lsb

ack stop

SCL

SDA

start

id = 001 0001b

w

ack

address = 02h

ack

address 02h data

ack stop

图 46. Register Write Format

When a READ function is to be accomplished, a WRITE function must precede the READ function, as show in

the Read Cycle waveform.

ack from slave

ack from slave repeated start

ack from slavedata from slave nack from master

start msb Chip Address lsb

w

msb Register Add lsb

rs

msb Chip Address lsb

r

msb Data lsb

stop

SCL

SDA

start

id = 001 0001b

w

ack

address = 00h

ack rs

id = 001 0001b

r ack address 00h data nack stop

图 47. Register Read Format

注

w = write (SDA = 0), r = read (SDA = 1), ack = acknowledge (SDA pulled down by either

master or slave), rs = repeated start id = 7-bit chip address

7.5.1.6 Register Programming

For glitch-free operation, the following bits and/or registers must only be programmed while the LED Enable bits

are 0 (Register 0x08, Bit [2:0] = 0) and/or Backlight Enable bit is 0 (Register 0x08, Bit[4] = 0):

1. Register 0x02 Bit[0] (PWM Enable)

2. Register 0x02 Bits[1] (PWM Ramp)

3. Register 0x02 Bit[2] (PWM Config)

4. Register 0x02 Bits[3] (LED Current Mapping)

5. Register 0x03 Bit[1:0] (PWM Hysteresis)

6. Register 0x03 Bit[2] (PWM Sample)

7. Register 0x03 Bit[6:3] (LED Current Ramp)

8. Register 0x10 Bit[0] (PWM HF Sample)

9. Register 0x10 Bit[1] (PWM Glitch Filter)

10. Register 0x10 Bit [5:3] (LED Feedback Enable)

11. Register 0x06 (auto frequency high threshold)

12. Register 0x07 (auto frequency low threshold)

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7.6 Register Maps

表 10. Register Default Values

I²C ADDRESS

REGISTER NAME

READ/WRITE

R

POWER ON/RESET VALUE

SECTION

Go

0x01

Revision Register

0x01

0x28

0x8D

0x07

0xFF

0x00

0x18

0x11

0x00

0x28

0x1E

0x1C

0x00

0x06

0x35

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

Backlight Configuration1 Register

Backlight Configuration 2 Register

Backlight Brightness LSB Register

Backlight Brightness MSB Register

Backlight Auto-Frequency Low Register

Backlight Auto-Frequency High Register

Backlight Enable Register

R/W

R

Go

Display Bias Configuration 1 Register

Display Bias Configuration 2 Register

Display Bias Configuration 3 Register

LCM Boost Bias Register

Go

VPOS Bias Register

Go

VNEG Bias Register

Go

Flags Register

Go

Backlight Option 1 Register

R/W

Go

Backlight Option 2 Register

Go

PWM-to-Digital Code Readback LSB

Register

0x12

0x13

R

0x00

Go

PWM-to-Digital Code Readback MSB

Register

7.6.1 Revision Register (Address = 0x01)[Reset = 0x01]

图 48. Revision Register

7

6

5

4

3

2

1

0

DEV_REV[6]

R-0

DEV_REV[5]

R-0

DEV_REV[4]

R-0

DEV_REV[3]

R-0

DEV_REV[1]

R-0

DEV_REV[0]

R-0

DEV_REV[1]

R-0

DEV_REV[0]

R-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 11. Revision Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

DEVICE REVISION

R

000000 or DEV_REVISION,

000001

01

A0 = 000000

A1 = 000001

1-0

VENDOR

R

VENDOR, Texas Instruments = 01

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7.6.2 Backlight Configuration1 Register (Address = 0x02)[Reset = 0x28]

图 49. Backlight Configuration 1 Register

7

6

5

4

3

2

1

0

BL_OVP[2]

R/W-0

BL_OVP[1]

R/W-0

BL_OVP[0]

R/W-1

OVP_MODE

R/W-0

BLED_MAP

R/W-1

PWM_CONFIG

R/W-0

PWM_RAMP

R/W-0

PWM_ENABLE

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 12. Backlight Configuration 1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

BL_OVP

R/W

001

Backlight OVP

000: 17 V

001: 21 V

010: 25 V

011: 29 V

100 to 111 = 29 V

4

3

2

1

0

OVP_MODE

BLED_MAP

R/W

0

1

0

0: OVP is report only

1: OVP causes shutdown

0: Exponential

1: Linear

PWM_CONFIG

PWM_RAMP

PWM_ENABLE

0: Active high

1: Active low

0: No PWM ramp

1: LED current ramps with changes in duty cycle

0: PWM disabled

1: PWM enabled

7.6.3 Backlight Configuration 2 Register (Address = 0x03)[Reset = 0x8D]

图 50. Backlight Configuration 2 Register

7

6

5

4

3

2

1

0

BL BOOST

FREQUENCY

LED CURRENT

RAMP[3]

LED CURRENT

RAMP[2]

LED CURRENT

RAMP[1]

LED CURRENT

RAMP[0]

PWM SAMPLE⁽¹⁾

PWM HYST[1]

PWM HYST[0]

R/W-1

R/W-0

R/W-1

R/W-0

R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

(1) (Note: register 0x10 bit[0] = 1 enables 24-MHz sample mode.)

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表 13. Backlight Configuration 2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

BL BOOST FREQUENCY

1

Sets the backlight boost switch frequency

0: 500 kHz

1: 1 MHz (Default)

6-3

LED CURRENT RAMP

R/W

0001

Controls backlight LED ramping time. The transient time is a

constant time that the backlight takes to transition from an

existing programmed code to a new programmed code.

0000: 0 µs

0001: 500 µs

0010: 750 µs

0011: 1 ms

0100: 2 ms

0101: 5 ms

0110: 10 ms

0111: 20 ms

1000: 50 ms

1001: 100 ms

1010: 250 ms

1011: 800 ms

1100: 1 s

1101: 2 s

1110: 4 s

1111: 8 s

2

PWM SAMPLE

PWM HYST

R/W

1

Sets PWM sampling frequency

0: 1 MHz

1: 4 MHz (Default0 Note: register 0x10 bit[0] = 1 enables 24-

MHz sample mode

1-0

01

Sets the minimum change in PWM input duty cycle that results

in a change of backlight LED brightness level

PWM Sample Frequency = 1 MHz or 4 MHz:

00: 1 bit

01: 2 bits

10: 4 bits

11: 6 bits

PWM Sample Frequency = 24 MHz:

00: 0

01: 1 bit

10: 2 bits

11: 3 bits

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7.6.4 Backlight Brightness LSB Register (Address = 0x04)[Reset = 0x07]

图 51. Backlight Brightness LSB Register

7

6

5

4

3

2

1

0

NOT USED

BRT[2]

R/W-1

BRT[1]

R/W-1

BRT[0]

R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 14. Backlight Brightness LSB Register Field Descriptions

Bit

7-3

2-0

Field

Type

Reset

Description

NOT USED

BRT

R/W

111

11-bit brightness code LSBs

7.6.5 Backlight Brightness MSB Register (Address = 0x05)[Reset = 0xFF]

图 52. Backlight Brightness MSB Register

7

6

5

4

3

2

1

0

BRT[10]

R/W-1

BRT[9]

R/W-1

BRT[8]

R/W-1

BRT[7]

R/W-1

BRT[6]

R/W-1

BRT[5]

R/W-1

BRT[4]

R/W-1

BRT[3]

R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 15. Backlight Brightness MSB Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

BRT

R/W

11111111 11-bit brightness code MSBs

7.6.6 Backlight Auto-Frequency Low Threshold Register (Address = 0x06)[Reset = 0x00]

图 53. Backlight Auto-Frequency Low Threshold Register

7

6

5

4

3

2

1

0

AFLT[7]

R/W-0

AFLT[6]

R/W-0

AFLT[5]

R/W-0

AFLT[4]

R/W-0

AFLT[3]

R/W-0

AFLT[2]

R/W-0

AFLT[1]

R/W-0

AFLT[0]

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 16. Backlight Auto-Frequency Low Threshold Field Descriptions

Bit

Field

Type

Reset

Description

7-0

AFLT

R/W

00000000 Compared against 8 MSB’s of Brightness Code (register 0x05)

7.6.7 Backlight Auto-Frequency High Threshold Register (Address = 0x07)[Reset = 0x00]

图 54. Backlight Auto-Frequency High Threshold Register

7

6

5

4

3

2

1

0

AFHT[7]

R/W-0

AFHT[6]

R/W-0

AFHT[5]

R/W-0

AFHT[4]

R/W-0

AFHT[3]

R/W-0

AFHT[2]

R/W-0

AFHT[1]

R/W-0

AFHT[0]

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 17. Backlight Auto-Frequency High Threshold Field Descriptions

Bit

Field

Type

Reset

Description

7-0

AFHT

R/W

00000000 Compared against 8 MSB’s of Brightness Code (register 0x05)

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7.6.8 Backlight Enable Register (Address = 0x08)[Reset = 0x00]

图 55. Backlight Enable Register

7

6

5

4

3

2

1

0

SOFTWARE_

RESET

NOT USED

BL_EN

Reserved

LED3_EN

LED2_EN

LED1_EN

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 18. Backlight Enable Register Field Descriptions

Bit

Field

Type

Reset

Description

7

SOFTWARE_RESET

R/W

0

0 = No reset

1 = Device reset (automatically returns to 0 after reset)

6-5

4

NOT USED

BL_EN

R/W

0

0 = BL disabled

1 = BL enabled

3

2

Reserved

LED3_EN

R/W

0

Must be written to 0

0 = Current sink 3 disabled

1 = Current sink 3 enabled

1

0

LED2_EN

LED1_EN

R/W

0

0 = Current sink 2 disabled

1 = Current sink 2 enabled

0 = Current sink 1 disabled

1 = Current sink 1 enabled

7.6.9 Bias Configuration 1 Register (Address = 0x09)[Reset = 0x18]

图 56. Bias Configuration 1 Register

7

6

5

4

3

2

1

0

LCM_EN[2]

R/W-0

LCM_EN[1]

R/W-0

LCM_EN[0]

R/W-0

VPOS_DISCH

R/W-1

VNEG_DISCH

R/W-1

VPOS_EN

R/W-0

VNEG_EN

R/W-0

EXT_EN

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 19. Bias Configuration 1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7:5

LCM_EN

R/W

000

000 = Bias supply off (I²C and external)

100 = Normal mode

101 = Auto sequence

110 = Wake1

111 = Wake2

4

3

2

1

0

VPOS_DISCH

VNEG_DISCH

VPOS_EN

R/W

1

0

0 = No pulldown on VPOS

1 = Pulldown on VPOS when in shutdown

0 = No pulldown on VNEG

1 = Pulldown on VNEG when in shutdown

0 = VPOS disabled

1 = VPOS enabled

VNEG_EN

0 = VNEG disabled

1 = VNEG enabled

EXT_EN

Activates external enables (LCM_EN1 and LCM_EN2)

0 = External enables are disabled. VPOS and VNEG can only

be enabled via bit VPOS_EN and VNEG_EN, respectively.

(Default)

1 = External enables are enabled. VPOS and VNEG can only be

enabled via pin LCM_EN1 and LCM_EN2, respectively.

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7.6.10 Bias Configuration 2 register (Address = 0x0A)[Reset = 0x11]

图 57. Bias Configuration 2 Register

7

6

5

4

3

2

1

0

BIAS_SHORT

_MODE[1]

BIAS_SHORT

_MODE[0]

VPOS

_RAMP[1]

VPOS

_RAMP[0]

VNEG

_RAMP[3]

VNEG

_RAMP[2]

VNEG

_RAMP[1]

VNEG

_RAMP[0]

R/W-0

R/W-1

R/W-0

R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 20. Bias Configuration 2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7:6

BIAS_SHORT_MODE

R/W

00

0X = Flag only

10 = Flag + shutdown VPOS/VNEG

11 = Flag + shutdown VPOS/VNEG/Backlight

5:4

3:0

VPOS_RAMP

VNEG_RAMP

R/W

01

VPOS ramp time, low to high:

00 = 256 µs

01 = 512 µs

10 = 768 µs

11 = 1024 µs

0001

VNEG ramp time, high to low:

0000 = 512 µs

0001 = 1024 µs

0010 = 1536 µs

0011 = 2048 µs

0100 = 2560 µs

0101 = 3072 µs

0110 = 3584 µs

0111 = 4096 µs

1000 = 4608 µs

1001 = 5120 µs

1010 = 5632 µs

1011 = 6144 µs

1100 = 6656 µs

1101 = 7168 µs

1110 = 7680 µs

111 = 8192 µs

7.6.11 Bias Configuration 3 Register (Address = 0x0B)[Reset = 0x00]

图 58. Bias Configuration 3 Register

7

6

5

4

3

2

1

0

NOT USED

VPOS_SC

_FILT[1]

VPOS_SC

_FILT[0]

VNEG_SC

_FILT[1]

VNEG_SC

_FILT[0]

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 21. Bias Configuration 3 Register Field Descriptions

Bit

7:4

5:4

Field

Type

Reset

Description

NOT USED

VPOS_SC_FILT

R/W

00

VPOS short circuit filter timer

00 = 2 ms

01 = 1 ms

10 = 500 µs

11 = 100 µs

1:0

VNEG_SC_FILT

R/W

00

VNEG short circuit filter timer

00 = 2 ms

01 = 1 ms

10 = 500 µs

11 = 100 µs

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7.6.12 LCM Boost Bias Register (Address = 0x0C)[Reset = 0x28]

图 59. LCM Boost Bias Register

7

6

5

4

3

2

1

0

NOT USED

LCM_OUT[5]

R/W-1

LCM_OUT[4]

R/W-0

LCM_OUT[3]

R/W-1

LCM_OUT[2]

R/W-0

LCM_OUT[1]

R/W-0

LCM_OUT[0]

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 22. LCM Boost Bias Register Field Descriptions

Bit

7-6

5-0

Field

Type

Reset

Description

NOT USED

LCM_OUT

R/W

101000

LCM_OUT voltage (50-mV steps): LCM_OUT = 4 V + (Code ×

50 mV)

000000 = 4 V

000001 = 4.55V

:

101000 = 6 V (Default)

:

111111 = 7.15 V

7.6.13 VPOS Bias Register (Address = 0x0D)[Reset = 0x1E]

图 60. VPOS Bias Register

7

6

5

4

3

2

1

0

NOT USED

VPOS[5]

R/W-0

VPOS[4]

R/W-0

VPOS[3]

R/W-1

VPOS[2]

R/W-1

VPOS[1]

R/W-1

VPOS[0]

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 23. VPOS Bias Register Field Descriptions

Bit

7-6

5-0

Field

Type

Reset

Description

NOT USED

VPOS

R/W

011110

VPOS voltage (50-mV steps): VPOS = 4 V + (Code × 50 mV),

6.5 V max

000000 = 4 V

000001 = 4.05 V

:

011110 = 5.5 V (Default)

:

110010 = 6.5 V

110011 to 111111 map to 6.5 V

7.6.14 VNEG Bias Register (Address = 0x0E)[Reset = 0x1C]

图 61. VNEG Bias Register

7

6

5

4

3

2

1

0

NOT USED

VNEG[5]

R/W-0

VNEG[4]

R/W-1

VNEG[3]

R/W-1

VNEG[2]

R/W-1

VNEG[1]

R/W-0

VNEG[0]

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

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表 24. VNEG Bias Register Field Descriptions

Bit

7-6

5-0

Field

Type

Reset

Description

NOT USED

VNEG

R/W

011100

VNEG voltage (–50-mV steps): VNEG = -4 V - (Code × 50 mV),

-6.5 V min

000000 = –4 V

000000 = –4.05 V

:

011100 = -5.4 V (Default)

:

110010 = –6.5 V

110011 to 111111 map to –6.5 V

7.6.15 Flags Register (Address = 0x0F)[Reset = 0x00]

图 62. Flags Register

7

6

5

4

3

2

VNEG_SHORT

R-0

1

0

NOT USED

TSD

R-0

LCM_OVP

R-0

NOT USED

VPOS_SHORT

R-0

BL_OVP

R-0

BL_OCP

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 25. Flags Register Field Descriptions

Bit

Field

Type

Reset

Description

7

NOT USED

R

0

0 = Normal operation

1 = Thermal shutdown triggered (die temperature > 140°C)

6

TSD

0 = Normal operation

1 = V_{LCM_OUT}> 7.8 V

5

4

3

LCM_OVP

NOT USED

VPOS_SHORT

R

0

0 = Normal operation

1 = VPOS output has hit the overcurrent threshold

0 = Normal operation

1 = V_VNEG> 0.84 × V_{VNEG_target}

2

1

0

VNEG_SHORT

BL_OVP

0 = Normal operation

1 = Backlight boost output > OVP threshold

0 = Normal operation

1 = Backlight boost switch current > OCP threshold

BL_OCP

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7.6.16 Option 1 Register (Address = 0x10)[Reset = 0x06]

图 63. Option 1 Register

7

6

5

4

3

2

1

0

NOT USED

Reserved

LED3_FB

LED2_FB

LED1_FB

PWM_FILT[1]

PWM_ FILT[0]

PWM_24MHZ_

SAMPLE

RW-0

RW-1

RW-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 26. Option 1 Register Field Descriptions

Bit

7

Field

Type

Reset

Description

NOT USED

6

Reserved

R/W

0

Must be written to 0

5

LED3_FEEDBACK_DISABLE

0 = Feedback enabled

1 = Feedback disabled

4

3

LED2_FEEDBACK_DISABLE

LED1_FEEDBACK_DISABLE

PWM_FILT

R/W

0

0 = Feedback enabled

1 = Feedback disabled

0

0 = Feedback enabled

1 = Feedback disabled

2:1

11

PWM Glitch Filter

00 = No filter

01 = 100 ns

10 = 150 ns

11 = 200 ns

0

PWM_24MHz_SAMPLE

R/W

0

0 = Low-frequency options (see 0x03 bit[2])

1 = 24-MHz PWM sample frequency

7.6.17 Option 2 Register (Address = 0x11)[Reset = 0x35]

图 64. Option 2 Register

7

6

5

4

3

2

1

0

BL_L

SELECT[1]

BL_L

SELECT[0]

BL_SEL_P[1]

BL_SEL_P[0]

BL_SEL_I[1]

BL_SEL_I[0]

BL_CURRENT

_LIMIT[1]

BL_CURRENT

_LIMIT[0]

RW-0

RW-1

RW-0

RW-1

RW-0

RW-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 27. Option 2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

BACKLIGHT_BOOST_L_SELECT

RW

00

00 = 4.7 µH

01 = 10 µH

10 = 15 µH

11 = 15 µH

5-4

3-2

1-0

BACKLIGHT_SEL_P

BACKLIGHT_SEL_I

RW

11

01

These bits must be written to 11 (default values) to ensure

backlight boost stability with recommended external components

for all LED configurations

These bits must be written to 01 (default values) to ensure

backlight boost stability with recommended external components

for all LED configurations

BACKLIGHT_BOOST_CURRENT_ RW

LIMIT

00 = 0.9 A

01 = 1.2 A

10 = 1.5 A

11 = 1.8 A

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7.6.18 PWM-to-Digital Code Readback LSB Register (Address = 0x12)[Reset = 0x00]

图 65. PWM-to-Digital Code Readback LSB Register

7

6

5

4

3

2

1

0

PWM_TO

_DIG[7]

PWM_TO

_DIG[6]

PWM_TO

_DIG[5]

PWM_TO

_DIG[4]

PWM_TO

_DIG[3]

PWM_TO

_DIG[2]

PWM_TO

_DIG[1]

PWM_TO

_DIG[0]

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 28. PWM-to-Digital Code Readback LSB Register Field Descriptions

Bit

Field

Type

Reset

Description

7-0

PWM_TO_DIG

R

00000000 11-bit PWM-to-digital conversion code LSBs

7.6.19 PWM-to-Digital Code Readback MSB Register (Address = 0x13)[Reset = 0x00]

图 66. PWM-to-Digital Code Readback MSB Register

7

6

5

4

3

2

1

0

RESERVED

PWM_TO

_DIG[10]

PWM_TO

_DIG[9]

PWM_TO

_DIG[8]

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

表 29. PWM-to-Digital Code Readback MSB Register Field Descriptions

Bit

7-3

2-0

Field

Type

R

Reset

00000

000

Description

RESERVED

PWM_TO_DIG

Reserved

R

11-bit PWM-to-digital conversion code MSBs

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8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LM36273 integrates an LCD backlight driver and LCM positive and negative bias voltages into a single

device. The backlight boost converter generates the high voltage required for the LEDs. The device can drive

one, two, or three LED strings with up to eight white LEDs per string. Positive and negative bias voltages are

post-regulated from the LCM bias boost output voltage. The LM36273 offers high performance, is highly

configurable, and can support multiple LED configurations as well as independent control of the bias outputs.

8.2 Typical Application

D1

L1

10 µH

C2

1 µF

L2

2.2 µH

2.7 V to 5 V

IN

BL_OUT

LED1

V_BATT

C1

20 µF

LED2

SCL

LED3

SDA

C+

C-

LM36273

PWM

C_FLY

10 µF

µC/µP

HWEN

+5.8 V

LCM_OUT

VPOS

LCM_EN1

LCM_EN2

C4

10 µF

+5.5 V

C5

10 µF

-5.5 V

VNEG

C6

10 µF

图 67. LM36273 Typical Application

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LM36273

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Typical Application (接下页)

8.2.1 Design Requirements

DESIGN PARAMETER

EXAMPLE VALUE

Input voltage range (V_IN

)

2.7 V to 4.5 V (single Li-Ion cell battery)

LED parallel/series configuration

LED maximum forward voltage (V_f)

Backlight LED current

3 parallel, 6 series

3.35 V

maximum 30 mA / string

Backlight boost maximum voltage

Backlight boost SW frequency

Backlight boost inductor

29 V

1 MHZ, 500 kHz, 250 kHz (auto-frequency option)

10-μH, 1.5-A saturation current

Backlight boost Schottky diode

LCM boost output voltage

VPOS output voltage

NSR05F30NXT5G

5.8 V

5.5 V

–5.5 V

VNEG output voltage

LCM boost inductor

2.2-µH, 1.5-A saturation current

The number of LED strings, number of series LEDs, and minimum input voltage are needed in order to calculate

the peak input current. This information guides the designer to make the appropriate backlight boost inductor

selection for the application. The LM36273 backlight boost converter output voltage (V_OUT) is calculated as

follows: number of series LEDs × V_ƒ+ 0.31 V. The LM36273 boost converter output current (I_OUT) is calculated

as follows: number of parallel LED strings × 30 mA. The LM36273 peak input current is calculated using 公式 5.

8.2.2 Detailed Design Procedure

8.2.2.1 Component Selection

表 30 shows examples of external components for the LM36273. Boost converter output capacitors can be

replaced with dual output capacitors of lower capacitance as long as the minimum effective capacitance

requirement is met. DC bias effect of the ceramic capacitors must be taken into consideration when choosing the

output capacitors. This is especially true for the high output-voltage backlight-boost converter.

表 30. Recommended External Components

DESIGNATOR

DESCRIPTION

Ceramic capacitor

Inductor

VALUE

EXAMPLE

C1, C4, C5, C6, C_FLY

10 µF, 10 V

1 µF, 35 V

C1608X5R0J106M

C2

L1

L2

D1

C2012X7R1H105K125AB

VLF504012MT-4R7M

VLF504015MT-100M

VLF504015MT-150M

DFE201612P-2R2M

NSR053F30NXT5G

4.7 µH, 1.94 A

10 µH, 1.44 A

15 µH, 1.25 A

2.2 µH, 1.5 A

30 V, 500 mA

Inductor

Schottky diode

8.2.2.1.1 Inductor Selection

The LM36273 backlight boost requires a typical inductance in the range of 4.7 µH to 15 µH. To ensure boost

stability the Backlight Boost L Select bit (register 0x11 bits [7:6]) must be selected depending on the value of

inductance chosen. Use the 4.7-µH setting with a 6.8-µH inductor.

The LCM boost is internally compensated for a typical inductance in the range of 1 µH to 2.2 µH. If the LCM

boost output setting is greater than 6.3 V a 2.2-µH inductor must be used.

There are two main considerations when choosing an inductor: the inductor RMS current rating must be greater

than the RMS inductor current for the application, and the inductor saturation current must be greater than the

peak inductor current for the application. Different saturation current rating specifications are followed by different

manufacturers so attention must be given to details. Saturation current ratings are typically specified at 25°C.

However, ratings at the maximum ambient temperature of the application should be requested from the

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manufacturer. The saturation current must be greater than the sum of the maximum load current and the worst-

case average-to-peak inductor current. When the boost device is boosting (V_OUT> V_IN) the inductor is one of the

largest area of efficiency loss in the circuit. Therefore, choosing an inductor with the lowest possible series

resistance is important, especially for an LCM bias converter. For proper inductor operation and circuit

performance, ensure that the inductor saturation and the peak current limit setting of the LM36273 are greater

than I_PEAKin 公式 5:

ILOAD

VOUT

VIN ì(VOUT - VIN ì h)

2 ì fSW ì L ì VOUT

IPEAK =

ì

+ DILOAD where DILOAD =

h

VIN

(5)

See detailed information in Understanding Boost Power Stages in Switch Mode Power Supplies

http://focus.ti.com/lit/an/slva061/slva061.pdf. Power Stage Designer™ Tools can be used for the boost

calculation: http://www.ti.com/tool/powerstage-designer.

Also, the peak current calculated in 公式 5 is different from the peak inductor current setting (I_SAT). The NMOS

switch current limit setting (I_{CL_MIN}) must be greater than I_PEAKfrom 公式 5.

8.2.2.1.2 Boost Output Capacitor Selection

At least an 1-μF capacitor is recommended for the backlight boost converter output capacitor. A high-quality

ceramic type X5R or X7R is recommended. Voltage rating must be greater than the maximum output voltage that

is used. The effective output capacitance must always remain higher than 0.4 μF for stable operation.

表 31 lists possible backlight output capacitors that can be used with the LM36273. 图 68 shows the DC bias of

the four TDK capacitors. The useful voltage range is determined from the effective output voltage range for a

given capacitor as determined by 公式 6:

0.4 mF

(1- Tol) ì(1 - Temp_co)

DC Voltage Derating í

(6)

表 31. Recommended Backlight Output Capacitors

RECOMMENDED MAX

CASE

SIZE

VOLTAGE

RATING (V)

NOMINAL

CAPACITANCE (µF)

TEMPERATURE

COEFFICIENT (%)

OUTPUT VOLTAGE

(FOR SINGLE

PART NUMBER

MANUFACTURER

TOLERANCE (%)

CAPACITOR)

C2012X5R1H105K085AB

C2012X5R1H225K085AB

C1608X5R1V225K080AC

C1608X5R1H105K080AB

TDK

0805

0603

50

35

50

1

±10

±15

22

24

12

15

2.2

1

For example, with a 10% tolerance, and a 15% temperature coefficient, the DC voltage derating must be ≥ 0.4 /

(0.9 × 0.85) = 0.523 µF. For the C1608X5R1H225K080AB (0603, 50-V) device, the useful voltage range occurs

up to the point where the DC bias derating falls below 0.523 µF, or around 12 V. For configurations where V_OUT

is > 15 V, two of these capacitors can be paralleled, or a larger capacitor such as the C2012X5R1H105K085AB

must be used.

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LM36273

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2

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1

C2012X5R1H105K085AB

C2012X5R1H225K085AB

C1608X5R1V225K080AC

C1608X5R1H105K080AB

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28

C006

DC Bias

图 68. DC Bias Derating for 0805 Case Size and

0603 Case Size 35-V and 50-V Ceramic Capacitors

For the LCM bias boost output a high-quality 10-μF ceramic type X5R or X7R capacitor is recommended.

Voltage rating must be greater than the maximum output voltage that is used.

8.2.2.1.3 Input Capacitor Selection

Choosing the correct size and type of input capacitor helps minimize the voltage ripple caused by the switching

of the LM36273 boost converters and reduce noise on the input pin that can feed through and disrupt internal

analog signals. For the LM36273 a 10-μF ceramic input capacitor works well. It is important to place the input

capacitor as close to the input (IN) pin as possible. This reduces the series resistance and inductance that can

inject noise into the device due to the input switching currents.

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8.2.3 Application Curves

8.2.3.1 Backlight Curves

Ambient temperature is 25°C and V_INis 3.7 V unless otherwise noted. Backlight system efficiency is defined as

PLED / PIN, where PLED is actual power consumed in backlight LEDs. External components are from 表 30.

8.2.3.1.1 Two LED Strings

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

T_A= -40èC

T_A= 25èC

T_A= 85èC

T_A= -40èC

T_A= 25èC

T_A= 85èC

0

5

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

0

5

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

D201

D202

2p8s

ƒ = 1 MHz

L = 10 µH

2p8s

ƒ = 1 MHz

L = 10 µH

图 69. Backlight Boost Efficiency

图 70. Backlight System Efficiency

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

T_A= -40èC

T_A= 25èC

T_A= 85èC

T_A= -40èC

T_A= 25èC

T_A= 85èC

0

5

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

0

5

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

D203

D204

2p8s

ƒ = 500 kHz

L = 10 µH

2p8s

ƒ = 500 kHz

L = 10 µH

图 71. Backlight Boost Efficiency

图 72. Backlight System Efficiency

95

90

85

80

75

70

65

60

55

50

90

85

80

75

70

65

60

55

50

T_A= -40èC

T_A= 25èC

T_A= 85èC

T_A= -40èC

T_A= 25èC

T_A= 85èC

0

2

4

6

8

10

12

14

16

18

20

0

2

4

6

8

10

12

14

16

18

20

Load (mA)

D206

D205

2p8s

ƒ = 250 kHz

L = 10 µH

2p8s

ƒ = 250 kHz

L = 10 µH

图 74. Backlight System Efficiency

图 73. Backlight Boost Efficiency

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LM36273

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95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

0

5

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

0

5

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

D207

D208

2p8s

ƒ = 1 MHz

L = 10 µH

2p8s

ƒ = 1 MHz

L = 10 µH

图 75. Backlight Boost Efficiency

图 76. Backlight System Efficiency

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

D209

D210

2p8s

ƒ = 500 kHz

L = 10 µH

2p8s

ƒ = 500 kHz

L = 10 µH

图 77. Backlight Boost Efficiency

图 78. Backlight System Efficiency

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

T_A= -40èC

T_A= 25èC

T_A= 85èC

T_A= -40èC

T_A= 25èC

T_A= 85èC

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

D211

D212

2p7s

ƒ = 1 MHz

L = 10 µH

2p7s

ƒ = 1 MHz

L = 10 µH

图 79. Backlight Boost Efficiency

图 80. Backlight System Efficiency

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95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

T_A= -40èC

T_A= 25èC

T_A= 85èC

T_A= -40èC

T_A= 25èC

T_A= 85èC

50

0

5

10 15 20 25 30 35 40 45 50 55 60

5

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

D214

D213

2p7s

ƒ = 500 kHz

L = 10 µH

2p7s

ƒ = 500 kHz

L = 10 µH

图 82. Backlight System Efficiency

图 81. Backlight Boost Efficiency

95

90

85

80

75

70

65

60

55

95

90

85

80

75

70

65

60

55

50

T_A= -40èC

T_A= 25èC

T_A= 85èC

T_A= -40èC

T_A= 25èC

T_A= 85èC

50

0

2

4

6

8

10

12

14

16

18

20

2

4

6

8

10

12

14

16

18

20

Load (mA)

D215

D216

2p7s

ƒ = 250 kHz

L = 10 µH

2p7s

ƒ = 250 kHz

L = 10 µH

图 83. Backlight Boost Efficiency

图 84. Backlight System Efficiency

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

0

5

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

5

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

D217

D218

2p7s

ƒ = 1 MHz

L = 10 µH

2p7s

ƒ = 1 MHz

L = 10 µH

图 85. Backlight Boost Efficiency

图 86. Backlight System Efficiency

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95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

0

5

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

0

5

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

D219

D220

2p7s

ƒ = 500 kHz

L = 10 µH

2p7s

ƒ = 500 kHz

L = 10 µH

图 87. Backlight Boost Efficiency

图 88. Backlight System Efficiency

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

T_A= -40èC

T_A= 25èC

T_A= 85èC

T_A= -40èC

T_A= 25èC

T_A= 85èC

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

D221

D222

2p6s

ƒ = 1 MHz

L = 10 µH

2p6s

ƒ = 1 MHz

L = 10 µH

图 89. Backlight Boost Efficiency

图 90. Backlight System Efficiency

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

T_A= -40èC

T_A= 25èC

T_A= 85èC

T_A= -40èC

T_A= 25èC

T_A= 85èC

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

D224

D223

2p6s

ƒ = 500 kHz

L = 10 µH

2p6s

ƒ = 500 kHz

L = 10 µH

图 92. Backlight System Efficiency

图 91. Backlight Boost Efficiency

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ZHCSGN8D –FEBRUARY 2016–REVISED MARCH 2018

95

90

85

80

75

70

65

60

55

95

90

85

80

75

70

65

60

55

50

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

50

0

2

4

6

8

10

12

14

16

18

20

0

2

4

6

8

10

12

14

16

18

20

Load (mA)

D225

D226

2p6s

ƒ = 250 kHz

L = 10 µH

2p6s

ƒ = 250 kHz

L = 10 µH

图 93. Backlight Boost Efficiency

图 94. Backlight System Efficiency

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

0

5

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

5

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

D227

D228

2p6s

ƒ = 1 MHz

L = 10 µH

2p6s

ƒ = 1 MHz

L = 10 µH

图 95. Backlight Boost Efficiency

图 96. Backlight System Efficiency

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

0

5

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

5

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

D229

D230

2p6s

ƒ = 500 kHz

L = 10 µH

2p6s

ƒ = 500 kHz

L = 10 µH

图 97. Backlight Boost Efficiency

图 98. Backlight System Efficiency

55

LM36273

ZHCSGN8D –FEBRUARY 2016–REVISED MARCH 2018

www.ti.com.cn

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

T_A= -40èC

T_A= 25èC

T_A= 85èC

T_A= -40èC

T_A= 25èC

T_A= 85èC

0

5

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

0

5

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

D231

D232

2p8s

ƒ = 1 MHz

L = 4.7 µH

2p8s

ƒ = 1 MHz

L = 4.7 µH

图 99. Backlight Boost Efficiency

图 100. Backlight System Efficiency

90

85

80

75

70

65

60

55

50

45

90

85

80

75

70

65

60

55

50

45

T_A= -40èC

T_A= 25èC

T_A= 85èC

T_A= -40èC

T_A= 25èC

T_A= 85èC

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

D233

D234

2p8s

ƒ = 500 kHz

L = 4.7 µH

2p8s

ƒ = 500 kHz

L = 4.7 µH

图 101. Backlight Boost Efficiency

图 102. Backlight System Efficiency

90

85

80

75

70

65

60

55

50

45

90

85

80

75

70

65

60

55

50

45

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

D235

D236

2p8s

ƒ = 1 MHz

L = 4.7 µH

2p8s

ƒ = 1 MHz

L = 4.7 µH

图 103. Backlight Boost Efficiency

图 104. Backlight System Efficiency

56

LM36273

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ZHCSGN8D –FEBRUARY 2016–REVISED MARCH 2018

90

85

80

75

70

65

60

55

50

45

90

85

80

75

70

65

60

55

50

45

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

T_A= -40èC

T_A= 25èC

T_A= 85èC

0

5

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

0

5

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

D237

D238

2p8s

ƒ = 500 kHz

L = 4.7 µH

2p8s

ƒ = 500 kHz

L = 4.7 µH

图 105. Backlight Boost Efficiency

图 106. Backlight System Efficiency

90

85

80

75

70

65

60

55

50

45

90

85

80

75

70

65

60

55

50

45

T_A= -40èC

T_A= 25èC

T_A= 85èC

T_A= -40èC

T_A= 25èC

T_A= 85èC

5

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

D239

D240

2p6s

ƒ = 1 MHz

L = 4.7 µH

2p6s

ƒ = 1 MHz

L = 4.7 µH

图 107. Backlight Boost Efficiency

图 108. Backlight System Efficiency

90

85

80

75

70

65

60

55

50

45

90

85

80

75

70

65

60

55

50

45

T_A= -40èC

T_A= 25èC

T_A= 85èC

T_A= -40èC

T_A= 25èC

T_A= 85èC

5

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

D241

D242

2p6s

ƒ = 500 kHz

L = 4.7 µH

2p6s

ƒ = 500 kHz

L = 4.7 µH

图 109. Backlight Boost Efficiency

图 110. Backlight System Efficiency

57

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ZHCSGN8D –FEBRUARY 2016–REVISED MARCH 2018

www.ti.com.cn

90

85

80

75

70

65

60

55

50

45

90

85

80

75

70

65

60

55

50

45

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

0

5

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

0

5

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

D244

D243

2p6s

ƒ = 1 MHz

L = 4.7 µH

2p6s

ƒ = 1 MHz

L = 4.7 µH

图 112. Backlight System Efficiency

图 111. Backlight Boost Efficiency

90

85

80

75

70

65

60

55

50

45

90

85

80

75

70

65

60

55

50

45

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

0

5

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

0

5

10 15 20 25 30 35 40 45 50 55 60

Load (mA)

D245

D246

2p6s

ƒ = 500 kHz

L = 4.7 µH

2p6s

ƒ = 500 kHz

L = 4.7 µH

图 113. Backlight Boost Efficiency

图 114. Backlight System Efficiency

58

LM36273

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ZHCSGN8D –FEBRUARY 2016–REVISED MARCH 2018

8.2.3.1.2 Three LED Strings

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

T_A= -40èC

T_A= 25èC

T_A= 85èC

T_A= -40èC

T_A= 25èC

T_A= 85èC

0

10

3

20

30

40

50

60

70

80

90

0

10

3

20

30

40

50

60

70

80

90

Load (mA)

D301

D302

3p8s

ƒ = 1 MHz

L = 10 µH

3p8s

ƒ = 1 MHz

L = 10 µH

图 115. Backlight Boost Efficiency

图 116. Backlight System Efficiency

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

T_A= -40èC

T_A= 25èC

T_A= 85èC

T_A= -40èC

T_A= 25èC

T_A= 85èC

20

30

40

50

60

70

80

90

20

30

40

50

60

70

80

90

Load (mA)

D303

D304

3p8s

ƒ = 500 kHz

L = 10 µH

3p8s

ƒ = 500 kHz

L = 10 µH

图 117. Backlight Boost Efficiency

图 118. Backlight System Efficiency

90

85

80

75

70

65

60

55

50

45

90

85

80

75

70

65

60

55

50

45

T_A= -40èC

T_A= 25èC

T_A= 85èC

T_A= -40èC

T_A= 25èC

T_A= 85èC

6

9

12

15

18

21

24

27

30

6

9

12

15

18

21

24

27

30

Load (mA)

D305

D306

3p8s

ƒ = 250 kHz

L = 10 µH

3p8s

ƒ = 250 kHz

L = 10 µH

图 119. Backlight Boost Efficiency

图 120. Backlight System Efficiency

59

LM36273

ZHCSGN8D –FEBRUARY 2016–REVISED MARCH 2018

www.ti.com.cn

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

0

10

20

30

40

50

60

70

80

90

0

10

20

30

40

50

60

70

80

90

Load (mA)

D307

D308

3p8s

ƒ = 1 MHz

L = 10 µH

3p8s

ƒ = 1 MHz

L = 10 µH

图 121. Backlight Boost Efficiency

图 122. Backlight System Efficiency

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

20

30

40

50

60

70

80

90

20

30

40

50

60

70

80

90

Load (mA)

D309

D310

3p8s

ƒ = 500 kHz

L = 10 µH

3p8s

ƒ = 500 kHz

L = 10 µH

图 123. Backlight Boost Efficiency

图 124. Backlight System Efficiency

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

T_A= -40èC

T_A= 25èC

T_A= 85èC

T_A= -40èC

T_A= 25èC

T_A= 85èC

20

30

40

50

60

70

80

90

20

30

40

50

60

70

80

90

Load (mA)

D311

D312

3p6s

ƒ = 1 MHz

L = 10 µH

3p6s

ƒ = 1 MHz

L = 10 µH

图 125. Backlight Boost Efficiency

图 126. Backlight System Efficiency

60

LM36273

www.ti.com.cn

ZHCSGN8D –FEBRUARY 2016–REVISED MARCH 2018

95

90

85

80

75

70

65

60

55

95

90

85

80

75

70

65

60

55

50

T_A= -40èC

T_A= 25èC

T_A= 85èC

T_A= -40èC

T_A= 25èC

T_A= 85èC

50

0

10

20

30

40

50

60

70

80

90

0

10

20

30

40

50

60

70

80

90

Load (mA)

D313

D314

3p6s

ƒ = 500 kHz

L = 10 µH

3p6s

ƒ = 500 kHz

L = 10 µH

图 127. Backlight Boost Efficiency

图 128. Backlight System Efficiency

95

90

85

80

75

70

65

60

55

95

90

85

80

75

70

65

60

55

50

T_A= -40èC

T_A= 25èC

T_A= 85èC

T_A= -40èC

T_A= 25èC

T_A= 85èC

50

0

3

6

9

12

15

18

21

24

27

30

3

6

9

12

15

18

21

24

27

30

Load (mA)

D315

D316

3p6s

ƒ = 250 kHz

L = 10 µH

3p6s

ƒ = 250 kHz

L = 10 µH

图 129. Backlight Boost Efficiency

图 130. Backlight System Efficiency

95

90

85

80

75

70

65

60

55

95

90

85

80

75

70

65

60

55

50

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

50

0

10

20

30

40

50

60

70

80

90

10

20

30

40

50

60

70

80

90

Load (mA)

D317

D318

3p6s

ƒ = 1 MHz

L = 10 µH

3p6s

ƒ = 1 MHz

L = 10 µH

图 131. Backlight Boost Efficiency

图 132. Backlight System Efficiency

61

LM36273

ZHCSGN8D –FEBRUARY 2016–REVISED MARCH 2018

www.ti.com.cn

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

0

10

20

30

40

50

60

70

80

90

0

10

20

30

40

50

60

70

80

90

Load (mA)

D319

D320

3p6s

ƒ = 500 kHz

L = 10 µH

3p6s

ƒ = 500 kHz

L = 10 µH

图 133. Backlight Boost Efficiency

图 134. Backlight System Efficiency

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

T_A= -40èC

T_A= 25èC

T_A= 85èC

T_A= -40èC

T_A= 25èC

T_A= 85èC

20

30

40

50

60

70

80

90

20

30

40

50

60

70

80

90

Load (mA)

D321

D322

3p8s

ƒ = 1 MHz

L = 15 µH

3p8s

ƒ = 1 MHz

L = 15 µH

图 135. Backlight Boost Efficiency

图 136. Backlight System Efficiency

95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

50

T_A= -40èC

T_A= 25èC

T_A= 85èC

T_A= -40èC

T_A= 25èC

T_A= 85èC

20

30

40

50

60

70

80

90

20

30

40

50

60

70

80

90

Load (mA)

D323

D324

3p8s

ƒ = 500 kHz

L = 15 µH

3p8s

ƒ = 500 kHz

L = 15 µH

图 137. Backlight Boost Efficiency

图 138. Backlight System Efficiency

62

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ZHCSGN8D –FEBRUARY 2016–REVISED MARCH 2018

95

90

85

80

75

70

65

60

55

95

90

85

80

75

70

65

60

55

50

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

50

0

10

20

30

40

50

60

70

80

90

0

10

20

30

40

50

60

70

80

90

Load (mA)

D325

D326

3p8s

ƒ = 1 MHz

L = 15 µH

3p8s

ƒ = 1 MHz

L = 15 µH

图 139. Backlight Boost Efficiency

图 140. Backlight System Efficiency

95

90

85

80

75

70

65

60

55

95

90

85

80

75

70

65

60

55

50

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

50

0

20

30

40

50

60

70

80

90

20

30

40

50

60

70

80

90

Load (mA)

D327

D328

3p8s

ƒ = 500 kHz

L = 15 µH

3p8s

ƒ = 500 kHz

L = 15 µH

图 141. Backlight Boost Efficiency

图 142. Backlight System Efficiency

90

85

80

75

70

65

60

55

50

90

85

80

75

70

65

60

55

50

45

T_A= -40èC

T_A= 25èC

T_A= 85èC

T_A= -40èC

T_A= 25èC

T_A= 85èC

45

0

20

30

40

50

60

70

80

90

20

30

40

50

60

70

80

90

Load (mA)

D329

D330

3p8s

ƒ = 1 MHz

L = 4.7 µH

3p8s

ƒ = 1 MHz

L = 4.7 µH

图 143. Backlight Boost Efficiency

图 144. Backlight System Efficiency

63

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ZHCSGN8D –FEBRUARY 2016–REVISED MARCH 2018

www.ti.com.cn

90

85

80

75

70

65

60

55

50

45

90

85

80

75

70

65

60

55

50

45

T_A= -40èC

T_A= 25èC

T_A= 85èC

T_A= -40èC

T_A= 25èC

T_A= 85èC

0

10

20

30

40

50

60

70

80

90

0

10

20

30

40

50

60

70

80

90

Load (mA)

D331

D332

3p8s

ƒ = 500 kHz

L = 4.7 µH

3p8s

ƒ = 500 kHz

L = 4.7 µH

图 145. Backlight Boost Efficiency

图 146. Backlight System Efficiency

90

85

80

75

70

65

60

55

50

45

90

85

80

75

70

65

60

55

50

45

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

20

30

40

50

60

70

80

90

20

30

40

50

60

70

80

90

Load (mA)

D333

D334

3p8s

ƒ = 1 MHz

L = 4.7 µH

3p8s

ƒ = 1 MHz

L = 4.7 µH

图 147. Backlight Boost Efficiency

图 148. Backlight System Efficiency

90

85

80

75

70

65

60

55

50

45

90

85

80

75

70

65

60

55

50

45

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

20

30

40

50

60

70

80

90

20

30

40

50

60

70

80

90

Load (mA)

D335

D336

3p8s

ƒ = 500 kHz

L = 4.7 µH

3p8s

ƒ = 500 kHz

L = 4.7 µH

图 149. Backlight Boost Efficiency

图 150. Backlight System Efficiency

64

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ZHCSGN8D –FEBRUARY 2016–REVISED MARCH 2018

8.2.3.2 LCM Bias Curves

Ambient temperature is 25°C and V_INis 3.7 V unless otherwise noted. VPOS, VNEG and VPOS/VNEG efficiency

is defined as POUT / PIN, where POUT is actual power consumed in VPOS, VNEG and (VPOS + VNEG)

outputs, respectively. External components are from 表 30.

100

95

90

85

80

75

70

65

60

100

95

90

85

80

75

70

65

60

T_A= -40èC

T_A= 25èC

T_A= 85èC

T_A= -40èC

T_A= 25èC

T_A= 85èC

0

20

40

60

80

100

120

140

160

0

20

40

60

80

100

120

140

160

Load (mA)

D101

D102

V_{LCM_OUT}= 4.3 V

V_{LCM_OUT}= 5.3 V

图 151. LCM Boost Efficiency

图 152. LCM Boost Efficiency

100

95

90

85

80

75

70

65

60

100

95

90

85

80

75

70

65

60

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 4.5 V

T_A= -40èC

T_A= 25èC

T_A= 85èC

0

20

40

60

80

100

120

140

160

0

20

40

60

80

100

120

140

160

Load (mA)

D104

D103

V_{LCM_OUT}= 4.8 V

V_{LCM_OUT}= 6.3 V

图 154. LCM Boost Efficiency

图 153. LCM Boost Efficiency

100

95

90

85

80

75

70

65

60

100

95

90

85

80

75

70

65

60

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

0

20

40

60

80

100

120

140

160

0

20

40

60

80

100

120

140

160

Load (mA)

D105

D106

V_{LCM_OUT}= 5.8 V

图 155. LCM Boost Efficiency

V_{LCM_OUT}= 6.8 V

图 156. LCM Boost Efficiency

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95

90

85

80

75

70

65

60

55

50

45

95

90

85

80

75

70

65

60

55

50

45

T_A= -40èC

T_A= 25èC

T_A= 85èC

T_A= -40èC

T_A= 25èC

T_A= 85èC

0

10

20

30

40

50

60

70

80

0

10

20

30

40

50

60

70

80

Load (mA)

D107

D108

D110

D112

V_VPOS= 4 V

V_{LCM_OUT}= 4.3 V

图 157. VPOS Efficiency

V_VPOS= 5 V

V_{LCM_OUT}= 5.3 V

图 158. VPOS Efficiency

95

90

85

80

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70

65

60

55

50

45

95

90

85

80

75

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65

60

55

50

45

T_A= -40èC

T_A= 25èC

T_A= 85èC

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 4.5 V

0

10

30

40

50

60

70

80

0

10

30

40

50

60

70

80

Load (mA)

D109

V_VPOS= 6 V

V_{LCM_OUT}= 6.3 V

图 159. VPOS Efficiency

图 160. VPOS Efficiency

95

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55

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45

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80

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65

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55

50

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V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

0

10

30

40

50

60

70

80

0

10

30

40

50

60

70

80

Load (mA)

D111

V_VPOS= 6 V

V_{LCM_OUT}= 6.3 V

图 161. VPOS Efficiency

V_VPOS= 6.5 V

V_{LCM_OUT}= 6.8 V

图 162. VPOS Efficiency

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90

85

80

75

70

65

60

55

50

45

40

90

85

80

75

70

65

60

55

50

45

T_A= -40èC

T_A= 25èC

T_A= 85èC

T_A= -40èC

T_A= 25èC

T_A= 85èC

40

0

10

20

30

40

50

60

70

80

10

20

30

40

50

60

70

80

Load (mA)

D114

D116

D118

D113

D115

D117

V_VNEG= -5 V

V_{LCM_OUT}= 5.3 V

图 164. VNEG Efficiency

V_VNEG= -4 V

V_{LCM_OUT}= 4.3 V

图 163. VNEG Efficiency

90

95

85

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75

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65

60

55

50

45

40

90

85

80

75

70

65

60

55

50

45

T_A= -40èC

T_A= 25èC

T_A= 85èC

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 4.5 V

0

10

30

40

50

60

70

80

0

10

30

40

50

60

70

80

Load (mA)

V_VNEG= -6 V

V_{LCM_OUT}= 6.3 V

图 165. VNEG Efficiency

V_VNEG= –4.5 V

V_{LCM_OUT}= 4.8 V

图 166. VNEG Efficiency

95

90

85

80

75

70

65

60

55

50

45

90

85

80

75

70

65

60

55

50

45

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

0

10

30

40

50

60

70

80

0

10

30

40

50

60

70

80

Load (mA)

V_VNEG= –5.5 V

V_{LCM_OUT}= 5.8 V

图 167. VNEG Efficiency

V_VNEG= –6.5 V

V_{LCM_OUT}= 6.8 V

图 168. VNEG Efficiency

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LM36273

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95

90

85

80

75

70

65

60

55

50

95

90

85

80

75

70

65

60

55

T_A= -40èC

T_A= 25èC

T_A= 85èC

T_A= -40èC

T_A= 25èC

T_A= 85èC

0

10

20

30

40

50

60

70

80

0

10

20

30

40

50

60

70

80

Load (mA)

D119

D120

V_VPOS= 4 V

V_VNEG= –4 V

V_{LCM_OUT}= 4.3 V

V_VPOS= 5 V

V_VNEG= –5 V

V_{LCM_OUT}= 5.3 V

图 169. VPOS/VNEG Efficiency

图 170. VPOS/VNEG Efficiency

95

90

85

80

75

70

65

60

95

90

85

80

75

70

65

60

55

50

T_A= -40èC

T_A= 25èC

T_A= 85èC

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 4.5 V

0

10

20

30

40

50

60

70

80

0

10

20

30

40

50

60

70

80

Load (mA)

D121

D122

V_VPOS= 6 V

V_VNEG= –6 V

V_{LCM_OUT}= 6.3 V

V_VPOS= 4.5 V

V_VNEG= –4.5 V

V_{LCM_OUT}= 4.8 V

图 171. VPOS/VNEG Efficiency

图 172. VPOS/VNEG Efficiency

95

90

85

80

75

70

65

60

55

50

90

85

80

75

70

65

60

55

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

V_IN= 2.7 V

V_IN= 3.7 V

V_IN= 5 V

0

10

20

30

40

50

60

70

80

0

10

20

30

40

50

60

70

80

Load (mA)

D124

D123

V_VPOS= 6.5 V

V_VNEG= –6.5 V

V_{LCM_OUT}= 6.8 V

V_VPOS= 5.5 V

V_VNEG= –5.5 V

V_{LCM_OUT}= 5.8 V

图 174. VPOS/VNEG Efficiency

图 173. VPOS/VNEG Efficiency

68

LM36273

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ZHCSGN8D –FEBRUARY 2016–REVISED MARCH 2018

9 Power Supply Recommendations

The LM36273 is designed to operate from an input voltage supply range from 2.7 V to 5 V. This input supply

must be well regulated and capable to supply the required input current. If the input supply is located far from the

LM36273 additional bulk capacitance may be required in addition to the ceramic bypass capacitors.

10 Layout

10.1 Layout Guidelines

•

Place the boost converter output capacitors as close to the output voltage and GND pins as possible.

Minimize the boost converter switching loops by placing the input capacitors and inductors close to GND and

switch pins.

•

If possible, route the switching loops on top layer only. For best efficiency, try to minimize copper on the

switch node to minimize switch pin parasitic capacitance while preserving adequate routing width.

VIN input voltage pin must be bypassed to ground with a low-ESR bypass capacitor. Place the capacitor as

close as possible to VIN pin.

Place the output capacitor of the LDO as close to the output pins as possible. Also place the charge pump

flying capacitor and output capacitor close to their respective pins.

Route the internal pins on the second layer. Use offset micro vias to go from top layer to mid-layer1. Avoid

routing the signal traces directly under the switching loops of the boost converters.

69

LM36273

ZHCSGN8D –FEBRUARY 2016–REVISED MARCH 2018

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10.2 Layout Example

VIAs to

GND Plane

VIAs to

GND Plane

VINL

C_VNEG

C_VPOS

C_FLY

VNEG

C-

C+

CP_GND

C_IN

IN

VPOS

LCM_EN2

LCM_EN1

LCM_OUT

LCM_SW

BL_GND

BL_SW

NC

SCL

SDA

VINL

PWM

HWEN

LED3

LED2

LED1

L_LCM

C_LCM

AGND

BL_OUT

LCM_GND

BL_SW

VIAs to

GND Plane

L_BL

C_{BL_OUT}

D1

VINL

VIAs to

GND Plane

图 175. LM36273 Layout Example

70

LM36273

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ZHCSGN8D –FEBRUARY 2016–REVISED MARCH 2018

11 器件和文档支持

11.1 器件支持

11.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类

产品或服务单独或与任何 TI 产品或服务一起的表示或认可。

11.1.2 开发支持

Power Stage Designer™ 工具可用于升压计算：http://www.ti.com.cn/tool/cn/powerstage-designer

11.2 文档支持

11.2.1 相关文档

如需相关文档，请参阅：

•

《AN-1112 DSBGA 晶圆级芯片级封装》

《了解开关模式电源中的升压功率级》

11.3 接收文档更新通知

要接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。请单击右上角的提醒我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.4 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

11.5 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.6 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，也

不会对此文档进行修订。如欲获取此数据表的浏览器版本，请参阅左侧的导航。

71

D: Max = 2.44 mm, Min = 2.38 mm

E: Max = 1.671 mm, Min = 1.61 mm

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

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这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LM36273
厂家：	TEXAS INSTRUMENTS
描述：	三通道 LCD 背光和偏置电源 CD
文件：	总76页 (文件大小：4184K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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