LM49153_15 [TI]
Mono Audio Subsystem with Class G Headphone Amplifier, Class D Speaker Amplifier, Noise Gate and Speaker Protection;
| 型号： | LM49153_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Mono Audio Subsystem with Class G Headphone Amplifier, Class D Speaker Amplifier, Noise Gate and Speaker Protection 栅 |
| 文件： | 总32页 (文件大小：1064K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM49153
LM49153 Mono Audio Subsystem with Class G Headphone Amplifier, Class D
SpeakerAmplifier, Noise Gate and Speaker Protection
Literature Number: SNAS496B
April 4, 2011
LM49153
Mono Audio Subsystem with Class G Headphone
Amplifier, Class D Speaker Amplifier, Noise Gate and
Speaker Protection
General Description
Key Specifications
The LM49153 is a fully integrated audio subsystem designed
for portable handheld applications such as cellular phones.
Part of National’s PowerWise family of products, the
LM49153 combines an earpiece switch, a high efficiency
25mW class G headphone amplifier, and a high efficiency
1.35W class D loudspeaker into a single device.
■ꢀClass G Headphone Amplifier,
ꢀꢀHPVDD = 1.8V, RL = 32Ω
IDDQHP
1.2mA (typ)
POUT, THD+N ≤ 1%
HP VOS
25mW (typ)
0.5mV (typ)
The headphone amplifiers feature National’s class G ground
referenced architecture that creates a ground-referenced out-
put with dynamic supply rails for optimum efficiency. The
class D amplifier features an ALC (Automatic Level Control)
with a noise gate that provides both no-clip and speaker pro-
tection.
■ꢀMono Class D Speaker Amplifier
ꢀꢀRL = 8Ω, THD+N < 1%
POUT, LSVDD = 5.0V
POUT, LSVDD = 3.6V
Efficiency
1.35W (typ)
680mW (typ)
88% (typ)
Mode selection, shutdown control, and volume are controlled
through an I2C compatible interface.
Click and pop suppression eliminates audible transients on
power-up/down and during shutdown. The LM49153 is avail-
able in an ultra-small 25-bump 0.4mm pitch micro SMD pack-
age (2.30mm x 2.42mm).
Features
Class G Ground Referenced Headphone Outputs
High Efficiency Class D Amplifier with Spread Spectrum
No Clip
■
■
■
■
■
■
■
■
Speaker Protection
Noise Gate
I2C Volume and Mode Control
Advanced Click-and-Pop Suppression
Micro-power shutdown
Applications
Feature phones
■
■
Smart phones
Boomer® is a registered trademark of National Semiconductor Corporation.
© 2011 National Semiconductor Corporation
301210
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Typical Application
30121063
FIGURE 1. Typical Audio Amplifier Application Circuit
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Connection Diagrams
25 Bump micro SMD Package
30121064
Top View
Order Number LM49153TM
See NS Package Number TMD25MSA
25 Bump micro SMD Markings
30121075
Top View
XY - Date Code
TT - Die Traceability
G - Boomer Family
O7 - LM49153TM
Ordering Information
Order Number
Package
Package DWG #
Transport Media
MSL Level Green Status
RoHS and
no sB/Br
LM49153TM
25 Bump micro SMD
TMD25MSA
250 units on tape and reel
3000 units on tape and reel
1
RoHS and
no sB/Br
LM49153TMX
25 Bump micro SMD
TMD25MSA
1
3
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TABLE 1. Bump Description
Description
Bump
A1
A2
A3
A4
A5
B1
B2
B3
B4
B5
C1
C2
C3
C4
C5
D1
D2
D3
D4
D5
E1
E2
E3
E4
E5
Name
HPVDD
C1P
Headphone Power Supply
Charge Pump Flying Capacitor Positive Terminal
Charge Pump Ground
CPGND
LSOUT-
LSOUT+
CPVSS
C1N
Loudspeaker Inverting Output
Loudspeaker Non-Inverting Output
Charge Pump Output
Charge Pump Flying Capacitor Negative Terminal
I2C Serial Clock Input
SCL
SET
ALC Timing Set
LSVDD
CPVDD
SDA
Loudspeaker Power Supply
Charge Pump Power Supply
I2C Serial Data Input
INL2
Left Channel Input 2
EP+
Earpiece Non-Inverting Input
Earpiece Non-Inverting Output
Right Channel Headphone Output
Mid-Rail Bias Bypass Node
Right Channel Input 2
EPOUT+
HPR
BYPASS
INR2
EP-
Earpiece Inverting Input
EPOUT-
HPL
Earpiece Inverting Output
Left Channel Headphone Output
Ground
GND
VDD
Power Supply
INM-/INR1
INM+/INL1
Mono Channel Inverting Input/Right Channel Input 1
Mono Channel Non-Inverting Input/Left Channel Input 1
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Junction Temperature
Thermal Resistance
ꢁθJA (TMD25MSA)
Soldering Information
150°C
Absolute Maximum Ratings (Note 1, Note
2)
46°C/W
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ꢀSee AN-1112 “Micro SMD Wafer Level Chip Scale
Package”
Supply Voltage (VDD, LSVDD) (Note 1)
Supply Voltage (HPVDD) (Note 1)
Storage Temperature
6V
3V
Operating Ratings
−635°C to +150°C
−0.3 to VDD +0.3
Internally Limited
2.0kV
Temperature Range
Input Voltage
TMIN ≤ TA ≤TMAX
Supply Voltage (VDD, LSVDD
−40°C ≤TA ≤+85°C
2.7V ≤ VDD ≤ 5.5V
1.7V ≤HPVDD ≤2.0V
Power Dissipation (Note 3)
ESD Rating (Note 4)
ESD Rating (Note 5)
)
Supply Voltage (HPVDD
)
200V
Electrical Characteristics VDD = 3.6V, HPVDD = 1.8V (Note 1, Note 2)
The following specifications apply for VDD = LSVDD, AV = 0dB, RL = 15μH+8Ω+15µH (Loudspeaker), RL = 32Ω (Headphone),
CSET = 0.1µF, f = 1kHz, ALC off, unless otherwise specified. Limits apply for TA = 25°C. (Note 8).
LM49153
Units
Symbol
Parameter
Conditions
VIN = 0, No Load
Typical
Limits
(Limits)
(Note 6)
(Note 7)
EP Receiver
(Output Mode Bit EP Bypass = 1)
0.3
2.5
4.3
μA (max)
LS only (Mode 2)
VDD, LSVDD
HPVDD
3.0
0
mA (max)
mA
IDD
Supply Current
HP only (Mode 1)
VDD + LSVDD
HPVDD
1.8
1.2
2.5
1.6
mA (max)
mA (max)
LS + HP (Mode 6)
VDD + LSVDD
HPVDD
4.3
1.2
5.5
1.6
mA (max)
mA (max)
ISD
VSCL = VSDA = 3.6V
Shutdown Current
0.3
2.5
µA (max)
VIN = 0, Mode 3, 6, 9
VOS
LS Output, RL = 8Ω, AV = 12dB
HP Output, RL = 32Ω, AV = 0dB
9
mV
mV
Output Offset Voltage
0.5
HP Mode, CBYPASS = 2.2μF
Normal turn on time
Fast turn on time
tWU
Wake Up Time
Volume Control
32
18
ms
ms
Mute
–86
dB
Minimum Gain Setting
(mono input)
–51
–54
dB (max)
dB (min)
–52.5
12.5
11.5
dB (max)
dB (min)
Maximum Gain Setting (mono input)
Minimum Gain Setting (stereo input)
Maximum Gain Setting (stereo input)
12
–80
18
AVOL
dB (max)
dB (min)
dB (max)
dB (min)
5
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LM49153
Units
(Limits)
Symbol
Parameter
Conditions
Typical
Limits
(Note 6)
(Note 7)
LS Mode
Gain 0
12
18
dB
dB
Gain 1
HP Mode
5
7
dB (min)
dB (max)
Gain 0
6
Gain 1
Gain 2
Gain 3
Gain 4
Gain 5
Gain 6
Gain 7
3
0
dB
dB
dB
dB
dB
dB
AV
Gain
–1.5
–3
–6
–9
–13
–11
dB (min)
dB (max)
–12
LS Output
–80
–98
4.5
dB
dB
AVMUTE
Mute Attention
HP Output
Analog Switch
6
Ω (max)
MONO, RIN, LIN, Inputs
kΩ (min)
kΩ (max)
11
15.5
RIN
Input Resistance
Maximum Gain Setting
13
kΩ (min)
kΩ (max)
90
130
Minimum Gain Setting
110
LS Mode, AV = 18dB, RL = 8Ω
LSVDD = 3.3V
570
680
mW
mW (min)
mW
LSVDD = 3.6V
620
LSVDD = 4.2V
935
PO
Output Power
LSVDD = 5.0V
1350
mW
HP Mode, AV = 6dB
RL = 16Ω
25
25
mW
RL = 32Ω
22
mW (min)
f = 1kHz
LS Mode, PO = 250mW, mono input
HP Mode, PO = 12mW, Stereo input
0.02
0.02
0.05
%
%
%
THD+N Total Harmonic Distortion + Noise
EP Bypass Mode, RL = 32Ω
f = 217Hz, VRIPPLE = 200mVPP
,
CB = 2.2µF, Inputs AC GND
LS Mode, mono input, AV = 12dB
LS Mode, stereo input, AV = 12dB
HP Mode, mono input, ripple on VDD
HP Mode, mono input, ripple on HPVDD
HP Mode, stereo input, ripple on VDD
72
64
94
81
80
dB
dB
dB
dB
dB
Power Supply Rejection Ratio
(Output referred)
PSRR
VRIPPLE = 1VP-P, fRIPPLE = 217Hz, mono input, AV = 0dB
CMRR Common Mode Rejection Ratio
LS Mode 2
38
51
88
80
dB
dB
%
HP Mode 1
Efficiency
Crosstalk
LS Mode, THD+N = 1%
PO = 12mW, f = 1kHz
η
XTALK
dB
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LM49153
Units
(Limits)
Symbol
Parameter
Conditions
Typical
Limits
(Note 6)
(Note 7)
A-weighted, Inputs AC GND
LS Mode, mono input
46
52
11
11
µV
µV
µV
µV
εOS
Output Noise
LS Mode, stereo input
HP Mode, mono input
HP Mode, stereo input
LS Mode, PO = 680mW, A-weighted, Mono
HP Mode, PO = 25mW, A-weighted
94
98
dB
dB
SNR
tA
Signal to Noise Ratio
I2C = 1
I2C = 0
0.1
0.9
ms
ms
Noise Gate Attack Time
Noise Gate Release Time
I2C = 0
I2C = 1
1.2
2.1
s
s
tR
VP-P
VP-P
VP-P
Low 010
Medium 011
High 100
7.3
7.8
8.1
CC
Clip Control
LS Mode 1, THD+N ≤ 1%, (Note 9)
Voltage Level
VP-P
VP-P
VP-P
VP-P
VP-P
VP-P
001
010
011
100
101
110
4
4.8
5.6
6.4
7.2
8.0
PLIMIT
Output Power Limit
tA
tR
ALC Attack Time
0.5
ms
ms
ALC Release Time
200
7
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I2C Interface Characteristics VDD = 3.6V (Note 1, Note 2)
The following specifications apply for AV = 0dB, RL = 8Ω, f = 1kHz, unless otherwise specified. Limits apply for TA = 25°C.
LM49153
Units
(Limits)
Symbol
Parameter
Conditions
Typical
Limits
(Note 7)
(Note 6)
t1
t2
SCL Period
2.5
250
0
µs (min)
ns (min)
ns (min)
ns (min)
ns (min)
V (min)
V (max)
SDA Setup Time
t3
SDA Stable Time
Start Condition Time
Stop Condition Time
Input High Voltage
Input Low Voltage
t4
250
250
1.2
0.6
t5
VIH
VIL
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions. All voltages are measured with respect to the ground pin, unless otherwise specified
Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum
allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings, whichever is lower.
Note 4: Human body model, applicable std. JESD22-A114C.
Note 5: Machine model, applicable std. JESD22-A115-A.
Note 6: Typical values represent most likely parametric norms at TA = +25ºC, and at the Recommended Operation Conditions at the time of product
characterization and are not guaranteed.
Note 7: Datasheet min/max specification limits are guaranteed by test or statistical analysis.
Note 8: Loudspeaker RL is a resistive load in series with two inductors to simulate an actual speaker load. For RL = 8Ω, the load is 15µH + 8Ω, +15µH. For RL
4Ω, the load is 15µH + 4Ω + 15µH.
=
Note 9: The LM49153 ALC limits the output power to which ever is lower, the supply voltage or output power limit.
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Typical Performance Characteristics (Note 8)
THD+N vs Output Power
VDD = 3.6V, RL = 8Ω, f = 1kHz
AV = 18dB, Mode 2
THD+N vs Output Power
VDD = 4.2V, RL = 8Ω, f = 1kHz
AV = 18dB, Mode 2
30121082
30121083
THD+N vs Output Power
VDD = 5.0V, RL = 8Ω, f = 1kHz
AV = 18dB, Mode 2
THD+N vs Output Power
VDD = 3.6V, HPVDD = 1.8V, RL = 16Ω, f = 1kHz
AV = 6dB, Mode 4
30121084
30121085
THD+N vs Output Power
VDD = 3.6V, HPVDD = 1.8V, RL = 32Ω, f = 1kHz
AV = 6dB, Mode 4
THD+N vs Output Power
RL = 32Ω, f = 1kHz, Earpiece Mode
30121086
301210a0
9
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PSRR vs FREQUENCY
VDD = 3.6V, HPVDD = 1.8V, VDD-RIPPLE = 200mVP-P
PSRR vs FREQUENCY
VDD = 3.6V, HPVDD = 1.8V, VDD-RIPPLE = 200mVP-P
RL = 8Ω, Mono Input, LS Mode
RL = 8Ω, Stereo Input, LS Mode
30121087
30121088
PSRR vs FREQUENCY
VDD = 3.6V, HPVDD = 1.8V, VDD-RIPPLE = 200mVP-P
PSRR vs FREQUENCY
VDD = 3.6V, HPVDD = 1.8V, HPVDD-RIPPLE = 200mVP-P
RL = 32Ω, Mono Input, HP Mode
RL = 32Ω, Mono Input, HP Mode
30121089
30121090
SUPPLY CURRENT vs SUPPLY VOLTAGE
No Load, Loudspeaker Mode 2
SUPPLY CURRENT vs SUPPLY VOLTAGE
No Load, Loudspeaker Mode 4
301210a2
301210a1
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EFIICIENCY vs OUTPUT POWER
RL = 8Ω, f = 1kHz, Loudspeaker Mode 2
POWER DISSIPATION vs OUTPUT POWER
VDD = 3.6V, HPVDD = 1.8V, RL = 32Ω, f = 1kHz
Loudspeaker Mode 2
301210a3
301210a4
POWER DISSIPATION vs OUTPUT POWER
RL = 32Ω, f = 1kHz
OUTPUT POWER vs SUPPLY VOLTAGE
RL = 8Ω, f = 1kHz
Loudspeaker Mode 2
301210a6
301210a5
OUTPUT POWER vs SUPPLY VOLTAGE
RL = 32Ω, f = 1kHz
301210a7
11
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Application Information
WRITE-ONLY I2C COMPATIBLE INTERFACE
The 7-bit device address is written to the bus, most significant
bit (MSB) first, followed by the R/W bit. R/W = 0 indicates the
master is writing to the slave device, R/W = 1 indicates the
master wants to read data from the slave device. Set R/W =
0; the LM49153 is a WRITE-ONLY device and will not re-
spond the R/ W = 1. The data is latched in on the rising edge
of the clock. Each address bit must be stable while SCL is
HIGH. After the last address bit is transmitted, the master de-
vice releases SDA, during which time, an acknowledge clock
pulse is generated by the slave device. If the LM49153 re-
ceives the correct address, the device pulls the SDA line low,
generating an acknowledge bit (ACK).
The LM49153 is controlled through an I2C compatible serial
interface that consists of a serial data line (SDA) and a serial
clock (SCL). The clock line is uni-directional. The data line is
bi-directional (open drain). The LM49153 and the master can
communicate at clock rates up to 400kHz. Figure 2 shows the
I2C interface timing diagram. Data on the SDA line must be
stable during the HIGH period of SCL. The LM49153 is a
transmit/receive slave-only device, reliant upon the master to
generate the SCL signal. Each transmission sequence is
framed by a START condition and a STOP condition (Figure
3). Each data word, device address and data, transmitted
over the bus is 8 bits long and is always followed by an ac-
knowledge pulse (Figure 4). The LM49153 device address is
1100000.
Once the master device registers the ACK bit, the 8-bit reg-
ister data word is sent. Each data bit should be stable while
SCL is HIGH. After the 8-bit register data word is sent, the
LM49153 sends another ACK bit. Following the acknowl-
edgement of the register data word, the master issues a
STOP bit, allowing SDA to go high.
I2C BUS FORMAT
The I2C bus format is shown in Figure 4. The START signal,
the transition of SDA from HIGH to LOW while SCL is HIGH,
is generated, alerting all devices on the bus that a device ad-
dress is being written to the bus.
30121065
FIGURE 2. I2C Timing Diagram
30121066
FIGURE 3. Example I2C Write Cycle
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DEVICE ADDRESS REGISTER
B7
TABLE 2. Device Address
B6
B5
B4
B3
B2
B1
B0 (W)
Device Address
1
1
1
1
1
0
0
0
I2C CONTROL REGISTER
TABLE 3. I2C Control
Register Name
Shutdown control
Mode control
B7
0
B6
0
B5
0
B4
1
B3
B2
B1
ClassG_SD
B0
GAMP_ON
HPR_SD
PWR_ON
0
0
1
EP
MODE_CONTROL
POWER_LEVEL
Power limiter control
No clip control
Gain control
0
1
0
ATTACK_TIME
RELEASE_TIME
0
1
1
OUTPUT_CLIP_CONTROL
HP_GAIN
1
0
0
0
LSGAIN
Volume control
LS control
1
0
1
LS_VOLUME/HP_VOLUME
NOISE_GATE_LEVEL NOISE_GATE_TIME
1
1
0
0
0
0
Other control
1
1
1
0
1
0
0
0
0
Class-G control
1
1
1
CLASS_G_TRIP_LEVEL
TURN_ON
Other control
1
1
1
1
0
0
SS_EN
TIME
SHUTDOWN CONTROL REGISTER
TABLE 4. Shutdown Control
Bit
Name
Value
Description
This enables or disables the device.
B0
PWR_ON
0
1
Device disabled
Device enabled
This enables or disables the Class G of the headphone.
B1
B2
B3
Class G_SD
HPR_SD
0
Class G enabled
1
Class G disabled
This disables the right headphone output.
0
1
Normal Operation
Right headphone disabled
This disables the gain amplifiers that are not in use to minimize IDD
.
GAMP_ON
0
1
Normal Operation
Disable unused gain amplifiers
13
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MODE CONTROL REGISTER
TABLE 5. Mode Control
Description
Bits
B3:B0 MODE_ This set the different mixer output modes.
CONTROL
Field
Mode Input (Diff/SE)* Input**
SPK
HP
0
LS
SD
HP(L)
SD
HP ( R )
SD
0
1
2
3
4
0
0
0
0
1
X
X
X
X
0
0
0
0
1
0
1
SD
GM X M
SD
GM X M
SD
1
GM X M
GM X M
SD
1
GM X M
GST X L1
GM X M
GST X R1
1
GST X
(L1 + R1)
5
1
0
1
0
SD
SD
GST X
(L1 + R1)
6
7
8
1
1
1
0
1
1
1
0
1
1
1
0
GST X L1
GST X L2
SD
GST X R1
GST X R2
SD
SD
GST X
(L2 + R2)
GST X
(L2 + R2)
9
1
1
1
1
GST X L2
GST X R2
B4
EP
This enables the receiver bypass path.
0
Normal output mode operation
Enable the receiver bypass path
1
*0: Differential, 1: Single-Ended
**0: Stereo 1CH, 1: Stereo 2CH
M: Mono differential input
R1/R2: Right channel stereo input
L1/L2: Left channel stereo input
SD: Shutdown
GM: Differential input gain path
GST: Single-Ended input path
VOLTAGE LIMIT CONTROL REGISTER
TABLE 6. Shutdown Control
Description
Bits
Field
B2:B0
VOLTAGE
LEVEL
This sets the output voltage limit level.
000
001
010
011
100
101
110
111
Voltage limit disabled
VTH(VLIM) = 4.0VP-P
VTH(VLIM) = 4.8VP-P
VTH(VLIM) = 5.6VP-P
VTH(VLIM) = 6.4VP-P
VTH(VLIM) = 7.2VP-P
VTH(VLIM) = 8.0VP-P
Voltage limit disabled
B4:B3
ATTACK_
TIME
This sets the attack time of the automatic limiter control circuit based on CSET = 0.1μF.
00
01
10
11
0.7ms
0.975ms
1.5ms
2.025ms
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NO CLIP CONTROL REGISTER
TABLE 7. No Clip Control
Description
OUTPUT_CLIP_ This sets the output voltage limit level.
Bits
Field
B2:B0
CONTROL
000
010
011
100
101
No Clip disabled, output clip control disabled
No Clip enabled, output clip control disabled
Low
Med
High
B4:B3
RELEASE_TIME This sets the release time of the automatic limiter control circuit.
00
01
10
11
1s
0.8s
0.65s
0.4s
GAIN CONTROL REGISTER
TABLE 8. Gain Control
Description
Bits
Field
B2:B0
HP_GAIN
This sets the headphone output gain level.
000
0dB
-1.5dB
-3dB
001
010
011
-6dB
100
-9dB
101
-12dB
-15dB
-18dB
110
111
B3
LS_GAIN
This sets the loudspeaker output gain level.
0
1
12dB
18dB
15
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VOLUME CONTROL REGISTER
TABLE 9. Volume Control
VOLUME
_G4
Stereo GAIN
(dB)
Mono GAIN
(dB)
_G3
_G2
_G1
_G0
STEP
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
-109
-46.5
-40.5
-34.5
-30
-27
-24
-21
-18
-15
-13.5
-12
-10.5
-9
-115
-52.5
-46.5
-40.5
-36
-33
-30
-27
-24
-21
-19.5
-18
-16.5
-15
-13.5
-12
-10.5
-9
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
-7.5
-6
-4.5
-3
-1.5
0
-7.5
-6
1.5
3
-4.5
-3
4.5
6
-1.5
0
7.5
9
1.5
3
10.5
12
4.5
6
13.5
15
7.5
9
16.5
18
10.5
12
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16
NOISE GATE CONTROL REGISTER
TABLE 10. Noise Gate Control
Description
This sets the noise gate attack and release time.
Bits
Field
B1:B0
NOISE_GATE_
TIME
00
0.9ms
0.9ms
0.1ms
0.1ms
1.2s
2.1s
1.2s
2.1s
01
10
11
B4:B3
NOISE_GATE_
LEVEL
This sets the noise gate trip level *
000
010
011
100
Noise gate disabled
Low — 26mVRMS
Medium — 40mVRMS
High — 60mVRMS
* Levels listed for Mono Inputs. Levels double with Stereo Inputs.
CLASS-G CONTROL REGISTER
TABLE 11. Class-G Control
This sets the Class G trip level and determines when the headphone rails switches.
B4:B3
CLASS_G_TRIP_
LEVEL
00
01
10
11
Highest Level Trip Point (Default)
High Level Trip Point
Medium Level Trip Point
Low Level Trip Point
OTHER CONTROL REGISTER
TABLE 12. Other Control
B0
B1
TURN_ON_TIME
SS_EN
This sets the turn on time.
0
Normal Turn On Time
Fast Turn On Time
1
This enables Spread Spectrum.
0
1
Spread Spectrum Disabled
Spread Spectrum Enabled
17
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DIFFERENTIAL AMPLIFIER EXPLANATION
a 300kHz center frequency, reducing the wideband spectral
content, improving EMI emission radiated by the speaker and
associated cables and traces. Where a fixed frequency class
D exhibits large amounts of spectral energy at multiples of the
switching frequency, the spread spectrum architecture
spreads that energy over a larger bandwidth. The cycle-to-
cycle variation of the switching period does not affect the
audio reproduction, efficiency, or PSRR. Set bit B0 (SS_EN)
of the SS CONTROL register to 1 to enable spread spectrum
mode.
The LM49153 features a differential input stage for the mono
inputs, which offers improved noise rejection compared to a
single-ended input amplifier. Because a differential input am-
plifier amplifies the difference between the two input signals,
any component common to both signals is cancelled. An ad-
ditional benefit of the differential input structure is the possible
elimination of the DC input blocking capacitors. Since the DC
component is common to both inputs, and thus cancelled by
the amplifier, the LM49153 can be used without input coupling
capacitors when configured with a differential input signal.
GROUND REFERENCE HEADPHONE AMPLIFIER
INPUT MIXER/MULTIPLEXER
The LM49153 features a low noise inverting charge pump that
generates an internal negative supply voltage. This allows the
headphone outputs to be biased about GND instead of a
nominal DC voltage, like traditional headphone amplifiers.
Because there is no DC component, the large DC blocking
capacitors (typically 220μF) are not necessary. The coupling
capacitors are replaced by two small ceramic charge pump
capacitors, saving board space and cost. Eliminating the out-
put coupling capacitors also improves low frequency re-
sponse. In traditional headphone amplifiers, the headphone
impedance and the output capacitor from a high-pass filter
that not only blocks the DC component of the output, but also
attenuates low frequencies, impacting the bass response.
Because the LM49153 does not require the output coupling
capacitors, the low frequency response of the device is not
degraded by external components. In addition to eliminating
the output coupling capacitors, the ground referenced output
nearly doubles the available dynamic range of the LM49153
headphone amplifiers when compared to a traditional head-
phone amplifier operating from the same supply voltage.
The LM49153 includes a comprehensive mixer multiplexer
controlled through the I2C interface. The mixer/multiplexer al-
lows any input combination to appear on any output of
LM49153. Multiple input paths can be selected simultane-
ously. Under these conditions, the selected inputs are mixed
together and output on the selected channel. Table 5 (MODE
CONTROL) shows how the input signals are mixed together
for each possible input selection.
SHUTDOWN FUNCTION
The LM49153 features the following shutdown controls: Bit
B4 (GAMP_ON) of the SHUTDOWN CONTROL register con-
trols the gain amplifiers. When GAMP_SD = 1, it disables the
gain amplifiers that are not in use. For example, in Modes 1,
4 and 5, the Mono inputs are in use, so the Left and Right
input gain amplifiers are disabled, causing the IDD to be min-
imized. Bit B0 (PWR_ON) of the SHUTDOWN CONTROL
register is the global shutdown control for the entire device.
Set PWR_ON = 0 for normal operation. PWR_ON = 1 over-
rides any other shutdown control bit.
EARPIECE (EP) BYPASS
CLASS D AMPLIFIER
When B4 of MODE_CONTROL register is set to 1, earpiece
amplifier is enabled and differential inputs are passed down
to speaker outputs. This in turn disables the class D amplifier.
he LM49153 features a mono class D audio power amplifier
with a filterless modulation scheme that reduces external
component count, conserving board space and reducing sys-
tem cost. With no signal applied, the outputs (LSOUT+ and
LSOUT-) switch between VDD and GND with 50% duty cycle,
in phase, causing the two outputs to cancel. This cancellation
results in no net voltage across the speaker, thus there is no
current to the load in the idle state.
AUTOMATIC LIMITER CONTROL (ALC)
When enabled, the ALC continuously monitors and adjusts
the gain of the loudspeaker amplifier signal path if necessary.
The ALC serves two functions: voltage limiter/speaker pro-
tection and output clip prevention (No-Clip) with three clip
controls levels. The voltage limiter/speaker protection pre-
vents an output overload condition by maintaining the loud-
speaker output signal below a preset amplitude (See voltage
Limiter section). The No Clip feature monitors the output sig-
nal and maintains audio quality by preventing the loudspeaker
output from exceeding the amplifier’s headroom (see No Clip/
Output Clip Control section). The voltage limiter thresholds,
clip control levels, attack and release times are configured
through the I2C interface.
With an input signal applied, the duty cycle (pulse width) of
the class D output changes. For increasing output voltage, the
duty cycle of LSOUT+ increases, while the duty cycle of
LSOUT- decreases. For decreasing output voltages, the con-
verse occurs. The difference between the two pulse widths
yields the differential output voltage.
ENHANCED EMISSION SUPPRESSION (E2S)
The LM49153 class D amplifier features National’s patent-
pending E2S system that reduces EMI, while maintaining high
quality audio reproduction and efficiency. The E2S system
features selectable spread spectrum and advanced edge rate
control (ERC). The LM49153 class D ERC greatly reduces
the high frequency components of the output square waves
by controlling the output rise and fall times, slowing the tran-
sitions to reduces RF emissions, while maximizing THD+N
and efficiency performance.
VOLTAGE LIMITER
The voltage limiter function of the ALC monitors and prevents
the audio signal from exceeding the voltage limit threshold
(). The voltage limit threshold (VTH(VLIM)) is set by bits B2:B0
in the Voltage Limit Threshold Register (see Table 6). Al-
though the ALC reduces the gain of the speaker path to
maintain the audio signal below the voltage limit threshold, it
is still possible to overdrive the speaker output in which case
loudspeaker output will exceed the voltage limit threshold and
cause clipping on the output, and speaker damage is possi-
ble. Please see the ALC Headroom section for further details.
SPREAD SPECTRUM
The selectable spread spectrum mode minimizes the need for
output filters, ferrite beads or chokes. In spread spectrum
mode, the switching frequency varies randomly by 30% about
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18
30121076
FIGURE 4. Voltage Limit Output Level
NO CLIP/OUTPUT CLIP CONTROL
though the ALC reduces the gain of the speaker path to
prevent output clipping, it is still possible to overdrive the
speaker output. Please see the ALC Headroom section for
further details.
The LM49153 No Clip circuitry detects when the loudspeaker
output is near clipping and reduces the signal gain to prevent
output clipping and preserve audio quality (Figure 5). Al-
30121077
FIGURE 5. No Clip Function
The LM49153 also features an output clip control that allows
a certain amount of clipping at the output in order to increase
the loudspeaker output power. The clip level is set by B2:B0
in the No Clip Control Register (see Table 7). The clip control
works by allowing the output to enter clipping before the ALC
turns on and maintains the output level. The clip control has
three levels: low, medium, and high. The low and high clip
level control settings give the lowest distortion and highest
distortion respectively on the output (see SHUTDOWN
FUNCTION). The actual output level of the device will depend
upon the supply voltage, and the output power will depend
upon the load impedance.
19
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30121078
FIGURE 6. Clip Control Levels
ALC HEADROOM
So in the case of 0 dB volume gain, audio input has to be less
than VDD for both voltage limiter or No clip settings.
When either voltage limiter or no clip is enabled, it is still pos-
sible to drive LM49153 into clipping by overdriving the input
volume stage of the signal path beyond its output dynamic
range. In this case, clipping occurs at the input volume stage,
and although ALC is active, the gain reduction will have no
effect on the output clipping. The maximum input that can
safely pass through the input volume stage can be calculated
by following formula:
When voltage limiter is enabled, ALC can reach its max at-
tenuation for lower voltage limit levels as shown in the Figure
8. Typically, after the ALC started working, with 6dB of audio
input change ALC is well within its regulation. Voltage limiter
Input headroom can be increased by switching to the
LS_GAIN to 18dB in the Gain Control Register (see Table
8).
(1)
30121080
FIGURE 7. Voltage Limiter Function
VDD = 3.3V, RL = 8Ω+30μH
fIN = 1kHz, LS_GAIN = 0
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20
30121081
FIGURE 8. No Clip Function
VDD = 3.3V, RL = 8Ω+30μH
fIN = 1kHz, LS_GAIN = 0
Gray, Yellow = THD+N vs Input Voltage
When No Clip is enabled, class D speaker output reduces
RELEASE TIME
when it’s about to enter clipping region and power stay con-
stant as long as VIN is less than VDD for 0dB volume gain (see
Figure 8). For example, in the case of VDD = 3.3V, there is a
6dB of headroom for the change in input. Please see the ALC
typical performance curves for additional plots relating to dif-
ferent supply voltages and LS_GAIN settings for specific
application parameters.
Release time (tRL) is the time it takes for the gain to return
from 6dB (LS_GAIN = 0) to its normal level once the audio
signal returns below the ALC threshold. A fast release time
allows the ALC to react quickly to transients, preserving the
original dynamics of the audio source. However, similar to a
fast attack time, a fast release time contributes to volume
pumping. A slow release time reduces the effect of volume
pumping. The release time is set by a combination of the value
of CSET and release time coefficient as given by equation (3):
ATTACK TIME
Attack time (tATK) is the time it takes for the gain to be reduced
by 6dB (LS_GAIN = 0) once the audio signal exceeds the ALC
threshold. Fast attack times allow the ALC to react quickly and
prevent transients such as symbol crashes from being dis-
torted. However, fast attack times can lead to volume pump-
ing, where the gain reduction and release becomes notice-
able, as the ALC cycles quickly. Slower attack times cause
the ALC to ignore the fast transients, and instead act upon
longer, louder passages. Selecting an attack time that is too
slow can lead to increased distortion in the case of the No Clip
function, and possible output overload conditions in the case
of the Voltage limiter. The attack time is set by a combination
of the value of CSET and the attack time coefficient as given
by equation (2):
tRL = 20MΩCSET / αRL (s)
(3)
where αRL is the release time coefficient (Table 11) set by bits
B4:B3 in the No Clip Control Register. The release time co-
efficient allows the user to set a nominal release time. The
internal 20MΩ is subject to temperature change, and it has
tolerance between -11% to +20%.
TABLE 14. Release Time Coefficient
B5
0
B4
0
αRL
2
0
1
2.5
3
tATK = 20kΩCSET / αATK
(2)
1
0
1
1
5
Where αATK is the attack time coefficient (Table 13) set by bits
B4:B3 in the Voltage Limit Control Register (see Table 6). The
attack time coefficient allows the user to set a nominal attack
time. The internal 20kΩ resistor is subject to temperature
change, and it has tolerance between -11% to +20%.
PROPER SELECTION OF EXTERNAL COMPONENTS
ALC Timing (CSET) Capacitor Selection
The recommended range value of CSET is between .01μF to
1μF. Lowering the value below .01μF can increase the attack
time but LM49153 ALC ability to regulate its output can be
disrupted and approaches the hard limiter circuit. This in turn
increases the THD+N and audio quality will be severely af-
fected.
TABLE 13. Attack Time Coefficient
B5
0
B4
0
αATK
2.667
2
0
1
Charge Pump Capacitor Selection
1
0
1.333
1
Use low ESR ceramic capacitors (less than 100mΩ) for opti-
mum performance.
1
1
21
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Charge Pump Flying Capacitor (C1)
DEMO BOARD GUIDELINES
The flying capacitor (C1) affects the load regulation and out-
put impedance of the charge pump. A C1 value that is too low
results in a loss of current drive, leading to a loss of amplifier
headroom. A higher valued C1 improves load regulation and
lowers charge pump output impedance to an extent. Above
2.2μF, the RDS(ON) of the charge pump switches and the ESR
of C1 and C2 dominate the output impedance. A lower value
capacitor can be used in systems with low maximum output
power requirements.
Introduction
The LM49153 demoboard is shown in Figure TBD.
Quick Start Guide:
1. Connect the one end of the USB cable to the PC that will
be used to control the demo board and the other end to J1 of
the LM49153 demo board.
2. Install the LM49153 I2C interface software.
3. Apply 2.7V to 5.5V to the header labeled VDD and apply
a ground connection to the header labeled GND above C5.
Charge Pump Hold Capacitor (C2)
4. Apply 1.7V to 2.0V to the header labeled HPVDD and ap-
ply a ground connection to the header labeled GND7.
The value and ESR of the hold capacitor (C2) directly affects
the ripple on CPVSS. Increasing the value of C2 reduces out-
put ripple. Decreasing the ESR of C2 reduces both output
ripple and charge pump output impedance. A lower value ca-
pacitor can be used in systems with low maximum output
power requirements.
5. Apply a mono differential signal or two single-ended sig-
nal to headers labeled INM-/INR1 and INM+/INL1. Then,
apply a single-ended signal to headers labeled INL2 and
INR2.
6. A) For class D speaker output, connect a speaker or load
(> = 4Ω) to LSOUT- and LSOUT+ header pins (a low pass
filter may be required for measurements).
Input Capacitor Selection
Input capacitors may be required for some applications, or
when the audio source is single-ended. Input capacitors block
the DC component of the audio signal, eliminating any conflict
between the DC component of the audio source and the bias
voltage of the LM49153. The input capacitors create a high-
pass filter with the input resistors RIN. The -3dB point of the
high-pass filter is found using Equation (1) below.
B) For headphone output, connect either through head-
phone output jack or HPR and HPL header pins.
7. Run the LM49153 I2C interface software, select desired
mode, set 0dB volume gain, and Power on options from the
GUI.
Board Features
The LM49153 demonstration board has all of the necessary
connections, using 100mil headers, to apply the power supply
voltage and the audio input signals. The Class D amplifier’s
output is available on 100mil headers. The Class AB
headphone’s amplified audio signal is available on both a
stereo headphone jack and 100 mil headers. The input and
output of the earpiece analog switch are also available on
100mil headers. On-board I2C signal generation microcon-
troller allows for a convenient connection via USB jack.
f = 1 / 2πRINCIN (Hz)
(4)
Where the value of RIN is given in the Electrical Characteris-
tics Table.
High-pass filtering the audio signal helps protect the speak-
ers. When the LM49153 is using a single-ended source,
power supply noise on the ground is seen as an input signal.
Setting the high-pass filter point above the power supply noise
frequencies, 217Hz in a GSM phone, for example, filters out
the noise such that it is not amplified and heard on the output.
Capacitors with a tolerance of 10% or better are recommend-
ed for impedance matching and improved CMRR and PSRR.
Connections
Headers/Jumpers
Description
Function/Use
Power supply connection. Connect an external power supply's positive voltage source to VDD and the
supply's ground source to GND header pins respectively.
VDD and GND
HPVDD and GND7
Headphone power supply connection. Connect an external power supply's positive voltage source to
HPVDD and the supply's ground source to GND7 header pins respectively.
These header pins provide a connection to a mono differential or stereo left and right single-ended
input.
INM+/INL1 and INM-/INR1
INL2 and INR2
EP+ and EP-
These header pins provide a connection to stereo left and right single-ended input.
These header pins provide a connection to the input of the earpiece bypass switch.
These header pins provide a connection to Class D loudspeaker outputs. Apply a load greater than
4Ω. A low pass filter may be required for measurements.
LSOUT- and LSOUT+
HPL and HPR
These header pins provide a connection to headphone outputs. Apply a load greater than 16Ω.
J1 provides a USB connection to control the LM49153.
Stereo headphone jack
J1
JU1
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22
Power Supply Sequencing
I2C Interface GUI Software
The LM49153 uses two power supply voltages, VDD for the
Class D and HPVDD for the Headphones. If using two sepa-
rate power supplies, apply VDD first before applying HPVDD to
ensure proper operation.
The LM49153 demo board has the I2C signal generation mi-
crocontroller integrated and will generate the address byte
and the data byte when used with the LM49153 GUI software
(see Figure 9).
30121091
FIGURE 9. GUI Software
Software Installation Instructions
3) The LM49153 Control Software installation will begin.
1) Unzip the LM49153 setup.zip file to a specified folder.
2) Run “LM49153 setup.msi” from the specified folder. If
prompted to install Microsoft framework 2.0, please proceed
to do so, internet connection may be required)
23
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Bill Of Materials
Item
1
Ref Designator
Part Description
LM49153EVAL PCB
LM49153TMEVAL IC
C8051F320
Manufacturer
National
Part Number
551600453-001 RevA
LM49153TM
Value
Footprint Qty
PCB
1
1
2
U1
National
3
U2
U3
Silicon Labs
National
C8051F320
LQFP-32
uSMD-4
LLP-6
603
1
1
4
LP5900
LP5900TL-1.8
5
U4
LP38691-ADJ
National
LP38691SD-ADJ
ECJ-1VB1A225K
TPSB106K016R0800
EMK316B7105KF-T
ECJ-3VB1C224K
JMK107BJ106MA-T
6
C1, C4, C6, C7, C13
C5
Ceramic Capacitor
Tantalum capacitor
Ceramic Capacitor
Ceramic Capacitor
Ceramic Capacitor
Ceramic Capacitor
Ceramic Capacitor
Ceramic Capacitor
Mini USB B Type
Panasonic
AVX
2.2uF
10uF
1uF
7
1
2
2
2
2
2
2
1
1
7
B Case
1206
1206
603
8
C9, C10
C11, C12
C14, C15
C16, C17
C3, C18, C20
C2, C8, C19, C21
J1
Taiyo Yuden
Panasonic
Taiyo Yuden
Kemet
9
0.22uF
10uF
10
11
12
13
14
15
C0603C474K4RACTU 0.47uF
603
Kemet
C0603C104J3RACTU
LMK107BJ475KA-T
UX60-MB-5ST
0.1uF
4.7uF
603
Taiyo Yuden
Hirose
603
JU1
5-pole Headphone Jack Switch Craft
35RAPC4BH3
FERRITE
CHIP 30
16
L1, L2
FERRITE
Murata
BLM21PG300SN1D OHM
3000MA
0805
10ohm
805
2
17
18
19
20
R1, R2
0603 Resistor
0603 Resistor
0603 Resistor
0603 Resistor
Panasonic
Vishay/Dale
Vishay/Dale
Vishay/Dale
ERJ-3EKF10R0V
603
603
603
603
2
4
1
1
R4, R5, R8, R9
R6
R7
EP+, EP-, EPOUT+,
EPOUT-, GND,
GND1, GND2, GND3,
GND4, GND5, GND6,
GND7, GND8, HPL,
HPR, HPVDD, INL2,
INM+/INL1, INM-/
INR1, INR2, VDD,
LSOUT+, LSOUT-,
JU3
21
2–pin 100 mil Jumper
AMP
87220–2
24
CONN HEADR
BRKWAY. 10003POS
STR
22
23
JU2, JU4, JU5
R3
TYCO
9–146285–0–03
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24
Demo Board Schematic Diagram
25
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Demo Board Layout
30121098
30121094
30121093
30121097
30121095
30121096
Top Layer
Top Silkscreen
Layer 2
Layer 3
Bottom Silkscreen
Bottom Layer
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26
Revision History
Rev
1.0
Date
Description
12/02/10
12/08/10
03/31/11
04/01/11
Initial WEB released.
Text edits.
1.01
1.02
1.03
Changed the Typical value on Xtalk from 68 to 78 (EC table).
Changed the Typical value on Xtalk from 78 to 80 (EC table).
27
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Physical Dimensions inches (millimeters) unless otherwise noted
micro SMD Package
Order Number LM49153TM
NS Package Number TMD25MSA
X1 = 2.30mm, X2 = 2.42mm, X3 = 0.6mm
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28
Notes
29
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Notes
For more National Semiconductor product information and proven design tools, visit the following Web sites at:
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