LM5023MM-2/NOPB [TI]
交流/直流准谐振电流模式 PWM 控制器 | DGK | 8 | -40 to 125;
| 型号： | LM5023MM-2/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 交流/直流准谐振电流模式 PWM 控制器 | DGK | 8 | -40 to 125 控制器 |
| 文件： | 总30页 (文件大小：2983K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SNVS961C –APRIL 2013–REVISED AUGUST 2013
AC-DC Quasi-Resonant Current Mode PWM Controller
1
FEATURES
APPLICATIONS
•
•
•
•
Critical Conduction Mode
•
Universal Input AC-DC Notebook Adapters 10
W to 65 W
Peak Current Mode Control Mode
•
High Efficiency Housekeeping and Auxiliary
Power
Skip Cycle Mode for Low Standby Power
Hiccup Mode for Continuous Overload
Protection
•
•
Battery Chargers
Consumer Electronics (DVD Players, Set-Top
Boxes, DTV, Gaming, Printers, etc)
•
Cycle-by-Cycle Over-Current Protection
Maintains Accuracy over the Universal AC
Line
DESCRIPTION
•
•
•
•
•
Line Current Feed Forward
The LM5023 is a Quasi-Resonant Pulse Width
Modulated (PWM) controller which contains all of the
features needed to implement a highly efficient off-
line power supply. The LM5023 uses the transformer
auxiliary winding for demagnetization detection to
ensure Critical Conduction Mode (CCM) operation.
The LM5023 features a hiccup mode for over current
protection with an auto restart to reduce the stress on
the power components during an overload. A skip
cycle mode which reduces power consumption at
light loads for energy conservation applications
(ENERGY STAR®, CEPCP, etc.). The LM5023 also
uses the transformer auxiliary winding for output
overvoltage (OVP) protection, if an OVP fault is
detected the LM5023 latches off the controller.
OVP Protection by Sensing the Aux Winding
Integrated 0.7 A Peak Gate Driver
Direct Opto-Coupler Interface
Leading Edge Blanking of Current Sense
Signal
•
•
•
•
Maximum Frequency Clamp 130 kHz
Programmable Soft Start
Thermal Shutdown
8-Pin MSOP Package
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
LM5023
SNVS961C –APRIL 2013–REVISED AUGUST 2013
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SIMPLIFIED SCHEMATIC
Vout
+19V
90-264 VAC
High
Voltage
Start-up
Depletion
Mode
QR
OUT
FET
VCC
CS
LM5023
Output
voltage
regulation
VSD
SS
COMP
GND
2
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SNVS961C –APRIL 2013–REVISED AUGUST 2013
PIN FUNCTIONS
NAME
NO.
TYPE
DESCRIPTION
Control input for the Pulse Width Modulator and Skip cycle comparators.
COMP pull-up is provided by an internal 42 K resistor which may be
used to bias an opto-coupler transistor.
COMP
4
I
Current sense input for current mode control and over-current protection.
Current limiting is accomplished using a dedicated current sense
comparator. If the CS comparator input exceeds 0.5 V, the OUT pin
switches low for cycle-by-cycle current limit. CS is held low for 90 ns
after OUT switches high to blank the leading edge current spike.
CS
5
I
GND
OUT
6
7
G
O
Ground connection return for internal circuits.
High current output to the external MOSFET gate input with source/sink
current capability of 0.3 A and 0.7 A respectively.
The auxiliary FLYBACK winding of the power transformer is monitored to
detect the Quasi-Resonant operation. The peak auxiliary voltage is
sensed to detect an output overvoltage (OVP) fault and shuts down the
controller.
QR
1
I
An external capacitor and an internal 22 µA current source sets the soft-
start ramp.
SS
3
2
8
O
O
P
Connect this pin to the Gate of the external start-up circuit FET; it will
disable the start-up FET after VCC is valid.
VSD
VCC
VCC provides bias to controller and gate drive sections of the LM5023.
An external capacitor must be connected from this pin to ground.
ABSOLUTE MAXIMUM RATINGS(1)(2)
over operating free-air temperature range (unless otherwise noted)
VALUE
MIN
UNIT
MAX
IQR
Negative Injection Current When the QR Pin is Being Driven Below
Ground
–
4
mA
VSD
IVSD
Maximum Voltage
–0.3
–
45
V
VSD Clamp Continuous Current
SS, COMP, QR
500
µA
Voltage
Range
–0.3
–0.3
–0.3
7
V
V
V
Voltage
Range
CS
1.25
OUT
Gate-Drive Voltage at DRV
Self-
limiting
IOUT
IOUT
VCC
TJ
Peak OUT Current, Source
–
–
0.3
0.7
16
A
A
Peak OUT Current Sink
Bias Supply Voltage
–0.3
–40
–55
V
Operating Junction Temperature Range
Storage Temperature
+125
+150
2
ºC
ºC
kV
kV
TSTG
ESD
Human Body Model (HBM) JESD22-A114
Charged-Device Model (CDM) JESD22-C101
1
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
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THERMAL CHARACTERISTICS
UNIT
θJA
MSOP-8 Junction to Ambient
107
°C/W
(1) The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS
MIN
MAX
14
UNIT
V
VCC
IVSD
IQR
Bias Supply Voltage
Current Sense
8
2
10
µA
mA
ºC
QR Pin Current
1
4
TJ
Junction Temperature
–40
125
ELECTRICAL CHARACTERISTICS
Minimum and Maximum apply over the junction temperature range of –40°C to +125°C. Minimum and maximum limits are
specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at +25°C,
and are provided for reference purposes only. Unless otherwise specified, the following conditions apply: VCC = 10 V, FSW
100 kHz 50% Duty Cycle, No Load on OUT.
=
PARAMETER
BIAS SUPPLY INPUT
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCCON
VCCOFF
VRST
Controller enable threshold
Minimum operating voltage
Internal logic reset (fault latch)
ICC current while in standby mode
Operating supply current
12
7.0
4.5
12.8
7.5
13.5
8.0
V
V
5.0
5.5
V
ICCST
ICCOP
COMP = 0.5V, CS = 0 V, no switching
COMP = 2.25 V, OUT switching
340
800
420
µA
µA
SHUTDOWN CONTROL (VSD pin)
IVSD OFF
Off state leakage current
0.1
0.65
0.84
µA
V
VVSD ON1
VVSD_ON2
SKIP CYCLE MODE COMPARATOR
ON state pull-down voltage at 10 uA
After VCCON (IVSD = 10 uA)
ON state pull-down voltage at 100 uA After VCCON (IVSD = 100 uA)
V
VSKIP
Skip cycle mode enable threshold
CS Rising
70
120
12
170
mV
mV
VSK-HYS
QR DETECT
VOVP
Skip cycle mode hysteresis
Overvoltage comparator threshold
Sample delay for OVP
VDEM demagnetization threshold
Maximum frequency
2.85
870
3
1050
0.35
130
12
3.17
V
ns
V
TOVP
1270
VDEM
FMAX
114
9.4
148
kHz
µs
TRST
TRESTART
15.7
PWM COMPARATORS
TPPWM
COMP to OUT delay
COMP set to 2 V CS stepped 0 to 0.4
V, time to OUT transition low, CLOAD
0
=
20
ns
%
DMIN
Minimum duty cycle
COMP = 0 V
I(COMP)=20µa
COMP = 0 V
0
GCOMP
VCOMP-O
VCOMP-H
ICOMP
COMP to PWM comparator gain
COMP open circuit voltage
COMP at maximum VCS
COMP short circuit current
R pull-up
0.33
4.9
4.3
5.8
V
V
2.25
132
45
µA
kΩ
RCOMP
41
49
CURRENT LIMIT
VCS Cycle-by-cycle sense voltage
450
500
550
mV
threshold
4
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SNVS961C –APRIL 2013–REVISED AUGUST 2013
ELECTRICAL CHARACTERISTICS (continued)
Minimum and Maximum apply over the junction temperature range of –40°C to +125°C. Minimum and maximum limits are
specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at +25°C,
and are provided for reference purposes only. Unless otherwise specified, the following conditions apply: VCC = 10 V, FSW
100 kHz 50% Duty Cycle, No Load on OUT.
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TLEB
TPCS
Leading edge blanking time
Current limit to OUT delay
130
ns
CS step from 0 to 0.6 V time to onset
of OUT transition low, CLOAD = 0
22
ns
RLEB
GCM
CFF
CS blanking sinking impedance
Current mirror gain
15
100
140
35
Ω
IQR = 2 ma
IQR = 2 ma
A/A
mV
Current feed forward
HICCUP MODE
TOL_10
Over load detection timer
Over load detection timer
IVSD= 10 uA
12
ms
ms
TOL_100
IVSD= 100 uA
1.2
OUTPUT GATE DRIVER
VOH
OUT high saturated
IOUT = 50 mA, VCC-OUT
IOUT = 100 mA
OUT = VCC/2
0.3
0.3
0.3
0.7
25
1.1
1
V
V
VOL
OUT low saturated
Peak OUT source current
Peak OUT sink current
Rise time
IPH
A
IPL
OUT = VCC/2
A
tr
CLOAD = 1 nF
ns
ns
tf
Fall time
CLOAD = 1 nF
15
SOFT-START
ISS
Soft-start
17
22
30
µA
ºC
THERMAL
TSD
Thermal shutdown temp
165
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FUNCTIONAL BLOCK DIAGRAM
VCC
IVSD
VSD
RVSD
OLDT
SET
CLR
S
Q
Q
OLDTS
R
4 Counter
VCC
VCCON 12.5V Rising
VCCMIN 7.5V Falling
SET
S
Q
Q
CLR
R
EN
-
SET
R
S
Q
+
VRST 5.0V
THERMAL
SHUTDOWN
CLR
Q
OVP
+
-
SET
tdlay
MAX
D
Q
Q
VOVP
3V
CLR
Frequency
clamp
TRESTART
QR
Demag
-
IQR
+
EN
VDEMAG 0.35V
IQR/100
OUT
GND
SET
CLR
Auto Zero Comp
+
S
Q
Q
R
-
OLDT OLDTS
VCS
6.6K
LEB
0.5V
CS
standby
S
Over Load
Detection Timer
4x60x10ꢀ9
IVSD
OLDTS
sec
PWM
+
5V
R
42k
COMP
-
2R
R
SLEEP MODE
standby
-
+
VSKIP
5V
22uA
+
-
SS
EN
6
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SNVS961C –APRIL 2013–REVISED AUGUST 2013
TYPICAL CHARACTERISTICS
7.6
7.55
7.5
14
13.5
13
7.45
7.4
12.5
12
7.35
7.3
11.5
11
7.25
7.2
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
C002
C001
TEMPERATURE (C)
TEMPERATURE (C)
Figure 1. VCCON vs. Temperature
Figure 2. VCCOFF vs. Temperature
5.1
5.05
5
400
390
380
370
360
350
340
330
320
310
300
4.95
4.9
4.85
4.8
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
C003
C004
TEMPERATURE (C)
TEMPERATURE (C)
Figure 3. VRST vs. Temperature
Figure 4. ICCST vs. Temperature
800
790
780
770
760
750
740
730
132
131
130
129
128
127
126
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
C005
C006
TEMPERATURE (C)
TEMPERATURE (C)
Figure 5. ICCOP vs. Temperature
Figure 6. FMAX vs. Temperature
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TYPICAL CHARACTERISTICS (continued)
550
540
530
520
510
500
490
480
470
460
450
-50
-25
0
25
50
75
100
125
C007
TEMPERATURE (C)
Figure 7. CS Threshold vs. Temperature
8
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SNVS961C –APRIL 2013–REVISED AUGUST 2013
FUNCTIONAL DESCRIPTION
The LM5023 is a Quasi-Resonant controller which contains all of the features needed to implement a highly
efficient off-line power supply. The LM5023 uses the transformer auxiliary winding for demagnetization detection
to ensure Quasi-Resonant operation (Valley-Switching) to minimize switching losses. For application that need to
meet the ENERGY STAR® low standby power requirements, the LM5023 features an extremely low lq current
(346 µA) and skip cycle mode which reduces power consumption at light loads. The LM5023 uses a feedback
signal from the output to provide a very accurate output voltage regulation <1%. To reduce overheating and
stress during a sustained overload conditions the LM5023 offers a hiccup mode for over current protection and
provides a current limit restart timer to disable the outputs and forcing a delayed restart (hiccup mode).
For offline start-up, an external Depletion Mode N Channel MOSFET can be used. This method is recommended
for applications where a very low standby power (<50 mW) is required. For application where a low standby
power is not as critical an enhancement mode, N Channel MOSFET can be used. If an OVP is detected on the
auxiliary winding (QR pin), the IC permanently latches off, requiring recycling of power to restart Additional
features include line-current-feed forward, pulse-by-pulse current limit, and a maximum frequency clamp of 130
kHz.
START-UP
Referring to Figure 8, when the AC rectified line voltage is applied to the bulk energy storage capacitor; the N
Channel Depletion Mode MOSFET is turned on and supplies the charging current to the VCC capacitor. When
the voltage on the VCC pin reaches 12.5 V typical, the PWM controller, soft-start circuit and gate driver are
enabled.
When the LM5023 is enabled and the OUT drive signal starts switching the Flyback MOSFET, energy is being
stored and then transferred from the transformer primary to the secondary windings. A bias winding, shown in
Figure 8, delivers energy to the VCC capacitor to sustain the voltage on the VCC pin. The voltage supplied from
the auxiliary winding should be within the range of 10 V to 14 V (where 16 V is the absolute maximum rating).
After reaching the VCCON threshold the LM5023 VSD open Drain output, which is pulled up to VCC during start-
up, goes low. This applies a negative Gate to Source voltage on the Depletion Mode MOSFET turning it off. This
disables the high voltage start-up circuit. The high voltage start-up circuit can be implemented in either of two
ways; the first is shown in Figure 8, which uses an N Channel Depletion Mode FET, the second is shown in
Figure 9, which uses an N Channel Enhancement Mode FET. The circuit using the Depletion Mode FET will
have the lowest standby power. The standby power consumption of the FET is the voltage across the start-up
FET multiplied by the Drain to Source Cutoff current with Gate negatively biased, this is typically 0.1 µA.
Standby Power of the Start-up FET calculation:
•
•
Vin = 230Vac
VCC = 10V
Vdcmax = 230Vac · 2 = 325Vdc
IDOFF = 0.1mA
•
•
•
, IDOFF is the Depletion MODE FETs leakage current
Pd = IDOFF · Vdcmax = 0.1uA · 325Vdc = 32.5mW
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90-264 VAC
High
Voltage
Start-up
Depletion
Mode
QR
OUT
FET
VCC
RVSD
CVCC
CS
LM5023
VSD
GND
Figure 8. Start-Up With a Depletion Mode FET
An alternative start-up circuit employs an Enhancement Mode FET with resistors connected from the rectified dc
bus to the Gate of the FET, Figure 9. After the input AC power is applied the Enhancement Mode FET supplies
the charging current to the VCC capacitor CVCC. After reaching the VCCON threshold the LM5023 VSD open
Drain output, which is pulled up to VCC during start-up, goes low. This grounds the Gate of the start-up MOSFET
turning it off. The start-up resistors are always in the circuit, therefore the standby power consumed will be higher
than if a Depletion Mode FET were used.
•
•
Vin = 230 Vac
VCC = 10 V
Vdcmax = 230Vac · 2 = 325Vdc
Rstart - up = 10MW
•
•
Vdc2
3252
PRe sistors =
=
Rstart - up 10MW
= 10.56mW
•
10
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SNVS961C –APRIL 2013–REVISED AUGUST 2013
RSTART-UP
90-264 VAC
High
Voltage
Start-up Enhancement
Mode FET
QR
VCC
OUT
CVCC
CS
LM5023
VSD
GND
Figure 9. Start-Up With an Enhancement Mode FET
Quasi Resonant Operation
A Quasi-Resonant controlled Flyback converter operates by storing energy in the transformers primary during the
MOSFETs on-time. During the on-time (TON) VIN is applied across the primary of the transformer. The primary
current starts out at zero and ramps towards a peak value (IPEAK). When the peak primary current reaches the
feedback compensation error voltage the PWM comparator resets the output drive, turning off the MOSFET. Due
to the phasing of the transformer, the output diode is reversed biased during the MOSFET on-time.
During the MOSFETs off time the output diode is forward biased and the stored energy in the transformer
primary inductor is transferred to the output. The voltage seen on the secondary inductor is VOUT plus the output
diodes forward voltage drop, VF. The current in the output inductor linearly decreases from IPEAK • Ns/Np to zero,
refer to Figure 11.
When the current in the secondary reaches zero, the transformer is demagnetized, and there is an open circuit
on the secondary, and with the primary MOSFET also turned off, there is an open on the primary. A resonant
circuit is formed between the transformers primary inductance and the MOSFET output capacitance. The
resonant frequency is calculated by:
Freq = 2gp LpgCOSS
During the resonant period the Drain voltage of the MOSFET will ring down towards ground, refer to Figure 10.
When the Drain voltage is at its minimum the Flyback MOSFET is turned back on. The point where the voltage is
at its minimum is calculated by:
td = p · Lp · COSS
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Transformer is
demagnetized
Figure 10. The Flyback Drain Voltage Waveform
Transformer demagnetization is detected by sensing the transformers auxiliary winding. When the transformer is
demagnetized the auxiliary winding voltage follows the Drain of the MOSFET and changes from Vout•Naux/Ns to
-Vin•Naux/Np. Internal to the LM5203 QR pin is a comparator with a 0.35 V reference. As the auxiliary winding
voltage falls below 0.35 V, the voltage is sensed and the comparator sets the PWM Flip-Flop turning on the
Flyback MOSFET. Figure 11 shows the QR Converter typical waveforms; the auxiliary winding voltage, primary,
and secondary current waveforms. It is possible to adjustable the delay on the auxiliary winding with a resistor
and external capacitor to ensures that the MOSFET switches when its Drain voltage is at its minimum, refer to
the schematic in Figure 13 and the section on Valley Switching for details. The benefits of QR operation are
reduced EMI, and turn-on switching losses.
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Naux
Vaux Vout x
Ns
0V
0.35V
The Auxillary
Winding voltage
Naux
Np
Vaux ꢀVinx
TOVP
The peak Primary Current
The peak Secondary Current
ton
toff
td
Tp
Figure 11. QR Converter Typical Waveforms
Quasi Resonant Operating Frequency
When the primary side Flyback MOSFET turns on, the current ramps up until the peak primary current exceeds
the feedback compensation error voltage. When this occurs the PWM comparator resets the output drive, turning
off the MOSFET. The current ramps up with a slope of:
Vin di
=
Lp dt
The tON time of the switch is calculated by:
Lp
ton =
·Ipk
Vin
When the primary side Flyback MOSFET is turned off, the energy stored in the primary inductance is transfer to
the secondary inductance, the off time to transfer all of the energy is:
n ·Lp
toff = Ipk ·
Vo + Vf
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The total switching period is:
Tp = ton + toff + tdly
The resonant circuit created by the transformer primary inductance and the MOSFETs output capacitance is the
tdly time, refer to Figure 11.
p
tdly = · Lp · COSS
1
Pout = ·Lp ·Ipk2 ·Freq · h
Combining equations:
1
Freq:=
é
ê
ê
2 ù
ú
é
ê
ù
ú
ng(Vo + Vf + Vin
Lpg2gPoutg
+ tdly
ú
ê
ú
é
ù
ù
)
û
û
é
hg Ving ng Vo + Vf
(
ë
ê
ë
ú
ë
ë
û
û
From inspection of the equations, it can be seen that the QR Flyback converter does not operate at a fixed
frequency. The frequency varies with the output load, input line voltage, or a combination of the two. In order to
keep LM5023 frequency below the EMI starting limit of 150 kHz per CISPR--22, the LM5023 has an internal
timer which prevents the output drive from restarting within 7.69 μs of the previous driver output (OUT) high to
low transition. This timer clamps the maximum switching frequency from exceeding 130 kHz (typical).
PWM Comparator
The PWM comparator compares the current sense signal with the loop error voltage from the COMP pin. The
COMP pin voltage is reduced by a fixed 0.75 V offset and then attenuated by a 3:1 resistor divider. The PWM
comparator input offset voltage is designed such that less than 0.75 V at the COMP pin will result in a zero duty
cycle at the controller output.
Soft-Start
The soft-start feature allows the power converter to gradually reach the initial steady state operating point,
thereby reducing start-up stresses and current surges. At power on, after the VCC reaches the VCCON threshold
an internal 22 μA current source charges an external capacitor connected to the SS pin. The capacitor voltage
will ramp up slowly and will limit the COMP pin voltage and the duty cycle of the output pulses.
Gate Driver
The LM5023 driver (OUT) was designed to drive the gate of an N Channel MOSFET and is capable of sourcing
a peak current of 0.4 A and sinking 0.7 A.
Skip Cycle Operation
During light load conditions, the efficiency of the switching power supply typically drops as the losses associated
with switching and operating bias currents of the converter become a significant percentage of the power
delivered to the load. The largest component of the power loss is the switching loss associated with the gate
driver and external MOSFET gate charge. Each PWM cycle consumes a finite amount of energy as the MOSFET
is turned on and then turned off. These switching losses are proportional to the frequency of operation.
To improve the light load efficiency the LM5023 enters a Skip Cycle mode during light load conditions. As the
output load is decreased, the COMP pin voltage is reduced by the voltage feedback loop to reduce the Flyback
converters peak primary current. Referring to the Block Diagram , the PWM comparator input tracks the COMP
pin voltage through a 0.75 V level shift circuit and a 3:1 resistor divider. As the COMP pin voltage falls, the input
to the PWM comparator falls proportionately. When the PWM comparator input falls to 125 mV, the Skip Cycle
comparator detects the light load condition and disables output pulses from the controller. The LM5023 also
reduces all internal bias currents, while in skip mode, to further reduce quiescent power. The controller continues
to skip switching cycles until the power supply output falls and the COMP pin voltage increases to demand more
output current. The number of cycles skipped will depend on the load and the response time of the frequency
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voltage loop compensation network. Eventually the COMP voltage will increase when the voltage loop requires
more current to sustain the regulated output voltage. When the PWM comparator input exceeds 135 mV (10 mV
hysteresis), normal fixed frequency switching resumes. Typical light load operation power supply designs will
produce a short burst of output pulses followed by a long skip cycle interval (no drive pulses). The result is a
large reduction in the average input power.
Current Limit/Current Sense
The LM5023 provides a cycle-by-cycle over current protection feature. Current limit is triggered by an internal
current sense comparator with a threshold of 500 mV. If the CS pin voltage plus the current limit feed forward
signal voltage exceeds 500 mV, the MOSFET drive signal (OUT) will be terminated. An RC filter, located near
the LM5023 CS pin is recommended to attenuate the noise coupled from the power FET’s gate to source
switching. The CS pin capacitance is discharged at the end of each PWM cycle by an internal switch. The
discharge switch remains on for an additional 90 ns for Leading Edge Blanking (LEB). LEB prevents the LM5023
current sense comparator from being falsely triggered due to the noise generated by the switch currents initial
spike. The LM5023 current sense comparator is very fast, and may respond to short duration noise pulses.
Layout considerations are critical for the current sense filter and sense resistor. The capacitor associated with the
CS filter must be placed very close to the device and connected directly to the pins of the IC (CS and GND). If a
current sense transformer is used, both leads of the transformer secondary should be routed to the sense
resistor, which should also be located close to the IC. If a current sense resistor located in the power FET’s
source is used for current sense, a low inductance resistor is required. In this case, all of the noise sensitive low
current grounds should be connected in common near the IC and then a single connection should be made.
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APPLICATION INFORMATION
Line Current Limit Feed Forward
In a peak current mode controlled when the power supply is in an overload, the peak current (measured across
the current sense resistor VCS) is compared to a voltage reference for overload protection. If the peak current
exceeds the reference the LM5023 controller will turn off the primary side Flyback MOSFET on a cycle-by-cycle
basIs. However, the primary switch can’t be turned off instantly, as there are several unavoidable delays. The
first delay is caused by the LEB circuit which provides leading-edge blanking. The second delay is caused by the
propagation delay between the detecting point of VCS and the actual turn off of the power MOSFET. The total
delay time (tprop) refer to Figure 12, includes the current limit comparator, the logic, the gate driver, and the
power MOSFET turning off.
The propagation delay causes the peak primary current to overshoot, the overshoot increase the maximum peak
current beyond the calculated value. The peak current overshoot increase as the AC line voltage increase
because of the increase in the slope of the primary current:
Vin
di
=
Lp tprop
This increase in the peak input current overshoot causes a wide variation of overpower limit in a Flyback
converter. In Figure 4, it can be seen that the overpower limit increases with the input line voltage, because of
Ipkmax increase:
Pout · 2
Vin
Ipkmax =
+
Lp ·Freq · h Lp
· tprop
1
Pin = ·Ipk max ·Lp ·Freq
2
Pin
Pout =
h
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Vin
Lp
'IHL
High Line
'ILL
Ipk/Rsense
Low Line
tpropHL
Gate
Drive
tpropLL
Figure 12. Line Current Feed Forward
To improve the overpower limit accuracy over the full Universal Input Line; the LM5023 integrates Line Current
Limit Feed Forward. Line Current Limit Feed Forward improve the overpower limit by summing a current
proportional to the input rectified line into the current sense resistor RSENSE), refer to Figure 13. The current
proportional to the input line biases up the current sense pin, this turns off the Flyback MOSFET earlier at high
input line. This feature compensates for the propagation delays creating a overpower protection that is nearly
constant over the Universal Input Line.
To implement Line Current Limit Feed Forward, the first step is to calculate the QR switching frequency at low
line and then at high line when the power supply is operating in current limit.
For our example:
•
•
•
•
•
•
Lp = 400 µH
RSENSE = 0.15 Ω
Vdcmin = 127 V
Vdcmax = 325 V
Tprop = 160 ns
VCS = 0.5 V
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•
•
•
naux = 10.9
n = ns/np = .167
tdly = 580 ns
1
Freq_LL =
Freq_LL =
Freq_HL =
Freq_HL =
é
ù
VCS
1
1
æ
ö
æ
ö
·Lp ·
+
+ tdly
ç
÷
êç
÷
ú
Rsense
Vdc min
(Vout + Vf) ·n
è
ø
è
ø
ë
û
1
= 49.6kHz
é
ù
0.5V
1
1
æ
ö
æ
ö
· 400mH·
+
+ 580ns
ç
è
÷
ø
êç
÷
ø
ú
0.15W
127V
(19V + 0.7V) · 6
è
ë
û
1
1
é
ù
VCS
1
æ
ö
æ
ö
·Lp ·
+
+ tdly
ç
÷
êç
÷
ú
Rsense
Vdc max
(Vout + Vf) · 6
è
ø
è
ø
ë
û
1
= 62.3kHz
é
ù
ú
0.5V
1
1
æ
ö
æ
ö
· 400mH·
+
+ 580ns
ç
è
÷
ø
êç
÷
ø
0.15W
325V
(19V + 0.7V) · 6
û
è
ë
The next step is to calculate the uncompensated output power at the minimum and maximum input line voltage
while in current limit.
1
VCS
æ
ö2
Pout _LL = ·Lp ·
·Freq_LL · h
ç
÷
2
Rsense
è
ø
1
0.5
æ
ö2
Pout _LL = · 400mH·
· 49.6kHz · 0.86 = 94.9W
ç
÷
2
0.15
è
ø
1
VCS
æ
ö2
Pout _HL = gLpg
gFreq_HLgh
ç
è
÷
2
Rsense
ø
1
0.5
æ
ö2
Pout _HL = g400mHg
g62.3kHzg0.86 = 119.1W
ç
÷
2
0.15
è
ø
Step three is to calculate the peak current at high line so it does not deliver more power than while it is operating
at low line (94.9 W). One thing that complicates the Line Current Limit Feed Forward calculation is that with
Quasi Resonant operation the switching frequency changes with line and load. We have one equation and two
unknowns, the peak primary current and the QR frequency. This requires use of the quadratic equation:
ax2 + Bx + C = 0
The positive root is:
B + B2 + 4DT
)
(
X =
4
4
Freq_ Comp =
é
ê
ê
ê
ê
ù2
ú
Pout _LL
2 ·Lp · Vout + Vf + n · Vdcmax·
Vdcmax· (Vout + Vf)
æ
ç
ö
÷
2 ·Lp ·Pout _LL · (Vout + Vf + n · Vdcmax)2
h ·Lp
ú
4 · tdly +
+
2
h · Vdcmax2 · Vout + Vf
ú
ç
÷
(
)
è
ø
ú
ê
ú
ë
û
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4
Freq_ Comp =
= 76.8kHz
é
ê
ê
ê
ê
ù2
94.9W
2 · 400mH· (19V + 0.7V + 0.167 · 325V) ·
ú
ú
ú
ú
æ
ç
ö
÷
2 · 400mH· 94.9 · (19 + 0.7 + 0.167 · 325V)2
0.86 · 400mH
4 · 580ns +
+
2
0.86 · 325V2 · 19V + 0.7V
ç
÷
325V · (19V + 0.7V)
(
)
è
ø
ê
ú
ë
û
Step four is to calculate the peak current.
2 ·Pout _LL
ILmax_LL =
h ·Lp ·Freq_ Comp
2 · 94.9W
ILmax_LL =
= 2.679Apk
0.86 · 400mH· 76.8kHz
é
ù
ú
û
æ
ö
Vdcmax
Lp
VCS _ CL = Rsense · ILmax_ CL -
· tprop
ê
ç
÷
è
ø
ë
é
ù
æ
ç
è
ö
÷
ø
325V
VCS _ CL = 0.15W · 2.679Apk -
·160ns = 0.382V
ê
ú
400mH
ë
û
For the power supply to go into pulse-by-pulse current limit the voltage across the current sense resistor must be
0.5 V, so:
VCS _ OFFSET := VCS - VCS _ CL
VCS_OFFSET is the required voltage offset that must be injected across the current sense resistor, RSENSE
.
VCS _ OFFSET := VCS - VCS _ CL = 0.5V - 0.382V = 0.118V
After calculating the required offset voltage, use the following equations to calculate the required current feed
forward:
While the main Flyback switch is on, Q1, the voltage on the Auxiliary winding will be negative and proportional to
the rectified line.
Vdc
-Vaux =
Naux
-Vaux
IQR =
ROFFSET
IQR should be chosen in the range of 1 ma to 4 ma. The demagnetization circuit impedance should be
calculated to limit the maximum current flowing through Pin 1 to less than 4 mA.
ROFFSET = 6.6 kΩ + REXTERNAL (the 6.6 kΩ resistance is internal to the LM5023).
Where: Naux is the number of turns on the Flyback primary (Np) divided by the number of turns on the
transformer Auxiliary (Naux) winding. The current mirror in the QR pin input has a gain of 100; this will offset the
voltage on the current sense pin by:
IQR
VCSOFFSET =
· 6.6kW + REXTERNAL
(
)
100
Set IQR= 1.75 mA
Vdcmax
naux
325V
= 17.0kW
10.9
R1 =
=
IQR
1.75mA
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VOFFSET
IQR
0.118V
ROFFSET =
·100 =
·100 = 6742W
1.75mA
ROFFSET = RINTERNAL + REXTERNAL
REXTERNAL = ROFFSET - 6.6kW = 6742W - 6.6kW = 142W
No external resistor is required based on the applications describe above, so a 499 Ω resistor and 100 pF
capacitor are installed in the CS pin input as a noise filter.
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VCC+VD
0V
-Vdc/naux
Vaux
Np
Ns
Naux
R1
R2
RCFF=R1//R2
Cd
Vaux
IQR
QR
VCC
OUT
CS
Q1
REXTERNAL
1k
IQR/100
Rsense
VCSOFFSET
LM5023
GND
Figure 13. Current Feed Forward
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Overvoltage Protection
Output overvoltage protection is implemented with the LM5023 by monitoring the QR pin during the time when
the main Flyback MOSFET is off and the energy stored in the transformer primary is being transferred to the
secondary. There is a delay prior to sampling the QR pin during the MOSFETs off time, TOVP. There are two
reasons for the delay, the first is to blank the voltage spike which is a result of the transformers leakage
inductance. The second is to improve the accuracy of the output voltage sensing, referring to the transformer
auxiliary winding voltage shown in Figure 11. It is clear there is a down slope in the voltage which represents the
decreasing VF of the output rectifier and resistance voltage drop (IS x RS) as the secondary current decreases
to zero, so by delaying the sampling of the QR voltage a more accurate representation of the output voltage is
achieved.
Connected to the QR pin is a comparator with a 3.0 V reference. The transformers auxiliary voltage is
proportional to Vout by the transformers turns ratio:
Vaux=(VO+VF)·Naux/Ns
(1)
To set the OVP, a voltage divider is connected to the transformers auxiliary winding, refer to Figure 12. In the
section titled Line Current Limit Feed Forward, we developed equations to improve the power limit. Resistor R1
was calculated for Line Current Limit Feed Forward; to implement OVP we now need to calculate R2.
R2
VOVP = Vaux _ OVP ·
+
R1
R2 = 3.0V ·
Vaux _ OVP - 3V
When an OVP fault has been detected, the LM5023 OUT driver is latched-off. VCC will discharge to VCCMIN
and the VSD pin will be asserted high, allowing the Depletion Mode FET to turn-on and charge up the VCC
capacitor to VCCON. The VSD pin will be toggled on-off-on to maintain VCC to the controller. The only way to
clear the fault is to removed the input power and allow the controllers VCC voltage to drop below VRST, 5.0 V.
Valley Switching
For QR operation the Flyback MOSFET is turned on with the minimum Drain voltage. The delay on the auxiliary
winding can be adjusted with an external resistor and capacitor to improve valley switching. The delay-time, tdly,
must equal half of the natural oscillation period:
p
tdly = · Lp · COSS
By substituting
tdly = RFF · Cd
We can calculate the RC time constant to achieve the minimum Drain voltage when the LM5023 turns on the
Flyback MOSFET.
é
ù
p
æ ö
g Lpused gCoss
êç ÷
ú
2
è ø
ë
û
Cd:=
The LM5023 QR pin’s capacitance is approximately 20 pF, so CdUSED = Cd -20 pF
R1gR2
(
)
RFF :=
R1+ R2
(
)
R1 and R2 were previously calculated to set the Line Current Limit Feed Forward and Overvoltage protection.
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Hiccup Mode
Hiccup Mode is a method to prevent the power supply from over-heating during and extended overload condition.
In an overload fault, the current limit comparator turns off the driver output on pulse-by-pulse basis. This starts
the Over Load Detection Timer, after the Over Load Detection Timer (OLDT) times out, the current limit
comparator is rechecked, if the power supply is still in an overload condition, the OUT drive is Latched-off and
VCC is allowed to drop to VCCOFF (7.5 V).
When VCC reaches VCCOFF, the VSD open drain output is disabled allowing the Depletion Mode start-up FET to
turn-on, charging up the VCC capacitor to VCCON (12.5 V). When VCC reaches VCCON, the VSD output goes
low turning-off the Depletion Mode FET. The VCC capacitor is discharged from VCCON to VCCOFF at a rate
proportional to the VCC capacitor and the ICCST current (346 µA typical). The charging and discharging of the
VCC capacitor is repeated four times (refer to Figure 14) so the total Hiccup time is:
tHICCUP = tCHARGE · 4 + tDISCHARGE · 4
After allowing VCC to charge and discharge four times, the LM5023 goes through an auto restart sequence,
enabling the LM5023 soft-start and driver output. It is important to set the Over Load Detection Timer long
enough so that under low input line and full load conditions that the power supply will have enough time to start-
up.
The Over Load Detection Timer can be set with the resister in series with the VSD pin ®VSD), refer to Figure 8.
VCC 10V
=
RVSD 1M
IVSD =
= 10mA
2 · 60nA 2 · 60nA
=
OVER _Load_Detection _ Timer =
= 12msec
IVSD
10mA
Normally it is recommended that RVSD>1 MΩ, if a lower value is used then the standby power will be higher.
Assuming:
If
the
Depletion
Mode
FET
charges
the
VCC
capacitor
with
2
mA,
VCC Capacitor is 10 uF.
VCCON - VCCOFF
(
tCHARGE =
ICHARGE
)
12.5V-7.5V
· CVCC =
· 10nF = 25ms
2mA
VCCON - VCCOFF
(
)
12.5V-7.5V
346mA
tDISCHARGE =
· CVCC =
· 10mF = 145ms
ICCST
tHICCUP = 25ms · 4 +145ms · 4 = 680ms
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The Depeletion FET charging
current into the VCC cap 2mA
The current comsumption of the LM5023 while the
OCP Flag is set ICCST=346uA
VCCON 12.5V
VCCAUX 10V
VCCOFF 7.5V
OLDTS
OUT
VSD
SS
25ms
145ms
Hicup Mode
Figure 14. Hiccup Mode Timing
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EVALUATION BOARD SCHEMATIC
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PACKAGE OPTION ADDENDUM
www.ti.com
15-Aug-2013
PACKAGING INFORMATION
Orderable Device
LM5023MM-2/NOPB
LM5023MMX-2/NOPB
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE
VSSOP
VSSOP
DGK
8
8
1000
Green (RoHS
& no Sb/Br)
CU SN
CU SN
Level-1-260C-UNLIM
SK9B
SK9B
ACTIVE
DGK
3500
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
-40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Aug-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5023MM-2/NOPB
LM5023MMX-2/NOPB
VSSOP
VSSOP
DGK
DGK
8
8
1000
3500
178.0
330.0
12.4
12.4
5.3
5.3
3.4
3.4
1.4
1.4
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Aug-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LM5023MM-2/NOPB
LM5023MMX-2/NOPB
VSSOP
VSSOP
DGK
DGK
8
8
1000
3500
210.0
367.0
185.0
367.0
35.0
35.0
Pack Materials-Page 2
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相关型号：
LM5025AMTCX/NOPB
IC 3 A SWITCHING CONTROLLER, 650 kHz SWITCHING FREQ-MAX, PDSO16, TSSOP-16, Switching Regulator or Controller
NSC
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