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LM5140-Q1

ZHCSEI6 –JANUARY 2016

LM5140-Q1 具有宽输入范围的双路同步降压控制器

1 特性

2 应用

1

•

符合 AEC-Q100 1 级标准

（T_A= -40ºC 至 125ºC）

•

汽车电子产品

信息娱乐系统

输入工作电压范围为 3.8V 至 65V（最高绝对电压

为 70V）

仪表板

高级驾驶员辅助系统 (ADAS)

两个具有以下电压特性的交错式降压控制器：

3 说明

–

VOUT1：3.3V、5V 固定电压或 1.5V 至 15V

可调节电压，精度为 ±1%

LM5140-Q1 是一款双路同步降压控制器，用于高电

压、宽 V_IN降压转换器应用. 此控制方法基于电流模式

控制。电流模式控制可提供固有线路前馈、逐周期电流

限制和简化的环路补偿。

–

VOUT2：5V、8V 固定电压或 1.5V 至 15V

可调节电压，精度为 ±1%

•

2.2MHz 或 440kHz 固定开关频率，精度为 ±7%

可选择与外部时钟保持同步

LM5140-Q1 具有可调节转换率控制功能，能够简化

CISPR 和汽车级电磁干扰 (EMI) 要求的合规性。

LM5140-Q1 可在 2.2MHz 或 440kHz 的可选开关频率

下运行，两条控制器通道发生 180º 出相。在轻负载或

无负载条件下，LM5140-Q1 通过在跳周期模式下运行

来提升低功耗效率。LM5140-Q1 具备一个自动切换至

外部偏置电源的高电压偏置稳压器，能够提升效率并降

低输入电流。其他功能包括频率同步、逐周期电流限

制、针对持续过载条件的断续模式保护、独立的电源正

常输出以及独立的使能输入。

用于附加转换器的 SYNC 输出时钟

关断模式电流：9µA（典型值）

无负载待机电流：35µA（典型值）（单通道运行）

电流限值阈值可编程为 50mV 或 75mV，精度为

±10%

•

用于 VOUT1 和 VOUT2 的独立使能输入

针对持续过载条件的断续模式保护

独立的电源正常输出

具有可调节转换率控制的高侧和低侧栅极驱动器

在轻负载条件下可选择二极管仿真或连续导通

具有可湿性侧面的超薄型四方扁平无引线 (VQFN)-

40 封装

器件信息⁽¹⁾

器件型号

LM5140-Q1

封装

VQFN (40)

封装尺寸（标称值）

6.00mm x 6.00mm

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

4 简化电路原理图

VIN

VCC

HB1

HB2

HO2

HO1

HOL1

VOUT2

HOL2

VOUT1

SW1

SW2

LO1

LO2

LOL2

LOL1

PGND1

PG1

PGND2

LM5140-Q1

EN2

VIN

EN1

VIN

PG2

ILSET

VCC

SYNOUT

CS1

VOUT1

CS2

VOUT2

VCCX

SYNIN

COMP1

COMP2

FB2

VCC

FB1

VCC

OSC AGND SS1 RES SS2 DEMB VDDA

VCC

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SNVSA02

LM5140-Q1

ZHCSEI6 –JANUARY 2016

www.ti.com.cn

8.3 Feature Description................................................. 15

8.4 Device Functional Modes........................................ 22

Application and Implementation ........................ 25

9.1 Application Information............................................ 25

9.2 Typical Application ................................................. 25

1

2

3

4

5

6

7

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

简化电路原理图........................................................ 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings.............................................................. 5

7.3 Recommended Operating Conditions....................... 6

7.4 Thermal Information.................................................. 6

7.5 Electrical Characteristics........................................... 7

7.6 Switching Characteristics.......................................... 9

7.7 Typical Characteristics............................................ 10

Detailed Description ............................................ 13

8.1 Overview ................................................................. 13

8.2 Functional Block Diagram ....................................... 14

9

10 Power Supply Recommendations ..................... 37

11 Layout................................................................... 38

11.1 Layout Procedure.................................................. 38

11.2 Layout Example .................................................... 38

12 器件和文档支持 ..................................................... 42

12.1 器件支持 ............................................................... 42

12.2 社区资源................................................................ 42

12.3 商标....................................................................... 42

12.4 静电放电警告......................................................... 42

12.5 Glossary................................................................ 42

13 机械、封装和可订购信息....................................... 42

8

5 修订历史记录

日期

修订版本

注释

2016 年 1 月

*

最初发布版本。

2

LM5140-Q1

www.ti.com.cn

ZHCSEI6 –JANUARY 2016

6 Pin Configuration and Functions

RWG Package

40 Pin VQFN

Top View

37

36

35

34

33

40

39

38

32

31

1

SS2

30

29

SS1

2

3

4

COMP2

FB2

COMP1

FB1

28

27

CS2

CS1

5

6

VOUT2

VCCX

26

25

VOUT1

VIN

Exposed Pad on Bottom

Connect to Ground

PG2

7

8

24

23

PG1

HOL2

HOL1

HO2

SW2

9

22

21

HO1

SW1

10

20

11

12

13

14

15

16

17

18

19

Connect Exposed Pad on bottom to AGND and PGND on the PCB.

Pin Functions

I/O

DESCRIPTION

NAME

SS2

NO.

Channel 2 soft-start programming pin. An external capacitor and an internal 20-μA current

source set the ramp rate of the internal error amplifier reference during soft-start. Pulling SS

pin below 80mV turns-off the channel 2 gate driver outputs, but all the other functions remain

active.

1

2

3

I

O

I

COMP2

FB2

Output of the channel 2 transconductance error amplifier.

Feedback input of channel 2. Connect the FB2 pin to VDD for a 5 V output or connect FB2 to

ground for a fixed 8V output. A resistive divider from the VOUT2 to the FB2 pin sets the

output voltage level between 1.5 V and 15 V. The regulation threshold at the FB2 pin is 1.2

V.

Channel 2 current sense amplifier input. Make a low current Kelvin connection between this

pin and the inductor side of the external current sense resistor.

CS2

4

5

6

I

Output and the current sense amplifier input of channel 2 . Connect this pin to the output

side of the channel 2 current sense resistor.

VOUT2

VCCX

Optional input for an external bias supply. If VCCX > 4.5 V, VCCX is internally connected to

VCC and the internal VCC regulator is disabled. If VCCX is unused, it should be grounded.

PG2

7

8

9

O

An open collector output which goes low if VOUT2 is outside a specified regulation window.

Channel 2 high-side gate driver turn-off output.

HOL2

HO2

Channel 2 high-side gate driver turn-on output.

Switching node of the channel 2 buck regulator. Connect to the bootstrap capacitor, the

source terminal of the high-side MOSFET and the drain terminal of the low-side MOSFET.

SW2

10

I

HB2

11

12

13

14

O

G

Channel 2 high-side driver supply for bootstrap gate drive.

Channel 2 low-side gate driver turn-off output.

LOL2

LO2

Channel 2 low-side gate driver turn-on output.

PGND2

Power ground connection pin for low-side NMOS gate driver.

3

LM5140-Q1

ZHCSEI6 –JANUARY 2016

www.ti.com.cn

Pin Functions (continued)

I/O

DESCRIPTION

NAME

VCC

NO.

15

16

17

18

19

20

P

VCC bias supply pin. Pin 15 and pin 16 must to be connected together on the PCB.

Power ground connection pin for low-side NMOS gate driver.

Channel 1 low-side gate driver turn-on output.

VCC

PGND1

LO1

G

O

LOL1

HB1

Channel 1 low-side gate driver turn-off output.

Channel 1 high-side driver supply for bootstrap gate drive.

Switching node of the channel 1 buck regulator. Connect to the bootstrap capacitor, the

source terminal of the high-side MOSFET and the drain terminal of the low-side MOSFET.

SW1

21

I

HO1

HOL1

PG1

VIN

22

23

24

25

O

P

Channel 1 high-side gate driver turn-on output

Channel 1 high-side gate driver turn-off output.

An open collector output which goes low if VOUT1 is outside a specified regulation window.

Supply voltage input source for the VCC regulators.

VOUT1 and current sense amplifier input of channel 1. Connect to the output side of the

channel 1 current sense resistor.

VOUT1

CS1

26

27

I

Channel 1 current sense amplifier input. Make a low current Kelvin connection between this

pin and the inductor side of the external current sense resistor.

Feedback input of channel 1. Connect the FB1 pin to VDDA for a 3.3-V output or connect

FB1 to ground for a 5-V output. A resistive divider from the VOUT1 to the FB1 pin sets the

output voltage level between 1.5 V and 15 V. The regulation threshold at the FB1 pin is 1.2

V.

FB1

28

29

30

31

I

O

I

COMP1

SS1

Output of the channel 1 transconductance error amplifier.

Channel 2 soft-start programming pin. An external capacitor and an internal 20μA current

source set the ramp rate of the internal error amplifier reference during soft-start. Pulling SS

pin below 80mV turns-off the channel 1 gate driver outputs, but the all the other function

remain active.

EN1

I

An active high logic input enables channel 1.

Restart timer pin. An external capacitor configures the hiccup mode current limiting. The

capacitor at the RES pin determines the time the controller will remain off before

automatically restarting in hiccup mode. The two regulator channels operate independently.

One channel may operate in normal mode while the other is in hiccup mode overload

protection. The hiccup mode commences when either channel experiences 512 consecutive

PWM cycles with cycle-by-cycle current limiting. Connect the RES pin to VDD during power

up to disable hiccup mode protection.

RES

32

O

Diode Emulation pin. If the DEMB pin is grounded, diode emulation is enabled. If it is

connected to VDDA the LM5140-Q1 operates in FPWM mode with continuous conduction at

light loads.

DEMB

ILSET

33

34

I

Current Limit Threshold pin. Connecting the ILSET pin to VDDA sets the current limit

threshold to 73 mV for channel 1 and channel 2.

Connecting the ILSET pin to GND sets the current limit thresholds to 48 mV.

Analog ground connection. Ground return for the internal voltage reference and analog

circuits.

AGND

VDDA

OSC

35

36

37

G

P

I

Internal analog bias regulator output. Connect a capacitor from the VDDA pin the AGND.

Frequency selection pin. Connecting the OSC pin to VDDA selects the default oscillator

frequency of 2.2 MHz. Connecting the OSC pin to ground sets frequency to 440 kHz.

Sync input pin. The internal oscillator can be synchronized to an external clock. If the

synchronization feature is not used, the SYNIN pin should be connected to AGND.

SYNIN

38

I

Sync output pin. The TTL level output signal is 180º out of phase with the HO1 gate drive of

channel 1.

SYNOUT

EN2

39

40

O

I

An active high logic input enables channel 2.

4

LM5140-Q1

www.ti.com.cn

ZHCSEI6 –JANUARY 2016

7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

-0.3

-5

MAX

UNIT

V

VIN

70

SW1,SW2 to PGND

V

SW1, SW2 to PGND (20ns transient)

HB1 to SW1, HB2 to SW2

V

-0.3

-5

6.5

V

HB1 to SW1, HB2 to SW2 (20ns transient)

HO1 to SW1, HOL1 to SW1, HO2 to SW2, HOL2 to SW2

V

-0.3

-5

HB + 0.3

V

HO1 to SW1, HOL1 to SW1, HO2 to SW2, HOL2 to SW2 (20ns transient)

V

Input voltage

LO1, LOL1, LO2, LOL2 to PGND

-0.3

-1.5

-0.3

VCC + 0.3

VDDA + 0.3

70

V

LO1, LOL1, LO2, LOL2 to PGND ( 20ns transient)

OSC, SS1, SS2, COMP1, COMP2, RES, DEMB, ILSET

EN1, EN2 to PGND

V

VCC, VCCX, VDDA, PG1, PG2, FB1, FB2, SYNIN

VOUT1, VOUT2, CS1, CS2

6.5

V

15.5

V

VOUT1 to CS1, VOUT2 to CS2

0.3

V

PGND to

AGND

-0.3

0.3

V

Operating Junction Temperature⁽²⁾

–40

150

ºC

°C

Storage temperature, T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

7.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾⁽²⁾

V_(ESD)

Electrostatic discharge

All pins

V

Charged-device model (CDM), per AEC

Q100-011⁽³⁾

Corner pins

±750

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

(2) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500 V HBM allows safe

manufacturing with a standard ESD control process.

(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250 V CDM allows safe

manufacturing with a standard ESD control process.

5

LM5140-Q1

ZHCSEI6 –JANUARY 2016

www.ti.com.cn

7.3 Recommended Operating Conditions⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN

3.8

NOM

MAX

UNIT

VIN

65

V

SW1, SW2 to PGND

HB1 to SW1, HB2 to SW2

–0.3

5

5.25

HO1 to SW1, HOL1 to SW1, HO2

to SW2, HOL2 to SW2

–0.3

HB + 0.3

5.25

V

LO1, LOL1, LO2, LOL2 to PGND

V_IN

Input voltage range

FB1, FB2, PG1, PG2, SYNIN,

OSC, SS1, SS2, RES, DEMB,

VCCX, ILSET

–0.3

5

V

EN1, EN2 to PGND

VCC, VDDA

–0.3

1.5

65

5.25

15

V

5

VOUT1, VOUT2, CS1, CS2

SYNOUT

V

V_O

T_J

Output voltage range

–0.3

–40

5.25

0.3

V

PGND to AGND

Operating Junction Temperature⁽²⁾

V

150

°C

(1) Recommended Operating Conditions are conditions under which the device is intended to be functional. For specifications and test

conditions, see the Electrical Characteristics.

(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

7.4 Thermal Information

LM5140-Q1

THERMAL METRIC⁽¹⁾

VQFN (RWG)

UNIT

40 PINS

34.8

22.8

9.5

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1.3

ψ_JB

9.4

R_θJC(bot)

0.3

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6

LM5140-Q1

www.ti.com.cn

ZHCSEI6 –JANUARY 2016

7.5 Electrical Characteristics

T_J= –40°C to 125°C, V_IN= 12 V, VCCX = 5 V, VOUT1 = 3.3 V, VOUT2 = 5 V, EN1 = EN2 = 5 V, OSC = VDDA, SYNIN = 0

V, FSW = 2.2 MHz, no-load on the Drive Outputs (HO1, HOL1, LO2, LOL1, HO2, HOL2, LO2, and LOL2 outputs) (unless

(1)(2)

otherwise noted).

PARAMETER

VIN SUPPLY VOLTAGE

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_IN8 V- 18 V, EN1 = 0 V, EN2 = 0 V,

VCCX = 0 V

I_(SHUTDOWN)

Shutdown mode current

Standby Current

9

12.5

µA

EN1 = 5 V, EN2 = 0 V, VOUT1, in

regulation, no-load, not switching.

VIN 8 V - 18 V. DEMB = GND

35

I_(STANDBY)

Or EN1 = 0 V, EN2 = 5 V, VOUT2 in

regulation, no-load, not switching,

VOUT2 connected to VCCX,

DEMB = GND.

42

µA

VCC REGULATOR

V_IN= 6 V - 18 V, 0 - 150 mA,

VCCX = 0 V

VCC_(REG)

VCC regulation voltage

4.75

3.25

5.0

5.25

3.55

V

VCC_(UVLO)

VCC_(HYST)

I_CC(LIM)

VCC under voltage threshold

VCC hysteresis voltage

VCC rising, VCCX = 0 V

VCCX = 0 V

3.4

175

250

V

mV

mA

VCC sourcing current limit

VCCX = 0 V

170

VDDA

VDDA_(REG)

VDDA_(UVLO)

VDDA_(HYST)

R_(VDDA)

Internal bias supply power

VCCX = 0 V

4.75

3.1

5.0

3.2

180

50

5.25

3.3

V

V_CCrising, VCCX = 0 V

VCCX = 0 V

mV

Ω

VCCX = 0 V

VCCX

VCCX_(ON)

R_(VCCX)

V_CCrising

4.1

2.4

4.3

1

4.4

V

Ω

VCCX = 5 V

VCCX_(HYST)

200

mV

OSCILLATOR SELECT THRESHOLDS

2.2 MHz Oscillator select threshold (OSC pin)

440 kHz Oscillator select threshold (OSC pin)

CURRENT LIMIT

V

0.4

ILSET = VDDA, Measure from

CS to VOUT

V_(CS1)

V_(CS2)

Current limit threshold1

Current limit threshold2

66

44

73

48

80

53

mV

ILSET = GND, Measure from

CS to VOUT

Current sense delay to output

Current sense amplifier gain

Amplifier input bias

40

12

ns

V/V

nA

11.4

2.4

12.6

10

ICS_(BIAS)

75mV current limit select threshold

(ILSET)

V

75mV current limit select threshold

(ILSET)

0.4

RES

I_(RES)

V_(RES)

RES current source

RES threshold

20

1.2

µA

V

Timer hIccup mode fault

RES pull-down

512

5.0

cycles

Ω

R_DS(ON)

(1) All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and

applying statistical process control.

(2) The junction temperature (T_Jin °C) is calculated from the ambient temperature (T_Ain °C) and power dissipation (P_Din Watts) as follows:

T_J= T_A+ (P_D• R_θJA) where R_θJA(in °C/W) is the package thermal impedance provided in the Thermal Information section.

7

LM5140-Q1

ZHCSEI6 –JANUARY 2016

www.ti.com.cn

Electrical Characteristics (continued)

T_J= –40°C to 125°C, V_IN= 12 V, VCCX = 5 V, VOUT1 = 3.3 V, VOUT2 = 5 V, EN1 = EN2 = 5 V, OSC = VDDA, SYNIN = 0

V, FSW = 2.2 MHz, no-load on the Drive Outputs (HO1, HOL1, LO2, LOL1, HO2, HOL2, LO2, and LOL2 outputs) (unless

otherwise noted). ⁽¹⁾⁽²⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OUTPUT VOLTAGE REGULATION

3.3 V

V_IN= 3.8 V - 42 V

3.273

4.95

7.92

3.3

5.0

8.0

3.327

5.05

8.08

V

5 V

8 V

V_IN= 5.5 V - 42 V

V_IN= 8.5 V - 42 V

FEEDBACK

VOUT1 select threshold 3.3V

Output

VDDA-

0.3

V

VDDA-

0.3

VOUT2 select threshold 5.0V

Regulated

Feedback

Voltage

1.19

1.2

1.21

500

V

Resistance to ground on FB for

FB=0 detection

FB_(LOWRES)

FB_(EXTRES)

Ω

Thevenin equivalent resistance at

FB for external regulation detection

FB < 2 V

5

kΩ

TRANSCONDUCTANCE AMPLIFIER

Gm

FB

Gain

Feedback to COMP

1010

1200

µS

nA

Input Bias Current

15

Transconductance Amplifier source

current

COMP = 1 V, FB = 1.0 V

COMP = 1 V, FB = 1.4 V

100

µA

Transconductance Amplifier sink

current

POWER GOOD

PG1 and PG2 Under Voltage trip

levels

Falling with respect to the regulation

voltage

PG_(UV)

90%

92%

94%

PG1 and PG2 Over Voltage trip

levels

Rising with respect to the regulation

voltage

PG_(OVP)

108%

110%

3.4%

112%

PG_(HYST)

PG_(VOL)

PG_(rdly)

PG_(fdly)

PG1 and PG2

OV Filter Time

UV Filter Time

Open Collector, I_sink= 2 mA

V_OUTrising

0.4

V

25

30

µs

V_OUTfalling

HO GATE DRIVER

V_OLH

V_OHH

t_rHO

HO Low-state output voltage

I_HO= 100 mA

0.05

0.07

4

V

HO High-state output voltage

HO rise time (10% to 90%)

HO fall time (90% to 10%)

I_HO= -100 mA, V_OHH= V_HB- V_HO

C_LOAD= 2700 pf

ns

t_fHO

C_LOAD= 2700 pf

3

V_HO= 0 V, SW = 0 V, HB = 5 V,

VCCX = 5 V

I_OHH

I_OLH

V_(BOOT)

I_(BOOT)

HO peak source current

3.25

Apk

HO peak sink current

UVLO

VCCX = 5 V

HO falling

4.25

2.5

110

3

Apk

V

Hysteresis

mV

µA

Quiescent current

8

LM5140-Q1

www.ti.com.cn

ZHCSEI6 –JANUARY 2016

Electrical Characteristics (continued)

T_J= –40°C to 125°C, V_IN= 12 V, VCCX = 5 V, VOUT1 = 3.3 V, VOUT2 = 5 V, EN1 = EN2 = 5 V, OSC = VDDA, SYNIN = 0

V, FSW = 2.2 MHz, no-load on the Drive Outputs (HO1, HOL1, LO2, LOL1, HO2, HOL2, LO2, and LOL2 outputs) (unless

otherwise noted). ⁽¹⁾⁽²⁾

PARAMETER

LO GATE DRIVER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_OLL

V_OHL

t_rLO

LO Low-state Output Voltage

LO High-state Output voltage

LO rise time (10% to 90%)

LO fall time (90% to 10%)

LO peak source current

LO peak sink current

I_LO= 100 mA

0.05

0.07

4

V

I_LO= -100 mA, V_OHL= VCC - V_LO

C_LOAD= 2700 pf

ns

t_fLO

C_LOAD= 2700 pf

3

ns

I_OHL

I_OLL

VCCX = 5 V

3.25

4.25

Apk

VCCX = 5 V

ADAPTIVE DEAD TIME CONTROL

V_(GS-DET)

tdly1

VGS detection threshold

HO off to LO on dead time

LO off to HO on dead time

VGS falling, no-load

2.5

20

15

V

ns

tdly2

DIODE EMULATION

V_IL

DEM input low threshold

0.4

V

V_IH

SW

FPWM input high threshold

zero cross threshold

2.4

-5

1

mV

ENABLE INPUTS EN1 AND EN2

V_IL

Enable input low threshold

VCCX = 0 V

V

V_IH

Enable input high threshold

Leakage

VCCX = 0 V

I_lkg

EN1, EN2 logic inputs only

µA

SYN INPUT

V_IL

V_IH

SYNIN input low threshold

SYNIN input high threshold

V

2.4

SYNIN input low frequency range

440kHz

350

550

kHz

SYNIN input low frequency range

2.2MHz

1800

2.4

2600

SYN OUTPUT

V_OH

V_OL

Source -16 mA, VDDA = 5 V

Sink 16 mA

V

0.4

28

Phase between HO1 and HO2

Duty Cycle

180

degrees

50%

SOFT-START

I_SS

Soft-Start current

16

22

3

µA

R_DS(ON)

Soft-start pull-down resistance

Ω

THERMAL

TSD Thermal Shutdown

175

15

ºC

Thermal shutdown hysteresis

7.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

2060

410

TYP

2200

440

45

MAX

2340

470

UNIT

kHz

ns

Oscillator Frequency, 2.2 MHz

Oscillator Frequency, 440 kHz

Minimum on-time

OSC = VDDA, V_IN= 8 V -18 V

OSC = GND, V_IN= 8 V - 18 V

t_on

t_off

Minimum off-time

100

ns

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7.7 Typical Characteristics

100

90

80

70

60

50

40

30

20

10

100

90

80

70

60

50

40

30

20

10

V_IN8 V

V_IN12 V

V_IN18 V

V_IN8 V

V_IN12 V

V_IN18 V

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

I_OUT(A)

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

I_OUT(A)

V_IN8-18 V

EN1 = EN2 = 12 V

V_IN8-18 V

EN1 = EN2 = 12 V

Figure 1. Efficiency vs VIN, FPWM

Figure 2. Efficiency vs VIN, DEMB

12

10

8

45

40

35

30

25

20

125èC

25èC

-40èC

6

4

V_IN8 V

V_IN12 V

V_IN18 V

2

0

-60

-30

0

30

60

90

120

150

8

9

10

11

12

13

14

15

16

17

18

Temperature (èC)

V_IN(V)

V_IN8-18 V

EN1 = EN2 = 12 V

V_IN8-18 V

EN1 = 12 V, EN2 = 0 V

Figure 3. I_(SHUTDOWN)vs Temperature

Figure 4. I_(STANDBY)vs VIN

5.25

5.20

5.15

5.10

5.05

5.00

4.95

4.90

4.85

4.80

4.75

3.50

3.48

3.46

3.44

3.42

3.40

3.38

3.36

3.34

3.32

3.30

6

8

10

12

14

16

18

-60

-30

0

30

60

90

120

150

V_IN(V)

Temperature(èC)

V_IN6-18V

EN1 = EN2 = 12 V

VCC Rising

EN1 = EN2 = 12 V

Figure 5. VCC_(REG)vs V_IN

Figure 6. VCC_(UVLO)vs Temperature

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Typical Characteristics (continued)

5.25

5.20

5.15

5.10

5.05

5.00

4.95

4.90

4.85

4.80

4.75

3.30

3.28

3.26

3.24

3.22

3.20

3.18

3.16

3.14

3.12

3.10

-60

-20

20

60

100

140

-60

-30

0

30

60

90

120

150

Temperature (èC)

Temperature(èC)

VCC Rising

EN1 = EN2 = 12 V

VCC Rising

Figure 8. VDDA_(UVLO)vs Temperature

Figure 7. VDDA_(REG)vs Temperature

4.36

4.34

4.32

4.30

4.28

4.26

4.24

4.22

4.20

4.18

4.16

4.14

4.12

4.10

86

84

82

80

78

76

74

72

70

68

66

-60

-30

0

30

60

90

120

150

-60

-30

0

30

60

90

120

150

Temperature (èC)

V_IN= 12 V

VCC Rising

V_IN= 12 V

I_LSET= VCC

Figure 9. VCCX_(ON)vs Temperature

Figure 10. V_(CS1)73 mV Current Limit Threshold vs

Temperature

53

52

51

50

49

48

47

46

45

44

13.0

12.8

12.6

12.4

12.2

12.0

11.8

11.6

11.4

11.2

11.0

-60

-30

0

30

60

90

120

150

-60

-30

0

30

60

90

120

150

Temperature (èC)

V_IN= 12 V

I_LSET= GND

VCC Rising

Figure 12. Current Sense Amplifier Gain vs Temperature

Figure 11. V_(CS2)48 mV Current Limit Threshold vs

Temperature

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Typical Characteristics (continued)

3.332

3.326

3.320

3.314

3.308

3.302

3.296

3.290

3.284

3.278

3.272

5.05

5.04

5.03

5.02

5.01

5.00

4.99

4.98

4.97

4.96

4.95

125èC

25èC

-40èC

125èC

25èC

-40èC

0

1

2

3

4

5

6

0

1

2

3

4

5

Output Current (A)

VI_N12 V

EN1 = 12 V

EN2 = GND

V_IN5.5 V - 42 V

EN1 = GND

EN2 = 12 V

Figure 13. 3.3-V Output Voltage Regulation

Figure 14. 5-V Output Voltage Regulation

470

465

460

455

450

445

440

435

430

425

420

415

410

2360

2310

2260

2210

2160

2110

2060

-60

-30

0

30

60

90

120

150

-60

-30

0

30

60

90

120

150

Temperature (èC)

V_IN12 V

OSC = VCC

V_IN12 V

OSC = GND

Figure 15. 2.2-MHz Oscillator Frequency vs Temperature

Figure 16. 440-kHz Oscillator Frequency vs Temperature

80

90

85

80

75

70

65

60

55

50

45

40

70

60

50

40

30

20

-60

-30

0

30

60

90

120

150

-40

-20

0

20

40

60

80

100 120 140

Temperature (èC)

V_IN18 V

V_IN3.8 V

Figure 17. t_onMinimum vs Temperature

Figure 18. t_offMinimum vs Temperature

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8 Detailed Description

8.1 Overview

The LM5140-Q1 is a dual channel switching controller which features all of the functions necessary to implement

a high efficiency buck power supply that can operate over a wide input voltage range. The LM5140-Q1 is

configured to provide two independent outputs. VOUT1 can be a fixed 3.3 V, 5 V, or adjustable between 1.5 V to

15 V. VOUT2 can be a fixed 5 V, 8 V, or adjustable between 1.5 V to 15 V. This easy to use controller integrates

high-side and low-side MOSFET drivers capable of sourcing 3.25 A and sinking 4.25 A peak . The control

method is current mode control which provides inherent line feed-forward, cycle-by-cycle current limiting, and

ease of loop compensation. With the OSC pin connected to VDD the default oscillator frequency is 2.2 MHz.

With the OSC pin grounded the oscillator frequency is 440 kHz. A synchronization pin allows the LM5140-Q1 to

be synchronized to an external clock. Fault protection features include current limiting, thermal shutdown, and

remote shutdown capability. The LM5140-Q1 incorporates features that simplify compliance with the CISPR and

Automotive EMI requirements. The LM5140-Q1 gate drivers provide adaptive slew rate control and interleaved

operation (180 degree output of phase) of the two controller channels. The QFN-40L package with Wettable

Flanks features an exposed pad to aid in thermal dissipation.

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8.2 Functional Block Diagram

SYNIN

OSC

CLK1

CLK2

VIN

VREF 1.2 V

BIAS

VCCX

COMMON

OSCILLATOR

SYNOUT

VCC

VDDA

CONTROL

VDDA

DEMB1

DEMB2

DEMB

20 µA

DEMB

AGND

HICCUP FAULT

TIMER 512

CYCLES

RESTART

LOGIC

RES

CL

OUT1 OUT2

ILSET

75 mV or

50 mV

ILSET

EN1

ILSET

CL

OUT1

CURRENT

LIMIT

Gain = 12

ILSET

+

CS1

+

-

VOUT1

SLOPE

COMPENSATION

RAMP

HB1

HB1 UVLO

3.3 V

5.0 V

300 mV

8.0 V

VOUT

DECODER/

MUX

DEMB1

OUT1

+

HO1

HOL1

LEVEL

SHIFT

ADAPTIVE

DEAD TIME

FB1

SW1

+

-

PWM

VCC

R

S

Q

SScomplete

1200 µS

_

STBY

CLK1

FBi

300 mV

LO1

LOL1

20 µA

V_REF

+

SS1

PGND1

SS1

COMP1

PG1

STBY

-

1.356 V

1.056 V

PGOV

+

Pgdly

25 µs

_

STAND-BY

-

PGUV

+

V_STBY

EN2

CL

OUT2

CURRENT

LIMIT

Gain = 12

ILSET

+

CS2

+

-

VOUT2

HB2

SLOPE

HB2 UVLO

3.3 V

COMPENSATION

RAMP

300 mV

5.0 V

8.0 V

VOUT

DECODER/

MUX

DEMB2

OUT2

+

HO2

HOL2

FB2

LEVEL

SHIFT

ADAPTIVE

DEAD TIME

SW2

PWM

+

-

VCC

R

Q

SScomplete

1200 µS

_

S

STBY

CLK2

FBi

V_REF

300 mV

LO2

LOL2

20 µA

+

SS2

PGND2

SS2

COMP2

PG2

STBY

-

1.356 V

1.056 V

PGOV

+

Pgdly

25 µs

_

+

STAND-BY

-

PGUV

+

V_STBY

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8.3 Feature Description

8.3.1 High Voltage Start-up Regulator

The LM5140-Q1 contains an internal high voltage VCC bias regulator that provides the bias supply for the PWM

controller and the gate drivers for the external MOSFETs. The input pin (VIN) can be connected directly to an

input voltage source up to 65 V. The output of the VCC regulator is set to 5 V. When the input voltage is below

the VCC set-point level, the VCC output will track VIN with a small voltage drop.

In high voltage applications extra care should be taken to ensure the VIN pin does not exceed the absolute

maximum voltage rating of 70 V curing line or load transients. Voltage ringing on the VIN pin that exceeds the

Absolute Maximum Ratings can damage the IC. Use care during PCB board layout and high quality bypass

capacitors to minimize ringing.

8.3.2 VCC Regulator

The VCC regulator output current limit is 150 mA (minimum). At power-up, the regulator sources current into the

capacitors connected to the VCC pin. When the voltage on the VCC pin exceeds 3.4 V both output channels are

enabled (if EN1 and EN2 are connected to a voltage source > 2.4 V) and the soft-start sequence begins. Both

channels remain active unless the voltage on the VCC pin falls below the VCC_UVLOthreshold, of 3.2 V (typical) or

the enable pins are switched to a low state. The LM5140-Q1 has two VCC pins; these pin must be connected

together on the PCB. It is recommended that the VCC capacitor be split between the two VCC pins and

connected to the respective PGND pins. The recommended range for the VCC capacitor is from 2.2 µF to 5 µF

total.

An internal 5-V linear regulator generates the VDDA bias supply. Bypass VDDA with a 100-nF or greater ceramic

capacitor to ensure a low noise internal bias rail. Normally VDDA is 5 V, but there are two operating conditions

where it regulates at 3.3 V. The first is in skip cycle mode with VOUT1 set to 3.3 V, and VOUT2 is disabled. The

second is in a cold crank start-up where VIN is 3.8 V and VOUT1 is 3.3 V.

Internal power dissipation in the VCC Regulator can be minimized by connecting the VCCX pin to a 5 V output at

VOUT1 or VOUT2 or to an external 5 V supply. If VCCX > 4.5 V, VCCX is internally connected to VCC and the

internal VCC regulator is disabled. If VCCX is unused, it should be grounded. Never connect the VCCX pin to a

voltage greater than 6.5 V.

8.3.3 Oscillator

The LM5140-Q1 has independent oscillators that generate the clock for each channel and can be programmed to

2.2 MHz or 440 kHz with the OSC pin. With the OSC pin connected to VDDA, both oscillators will be set to 2.2

MHz. With OSC grounded, they will both be set to 440 kHz. The state of the OSC pin is read and latched during

VCC power up and thus cannot be changed until VCC drops below the VCC_UVLOthreshold. CLK1 is the clock for

channel 1; CLK2 is for channel 2. CLK1 and CLK2 are 180º out of phase. The rising edge of SYNOUT always

corresponds to the rising edge of CLK2 which is 180º out of phase with CLK1.

Under low VIN conditions when either of the high-side buck switch on time exceeds the programmed oscillator

period, the LM5140-Q1 will extend the oscillator period of that channel until the PWM latch is reset by the current

sense ramp exceeding the controller compensation voltage. In such an event, the oscillators (CLK1 and CLK2)

operate independently and asynchronously until both channels can maintain output regulation at the programmed

frequency.

The approximate input voltage level where this occurs is:

t_p

VIN_min= VOUT ´

ton_(max)

(1)

Where t_p= is the oscillator period, 454 ns (for 2.2 MHz operation) ton_(max)= 354 ns

For example, if VOUT1 = 3.3 V and VOUT2 = 5 V and VIN drops to 6.41 V:

454 ns

VIN = 5.0 V ´

= 6.41V

354 ns

(2)

In the above example, CLK2 frequency is required to drop to maintain regulation of VOUT2 while CLK1 can

remain at the programmed frequency (refer to Figure 19). If VIN continues to drop, both CLK1 and CLK2

frequencies are reduced Figure 20.

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Feature Description (continued)

HO1 (Red)

HO2 (Blk)

SYNOUT (Blue)

Figure 19. HO1, HO2, and SYNOUT VIN 6.41 V

HO1 (Red)

HO2 (Blk)

SYNOUT (Blue)

Figure 20. HO1, HO2, SYNOUT VIN 4.2 V

Under high input voltage conditions (VIN > 20V) when the buck switch on time of either controller reaches the

minimum on-time of 45ns typical, the LM5140-Q1 will reduce the oscillator frequency by skipping clock cycles for

the appropriate channel.

Using the same output voltages as in the example above with VIN = 36 V, CLK1 drops to 1.1 MHz and CLK2 is

2.2 MHz, (refer to Figure 21), and SYNOUT is 2.2 MHz.

HO1 (Red)

HO2 (Blk)

SYNOUT (Blue)

Figure 21. HO1, HO2, and SYNOUT VIN 36 V

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Feature Description (continued)

8.3.4 SYNIN and SYNOUT

The SYNIN pin can be used to synchronize the LM5140-Q1 to an external clock. The synchronization range

when the internal oscillator is set to 440 kHz is 374 kHz minimum to 506 kHz maximum. When the internal

oscillator is set to 2.2 MHz the synchronization range is 1.87 MHz to 2.53 MHz. If the synchronization feature is

not being used, the SYNIN pin should be grounded.

CLK1 starts on the rising edge of the external synchronization clock (SYNIN). The HO1 pulse will follow

approximately 110ns after CLK1 due to internal delays (refer to Figure 22). Similarly, CLK2 generates the HO2

pulse after a short delay, and CLK2 is 180º out of phase with CLK1. SYNOUT always corresponds to the rising

edge of CLK2.

Figure 22. SYNIN and HO1 Timing (2.2 MHz)

Under low VIN conditions when the frequency must be reduced to maintain output voltage regulation, the SYNIN

input function will adapt as necessary. If VOUT1 can maintain regulation at the SYNIN frequency and VOUT2

cannot, then CLK1 remains synchronized to SYNIN and the CLK2 frequency is reduced (refer to Figure 23). If

VOUT1 cannot maintain regulation at the SYNIN frequency, then the SYNIN signal is ignored and channel 1

frequency is reduced to maintain regulation. Channel 2 runs at the frequency determined by OSC pin or lower if

required to maintain regulation on VOUT2 (refer to Figure 24).

SYNIN

SYNOUT

HO1 (Red)

HO2 (Blk)

Figure 23. SYNIN (2.2 MHz) VIN 6.41 V

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Feature Description (continued)

SYNIN

SYNOUT

HO1 (Red)

HO2 (Blk)

Figure 24. SYNIN (2.2 MHz) VIN 4.2 V

At high VIN when pulse skipping is necessary, HO1 drops to 1.1 MHz and HO2 remains at 2.2 MHz (refer to

Figure 25), and SYNOUT is 2.2 MHz.

SYNIN

SYNOUT

HO1 (Red)

HO2 (Blk)

Figure 25. SYNIN (2.2 MHz) VIN 36 V

8.3.5 Enable

The LM5140-Q1 contains two enable inputs, EN1 and EN2. The enable pins allow independent start-up and

shutdown control of VOUT1 (EN1) and VOUT2 (EN2). The enable pins can be connected to a voltage as high as

70 V. If the enable input is greater than 2.4 V, the respective controller output is enabled. If the enable pins is

pulled below 0.4 V, the respective output will be in shutdown. If both outputs are disabled the LM5140-Q1 is in a

low I_Qshutdown mode, with 9-µA typical current drawn from the VIN pin. It is not recommended to leave either of

the EN pins floating.

8.3.6 Power Good

The LM5140-Q1 includes output voltage monitoring signals for VOUT1 and VOUT2 to simplify sequencing and

supervision. The power good function can be used to enable circuits that are supplied by the corresponding

voltage rail or to turn-on sequenced supplies. Each power good output (PG1 and PG2) switches to a high

impedance open drain state when the corresponding output voltage is in regulation. Each output switches low

when the corresponding output voltage drops below the lower power good threshold (92% typical) or rises above

the upper power good threshold (110% typical). A 25µs deglitch filter prevents any false tripping of the power

good signals due to transients. Pull-up resistors of 10 kΩ (typical) are recommended from PG1 and PG2 to the

relevant logic rail. PG1 and PG2 are asserted low during soft-start and when the corresponding buck converter is

disabled by EN1 or EN2.

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Feature Description (continued)

8.3.7 Output Voltage

The LM5140-Q1 outputs can be independently configured for one of two fixed output voltages with no external

feedback resistors or adjusted to the desired voltage using external resistor dividers. VOUT1 can be configured

as a 3.3-V output by connecting the FB1 pin to VDDA, or a 5-V output by connecting the FB1 pin to ground with

a maximum resistance of 500 Ω. VOUT2 can be configured as either a 5-V output or 8-V output. For a 5-V output

at VOUT2, connect the FB2 pin to VDDA. For a fixed 8-V output at VOUT2 connect FB2 to ground with a

maximum resistance of 500 Ω. The FB1 and FB2 connections (either VDDA or GND) are detected during power-

up. The configuration setting is latched and can not be changed until the LM5140-Q1 is powered down with VCC

falling below V_CC(UVLO)(3.4 V typical) and then powered up again.

Alternative output voltages can be set external resistive dividers from output to the FB pins. The output voltage

adjustment range is between 1.5 V and 15 V. The regulation threshold at the FB pin is 1.2 V (VREF). To

calculate R_FB1and R_FB2use Equation 3, refer to Figure 26:

VOUT

æ

ö

R_FB2

=

-1 ´R_FB1

ç

÷

VREF

è

ø

(3)

The recommend value for R_(FB1)is between 10 kΩ to 20 kΩ.

The Thevenin equivalent impedance of the resistive divider connected to the FB pins must be greater than 5 kΩ

for the LM5140-Q1 to detect the divider and set the channel to the adjustable output mode.

R_FB1´R_FB2

R_TH

=

> 5 kW

R_FB1+ R_FB2

(4)

If a low I_Qmode is required, care should be taken when selecting the external resistors. The extra current drawn

from the external divider is added to the LM5140-Q1 I_(STANDBY)current (35 µA typical). The divider current

reflected to VIN is divided down by the ratio of VOUT/VIN. For example, if VOUT is set to 5.5 V with R_FB110 kΩ,

and R_FB2= 35.8 kΩ (use 35.7 kΩ), the input current at VIN required to supply the current in the feedback

resistors is:

VOUT

5.5 V

I_DIVIDER

=

´

=

´

10 k + 35.8 k 12 V

= 55.04 mA

R

_FB1+ R_FB2

VIN

(5)

(6)

I_VIN» I_(STANDBY)+ I_DIVIDER» 35 mA + 55.04 m » 90.4 mA

VIN = 12 V

L_OUT

VOUT

C_OUT

R_FB2

LM5140-Q1 Transconductance Amplifier

gm 1200uS

_

FB

VREF

+

R_FB1

+

SS

COMP

Figure 26. Voltage Feedback

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Feature Description (continued)

If one output is enabled and the other disabled, VCC output will be in regulation. The HB pin voltage of the

disabled channel will charge to VCC through the boot strap diode. As a result, the HO driver bias current (~3uA)

can charge the disabled channel VOUT to approximately 2.2 V. If this is not desired, a load resistor (100 kΩ) can

be added to the output that is disabled to maintain a low voltage off state.

8.3.8 Minimum Output Voltage Adjustment

There are two limitations to the minimum output voltage adjustment range: the LM5140-Q1 voltage reference 1.2

V and the minimum switch node pulse width, t_SW

.

The minimum t_SWtime limits the voltage conversion ratio (VOUT/VIN). For fixed-frequency PWM operation, the

voltage conversion ratio should meet the following condition:

VOUT

> t_SW´Fsw

VIN

(7)

Where t_SWis 70 ns (typical) and Fsw is the switching frequency. If the desired voltage conversion ratio does not

meet the above condition, the controller transitions from fixed frequency operation into a pulse skipping mode to

maintain regulation of the output voltage.

For example if the desired output voltage is 3.3 V with a VIN of 20 V and operating at 2.2 MHz, the voltage

conversion ratio test is:

3.3 V

> 70 ns´ 2.2 MHz

20 V

0.165 > 0.154

(8)

For Wide V_INapplications and lower output voltages, an alternative is to use the LM5140-Q1 with 440-kHz

oscillator frequency. Operating at 440 kHz, the limitation with the minimum ton time is less significant. For

example, if a 1.8-V output is required with a V_INof 50 V:

1.8 V

> 70 ns´ 440 kHz

50 V

0.036 > 0.0308

(9)

8.3.9 Current Sense

There are two methods to sense the inductor current of the buck converters. The first is using current sense

resistor in series with the inductor and the second is to use the dc resistance of the inductor (DCR sensing).

Figure 27 illustrates inductor current sensing using a current sense resistor. This configuration continuously

monitors the inductor current providing accurate current-limit protection. For the best current-sense accuracy and

over current protection, use a low inductance ±1% tolerance current-sense resistor between the inductor and

output, with a Kelvin connection to the LM5140-Q1 sense amplifier.

The LM5140-Q1 provides two user selectable current limit levels of 48 mV and 73 mV. If the ILSET pin is

connected to VDDA, the current limit threshold is 73 mV. When the ILSET pin is connected to ground, the current

limit set point is 48 mV. The ILSET pin is monitored during power up and the setting is latched. To change the

setting, VIN power must be removed from the controller allowing the VCC voltage to drop below V_CC(UVLO)

.

If the peak differential current signal sensed from CS to VOUT exceeds the user selectable current limit level of

48 mV or 73 mV, the current limit comparator immediately terminates the HO output for cycle-by-cycle current

limiting.

V_CS

Rsense =

DI

æ

ö

IOUT_max

+

ç

÷

2

è

ø

(10)

Where: V_CSis user selectable threshold of 48 mV or 73 mV.

IOUT_maxis the over current set point which is set higher than the maximum load current to avoid tripping the over

current comparator during load transients.

ΔI is the peak-peak inductor current.

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Feature Description (continued)

L_OUT

Rsense

VOUT

C_OUT

LM5140-Q1 Current Sense Amplifier

Gain 12

CS

+

_

VOUT

Figure 27. Current Sense

8.3.10 DCR Current Sensing

For high-power applications which do not require high accuracy current-limit protection, DCR sensing may be

preferrable. This technique provides lossless and continuous monitoring of the output current using an RC sense

network in parallel with the inductor. Using an inductor with a low DCR tolerance, the user can achieve a typical

current limit accuracy within the range of 10% to 15% at room temperature.

Components R_SCand C_CSin Figure 28 create a low-pass filter across the inductor to enable differential sensing

of the voltage drop across inductor DCR. When R_CSX C_CSis equal to L_OUT/L_DCR, the voltage developed across

the sense capacitor, CS, is a replica of the inductor DCR voltage waveform. Choose the capacitance of C_CSto

be greater than 0.1 μF to maintain a low impedance sensing network, thus reducing the susceptibility of noise

pickup from the switch node. Carefully observe the PCB layout guidelines to ensure the noise and DC errors do

not corrupt the differential current-sense signals applied across the CS and VOUT pins.

The voltage drop across C_CS

:

1+ sL_out

V_CS

=

Ipk ´L_DCR

L_DCR

1+ sR_CSC_CS

(11)

L_OUT

L_DCR

VOUT

C_OUT

C_CS

R_CS

LM5140-Q1 Current Sense Amplifier

Gain 12

+

CS

VOUT

_

Figure 28. DCR Current Sensing

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Feature Description (continued)

R_CSC_CS= L_OUT/L_DCR→ accurate DC and AC current sensing.

If the RC time constant is not equal to the L_OUT/L_DCRtime constant there will be an error.

R_CSC_CS> L_OUT/L_DCR→ DC level still correct, the AC amplitude will be attenuated.

R_CSC_CS< L_OUT/L_DCR→ DC level still correct, the AC amplitude will be amplified.

8.3.11 Error Amplifier and PWM Comparator

Each channel of the LM5140-Q1 has an independent high-gain transconductance amplifier which generates an

error current proportional to the difference between the feedback voltage and an internal precision reference (1.2

V). The output of each transconductance amplifier is connected to the COMP pin allowing the user to provide

external control loop compensation. Generally for current mode control a type II network is recommended.

8.3.12 Slope Compensation

The LM5140-Q1 provides internal slope compensation to ensure stable operation with duty cycle greater than

50%. To correctly use the internal slope compensation, the inductor value must be calculated based on the

following guidelines:

VOUT

L_OUT

=

Fsw ´LX

(12)

Where LX is 1 ±0.25

•

Lower inductor values increase the peak-to-peak inductor current, which minimizes size and cost and

improves transient response at the cost of reduced efficiency due to higher peak currents.

Higher inductance values decrease the peak-to-peak inductor current, which increases efficiency by reducing

the RMS current at the cost of requiring larger output capacitors to meet load-transient specifications.

8.4 Device Functional Modes

8.4.1 Hiccup Mode Current Limiting

The LM5140-Q1 includes an optional hiccup mode protection function that is enabled when a capacitor is

connected to the RES pin. In normal operation the RES capacitor is discharged to ground. If 512 cycles of cycle-

by-cycle current limiting occur on a either channel, the SS pin capacitor of that channel is pulled low and the HO

and LO outputs are disabled (refer to Figure 29). A 20-μA current source begins to charge the RES capacitor.

When the RES pin charges to 1.2 V, the RES pin is pulled low and the SS capacitor begins to charge. The 512

cycle hiccup counter is reset if 4 consecutive switching cycles occur without exceeding the current limit threshold.

Separate hiccup counters are provided for each channel, but the RES pin is shared by both channels. One

channel can be in the hiccup protection mode while the other operates normally. In the event that both channels

are in an over-current condition triggering hiccup protection, the last hiccup counter to expire will pull RES low

and start the RES capacitor charging cycle. Both channels will then restart together when RES=1.2 V. If RES is

connected to VDDA at power-up, the hiccup function is disabled for both channels.

The controller is in forced PWM (FPWM) continuous conduciton mode when the DEMB pin is connected to

VDDA. In this mode the SS pin is clamped to a level 200 mV above the feedback voltage to the internal error

amplifier. This ensures that SS can be pulled low quickly during a brief overcurrent event and prevent overshoot

of VOUT when the overcurrent condition is removed.

If DEMB=0 V, the controller operates in diode emulation with light loads (discontinous conduction mode) and the

SS pin is allowed to charge to VDDA. This reduces the quiescent current of the LM5140-Q1. If 32 or more cycle-

by-cycle current limit events occur, the SS pin is clamped to 200 mV above the feedback voltage to the internal

error amplifier until the hiccup counter is reset. Thus, if a momentary overload occurs that causes at least 32

cycles of current limiting, the SS capacitor voltage will be slightly higher than the FB voltage and will control

VOUT during recovery.

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Device Functional Modes (continued)

Current Limit

Detected

1.2 V RES Threshold

I_{RES= 20 mA}

0 V

RES

I

_SS= 20 mA

SS

1.2 V REF

HO/HOL

LO/LOL

t_RES

t_SS

Current Limit persists

during 512

consecutive cycles

Figure 29. Hiccup Mode

8.4.2 Standby Mode

The LM5140-Q1 operates with peak current mode control such that the feedback compensation voltage is

proportional to the peak inductor current. During no-load or light load conditions, the output capacitor will

discharge very slowly. As a result the compensation voltage will not demand a driver output pulses on a cycle-

by-cycle basis. When the LM5140-Q1 controller detects that there have been 16 missing switching cycles, it

enters Standby Mode and switches to a low I_Qstate to reduce the current drawn from VIN. For the LM5140-Q1 to

go into a Standby Mode, the controller must be programmed for diode emulation (DEMB pin < 0.4 V). The typical

I_Qin Standby Mode is 35 µA with VOUT1 regulating at 3.3 V and VOUT2 disabled. With VOUT1 disabled and

VOUT2 regulating to 5 V, the Standby Mode current is 42μA. With both channels in standby mode (VOUT1 = 3.3

V and VOUT2 = 5 V) the VIN current is 75μA. Using external feedback resistors will add additional load to VOUT

and significantly increase the Standby Mode VIN current.

8.4.3 Soft-Start

The soft-start feature allows the regulator to gradually reach the steady state operating point, thus reducing

startup stresses and surges. The LM5140-Q1 regulates the FB pin to the SS pin voltage or the internal 1.2-V

reference, whichever is lower. At the beginning of the soft-start sequence when SS = 0 V, the internal 20-μA soft-

start current source gradually increases the voltage on an external soft-start capacitor connected to the SS pin,

resulting in a gradual rise of the FB and output voltages.

The controller is in the forced PWM (FPWM) mode when the DEMB pin is connected to VDDA. In this mode, the

SS pin is clamped at 200 mV above the feedback voltage to the internal error amplifier. This ensures that SS can

be pulled low quickly during brief over-current events and prevent overshoot of VOUT during recovery. SS can

be pulled low with an external circuit to stop switching, but this is not recommended. Pulling SS low will result in

COMP being pulled down internally as well. If the controller is operating in FPWM mode (DEMB = VDDA), LO

will remain on and the low-side MOSFET will discharge the VOUT capacitor resulting in large negative inductor

current. When the LM5140-Q1 pulls SS low internally due to a fault condition, the LO gate driver is disabled.

8.4.4 Diode Emulation

A fully synchronous buck regulator implemented with a free-wheel MOSFET rather than a diode has the

capability to sink current from the output in certain conditions such as light load, over-voltage, and pre-bias

startup. The LM5140-Q1 provides a diode emulation feature that can be enabled to prevent reverse (drain to

source) current flow in the low-side free-wheel MOSFET. When configured for diode emulation, the low-side

MOSFET is disabled when reverse current flow is detected. The benefit of this configuration is lower power loss

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Device Functional Modes (continued)

at no load or light load conditions and the ability to turn on into a pre-biased output without discharging the

output. The negative effect of diode emulation is degraded light load transient response times. Enabling the

diode emulation feature is recommended to allow discontinuous conduction operation. The diode emulation

feature is configured with the DEMB pin. To enable diode emulation, connect the DEMB pin to ground or leave

the pin floating. If continuous conduction operation is desired, the DEMB pin should be tied to VDDA.

8.4.5 High and low-side Drivers

The LM5140-Q1 contains a N-channel MOSFET gate drivers and an associated high-side level shifter to drive

the external N-channel MOSFET. The high-side gate driver works in conjunction with an external bootstrap diode

D_BST, and bootstrap capacitor C_BST, refer to Figure 30. During the on-time of the low-side MOSFET, the SW pin

voltage is approximately 0 V and C_BSTis charged from VCC through the D_BST. A 0.1-μF or larger ceramic

capacitor, connected with short traces between the BST and SW pin, is recommended.

The LO and HO outputs are controlled with an adaptive dead-time methodology which ensures that both outputs

(HO and LO) are never enabled at the same time, preventing cross condiction. When the controller commands

LO to be enabled, the adaptive dead-time logic first disables HO and waits for the HO-SW voltage to drop below

2.5 V typical. LO is then enabled after a small delay (HO fall to LO rise delay). Similarly, the HO turn-on is

delayed until the LO voltage has dropped below 2.5 V. HO is then enabled after a small delay (LO fall to HO rise

delay). This technique ensures adequate dead-time for any size N-channel MOSFET device or parallel MOSFET

configurations. Caution is advised when adding series gate resistors, as this may decrease the effective dead-

time. Eachof the high and low-side drivers have an independent driver source and sink output pins. This allows

the user to adjust drive strength to optimize the switching losses for maximum efficiency and control the slew rate

for reduced EMI. The selected N-channel high-side MOSFET determines the appropriate boost capacitance

values C_BSTin the Figure 30 according to Equation 13.

Q_G

C_BST

=

DV_BST

(13)

Where Q_Gis the total gate charge of the high-side MOSFET and ΔV_BSTis the voltage variation allowed on the

high-side MOSFET driver after turn-on. Choose ΔV_BSTsuch that the available gate-drive voltage is not

significantly degraded when determining C_BST. A typical range of ΔV_BSTis 100 mV to 300 mV. The bootstrap

capacitor should be a low-ESR ceramic capacitor. A minimum value of 0.1 µF to 0.47 µF is best in most cases.

Care should be taken when choosing the high-side and low-side MOSFET devices with logic level gate

thresholds.

VCC

D_BST

HB

C_BST

R_HO

HO

HOL

R_HOL

SW

VCC

C_VCC

R_LO

LO

LOL

R_LOL

PGND

Figure 30. Drivers

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The LM5140-Q1 is a synchronous buck controller used to convert a higher input voltage to two lower output

voltages. The following design procedure can be used to select external component values. Alternately, the

WEBENCH^®software may be used to generate a complete design. The WEBENCH software uses an iterative

design procedure and accesses a comprehensive database of components when generating a design. This

section presents a simplified discussion of the design process. In addition to the WEBENCH software the

LM5140ADESIGN-CALC.XIXS quick start Excel calculator is available at www.ti.com.

9.2 Typical Application

V_IN

VCC

HB1

VIN

HB2

HO2

HOL2

SW2

HO1

OUT1

OUT2

HOL1

SW1

LO2

LO1

LM5140-Q1

LOL2

LOL1

PGND1

PGND2

PG1

EN1

VIN

EN2

PG2

VIN

VCC

ILSET

SYNOUT

CS2

CS1

VOUT1

VOUT2

VCCX

SYNIN

COMP1

COMP2

FB2

VCC

FB1

OSC AGND SS1 RES SS2 DEMB VDDA

VCC

Figure 31. 12-V to 3.3-V and 5-V Converter

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Typical Application (continued)

9.2.1 Design Requirements

For this design example, the intended input, output and performance parameters are shown in Table 1.

Table 1. Design Parameters

DESIGN PARAMETER

Input voltage range (Steady State)

Transient

EXAMPLE VALUE

8 V to 18 V

42 V

Cold Crank

3.8 V

Output voltage

3.3 V

Output current

6 A

Operating frequency

2.2 MHz

± 1%

Output voltage regulation

Standby current, one output enabled, no-load

Shutdown Current

< 35 µA

9 µA

9.2.2 Detailed Design Procedure

•

Buck Inductor calculation

Peak inductor current calculation

Current Sense resistor

Output capacitor

Input filter design

MOSFET selection

Control Loop design

9.2.2.1 Inductor Calculation

For design simplification, the LM5140-Q1 has internal slope compensation to eliminate sub-harmonic oscillation.

For proper slope compensation, the inductor value should be calculated based on the following guidelines:

VOUT

L_OUT

=

Fsw ´LX

(14)

Where LX is 1 ±0.25

•

Lower inductor values increase the peak-to-peak inductor current, which minimizes size and cost and

improves transient response at the expense of reduced efficiency due to higher peak currents.

Higher inductance values decrease the peak-to-peak inductor current, which increases efficiency by reducing

the RMS current but requires larger output capacitors to meet load-transient specifications.

3.3 V

L_OUT

=

= 1.5 mH

2.2 MHz ´1

(15)

A standard inductor value of 1.5 µH is selected.

VOUT 3.3 V

=

D_max

=

= 0.413

= 0.183

VIN_min

8 V

(16)

(17)

VOUT 3.3 V

=

D_min

=

VIN_max18 V

The maximum peak-to-peak inductor current is:

VIN_max- VOUT D_min

DI =

´

L_OUT

Fsw

(18)

(19)

18 V - 3.3 V

1.5 mH

0.183

DI =

´

= 0.815 Apk

2.2 MHz

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DI

Ipk = IOUT +

2

(20)

(21)

0.815

2

Ipk = 6A +

= 6.41Apk

9.2.2.2 Current Sense Resistor

When calculating the current sense resistor, the maximum output current capability (IOUT_MAX) should be at least

20% higher than the required full load current to account for tolerances, ripple current, and load transients. For

this example, 120% of the 6.41 A peak inductor current calculated in the previous section (Ipk) is 7.69 A. The

current sense resistor value can be calculated using:

V_CS

Rsense =

IOUT_max

(22)

73 mV

Rsense =

= 0.00949 W

7.69 Apk

(23)

Where:V_CSis the 73 mV current limit threshold.

The Rsense value selected is 9 mΩ

Carefully observe the PCB layout guidelines to ensure that noise and DC errors do not corrupt the differential

current sense signals betwen the CS and VOUT pins. Place the sense resistor close to the devices with short,

direct traces, creating Kelvin-sense connections between the current-sense resistor and the LM5140-Q1.

The propagation delays through the current limit comparator, logic, and external MOSFET gate drivers allow the

peak current to increase above the calculated current limit threshold. For a total propogation delay of t_dlyTOTAL

,

the worst case peak current through the inductor with the output is shorted can be calculated from:

VIN_max´ t_dlyTOTAL

V_CS

Ipk_shortckt

=

+

Rsense

L

(24)

From the Electrical Characteristics, t_dlyTOTAL40 ns. Therefore:

73 mV 18 V ´ 40 ns

Ipk_shortckt

=

+

= 8.59 Apk

0.009

1.5 mH

(25)

Once the peak current and the inductance parameters are known, the inductor can be chosen. An inductor with a

saturation current greater than Ipk_shortckt(8.59 Apk) should be selected.

9.2.2.3 Output Capacitor

In a switch mode power supply, the minimum output capacitance is typically selected based on the capacitor

ripple current rating and the load transient requirements. The output capacitor must be large enough to absorb

the inductor energy and limit over voltage when transitioning from full-load to no-load, and to limit the output

voltage undershoot during no-load to full load transients. The worst-case load transient from zero to full load

occurs when the input voltage is at the maximum value and a current switching cycle has just finished. The total

output voltage drop VOUT_UVis the sum of the voltage drop while the inductor is ramping up to support the full

load and the voltage drop before the next pulse can occur.

The output capacitance required to maintain the minimum output voltage drop VOUT_UVcan be calculated as

follows:

2

L ´I_STEP

COUT_min

=

2´ VOUT_UV´D_min´(VIN_max- VOUT)

(26)

(27)

1.5 mH x 6 A²

COUT_min

=

= 304 µF

2 x 33 mV x 0.183 x 18 V - 3.3 V

(

)

.

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LM5140-Q1

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Where:

•

I_STEP= 6A

VOUT_UV= 1% of 3.3 V, or 33 mV

For this example a total of 293 µF of capacitance is used, three 82-µF aluminum capacitors for energy storage

and one 47 µF low ESR ceramic capacitor to reduce high frequency noise.

Generally, when sufficient capacitance is used to satisfy the undershoot requirement, the overshoot during a full-

load to no-load transient will also be satisfactory. After the output capacitance has been selected, calculate the

output ripple current and verify that the ripple current is within the capacitor ripple current ratings.

For this design, the output ripple current is:

DI

IOUT

=

rms

12

(28)

(29)

0.815 A

12

IOUT

=

0.235 Arms

rms

9.2.2.4 Input Filter

A power supply input typically has a relatively high source impedance at the switching frequency. Good quality

input capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current

during the buck switch on-time. When the buck switch turns on, the current drawin from the input capacitor steps

from zero to the valley of the inductor current waveform, then ramps up to the peak value, and then drops to the

zero at turn-off.

Average input current can be calculated from the total input power required to support the loads at VOUT1 and

VOUT2:

VOUT1´IOUT1+ VOUT2´IOUT2

Pin =

h

(30)

The efficiency η is assumed to be 83% for this design example, yielding total input power:

3.3 V ´ 6 A + 5.0 V ´5 A

Pin =

= 54 W

0.83

(31)

I_avg

=

VIN_min

(32)

(33)

54 W

8 V

I_avg

=

= 6.75 A

The ripple voltage on the input capacitors will be reduced significantly with a dual channel operation since each

channel operates 180º out of phase from the other. Capacitors connected in parallel should be evaluated for their

RMS current rating. The ripple current will split between the input capacitors based on the relative impedance of

the capacitors at the switching frequency.

The input capacitors should be selected with sufficient RMS current rating and the maximum voltage rating. The

input ripple current with one channel operating is:

é

²ù

ú

û

DI

(Ipk -I_avg)²+

´D

+ (I_avg²)´(1-D_max

é

ë

)

ù

û

I

=

ê

IN(rms)

max

12

ê

ë

ú

(34)

(35)

é

²ù

ú

û

0.815

12

I

=

(6.41- 2.98)²+

´0.413 + (2.98²´(1- 0.413)) = 3.16 A

ê

IN(rms)

ê

ë

ú

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9.2.2.5 EMI Filter Design

Switching regulators exhibit negative input impedance, which is lowest at the minimum input voltage. An under-

damped LC filter exhibits a high output impedance at the resonant frequency of the filter. For stability, the filter

output impedance must be less than the absolute value of the converter input impedance.

2

VIN_min

Zin = -

(36)

8 V²

Zin = -

= 1.18 W

54 W

(37)

EMI Filter Design Steps:

•

Calculate the required attenuation

Capacitor C_INrepresents the existing capacitor at the input of the switching converter

Filter inductor L_fis usually selected between 1 μH and 10 μH (3.6 µH was used for this application), but it can

be smaller to reduce losses in a high current design

•

Calculate capacitor C_f

L

f

C

d

C

f

d

IN

R

Figure 32. Input EMI Filter

By calculating the first harmonic current from the Fourier series of the input current waveform and multiplying it

by the input impedance (the impedance is defined by the existing input capacitor C_IN), a formula can be derived

to obtain the required attenuation:

æ

ç

ö

÷

I_pk

Attn = 20log

´ sin p x D

- V

(

)

max max

2

p ´ ƒsw ´ C_IN

1mV

ç

÷

ç

÷

è

ø

(38)

æ

ç

ö

÷

6.41

´ sin(p´0.413) - 45 dBmV = 44.06 dB

2

÷

p ´ 2.2 MHz ´10 mF

1mV

ç

÷

ç

÷

è

ø

(39)

Vmax is the allowed dBμV noise level for the particular EMI standard, C_INis the existing input capacitors of the

buck converter. For this application 10 µF was selected. Dmax is the maximum duty cycle. I_pkis the peak

inductor current and for filter design purposes, the current at the input can be modeled as a squarewave. The

EMI filter capacitor C_fis determined from:

Attn

æ

ç

ö²

÷

40

1

10

÷

ø

C_ƒ=

L_ƒ2´ p´F

ç

SW

ç

è

(40)

ö²

÷

44.06

40

æ

ç

1

10

2´ p´ 2.2 MHz

C_ƒ=

=

= 0.25 mF

÷

3.6 mF

ç

÷

è

ø

(41)

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For this application, C_fwas chosen to be 1 µF. Adding an input filter to a switching regulator modifies the control-

to-output transfer function. The output impedance of the filter must be sufficiently small such that the input filter

does not significantly affect the loop gain of the buck converter. The impedance peaks at the filter resonant

frequency. The resonant frequency of the filter is given by:

1

fr =

2´ p L_ƒ´ C_ƒ

(42)

1

fr =

= 37.53 kHz

2´ p 1.8 mH´10 mF

(43)

The purpose of R_dis to reduce the peak output impedance of the filter at the resonant frequency. The capacitor

C_dblocks the dc component of the input voltage to avoids excessive power dissipation in R_d. The capacitor C_d

should have lower impedance than R_dat the resonant frequency with a capacitance value greater than the input

capacitor C_IN. This will prevent C_INfrom interfering with the cutoff frequency of the main filter. Added damping is

needed when the output impedance is high at the resonant frequency ( Q of filter formed by C_INand L_fis too

high): An electrolytic cap C_dcan be used as damping device, with the value of:

C_d= 4 ³ C_IN

(44)

C_d= 4 x 10 µF, a 47-µF capacitor was selected and R_dis chosen using:

L_ƒ

R_d=

C_IN

(45)

1.8 mH

R_d=

= 0.424 W

10 mF

(46)

9.2.2.6 MOSFET Selection

The LM5140-Q1 gate drivers are powered by the internal 5-V VCC bias regulator. To reduce power dissipation in

the controller and improve efficiency, the VCCX pin which should be connected to 5-V output or an external 5 V

bias supply. The MOSFETs used with the LM5140 require a logic-level gate threshold with on-resistance

specified with V_GS= 4.5 V or lower.

The four MOSFETs must be chosen with a V_DSrating to withstand the maximum V_INvoltage plus supply voltage

transients and spikes (ringing). For automotive applications, the maximum V_INoccurs during a load dump and the

voltage can surge to 42 V under some conditions. A MOSFET with a V_DSrating of 60 V would meet most

application requirements. The N-channel MOSFETs must be capable of delivering the average load current plus

peak ripple current during switching.

The high-side MOSFET losses are associated with the R_DS(ON)of the MOSFET and the switching losses.

1

Pd_HS= (IOUT²´R_DS(on)´D_max) + VIN´(tr + tƒ)´IOUT ´ ƒsw

2

(47)

(48)

1

Pd_HS= (6 A²´ 0.026 W ´0.413) + ´12 V ´(17 ns +17 ns)´ 6 A ´ 2.2 MHZ = 2.69 W

2

The losses in the low-side MOSFET include the R_DS(ON)losses, the dead time losses, and losses in the

MOSFETs internal body diode. The body diode conducts the inductor current during the dead time before the

rising edge of the switch node. Minority carriers are injected into and stored in the body diode PN junction. As the

high-side FET begins to turn-on, a negative current must first flow through the diode to remove the stored charge

before the diode can be reverse biased. During this time, the high-side MOSFET drain-source voltage remains at

V_INuntil all the diode minority carriers are removed. Then the diode begins to block negative voltage and the

reverse current continues to flow to charge the depletion capacitance of the body diode junction. The total charge

requierd to reverse bias the diode is called reverse-recovery charge Qrr. The power loss in the low-side

MOSFET can be calculated from:

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Pd_LS= (IOUT²´R_DS(on)´(1- D_max)) + (IOUT ´(t_dr+ t_dƒ)´F_SW´ V_DFET) + (D_Qrr´F_SW´ VIN)

Pd_LO= 6²A ´ 26 mW ´(1- 0.413) + (6A ´ 20 ns + 6A ´ 20 ns)´ 2.2 MHz ´0.8 V +105 nc ´ 2.2 MHz ´12 V = 3.744 W

(49)

(50)

Where t_drand t_dfare the switch node voltage rise and fall times (20 ns).

V_DFETthe forward voltage drop across the low-side MOSFET internal body diode (0.8 V).

D_Qrrthe internal body diode reverse recovery charge (105 nC).

R_DS(ON)the on resistance of the low-side MOSFET ( 26 mΩ at T_J= 125ºC).

The table below provides parameters for several MOSFETs that have tested in the LM5140-Q1 evaluation

module.

Q_gMAX(nC)

VGS = 4.5 V

RD_SONMAX (mΩ)

Manufacturer

Part Number

VDS (V) ID (A)

C_OSS/MAX

Application

VGS = 4.5

VISHAY

SQJ850EP

SQ7414EN

60

24

5.6

13

30

25

32

36

215

175

217

Automotive High Power

Automotive Low Power

Industrial

Texas Instruments CSD18534Q5A

11.1

12.4

9.2.2.7 Driver Slew Rate Control

Figure 33 shows the high current driver outputs with independent source and current sink pins for slew rate

control. Slew rate control enables the user to adjust the switch node rise and fall times which can reduce the

conducted EMI in the FM radio band (30 MHz to 108 MHz). Using the LM5140-Q1 EVM, conducted emission

were measured in accordance with CISPR 25. Figure 34 shows the measured results without slew rate control.

The conducted EMI results with slew rate control are shown in Figure 35.

VCC

D_BST

HB

C_BST

R_HO

HO

HOL

R_HOL

SW

VCC

C_VCC

R_LO

LO

LOL

R_LOL

PGND

Figure 33. Drivers with Slew Rate Control

31

LM5140-Q1

ZHCSEI6 –JANUARY 2016

www.ti.com.cn

Figure 34. EMI Measurements CISPR 25, No Slew Rate Control

Referring to Figure 34 and Figure 35 a 10 dB reduction in conduction emissions in the FM band is attained by

using slew rate control. This can reduce the size and cost of the EMI filters.

Figure 35. EMI Measurements CISPR 25 with Slew Rate Control

9.2.2.8 Sub-Harmonic Oscillation

For peak current mode control, sub-harmonic oscillation occurs with a duty cycle greater than 50% and is

characterized by alternating wide and narrow pulses at the SW pin. By adding a compensating ramp equal to the

down-slope of the inductor current, any tendency toward sub-harmonic oscillation is damped within one switching

cycle.

In time-domain analysis, the steady-state inductor current starts and ends at the same value during one clock

cycle. If the magnitude of the end-of-cycle current error, dI₁, caused by an initial perturbation, dI₀, is less than the

magnitude of dI₀or dI₁/dI₀> –1, the perturbation naturally disappears after a few cycles, refer to Figure 36. When

dI₁/dI₀< –1, the initial perturbation does not disappear resulting in sub-harmonic oscillation in steady-state

operation. By choosing K > 1 , sub-harmonic oscillation will be avoided.

32

LM5140-Q1

www.ti.com.cn

ZHCSEI6 –JANUARY 2016

Steady-State

Inductor Current

dI₀

t_on

dI₁

Inductor Current

with Initial

Perturbation

Figure 36. Sub-Harmonic Oscillation

dI₀

1

k

= 1-

dI₁

(51)

The relationship between Q and K factor is illustrated graphically in Figure 37.

Figure 37. Sampling Gain Q vs K Factor

The minimum value of K is 0.5. This is the same as time domain analysis result. When K < 0.5, the regulator is

unstable. High gain peaking at 0.5 results in sub-harmonic oscillation at F_SW//2. When K = 1, one-cycle damping

is realized and Q is equal to 0.673 at this point. A higher K factor may introduce additional phase shift by moving

the sampled gain inductor pole closer to the crossover frequency but will help reduce noise sensitivity in the

current loop.

9.2.2.9 Control Loop

The open loop response of a buck converter is defined as the product of modulator and feedback transfer

functions. When plotted on a dB scale, the open loop gain is shown as the sum of modulator gain and feedback

gain. The modulator transfer function includes a power stage transfer function with an embedded current loop

that can be simplified as one pole and a one zero system as shown in Equation 52. The modulator transfer

function is defined as follows:

33

LM5140-Q1

ZHCSEI6 –JANUARY 2016

www.ti.com.cn

æ

ç

è

ö

÷

ø

s

1+

w_Z

VOUT

= AM´

V_C

æ

ç

è

ö æ

ö

÷

ø

s

s²

w_n²

1+

´ 1+

+

÷ ç

ø è

w_p

w_nQ

(52)

F_SW

s = 2´ p´

2

K = 1

1

Q =

p(K - 0.5)

1

w_Z=

C

_ESR´ C_O

1

w_P=

R

_LOAD´ C_O

F_SW

w_n= p´

2

(53)

The equation includes the sample gain at f_SW//2 (ωn), which is caused by sampling effect of current mode

control. Refer to section Sub-Harmonic Oscillation:

s

s²

1+

+

2

w_n

w_nQ

(54)

R_LOAD

AM =

(Rsense + R_DCR)´ G_CS

0.471W

= 3.035

(0.007 + 0.0081)´12

(55)

(56)

(57)

Gain in dB 20log(AM)

20 logM (3.035) = 9.64

G_CSis the current sense amplifier gain (12).

R_LOADis the load resistance.

R_DCRis the dc resistance on the output inductor.

9.2.2.10 Error Amplifier

R_COMPand C_COMPconfigure the error amplifier gain characteristic to achieve a stable voltage feedback loop. One

advantage of current mode control is the ability to compensate the loop with only two compensation components,

R_COMPand C_COMP. The voltage loop gain is the product of the modulator gain and the error amplifier gain. For the

3.3-V output of this design example, the modulator is treated as an ideal voltage-to-current converter. The

modulator gain of the LM5140-Q1 can be modeled as:

æ

ç

è

ö

÷

ø

s

1+

w_ZEA

V_REF

VO

V_C

=

´ Gm´R_AMP´

VOUT

æ

ç

è

ö

÷

ø

s

w_PEA

(58)

(59)

(60)

1

w_ZEA

=

R

_COMP´ C_COMP

1

w_PEA

»

R

_AMP´ C_COMP

Where:

34

LM5140-Q1

www.ti.com.cn

ZHCSEI6 –JANUARY 2016

V_REFis the feedback voltage reference (1.2 V)

Gm is the error amplifier gain transconductance (1200 µS)

R_AMPis the error amplilfier output impedance (2.5 MΩ)

R_UPPER

C_O

V_REF

V_C

+

-

R_LOAD

R_COMP

C_ESR

R_LOWER

C_COMP

Figure 38. Transconductance Amplifier

The procedure for choosing compensation components for a stable closed loop is:

•

Select the desired open loop gain crossover frequency (fc); for this application 30 kHz was chosen

Calculate the R_COMPresistor for the gain crossover frequency at 30 kHz

2´ p´ C_O´Rsense´G_CS

VOUT

R_COMP= fc

´

V_REF

Gm

(61)

(62)

3.3 V 2´ p´ 290 mF´0.007´12

´

1.2 V

R_COMP= 30 kHz ´

= 10517 W

1200´10^-6

The value selected for R_COMPis 10 kΩ

Calculate the C_COMPcapacitor value to create a zero that cancels the pole ωp (ωp = 1/(R_LOADx C_O).

R_LOAD´ C_O

•

C_COMP

=

R_COMP

(63)

(64)

0.477´ 290 mF

C_COMP

=

= 13.8 nF

10000

The value seleced for C_COMPis 10 nF

35

LM5140-Q1

ZHCSEI6 –JANUARY 2016

www.ti.com.cn

9.2.3 Application Curves

Plotting the modulator gain and feedback gain, (refer to Figure 39).

The results are a gain crossover frequency of 20 kHz with 82º of phase margin, (refer to Figure 40).

-10

-20

-30

-40

-50

-60

-70

-80

-90

10

0

-10

-20

-30

-40

10

20

50

100

200

500

1k

2k

5k

10k

20k

50k

100k 200k

500k

1M

Frequency/Hertz

Figure 39. (V_O/V_C) Modulator Gain and Phase

140

120

100

80

60

40

20

0

-20

-40

-60

60

40

20

0

-20

-40

10

20

50

100

200

500

1k

2k

5k

10k

20k

50k

100k 200k

500k

1M

Frequency/Hertz

Figure 40. Open Loop Gain and Phase

36

LM5140-Q1

www.ti.com.cn

ZHCSEI6 –JANUARY 2016

10 Power Supply Recommendations

The LM5140EVM was designed to operate over an input voltage supply range between 3.8 V and 42 V. This

input supply must be well regulated. If the power source is located more than a few inches from the LM5140-Q1

EVM, additional bulk capacitance and ceramic bypass capacitors may be required at the power supply input. An

electrolytic capacitor with a value of 47 µF is typically a good choice.

37

LM5140-Q1

ZHCSEI6 –JANUARY 2016

www.ti.com.cn

11 Layout

Careful PCB layout is critical to achieve low EMI and stable power supply operation. If possible, mount all the

power components on the top side of the board, making the high frequency current loops as small as possible,

and follow these guidelines of good layout practices:

1. Keep the high-current paths short. This practice is essential for stable, jitter-free operation.

2. Keep the power traces and load connections short. This practice is essential for high efficiency. Using thick

copper (2 oz) can enhance full load efficiency by 1% or more.

3. Minimize current-sensing errors by routing CS and VOUT using a kelvin sensing directly across the current-

sense resistor (Rsense).

4. Route high-speed switching nodes (HB, HO, LO, and SW) away from sensitive analog areas (FB, CS, and

VOUT).

11.1 Layout Procedure

•

Place the power components first, with ground terminals adjacent to the low-side FET. If possible, make all

these connections on the top layer with wide, copper-filled areas.

•

Mount the controller IC as close as possible to the high and low-side MOSFETs. Make the grounds and high

and low-sided drive gate drive lines as short and wide as possible. Place the series gate drive resistor as

close to the MOSFET as possible to minimize gate ringing.

•

Locate the gate drive components (D1 and C17) together and near the controller IC; refer to Figure 41. Be

aware that peak gate drive currents can be as high as 4 A. Average current up to 150 mA can flow from the

VCC pin to the V_CCcapacitor through the bootstrap diode to the bootstrap capacitor. Size the traces

accordingly.

Make the ground connections to the LM5140-Q1 controller as shown in Figure 43. Create a power grounds

directly connected to all high-power components and an analog ground plane for sensitive analog

components. The analog ground plane (AGND) and power ground plane (PGND1, and PGND2) must be

connected at a single point directly under the IC (at the die attach pad or DAP).

Figure 41 shows the schematic of the high frequency loops of one synchronous buck channel. The current

flows through Q1 and Q2, through the power ground plane and back to VIN through the ceramic capacitors

C11 and C12. This loop must be as small as possible to minimize EMI. Refer to Figure 42 For the

recommended PCB layout.

11.2 Layout Example

Figure 41. Synchronous Buck Power Flow

38

LM5140-Q1

www.ti.com.cn

ZHCSEI6 –JANUARY 2016

Layout Example (continued)

D1/C17 High-Side Bootstrap Circuit

Buck High Frequency Current Path

R10/C10 Snubber

Figure 42. Synchronous Buck High Frequency Current Path

39

LM5140-Q1

ZHCSEI6 –JANUARY 2016

www.ti.com.cn

Layout Example (continued)

AGND Plane

AGND

PGND1

PGND2

Figure 43. AGND and PGND Connections

40

LM5140-Q1

www.ti.com.cn

ZHCSEI6 –JANUARY 2016

Layout Example (continued)

Figure 44. Top/Bottom PWM Layers

41

LM5140-Q1

ZHCSEI6 –JANUARY 2016

www.ti.com.cn

12 器件和文档支持

12.1 器件支持

12.2 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.3 商标

E2E is a trademark of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.4 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏

42

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IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道1568 号，中建大厦32 楼邮政编码： 200122

PACKAGE OUTLINE

RWG0040A

VQFN - 0.9 mm max height

SCALE 2.200

PLASTIC QUAD FLATPACK - NO LEAD

6.1

5.9

A

B

0.05

0.00

(0.09)

PIN 1 ID

DETAIL A

6.1

5.9

DETAIL

SCALE 20.000

A

TYPICAL

(

5.75)

(0.15)

DETAIL

B

S

C

A

L

E

2

0

.

0

DETAIL B

TYPICAL

0.9 MAX

C

SEATING PLANE

0.05 C

(0.2)

SEE DETAIL A

SEE DETAIL B

4X

45 X 0.6 MAX

11

20

10

21

SYMM

4X

3.3 0.1

4.5

1

30

0.3

40X

36X 0.5

0.2

40

31

SYMM

PIN 1 ID

(R0.2)

0.1

C B

C

A

0.5

0.3

0.05

40X

4221568/A 07/2014

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RWG0040A

VQFN - 0.9 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

3.3)

SYMM

40

31

40X (0.6)

40X (0.25)

1

30

36X (0.5)

4X

(1.4)

SYMM

(5.8)

(

0.2) TYP

VIA

10

21

11

20

(5.8)

LAND PATTERN EXAMPLE

SCALE:12X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL

UNDER SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4221568/A 07/2014

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

RWG0040A

VQFN - 0.9 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(5.8)

2X (1.63)

40

31

40X (0.6)

40X (0.25)

1

30

36X (0.5)

SYMM

2X

(1.63)

(5.8)

METAL

TYP

4X

1.43)

(

10

21

11

20

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

75% PRINTED SOLDER COVERAGE BY AREA

SCALE:12X

4221568/A 07/2014

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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型号：	LM5140QRWGTQ1
厂家：	TEXAS INSTRUMENTS
描述：	宽输入电压、双路 2.2MHz 低 Iq 同步降压控制器 \| RWG \| 40 \| -40 to 150 控制器开关
文件：	总49页 (文件大小：2726K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LM5140QRWGTQ1 [TI]

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