LM5163DDAR [TI]
具有超低 IQ 的 100V 输入、0.5A 同步降压直流/直流转换器 | DDA | 8 | -40 to 150;
| 型号： | LM5163DDAR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有超低 IQ 的 100V 输入、0.5A 同步降压直流/直流转换器 | DDA | 8 | -40 to 150 转换器 |
| 文件： | 总37页 (文件大小：2640K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LM5163
ZHCSKD6 –OCTOBER 2019
具有超低 IQ 的 LM5163 100V 输入、0.5A 同步降压直流/直流转换器
1 特性
2 应用
1
•
专为可靠耐用的应用 设计
•
•
•
工业电池组 (≥10S)
电池组 – 电动自行车/电动踏板车/LEV
–
–
–
–
–
6V 至 100V 的宽输入电压范围
结温范围：–40°C 至 +150°C
固定 3ms 内部软启动计时器
峰值和谷值电流限制保护
电机驱动器、无人机、通信设备
3 说明
LM5163 同步降压转换器用于在宽输入电压范围内进行
调节，从而最大限度地减少对外部浪涌抑制组件的需
求。50ns 的最短可控导通时间有助于实现较大的降压
比，支持从 48V 标称输入到低电压轨的直接降压转
换，从而降低系统的复杂性并减少解决方案成本。
LM5163 在输入电压突降至 6V 时能够根据需要以接近
100% 的占空比继续工作，使其成为宽输入电源范围工
业和高电池节数电池组 应用的理想选择。
输入 UVLO 和热关断保护
•
适用于可扩展的工业电源和电池组
–
–
–
–
–
最短导通时间和关闭时间低：50ns
高达 1MHz 的可调节开关频率
可实现高轻负载效率的二极管仿真
10.5µA 空载输入静态电流
3µA 关断静态电流
•
•
超低 EMI 辐射
针对 CISPR 25 5 类 标准进行了优化
通过集成技术减小解决方案尺寸，降低成本
LM5163 具有集成式高侧和低侧功率 MOSFET，可提
供高达 0.5A 的输出电流。恒定导通时间 (COT) 控制
架构可提供几乎恒定的开关频率，具有出色的负载和线
路瞬态响应。其他 特性 LM5163 的其他特性包括超低
IQ 和二极管仿真模式运行（可实现高轻负载效率）、
创新的峰值和谷值过流保护、集成式 VCC 偏置电源和
自举二极管、精密使能和输入 UVLO 以及具有自动恢
复功能的热关断保护。开漏 PGOOD 指示器可提供进
行定序、故障报告和输出电压监视功能。
–
–
–
–
COT 模式控制架构
集成式 0.725Ω NFET 降压开关
集成式 0.34Ω NFET 同步整流器省去了外部肖
特基二极管
–
–
–
–
–
1.2V 内部电压基准
无环路补偿组件
内部 VCC 偏置稳压器和自举二极管
漏极开路电源正常指示器
带 PowerPAD™ 的 8 引脚 SOIC 封装
LM5163 采用热增强型 8 引脚 SO PowerPAD™ 封
装。其 1.27mm 引脚间距可以为高电压 应用的实施。
•
使用 WEBENCH® 电源设计器创建定制稳压器设计
器件信息(1)
器件型号
LM5163
封装
封装尺寸（标称值）
SO PowerPAD (8)
4.89mm × 3.90mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
典型应用
典型应用效率，VOUT = 12V
100
VOUT = 12 V
IOUT = 0.5 A
LO
120 µH
U1
V
IN = 6 V...100 V
95
90
85
80
75
VIN
SW
CBST
LM5163
CIN
2.2 µF
2.2 nF RFB1
EN/UVLO
BST
FB
448 kW
COUT
22 µF
RON
RRON
RFB2
100 kW
70
VIN = 15V
VIN = 24V
49.9 kW
PGOOD
GND
65
60
VIN = 48V
VIN = 60V
*VOUT tracks VIN if VIN < 12 V
0.001
0.01
0.1
0.5
Load (A)
D001
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVSBB3
LM5163
ZHCSKD6 –OCTOBER 2019
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
8
9
Application and Implementation ........................ 16
8.1 Application Information............................................ 16
8.2 Typical Application .................................................. 16
Power Supply Recommendations...................... 23
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics ............................................. 7
Detailed Description .............................................. 9
7.1 Overview .................................................................. 9
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 15
10 Layout................................................................... 24
10.1 Layout Guidelines ................................................. 24
10.2 Layout Example .................................................... 26
11 器件和文档支持 ..................................................... 27
11.1 器件支持................................................................ 27
11.2 相关文档 ............................................................... 27
11.3 接收文档更新通知 ................................................. 27
11.4 支持资源................................................................ 28
11.5 商标....................................................................... 28
11.6 静电放电警告......................................................... 28
11.7 Glossary................................................................ 28
12 机械、封装和可订购信息....................................... 28
7
4 修订历史记录
日期
修订版本
说明
2019 年 10 月
*
初始发行版
2
版权 © 2019, Texas Instruments Incorporated
LM5163
www.ti.com.cn
ZHCSKD6 –OCTOBER 2019
5 Pin Configuration and Functions
DDA Package
8-Pin SO PowerPAD
Top View
GND
SW
VIN
BST
EP
EN/UVLO
PGOOD
RON
FB
Pin Functions
PIN
I/O(1)
DESCRIPTION
NO.
NAME
1
GND
G
Ground connection for internal circuits
Regulator supply input pin to high-side power MOSFET and internal bias regulator. Connect
directly to the input supply of the buck converter with short, low impedance paths.
2
3
VIN
P/I
Precision enable and undervoltage lockout (UVLO) programming pin. If the EN/UVLO voltage is
below 1.1 V, the converter is in shutdown mode with all functions disabled. If the UVLO voltage is
greater than 1.1 V and below 1.5 V, the converter is in standby mode with the internal VCC
regulator operational and no switching. If the EN/UVLO voltage is above 1.5 V, the start-up
sequence begins.
EN/UVLO
I
4
5
RON
FB
I
I
On-time programming pin. A resistor between this pin and GND sets the buck switch on-time.
Feedback input of voltage regulation comparator
Power good indicator. This pin is an open-drain output pin. Connect to a source voltage through an
external pullup resistor between 10 kΩ to 100 kΩ.
6
7
PGOOD
BST
O
Bootstrap gate-drive supply. Required to connect a high-quality 2.2-nF 50-V X7R ceramic capacitor
between BST and SW to bias the internal high-side gate driver.
P/I
Switching node that is internally connected to the source of the high-side NMOS buck switch and
the drain of the low-side NMOS synchronous rectifier. Connect to the switching node of the power
inductor.
8
SW
EP
P
Exposed pad of the package. No internal electrical connection. Solder the EP to the GND pin and
connect to a large copper plane to reduce thermal resistance.
—
—
(1) G = Ground, I = Input, O = Output, P = Power
Copyright © 2019, Texas Instruments Incorporated
3
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ZHCSKD6 –OCTOBER 2019
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6 Specifications
6.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of –40°C to +150°C (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
MAX
100
100
5.5
UNIT
VIN to GND
EN to GND
FB to GND
RON to GND
Input voltage
V
5.5
Bootstrap
capacitor
External BST to SW capacitance
1.5
2.5
nF
V
BST to GND
–0.3
–0.3
–1.5
–3
105.5
5.5
BST to SW
Output voltage
SW to GND
100
SW to GND (20-ns transient)
PGOOD to GND
–0.3
–40
–65
14
150
150
Operating junction temperature, TJ
Storage temperature, Tstg
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40°C to +150°C (unless otherwise noted)(1)
MIN
NOM
MAX
100
100
100
0.6
UNIT
V
VIN
Input voltage
6
VSW
Switch node voltage
Enable voltage
V
VEN/UVLO
ILOAD
FSW
V
Load current
0.5
2.2
A
Switching frequency
External BST to SW capacitance
Programmable on-time
1000
kHz
nF
ns
CBST
tON
50
10000
4
Copyright © 2019, Texas Instruments Incorporated
LM5163
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ZHCSKD6 –OCTOBER 2019
6.4 Thermal Information
LM5163
DDA (SOIC)
8 PINS
43.4
THERMAL METRIC
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
59.5
16.1
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
4.0
ΨJB
16.3
RθJC(bot)
3.9
6.5 Electrical Characteristics
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the full –40°C to 150°C junction
temperature range unless otherwise indicated. VIN = 24 V and VEN/UVLO = 2 V unless otherwise stated.
PARAMETER
SUPPLY CURRENT
IQ-SHUTDOWN VIN shutdown current
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VEN = 0 V
3
10.5
600
15
25
µA
µA
µA
IQ-SLEEP1
IQ-ACTIVE
EN/UVLO
VSD-RISING
VSD-FALLING
VEN-RISING
VEN-FALLING
FEEDBACK
VREF
VIN sleep current
VIN active current
VEN = 2.5 V, VFB = 1.5 V
VEN = 2.5 V
880
Shutdown threshold
Shutdown threshold
Enable threshold
Enable threshold
VEN/UVLO rising
VEN/UVLO falling
VEN/UVLO rising
VEN/UVLO falling
1.1
V
V
V
V
0.45
1.45
1.35
1.5
1.4
1.55
1.44
FB regulation voltage
VFB falling
1.181
1.2
1.218
V
TIMING
tON1
On-time1
On-time2
On-time3
On-time4
VVIN = 6 V, RRON = 75 kΩ
VVIN = 6 V, RRON = 25 kΩ
VVIN = 12 V, RRON = 75 kΩ
VVIN = 12 V, RRON = 25 kΩ
5000
650
ns
ns
ns
ns
tON2
tON3
2550
830
tON4
PGOOD
FB upper threshold for PGOOD high
to low
VPG-UTH
VPG-LTH
VPG-HYS
VFB rising
VFB falling
1.105
1.055
1.14
1.08
1.175
1.1
V
V
FB lower threshold for PGOOD high to
low
PGOOD upper and lower threshold
hysteresis
VFB falling
VFB = 1 V
60
30
mV
RPG
PGOOD pulldown resistance
Ω
BOOTSTRAP
VBST-UV
Gate drive UVLO
VBST rising
2.7
3.4
V
POWER SWITCHES
RDSON-HS High-side MOSFET RDSON
RDSON-LS Low-side MOSFET RDSON
ISW = –100 mA
ISW = 100 mA
0.725
0.33
Ω
Ω
Copyright © 2019, Texas Instruments Incorporated
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Electrical Characteristics (continued)
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the full –40°C to 150°C junction
temperature range unless otherwise indicated. VIN = 24 V and VEN/UVLO = 2 V unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SOFT START
tSS
Internal soft-start time
1.75
3
4.75
ms
CURRENT LIMIT
IPEAK1
Peak current limit threshold (HS)
0.63
0.63
0.75
0.75
100
0.6
0.87
0.87
A
A
IPEAK2
Peak current limit threshold (LS)
Min of (IPEAK1 or IPEAK2) minus IVALLEY
Valley current limit threshold
IDELTA-ILIM
IVALLEY
mA
A
0.5
0.72
THERMAL SHUTDOWN
TSD
Thermal shutdown threshold
Thermal shutdown hysteresis
TJ rising
175
10
°C
°C
TSD-HYS
6
版权 © 2019, Texas Instruments Incorporated
LM5163
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ZHCSKD6 –OCTOBER 2019
6.6 Typical Characteristics
At TA = 25°C, VOUT = 12 V, LO = 120 µH, RRON = 105 kΩ, unless otherwise specified.
100
95
90
85
80
75
70
65
60
100
90
80
70
60
VIN = 15V
VIN = 24V
VIN = 48V
VIN = 60V
VIN = 15V
VIN = 24V
VIN = 48V
VIN = 60V
0.001
0.01
0.1
0.5
0
0.1
0.2
0.3
0.4
0.5
Load (A)
Load (A)
D001
D002
图 1. Conversion Efficiency (Log Scale)
图 2. Conversion Efficiency (Linear Scale)
25
20
15
10
5
25
20
15
10
5
Sleep
Shutdown
Sleep
Shutdown
0
0
-50
-25
0
25
50
75
100
125
150
0
10
20
30
40
Input Voltage (V)
50
60
70
80
90 100
Junction Temperature (èC)
D005
D006
图 3. VIN Shutdown and Sleep Supply Current versus
图 4. VIN Shutdown and Sleep Supply Current versus Input
Temperature
Voltage
725
600
580
560
540
520
500
700
675
650
625
600
575
550
-50
-25
0
25
50
75
100
125
150
0
10
20
30
40
50
60
Input Voltage (V)
70
80
90 100
Junction Temperature (èC)
D007
D008
图 5. VIN Active Current versus Temperature
图 6. VIN Active Current versus Input Voltage
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7
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ZHCSKD6 –OCTOBER 2019
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Typical Characteristics (接下页)
At TA = 25°C, VOUT = 12 V, LO = 120 µH, RRON = 105 kΩ, unless otherwise specified.
1.21
1.205
1.2
1.4
1.2
1
0.8
0.6
0.4
0.2
0
1.195
High-Side FET
Low-Side FET
1.19
-50
-25
0
25
50
75
100
125
150
-50
-25
0
25
50
75
100
125
150
Junction Temperature (èC)
Junction Temperature (èC)
D009
D010
图 7. Feedback Comparator Threshold versus Temperature
0.8
图 8. MOSFETs On-State Resistance versus Temperature
6
5
4
3
2
1
0
RRT = 105 kW
RRT = 43.2 kW
0.7
0.6
0.5
0.4
Peak Current
Valley Current
-50
-25
0
25
50
75
100
125
150
0
10
20
30
40
50
60
Input Voltage (V)
70
80
90 100
Junction Temperature (èC)
D011
D012
图 9. Peak and Valley Current Limit versus Temperature
图 10. COT On-Time versus VIN
8
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LM5163
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ZHCSKD6 –OCTOBER 2019
7 Detailed Description
7.1 Overview
The LM5163 is an easy-to-use, ultra-low IQ constant on-time (COT) synchronous step-down buck regulator. With
integrated high-side and low-side power MOSFETs, the LM5163 is a low-cost, highly efficient buck converter that
operates from a wide input voltage of 6 V to 100 V, delivering up to 0.5-A DC load current. The LM5163 is
available in an 8-pin SO Power PAD package with 1.27-mm pin pitch for adequate spacing in high-voltage
applications. This constant on-time (COT) converter is ideal for low-noise, high-current, and fast load transient
requirements, operating with a predictive on-time switching pulse. Over the input voltage range, input voltage
feedforward is employed to achieve a quasi-fixed switching frequency. A controllable on-time as low as 50 ns
permits high step-down ratios and a minimum forced off-time of 50 ns provides extremely high duty cycles,
allowing VIN to drop close to VOUT before frequency foldback occurs. At light loads, the device transitions into an
ultra-low IQ mode to maintain high efficiency and prevent draining battery cells connected to the input when the
system is in standby. The LM5163 implements a smart peak and valley current limit detection circuit to ensure
robust protection during output short circuit conditions. Control loop compensation is not required for this
regulator, reducing design time and external component count.
The LM5163 incorporates additional features for comprehensive system requirements, including an open-drain
power good circuit for the following:
•
•
•
•
•
•
Power-rail sequencing and fault reporting
Internally-fixed soft start
Monotonic start-up into prebiased loads
Precision enable for programmable line undervoltage lockout (UVLO)
Smart cycle-by-cycle current limit for optimal inductor sizing
Thermal shutdown with automatic recovery
These features enable a flexible and easy-to-use platform for a wide range of applications. The LM5163 supports
a wide range of end-equipment systems requiring a regulated output from a high input supply where the transient
voltage deviates from the DC level. The following are examples of such end equipment systems:
•
•
•
•
48-V automotive systems
High cell-count battery-pack systems
24-V industrial systems
48-V telecom and PoE voltage ranges
The pin arrangement is designed for a simple layout requiring only a few external components.
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LM5163
ZHCSKD6 –OCTOBER 2019
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7.2 Functional Block Diagram
VIN
VIN
VDD
BIAS
REGULATOR
CIN
VDD UVLO
RUV1
EN/UVLO
œ
STANDBY
+
THERMAL
SHUTDOWN
RUV2
1.5 V
œ
SHUTDOWN
BST
+
LOGIC
0.4 V
VIN
CBST
RON
ON/OFF
TIMERS
DISABLE
CONSTANT
ON-TIME
CONTROL
LOGIC
VOUT
LO
VOUT
SW
VCC
RFB1
FEEDBACK
COMPARATOR
SLEEP
COUT
FB
DETECT
œ
ZC
+
RRON
VREF
+
PGOOD
ZX DETECT
œ
RFB2
PEAK/VALLEY
CURRENT LIMIT
œ
+
FB
GND
PGOOD
COMPARATOR
0.9*VREF
7.3 Feature Description
7.3.1 Control Architecture
The LM5163 step-down switching converter employs a constant on-time (COT) control scheme. The COT control
scheme sets a fixed on-time tON of the high-side FET using a timing resistor (RON). The tON is adjusted as Vin
changes and is inversely proportional to the input voltage to maintain a fixed frequency when in continuous
conduction mode (CCM). After expiration of tON, the high-side FET remains off until the feedback pin is equal or
below the reference voltage of 1.2 V. To maintain stability, the feedback comparator requires a minimal ripple
voltage that is in phase with the inductor current during the off-time. Furthermore, this change in feedback
voltage during the off-time must be large enough to dominate any noise present at the feedback node. The
minimum recommended ripple voltage is 20 mV. See 表 1 for different types of ripple injection schemes that
ensure stability over the full input voltage range.
During a rapid start-up or a positive load step, the regulator operates with minimum off-times until regulation is
achieved. This feature enables extremely fast load transient response with minimum output voltage undershoot.
When regulating the output in steady-state operation, the off-time automatically adjusts itself to produce the SW-
pin duty cycle required for output voltage regulation to maintain a fixed switching frequency. In CCM, the
switching frequency FSW is programmed by the RRON resistor. Use 公式 1 to calculate the switching frequency.
VOUT (V)∂ 2500
FSW (kHz) =
RRON(kW)
(1)
10
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LM5163
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ZHCSKD6 –OCTOBER 2019
Feature Description (接下页)
表 1. Ripple Generation Methods
TYPE 1
TYPE 2
TYPE 3
Lowest Cost
Reduced Ripple
Minimum Ripple
LO
LO
VOUT
VIN
LO
VOUT
VIN
VOUT
VIN
VIN
SW
VIN
SW
VIN
SW
RA
CA
LM5163
CBST
LM5163
LM5163
CBST
CFF
CIN
CIN
RFB1
CBST
RFB1
RESR
RESR
EN/UVLO
BST
FB
EN/UVLO
BST
FB
EN/UVLO
BST
FB
RFB1
COUT
CB
RON
RON
RON
RFB2
COUT
RFB2
COUT
RRON
RRON
RRON
RFB2
PGOOD
GND
PGOOD
GND
PGOOD
GND
10
CA
í
20mV
RESR
í
FSW ∂(RFB1 || RFB2
)
(7)
DIL(nom)
VOUT
20mV ∂ VOUT
(4)
(5)
(6)
RESR
í
RACA
Ç
VFB1 ∂ DIL(nom)
(2)
(3)
RESR
í
V
- VOUT ∂ t
(
)
20mV
IN-nom
ON @V
(
)
IN-nom
2∂ V ∂FSW ∂COUT
VOUT
IN
RESR
í
(8)
(9)
2∂ V ∂FSW ∂COUT
1
IN
tTR-settling
CFF
í
CB í
2p ∂FSW ∂(RFB1 || RFB2
)
3∂RFB1
表 1 presents three different methods for generating appropriate voltage ripple at the feedback node. Type-1
ripple generation method uses a single resistor, RESR, in series with the output capacitor. The generated voltage
ripple has two components: capacitive ripple caused by the inductor ripple current charging and discharging the
output capacitor and resistive ripple caused by the inductor ripple current flowing into the output capacitor and
through series resistance RESR. The capacitive ripple component is out of phase with the inductor current and
does not decrease monotonically during the off-time. The resistive ripple component is in phase with the inductor
current and decreases monotonically during the off-time. The resistive ripple must exceed the capacitive ripple at
VOUT for stable operation. If this condition is not satisfied, unstable switching behavior is observed in COT
converters, with multiple on-time bursts in close succession followed by a long off time. 公式 2 and 公式 3 define
the value of the series resistance RESR to ensure sufficient in-phase ripple at the feedback node.
Type-2 ripple generation uses a CFF capacitor in addition to the series resistor. As the output voltage ripple is
directly AC-coupled by CFF to the feedback node, the RESR and ultimately the output voltage ripple are reduced
by a factor of VOUT / VFB1
.
Type-3 ripple generation uses an RC network consisting of RA and CA, and the switch node voltage to generate a
triangular ramp that is in-phase with the inductor current. This triangular wave is the AC-coupled into the
feedback node with capacitor CB. Because this circuit does not use output voltage ripple, it is suited for
applications where low output voltage ripple is critical. The AN-1481 Controlling Output Ripple and Achieving
ESR Independence in Constant On-time (COT) Regulator Designs Application Note provides additional details
on this topic.
Diode emulation mode (DEM) prevents negative inductor current, and pulse skipping maintains the highest
efficiency at light load currents by decreasing the effective switching frequency. DEM operation occurs when the
synchronous power MOSFET switches off as inductor valley current reaches zero. Here, the load current is less
than half of the peak-to-peak inductor current ripple in CCM. Turning off the low-side MOSFET at zero current
reduces switching loss, and preventing negative current conduction reduces conduction loss. Power conversion
efficiency is higher in a DEM converter than an equivalent forced-PWM CCM converter. With DEM operation, the
duration that both power MOSFETs remain off progressively increases as load current decreases. When this idle
duration exceeds 15 μs, the converter transitions into an ultra-low IQ mode, consuming only 10-μA quiescent
current from the input.
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Feature Description (接下页)
7.3.2 Internal VCC Regulator and Bootstrap Capacitor
The LM5163 contains an internal linear regulator that is powered from VIN with a nominal output of 5 V,
eliminating the need for an external capacitor to stabilize the linear regulator. The internal VCC regulator supplies
current to internal circuit blocks including the synchronous FET driver and logic circuits. The input pin (VIN) can
be connected directly to line voltages up to 100 V. As the power MOSFET has a low total gate charge, use a low
bootstrap capacitor value to reduce the stress on the internal regulator. It is required to select a high-quality 2.2-
nF 50-V X7R ceramic bootstrap capacitor as specified in the Absolute Maximum Ratings section. Selecting a
higher value capacitance stresses the internal VCC regulator and damages the device. A lower capacitance than
required is not sufficient to drive the internal gate of the power MOSFET. An internal diode connects from the
VCC regulator to the BST pin to replenish the charge in the high-side gate drive bootstrap capacitor when the
SW voltage is low.
7.3.3 Regulation Comparator
The feedback voltage at FB is compared to an internal 1.2-V reference. The LM5163 voltage regulation loop
regulates the output voltage by maintaining the FB voltage equal to the internal reference voltage, VREF. A
resistor divider programs the ratio from output voltage VOUT to FB.
For a target VOUT setpoint, use 公式 10 to calculate RFB2 based on the selected RFB1
.
1.2V
RFB2
=
∂RFB1
VOUT -1.2V
(10)
TI recommends selecting RFB1 in the range of 100 kΩ to 1 MΩ for most applications. A larger RFB1 consumes
less DC current, which is mandatory if light-load efficiency is critical. RFB1 larger than 1 MΩ is not recommended
as the feedback path becomes more susceptible to noise. It is important to route the feedback trace away from
the noisy area of the PCB and keep the feedback resistors close to the FB pin.
7.3.4 Internal Soft Start
The LM5163 employs an internal soft-start control ramp that allows the output voltage to gradually reach a
steady-state operating point, thereby reducing start-up stresses and current surges. The soft-start feature
produces a controlled, monotonic output voltage start-up. The soft-start time is internally set to 3 ms.
7.3.5 On-Time Generator
The on-time of the LM5163 high-side FET is determined by the RRON resistor and is inversely proportional to the
input voltage, VIN. The inverse relationship with VIN results in a nearly constant frequency as VIN is varied. Use 公
式 11 to calculate the on-time.
RRON kW
(
)
tON ꢀs =
(
)
V
V ∂ 2.5
)
(
IN
(11)
Use 公式 12 to determine the RRON resistor to set a specific switching frequency in CCM.
VOUT (V)∂2500
RRON(kW) =
FSW (kHz)
(12)
Select RRON for a minimum on-time (at maximum VIN) greater than 50 ns for proper operation. In addition to this
minimum on-time, the maximum frequency for this device is limited to 1 MHz.
7.3.6 Current Limit
The LM5163 manages overcurrent conditions with cycle-by-cycle current limiting of the peak inductor current.
The current sensed in the high-side MOSFET is compared every switching cycle to the current limit threshold
(0.75 A). To protect the converter from potential current runaway conditions, the LM5163 includes a foldback
valley current limit feature, set at 0.6 A, that is enabled if a peak current limit is detected. As shown in 图 11, if
the peak current in the high-side MOSFET exceeds 0.75 A (typical), the present cycle is immediately terminated
12
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Feature Description (接下页)
regardless of the programmed on-time (tON), the high-side MOSFET is turned off and the foldback valley current
limit is activated. The low-side MOSFET remains on until the inductor current drops below this foldback valley
current limit, after which the next on-pulse is initiated. This method folds back the switching frequency to prevent
overheating and limits the average output current to less than 0.75 A to ensure proper short-circuit and heavy-
load protection of the LM5163.
vFB
VREF
iL
Peak ILIM
IAVG(ILIM)
Valley ILIM
IAVG1
t
tON
tSW
< tON
> tSW
图 11. Current Limit Timing Diagram
Current is sensed after a leading-edge blanking time following the high-side MOSFET turnon transition. The
propagation delay of the current limit comparator is 100 ns. During high step-down conditions when the on-time
is less than 100 ns, a back-up peak current limit comparator in the low-side FET also set at 0.75 A enables the
foldback valley current limit set at 0.6 A. This innovative current limit scheme enables ultra-low duty-cycle
operation, permitting large step-down voltage conversions while ensuring robust protection of the converter.
7.3.7 N-Channel Buck Switch and Driver
The LM5163 integrates an N-channel buck switch and associated floating high-side gate driver. The gate-driver
circuit works in conjunction with an external bootstrap capacitor and an internal high-voltage bootstrap diode. A
high-quality 2.2-nF, 50-V X7R ceramic capacitor connected between the BST and SW pins provides the voltage
to the high-side driver during the buck switch on-time. See the Internal VCC Regulator and Bootstrap Capacitor
section for limitations. During the off-time, the SW pin is pulled down to approximately 0 V, and the bootstrap
capacitor charges from the internal VCC through the internal bootstrap diode. The minimum off-timer, set to 50
ns (typical), ensures a minimum time each cycle to recharge the bootstrap capacitor. When the on-time is less
than 300 ns, the minimum off-timer is forced to 250 ns to ensure that the BST capacitor is charged in a single
cycle. This is vital during wake up from sleep mode when the BST capacitor is most likely discharged.
7.3.8 Synchronous Rectifier
The LM5163 provides an internal low-side synchronous rectifier N-channel MOSFET. This MOSFET provides a
low-resistance path for the inductor current to flow when the high-side MOSFET is turned off.
The synchronous rectifier operates in a diode emulation mode. Diode emulation enables the regulator to operate
in a pulse-skipping mode during light load conditions. This mode leads to a reduction in the average switching
frequency at light loads. Switching losses and FET gate driver losses, both of which are proportional to switching
frequency, are significantly reduced at very light loads and efficiency is improved. This pulse-skipping mode also
reduces the circulating inductor current and losses associated with conventional CCM at light loads.
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Feature Description (接下页)
7.3.9 Enable/Undervoltage Lockout (EN/UVLO)
The LM5163 contains a dual-level EN/UVLO circuit. When the EN/UVLO voltage is below 1.1 V (typical), the
converter is in a low-current shutdown mode and the input quiescent current (IQ) is dropped down to 3 µA. When
the voltage is greater than 1.1 V but less than 1.5 V (typical), the converter is in standby mode. In standby mode
the internal bias regulator is active while the control circuit is disabled. When the voltage exceeds the rising
threshold of 1.5 V (typical), normal operation begins. Install a resistor divider from VIN to GND to set the
minimum operating voltage of the regulator. Use 公式 13 and 公式 14 to calculate the input UVLO turnon and
turnoff voltages, respectively.
≈
’
÷
◊
RUV1
RUV2
V
= 1.5V ∂ 1+
∆
IN(on)
«
(13)
≈
’
÷
◊
RUV1
RUV2
V
= 1.4V ∂ 1+
∆
IN(off)
«
(14)
TI recommends selecting RUV1 in the range of 1 MΩ for most applications. A larger RUV1 consumes less DC
current, which is mandatory if light-load efficiency is critical. If input UVLO is not required, the power-supply
designer can either drive EN/UVLO as an enable input driven by a logic signal or connect it directly to VIN. If
EN/UVLO is directly connected to VIN, the regulator begins switching as soon as the internal bias rails are
active.
7.3.10 Power Good (PGOOD)
The LM5163 provides a PGOOD flag pin to indicate when the output voltage is within the regulation level. Use
the PGOOD signal for start-up sequencing of downstream converters or for fault protection and output
monitoring. PGOOD is an open-drain output that requires a pullup resistor to a DC supply not greater than 14 V.
The typical range of pullup resistance is 10 kΩ to 100 kΩ. If necessary, use a resistor divider to decrease the
voltage from a higher voltage pullup rail. When the FB voltage exceeds 95% of the internal reference VREF, the
internal PGOOD switch turns off and PGOOD can be pulled high by the external pullup. If the FB voltage falls
below 90% of VREF, an internal 25-Ω PGOOD switch turns on and PGOOD is pulled low to indicate that the
output voltage is out of regulation. The rising edge of PGOOD has a built-in deglitch delay of 5 µs.
7.3.11 Thermal Protection
The LM5163 includes an internal junction temperature monitor to protect the device in the event of a higher than
normal junction temperature. If the junction temperature exceeds 175°C (typical), thermal shutdown occurs to
prevent further power dissipation and temperature rise. The LM5163 initiates a restart sequence when the
junction temperature falls to 165°C, based on a typical thermal shutdown hysteresis of 10°C. This is a non-
latching protection, so the device cycles into and out of thermal shutdown if the fault persists.
14
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7.4 Device Functional Modes
7.4.1 Shutdown Mode
EN/UVLO provides ON and OFF control for the LM5163. When VEN/UVLO is below approximately 1.1 V, the
device is in shutdown mode. Both the internal linear regulator and the switching regulator are off. The quiescent
current in shutdown mode drops to 3 µA at VIN = 24 V. The LM5163 also employs internal bias rail undervoltage
protection. If the internal bias supply voltage is below the UV threshold, the regulator remains off.
7.4.2 Active Mode
The LM5163 is in active mode when VEN/UVLO is above the precision enable threshold and the internal bias rail is
above its UV threshold. In COT active mode, the LM5163 is in one of three modes depending on the load
current:
1. CCM with fixed switching frequency when load current is above half of the peak-to-peak inductor current
ripple
2. Pulse skipping and diode emulation mode (DEM) when the load current is less than half of the peak-to-peak
inductor current ripple in CCM operation
3. Current limit CCM with peak and valley current limit protection when an overcurrent condition is applied at
the output
7.4.3 Sleep Mode
The Control Architecture section gives a brief introduction to the LM5163 diode emulation (DEM) feature. The
converter enters DEM during light-load conditions when the inductor current decays to zero and the synchronous
MOSFET is turned off to prevent negative current in the system. In the DEM state, the load current is lower than
half of the peak-to-peak inductor current ripple and the switching frequency decreases when the load is further
decreased as the device operates in a pulse skipping mode. A switching pulse is set when VFB drops below 1.2
V.
As the frequency of operation decreases and VFB remains above 1.2 V (VREF) with the output capacitor sourcing
the load current for greater than 15 µs, the converter enters an ultra-low IQ sleep mode to prevent draining the
input power supply. The input quiescent current (IQ) required by the LM5163 decreases to 10 µA in sleep mode,
improving the light-load efficiency of the regulator. In this mode, all internal controller circuits are turned off to
ensure very low current consumption by the device. Such low IQ renders the LM5163 as the best option to
extend operating lifetime for off-battery applications. The FB comparator and internal bias rail are active to detect
when the FB voltage drops below the internal reference VREF and the converter transitions out of sleep mode into
active mode. There is a 9-µs wake-up delay from sleep to active states.
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM5163 requires only a few external components to step down from a wide range of supply voltages to a
fixed output voltage. Several features are integrated to meet system design requirements, including the following:
•
•
•
•
•
Precision enable
Input voltage UVLO
Internal soft start
Programmable switching frequency
A PGOOD indicator
To expedite and streamline the process of designing of a LM5163-based converter, a comprehensive LM5163
quickstart calculator is available for download to assist the designer with component selection for a given
application. This tool is complemented by the availability of an evaluation module (EVM), numerous PSPICE
models, as well as TI's WEBENCH® Power Designer. In order to modify the LM5164-Q1EVM-041 for the
LM5163-Q1, change the inductor LO to 120 µH, the resistor RA to 226 kΩ, and the capacitance COUT to 22 µF.
See 图 12 for the LM5163-Q1 applications circuit.
8.2 Typical Application
图 12 shows the schematic for a 12-V 0.5-A COT converter.
VOUT = 12 V
LO
IOUT = 0.5 A
U1
VIN = 15 V...100 V
120 mH
VIN
SW
CA
3.3 nF
RA
CBST
LM5163
CIN
226 kW
2.2 nF
RFB1
2.2 mF
EN/UVLO
BST
FB
453 kW
COUT
CB
22 mF
56 pF
RON
RRON
RFB2
100 kW
PGOOD
GND
49.9 kW
Copyright © 2018, Texas Instruments Incorporated
图 12. Typical Application VIN(nom) = 48 V, VOUT = 12 V, IOUT(max) = 0.5 A, FSW(nom) = 300 kHz
注
This and subsequent design examples are provided herein to showcase the LM5163
converter in several different applications. Depending on the source impedance of the
input supply bus, an electrolytic capacitor may be required at the input to ensure stability,
particularly at low input voltage and high output current operating conditions. See the
Power Supply Recommendations section for more details.
16
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LM5163
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Typical Application (接下页)
8.2.1 Design Requirements
The target full-load efficiency is 92% based on a nominal input voltage of 48 V and an output voltage of 12 V.
The required input voltage range is 15 V to 100 V. The LM5163 delivers a fixed 12-V output voltage. The
switching frequency is set by resistor RRON at 300 kHz. The output voltage soft-start time is 3 ms. 表 2 lists the
required components. Refer to the LM5164-Q1EVM-041 User's Guide for more detail.
表 2. List of Components
COUNT
REF DES
CIN
VALUE
2.2 µF
22 µF
DESCRIPTION
PART NUMBER
CGA6N3X7R2A225K230AB
TMK325B7226KMHT
CGA3E2X7R2A332K080AA
C0603C560J5GACTU
GCM155R71H222KA37D
MSS1260-124KL
MANUFACTURER
TDK
2
1
1
1
1
1
1
1
1
1
1
Capacitor, Ceramic, 2.2 µF, 100 V, X7R, 10%
Capacitor, Ceramic, 22 µF, 25 V, X7R, 10%
Capacitor, Ceramic, 3300 pF, 16 V, X7R, 10%
Capacitor, Ceramic, 56 pF, 50 V, X7R, 10%
Capacitor, Ceramic, 2200 pF, 50 V, X7R, 10%
Inductor, 120 µH, 210 mΩ, 1.65 A
COUT
CA
Taiyo Yuden
TDK
3300 pF
56 pF
CB
Kemet
CBST
LO
2.2 nF
120 µH
100 kΩ
453 kΩ
49.9 kΩ
226 kΩ
MuRata
Coilcraft
Susumu Co Ltd
Yageo
RRON
RFB1
RFB2
RA
Resistor, Chip, 100 k, 1%, 0.1 W, 0603
Resistor, Chip, 453 k, 1%, 0.1 W, 0603
Resistor, Chip, 49.9 k, 1%, 0.1 W, 0603
Resistor, Chip, 226 k, 1%, 0.1W, 0603
Wide VIN synchronous buck converter
RG1608P-1053-B-T5
RT0603BRD07448KL
RG1608P-4992-B-T5
RT0603BRD07226KL
LM5163DDAR
Susumu Co Ltd
Yageo
U1
TI
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM5163 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Switching Frequency (RRON
)
The switching frequency of the LM5163 is set by the on-time programming resistor placed at RON. As shown by
公式 15, a standard 100 kΩ, 1% resistor sets the switching frequency at 300 kHz.
VOUT (V)∂2500
RRON(kW) =
FSW (kHz)
(15)
Note that at very low duty cycles, the 50 ns minimum controllable on-time of the high-side MOSFET, tON(min)
,
limits the maximum switching frequency. In CCM, tON(min) limits the voltage conversion step-down ratio for a given
switching frequency. Use 公式 16 to calculate the minimum controllable duty cycle.
DMIN = tON(min) ∂FSW
(16)
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Ultimately, the choice of switching frequency for a given output voltage affects the available input voltage range,
solution size, and efficiency. Use 公式 17 to calculate the maximum supply voltage for a given tON(min) before
switching frequency reduction occurs.
VOUT
V
=
IN(max)
tON(min) ∂FSW
(17)
8.2.2.3 Buck Inductor (LO)
Use 公式 18 and 公式 19 to calculate the inductor ripple current (assuming CCM operation) and peak inductor
current, respectively.
≈
’
÷
◊
VOUT
VOUT
DIL =
∂ 1-
∆
FSW ∂LO
V
IN
«
(18)
(19)
DIL
2
IL(peak) = IOUT(max)
+
For most applications, choose an inductance such that the inductor ripple current, ΔIL, is between 30% and 50%
of the rated load current at nominal input voltage. Use 公式 20 to calculate the inductance.
≈
∆
«
’
VOUT
VOUT
LO
=
∂ 1-
∆
÷
÷
◊
FSW ∂ DIL
V
IN(nom)
(20)
Choosing a 120-μH inductor in this design results in 250-mA peak-to-peak ripple current at a nominal input
voltage of 48 V, equivalent to 50% of the 500-mA rated load current.
Check the inductor data sheet to make sure the saturation current of the inductor is well above the current limit
setting of the LM5163. Ferrite-core inductors have relatively lower core losses and are preferred at high switching
frequencies, but exhibit a hard saturation characteristic – the inductance collapses abruptly when the saturation
current is exceeded. This results in an abrupt increase in inductor ripple current, higher output voltage ripple, and
reduced efficiency, in turn compromising reliability. Note that inductor saturation current levels generally
decrease as the core temperature increases.
8.2.2.4 Output Capacitor (COUT
)
Select a ceramic output capacitor to limit the capacitive voltage ripple at the converter output. This is the
sinusoidal ripple voltage that is generated from the triangular inductor current ripple flowing into and out of the
capacitor. Select an output capacitance using 公式 21 to limit the voltage ripple component to 0.5% of the output
voltage.
DIL
COUT
í
8 ∂FSW ∂ VOUT(ripple)
(21)
Substituting ΔIL(nom) of 250-mA gives COUT greater than 3.1 μF. With voltage coefficients of ceramic capacitors
taken in consideration, a 22-µF, 25-V rated capacitor with X7R dielectric is selected.
8.2.2.5 Input Capacitor (CIN)
An input capacitor is necessary to limit the input ripple voltage while providing AC current to the buck power
stage at every switching cycle. To minimize the parasitic inductance in the switching loop, position the input
capacitors as close as possible to the VIN and GND pins of the LM5163. The input capacitors conduct a square-
wave current of peak-to-peak amplitude equal to the output current. It follows that the resultant capacitive
component of AC ripple voltage is a triangular waveform.
Along with the ESR-related ripple component, use 公式 22 to calculate the peak-to-peak ripple voltage amplitude.
IOUT ∂D ∂ 1-D
IN(ripple)
(
)
+ IOUT ∂RESR
V
=
FSW ∂CIN
(22)
18
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Use 公式 23 to calculate the input capacitance required for a load current, based on an input voltage ripple
specification (ΔVIN).
IOUT ∂D∂ 1- D
(
)
CIN
í
FSW ∂ V
-IOUT ∂RESR
IN(ripple)
(23)
The recommended high-frequency input capacitance is 2.2 µF or higher. Ensure the input capacitor is a high-
quality X7S or X7R ceramic capacitor with sufficient voltage rating for CIN. Based on the voltage coefficient of
ceramic capacitors, choose a voltage rating of twice the maximum input voltage. Additionally, some bulk
capacitance is required if the LM5163 is not located within approximately 5 cm from the input voltage source.
This capacitor provides parallel damping to the resonance associated with parasitic inductance of the supply
lines and high-Q ceramics. See the Power Supply Recommendations section for more detail.
8.2.2.6 Type 3 Ripple Network
A Type 3 ripple generation network uses an RC filter consisting of RA and CA across SW and VOUT to generate a
triangular ramp that is in phase with the inductor current. This triangular ramp is then AC-coupled into the
feedback node using capacitor CB as shown in 图 12. Type 3 ripple injection is suited for applications where low
output voltage ripple is crucial.
Use 公式 24 and 公式 25 to calculate RA and CA to provide the required ripple amplitude at the FB pin.
10
CA
í
FSW ∂ R
RFB2
FB1
(24)
For the feedback resistor values given in 图 12, 公式 24 dictates a minimum CA of 742 pF. In this design, a 3300
pF capacitance is chosen. This is done to keep RA within practical limits between 100 kΩ and 1 MΩ when using
公式 25.
V
- VOUT ∂ t
(
)
IN(nom)
ON(nom)
RACA
í
20mV
(25)
Based on CA set at 3.3 nF, RA is calculated to be 226 kΩ to provide a 20-mV ripple voltage at FB. The general
recommendation for a Type 3 network is to calculate RA and CA to get 20 mV of ripple at typical operating
conditions, while ensuring a 12-mV minimum ripple voltage on FB at minimum VIN.
While the amplitude of the generated ripple does not affect the output voltage ripple, it impacts the output
regulation as it reflects as a DC error of approximately half the amplitude of the generated ripple. For example, a
converter circuit with Type 3 network that generates a 40-mV ripple voltage at the feedback node has
approximately 10-mV worse load regulation scaled up through the FB divider to VOUT than the same circuit that
generates a 20-mV ripple at FB. Use 公式 26 to calculate the coupling capacitance CB.
tTR-settling
CB í
3∂RFB1
where
•
tTR-settling is the desired load transient response settling time
(26)
CB calculates to 56 pF based on a 75-µs settling time. This value avoids excessive coupling capacitor discharge
by the feedback resistors during sleep intervals when operating at light loads. To avoid capacitance fall-off with
DC bias, use a C0G or NP0 dielectric capacitor for CB.
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8.2.3 Application Curves
100
95
90
85
80
75
70
65
60
100
90
80
70
60
VIN = 15V
VIN = 24V
VIN = 48V
VIN = 60V
VIN = 15V
VIN = 24V
VIN = 48V
VIN = 60V
0.001
0.01
0.1
0.5
0
0.1
0.2
0.3
0.4
0.5
Load (A)
Load (A)
D001
D002
图 13. Conversion Efficiency (Log Scale)
图 14. Conversion Efficiency (Linear Scale)
12.6
12.5
12.4
12.3
12.2
12.1
12
VOUT 100mV/DIV
VIN = 15V
IOUT 250mA/DIV
VIN = 24V
VIN = 48V
VIN = 60V
11.9
11.8
100 µs/DIV
0
0.1
0.2 0.3
Output Current (A)
0.4
0.5
Load
VIN = 24 V
IOUT = 0.125 A to 0.5 A at 0.1
A/μs
图 15. Load and Line Regulation Performance
图 16. Load Step Response
VIN 10V/DIV
VIN 10V/DIV
VOUT 2V/DIV
VOUT 2V/DIV
IOUT 100mA/DIV
IOUT 100mA/DIV
1 ms/DIV
1 ms/DIV
VIN = 24 V
IOUT = 0 A
VIN = 24 V
IOUT = 0.5 A (Resistive)
图 17. No-Load Start-up with VIN
图 18. Full-Load Start-up with VIN
20
版权 © 2019, Texas Instruments Incorporated
LM5163
www.ti.com.cn
ZHCSKD6 –OCTOBER 2019
EN 5V/DIV
EN 5V/DIV
VOUT 5V/DIV
VOUT 5V/DIV
IOUT 500mA/DIV
IOUT 500mA/DIV
2 ms/DIV
2 ms/DIV
VIN = 24 V
IOUT = 0 A
VIN = 24 V
IOUT = 0.5 A (Resistive)
图 19. No-Load Start-up and Shutdown with EN/UVLO
图 20. Full-Load Start-up and Shutdown with EN/UVLO
VOUT 5V/DIV
EN 5V/DIV
VOUT 5V/DIV
VSW 10V/DIV
IOUT 500mA/DIV
IOUT 500mA/DIV
500 µs/DIV
2 ms/DIV
VIN = 24 V
IOUT = 0 A
VIN = 24 V
Load = 0 A to Short
图 21. Pre-bias Start-up with EN/UVLO
图 22. Short Circuit Applied
VOUT 5V/DIV
VOUT 5V/DIV
VSW 10V/DIV
VSW 10V/DIV
100 µs/DIV
10 ms/DIV
IOUT 500mA/DIV
IOUT 500mA/DIV
VIN = 24 V
Load = 0 A to Short to 0 A
VIN = 24 V
Load = Short to 0 A
图 24. No Load to Short Circuit/Short Circuit Recovery
图 23. Short Circuit Recovery
版权 © 2019, Texas Instruments Incorporated
21
LM5163
ZHCSKD6 –OCTOBER 2019
www.ti.com.cn
VSW 10V/DIV
VSW 10V/DIV
VOUT 20mV/DIV
VOUT 50mV/DIV
10 ms/DIV
5 µs/DIV
VIN = 24 V
IOUT = 0 A
图 25. No-Load Switching
VIN = 24 V
IOUT = 0.5 A
图 26. Full-Load Switching
Peak
Average
Peak
Average
Start 150 kHz
Stop
30 MHz
Start 30 MHz
Stop 108 MHz
VIN = 48 V
Load = 0.5 A
VIN = 48 V
Load = 0.5 A
图 27. CISPR 25 Class 5 Conducted Emissions Plot, 150
图 28. CISPR 25 Class 5 Conducted Emissions Plot, 30
kHz to 30 MHz
MHz to 108 MHz
22
版权 © 2019, Texas Instruments Incorporated
LM5163
www.ti.com.cn
ZHCSKD6 –OCTOBER 2019
9 Power Supply Recommendations
The LM5163 buck converter is designed to operate from a wide input voltage range between 6 V and 100 V. The
characteristics of the input supply must be compatible with the Absolute Maximum Ratings and Recommended
Operating Conditions tables. In addition, the input supply must be capable of delivering the required input current
to the fully-loaded regulator. Use 公式 27 to estimate the average input current.
VOUT ∂IOUT
IIN
=
V ∂ h
IN
where
•
η is the efficiency
(27)
If the converter is connected to an input supply through long wires or PCB traces with a large impedance, take
special care to achieve stable performance. The parasitic inductance and resistance of the input cables can have
an adverse affect on converter operation. The parasitic inductance in combination with the low-ESR ceramic
input capacitors form an underdamped resonant circuit. This circuit can cause overvoltage transients at VIN each
time the input supply is cycled ON and OFF. The parasitic resistance causes the input voltage to dip during a
load transient. If the converter is operating close to the minimum input voltage, this dip can cause false UVLO
fault triggering and a system reset. The best way to solve such issues is to reduce the distance from the input
supply to the regulator and use an aluminum electrolytic input capacitor in parallel with the ceramics. The
moderate ESR of the electrolytic capacitor helps to damp the input resonant circuit and reduce any voltage
overshoots. A 10-μF electrolytic capacitor with a typical ESR of 0.5 Ω provides enough damping for most input
circuit configurations.
An EMI input filter is often used in front of the regulator that, unless carefully designed, can lead to instability as
well as some of the effects mentioned above. The Simple Success with Conducted EMI for DC-DC Converters
Application Report provides helpful suggestions when designing an input filter for any switching regulator.
版权 © 2019, Texas Instruments Incorporated
23
LM5163
ZHCSKD6 –OCTOBER 2019
www.ti.com.cn
10 Layout
10.1 Layout Guidelines
PCB layout is a critical portion of good power supply design. There are several paths that conduct high slew-rate
currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise and EMI or
degrade the power supply performance.
1. To help eliminate these problems, bypass the VIN pin to GND with a low-ESR ceramic bypass capacitor with
a high-quality dielectric. Place CIN as close as possible to the LM5163 VIN and GND pins. Grounding for
both the input and output capacitors must consist of localized top-side planes that connect to the GND pin
and GND PAD.
2. Minimize the loop area formed by the input capacitor connections to the VIN and GND pins.
3. Locate the inductor close to the SW pin. Minimize the area of the SW trace or plane to prevent excessive
capacitive coupling.
4. Tie the GND pin directly to the power pad under the device and to a heat-sinking PCB ground plane.
5. Use a ground plane in one of the middle layers as a noise shielding and heat dissipation path.
6. Have a single-point ground connection to the plane. Route the ground connections for the feedback, soft-
start, and enable components to the ground plane. This prevents any switched or load currents from flowing
in analog ground traces. If not properly handled, poor grounding results in degraded load regulation or erratic
output voltage ripple behavior.
7. Make VIN, VOUT and ground bus connections as wide as possible. This reduces any voltage drops on the
input or output paths of the converter and maximizes efficiency.
8. Minimize trace length to the FB pin. Place both feedback resistors, RFB1 and RFB2, close to the FB pin. Place
CFF (if needed) directly in parallel with RFB1. If output setpoint accuracy at the load is important, connect the
VOUT sense at the load. Route the VOUT sense path away from noisy nodes and preferably through a layer on
the other side of a grounded shielding layer.
9. The RON pin is sensitive to noise. Thus, locate the RRON resistor as close as possible to the device and
route with minimal lengths of trace. The parasitic capacitance from RON to GND must not exceed 20 pF.
10. Provide adequate heat sinking for the LM5163 to keep the junction temperature below 150°C. For operation
at full rated load, the top-side ground plane is an important heat-dissipating area. Use an array of heat-
sinking vias to connect the exposed pad to the PCB ground plane. If the PCB has multiple copper layers,
these thermal vias must also be connected to inner layer heat-spreading ground planes.
10.1.1 Compact PCB Layout for EMI Reduction
Radiated EMI generated by high di/dt components relates to pulsing currents in switching converters. The larger
area covered by the path of a pulsing current, the more electromagnetic emission is generated. The key to
minimizing radiated EMI is to identify the pulsing current path and minimize the area of that path.
图 29 denotes the critical switching loop of the buck converter power stage in terms of EMI. The topological
architecture of a buck converter means that a particularly high di/dt current path exists in the loop comprising the
input capacitor and the integrated MOSFETs of the LM5163, and it becomes mandatory to reduce the parasitic
inductance of this loop by minimizing the effective loop area.
24
版权 © 2019, Texas Instruments Incorporated
LM5163
www.ti.com.cn
ZHCSKD6 –OCTOBER 2019
Layout Guidelines (接下页)
VIN
VIN
2
CIN
LM5163
High
di/dt
loop
BST
High-side
NMOS
gate driver
Q1
LO
SW
VOUT
8
CO
Q2
Low-side
NMOS
gate driver
GND
1
GND
图 29. DC/DC Buck Converter With Power Stage Circuit Switching Loop
The input capacitor provides the primary path for the high di/dt components of the current of the high-side
MOSFET. Placing a ceramic capacitor as close as possible to the VIN and GND pins is the key to EMI reduction.
Keep the trace connecting SW to the inductor as short as possible and just wide enough to carry the load current
without excessive heating. Use short, thick traces or copper pours (shapes) for current conduction path to
minimize parasitic resistance. Place the output capacitor close to the VOUT side of the inductor, and connect the
return terminal of the capacitor to the GND pin and exposed PAD of the LM5163.
10.1.2 Feedback Resistors
Reduce noise sensitivity of the output voltage feedback path by placing the resistor divider close to the FB pin,
rather than close to the load. This reduces the trace length of FB signal and noise coupling. The FB pin is the
input to the feedback comparator, and as such, is a high impedance node sensitive to noise. The output node is
a low impedance node, so the trace from VOUT to the resistor divider can be long if a short path is not available.
Route the voltage sense trace from the load to the feedback resistor divider, keeping away from the SW node,
the inductor, and VIN to avoid contaminating the feedback signal with switch noise, while also minimizing the
trace length. This is most important when high feedback resistances greater than 100 kΩ are used to set the
output voltage. Also, route the voltage sense trace on a different layer from the inductor, SW node, and VIN so
there is a ground plane that separates the feedback trace from the inductor and SW node copper polygon. This
provides further shielding for the voltage feedback path from switching noise sources.
版权 © 2019, Texas Instruments Incorporated
25
LM5163
ZHCSKD6 –OCTOBER 2019
www.ti.com.cn
10.2 Layout Example
图 30 shows an example layout for the PCB top layer of a 2-layer board with essential components placed on the
top side.
Type 3 ripple
injection
Connect BST cap
close to BST and SW
Place FB resistors very
close to FB & GND pins
PGOOD
connection
Thermal vias under
LM5163 PAD
Place resistor R8
close to the RON pin
GND
Optional RC
VOUT
connection
Connect ceramic
input cap close to
VIN and GND
EN/UVLO
connection
connection snubber to
reduce SW
node ringing
图 30. LM5163 Single-Sided PCB Layout Example
26
版权 © 2019, Texas Instruments Incorporated
LM5163
www.ti.com.cn
ZHCSKD6 –OCTOBER 2019
11 器件和文档支持
11.1 器件支持
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
11.1.2 开发支持
•
•
•
•
LM5163 快速入门计算器
LM5163 仿真模型
TI 参考设计库
技术文章：
–
–
–
–
–
使用低静态电流开关进行高电压转换
为工业应用中的智能传感器发送器 供电
Industrial Strength 设计 – 第 1 部分
楼宇自动化趋势：预测性维护
楼宇自动化趋势：用于改善用户舒适度的互联传感器
11.1.2.1 使用 WEBENCH® 工具创建定制设计
单击此处以使用带 WEBENCH® 电源设计器的 LM5163 器件来创建定制设计。
1. 首先输入输入电压 (VIN)、输出电压 (VOUT) 和输出电流 (IOUT) 要求。
2. 使用优化器拨盘优化该设计的关键参数，如效率、尺寸和成本。
3. 将生成的设计与德州仪器 (TI) 的其他可行的解决方案进行比较。
WEBENCH 电源设计器可提供定制原理图以及罗列实时价格和组件供货情况的物料清单。
在多数情况下，可执行以下操作：
•
•
•
•
运行电气仿真，观察重要波形以及电路性能
运行热性能仿真，了解电路板热性能
将定制原理图和布局方案以常用 CAD 格式导出
打印设计方案的 PDF 报告并与同事共享
有关 WEBENCH 工具的详细信息，请访问 www.ti.com.cn/WEBENCH。
11.2 相关文档
请参阅如下相关文档：
•
•
•
•
•
•
•
•
•
•
•
德州仪器 (TI)，《LM5164-Q1EVM-041 EVM 用户指南》
德州仪器 (TI)，《为您的 COT 降压转换器选择理想的纹波生成网络应用报告》
德州仪器 (TI)，《评估适用于具有成本效益的严苛应用的宽 VIN、低 EMI 同步降压 电路 白皮书》
德州仪器 (TI)，《电源的传导 EMI 规格概述白皮书》
德州仪器 (TI)，《电源的辐射 EMI 规格概述白皮书》
德州仪器 (TI)，《适用于智能恒温器且具有宽 VIN 转换器和电池电量计的 24V 交流功率级设计指南》
德州仪器 (TI)，《精确计量和 50μA 待机电流、13 节、48V 锂离子电池组参考设计指南》
德州仪器 (TI)，《AN-2162：轻松抑制直流/直流转换器中的传导 EMI 应用报告》
德州仪器 (TI)，《利用宽 VIN 直流/直流转换器为无人机供电应用报告》
德州仪器 (TI)，《使用新的热指标应用报告》
德州仪器 (TI)，《半导体和 IC 封装热指标应用报告》
11.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品
信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
版权 © 2019, Texas Instruments Incorporated
27
LM5163
ZHCSKD6 –OCTOBER 2019
www.ti.com.cn
11.4 支持资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 商标
PowerPAD, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
28
版权 © 2019, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
11-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM5163DDAR
ACTIVE SO PowerPAD
DDA
8
2500 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR
-40 to 150
LM5163
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LM5163 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Mar-2023
Automotive : LM5163-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE OUTLINE
DDA0008A
PowerPADTM SOIC - 1.7 mm max height
S
C
A
L
E
2
.
4
0
0
PLASTIC SMALL OUTLINE
C
6.2
5.8
TYP
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 1.27
8
1
2X
5.0
4.8
3.81
NOTE 3
4
5
0.51
8X
0.31
4.0
3.8
1.7 MAX
B
0.25
C A B
NOTE 4
0.25
0.10
TYP
SEE DETAIL A
5
4
EXPOSED
THERMAL PAD
0.25
2.34
2.24
GAGE PLANE
0.15
0.00
0 - 8
1.27
0.40
1
8
DETAIL A
TYPICAL
2.34
2.24
4218825/A 05/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012.
www.ti.com
EXAMPLE BOARD LAYOUT
DDA0008A
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.95)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.34)
SOLDER MASK
OPENING
SEE DETAILS
8X (1.55)
1
8
8X (0.6)
(2.34)
SOLDER MASK
SYMM
(1.3)
TYP
OPENING
(4.9)
NOTE 9
6X (1.27)
5
4
(R0.05) TYP
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
(
0.2) TYP
VIA
(1.3) TYP
LAND PATTERN EXAMPLE
SCALE:10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4218825/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DDA0008A
PowerPADTM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.34)
BASED ON
0.125 THICK
STENCIL
(R0.05) TYP
8X (1.55)
1
8
8X (0.6)
(2.34)
SYMM
BASED ON
0.125 THICK
STENCIL
6X (1.27)
5
4
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
2.62 X 2.62
2.34 X 2.34 (SHOWN)
2.14 X 2.14
0.125
0.150
0.175
1.98 X 1.98
4218825/A 05/2016
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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