LM5176QPWPRQ1 [TI]
符合 AEC-Q100 标准的 55V 宽输入电压同步 4 开关降压/升压控制器 | PWP | 28 | -40 to 125;
| 型号： | LM5176QPWPRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 符合 AEC-Q100 标准的 55V 宽输入电压同步 4 开关降压/升压控制器 | PWP | 28 | -40 to 125 开关 控制器 |
| 文件： | 总42页 (文件大小：2635K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM5176-Q1
ZHCSIQ6B –SEPTEMBER 2018 –REVISED AUGUST 2021
LM5176-Q1 55V 宽输入电压同步4 开关降压/升压控制器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准
LM5176-Q1 是一款同步四开关降压/升压直流/直流控
制器，能够将输出电压稳定在等于、高于或低于输入电
压的某一电压值上。LM5176-Q1 在 4.2V 至 55V（最
大绝对值为 60V）的宽输入电压范围内工作，可支持
各种不同的应用。
– 温度等级1：-40°C 至125°C TA
• 提供功能安全
– 可帮助进行功能安全系统设计的文档
• 单电感降压/升压控制器，用于升压/降压直流/直流
转换
• 宽VIN：4.2V（2.5V 偏置）至55V（60V 最大输入
电压）
LM5176-Q1 在降压和升压工作模式下均采用电流模式
控制，以提供出色的负载和线路调节性能。开关频率可
通过外部电阻进行编程，并且可与外部时钟信号同步。
• 灵活的VOUT：0.8V 至55V
• 输出电压短路保护
该器件还具有可编程的软启动功能，并且提供诸如逐周
期电流限制、输入欠压闭锁 (UVLO)、输出过压保护
(OVP) 和热关断等各类保护特性。此外，LM5176-Q1
具有平均输入或输出电流限制、用于减少峰值 EMI 的
展频以及持续过载情况下的断续模式保护等选项。
• 高效降压/升压转换
• 可调开关频率
• 可选频率同步和抖动
• 集成2A MOSFET 栅极驱动器
• 逐周期电流限制和可选断续模式
• 可选输入或输出平均电流限制
• 可编程输入UVLO 和软启动
• 电源正常和输出过压保护
• 采用HTSSOP-28 封装
器件信息
封装(1)
封装尺寸（标称值）
器件型号
LM5176QPWP
HTSSOP-28
9.7mm x 4.4mm
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
• 使用LM5176-Q1 并借助WEBENCH Power
Designer 创建定制设计方案
2 应用
• 汽车起停系统
• 备用电池和超级电容充电
• USB 电力输送
• 电池供电型系统
• LED 照明
VIN
VCC
VOUT
BOOT1
HDRV1
EN/UVLO
Enable
Power Good
PGOOD
SS
SW1
LDRV1
SLOPE
CS
CSG
LM5176
RT/SYNC
LDRV2
COMP
SW2
AGND
PGND
VCC
BOOT2
HDRV2
VOSNS
VCC
简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVSB46
LM5176-Q1
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ZHCSIQ6B –SEPTEMBER 2018 –REVISED AUGUST 2021
Table of Contents
8 Application and Implementation..................................21
8.1 Application Information............................................. 21
8.2 Typical Application.................................................... 21
9 Power Supply Recommendations................................29
10 Layout...........................................................................30
10.1 Layout Guidelines................................................... 30
10.2 Layout Example...................................................... 31
11 Device and Documentation Support..........................32
11.1 Device Support........................................................32
11.2 Documentation Support.......................................... 32
11.3 接收文档更新通知................................................... 32
11.4 支持资源..................................................................32
11.5 Trademarks............................................................. 32
11.6 Electrostatic Discharge Caution..............................32
11.7 术语表..................................................................... 33
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................6
6.6 Typical Characteristics................................................9
7 Detailed Description......................................................13
7.1 Overview...................................................................13
7.2 Functional Block Diagram.........................................14
7.3 Feature Description...................................................14
7.4 Device Functional Modes..........................................19
Information.................................................................... 33
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (June 2020) to Revision B (August 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
Changes from Revision * (September 2018) to Revision A (June 2020)
Page
• 向节1 添加了功能安全要点................................................................................................................................ 1
• Restructured the 节11.1 to meet the current data sheet standards................................................................. 32
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5 Pin Configuration and Functions
EN/UVLO
VIN
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SW1
2
HDRV1
BOOT1
LDRV1
BIAS
VISNS
MODE
DITH
3
4
5
RT
6
VCC
SLOPE
SS
7
PGND
LDRV2
BOOT2
HDRV2
SW2
LM5176
HTSSOP-28
8
COMP
AGND
FB
9
10
11
12
13
14
VOSNS
ISNS(œ)
ISNS(+)
PGOOD
CS
CSG
图5-1. HTSSOP-28 PWP Package Top View
表5-1. Pin Functions
PIN
DESCRIPTION
NAME
HTSSOP
Enable pin. For EN/UVLO < 0.4 V, the LM5176-Q1 is in a low current shutdown mode. For EN/UVLO > 1.22 V,
the PWM function is enabled, provided VCC exceeds the VCC UV threshold.
EN/UVLO
1
VIN
2
3
The input supply pin to the IC. Connect VIN to a supply voltage between 4.2 V and 55 V.
VIN sense input. Connect to power stage input rail.
VISNS
1.38 V < MODE < 2.22 V : CCM, Hiccup Enabled
2.6 V < MODE < VCC: CCM, Hiccup Disabled
(Set RMODE resistor to AGND = 93.1 kΩ)
MODE
4
(Set RMODE resistor to AGND = 200 kΩ or connect
to VCC)
A capacitor connected between the DITH pin and AGND is charged and discharged with a current source. As
the voltage on the DITH pin ramps up and down, the oscillator frequency is modulated by 10% of the nominal
frequency set by the RT resistor. Grounding the DITH pin will disable the dithering feature. In the external Sync
mode, the DITH pin voltage is ignored.
DITH
5
6
Switching frequency programming pin. An external resistor is connected to the RT/SYNC pin and AGND to set
the switching frequency. This pin can also be used to synchronize the PWM controller to an external clock.
RT/SYNC
A capacitor connected between the SLOPE pin and AGND provides the slope compensation ramp for stable
current mode operation in both buck and boost mode.
SLOPE
SS
7
8
Soft-start programming pin. A capacitor between the SS pin and AGND pin programs soft-start time.
Output of the error amplifier. An external RC network connected between COMP and AGND compensates the
regulator feedback loop.
COMP
AGND
FB
9
10
11
12
Analog ground of the IC
Feedback pin for output voltage regulation. Connect a resistor divider network from the output of the converter
to the FB pin.
VOSNS
VOUT sense input. Connect to the power stage output rail.
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表5-1. Pin Functions (continued)
PIN
DESCRIPTION
NAME
HTSSOP
Input or Output Current Sense Amplifier inputs. An optional current sense resistor connected between ISNS(+)
and ISNS(–) can be located either on the input side or on the output side of the converter. If the sensed voltage
across the ISNS(+) and ISNS(-) pins reaches 50 mV, a slow Constant Current (CC) control loop becomes active
and starts discharging the soft-start capacitor to regulate the drop across ISNS(+) and ISNS(-) to 50 mV. Short
ISNS(+) and ISNS(-) together to disable this feature.
13
14
ISNS(–)
ISNS(+)
The negative or ground input to the PWM current sense amplifier. Connect directly to the low-side (ground) of
the current sense resistor.
CSG
15
16
17
CS
The positive input to the PWM current sense amplifier
Power-Good open-drain output. PGOOD is pulled low when FB is outside a -9%/+10% regulation window
PGOOD
around the 0.8-V VREF
.
SW2
SW1
18
28
The boost and the buck side switching nodes respectively.
HDRV2
HDRV1
19
27
Output of the high-side gate drivers. Connect directly to the gates of the high-side MOSFETs.
BOOT2
BOOT1
20
26
An external capacitor is required between the BOOT1, BOOT2 pins and the SW1, SW2 pins respectively to
provide bias to the high-side MOSFET gate drivers.
LDRV2
LDRV1
21
25
Output of the low-side gate drivers. Connect directly to the gates of the low-side MOSFETs.
PGND
VCC
22
23
Power ground of the IC. The high current ground connection to the low-side gate drivers.
Output of the VCC bias regulator. Connect capacitor to ground.
Optional input to the VCC bias regulator. Powering VCC from an external supply instead of VIN can reduce
power loss at high VIN. For VBIAS > 8 V, the VCC regulator draws power from the BIAS pin.
BIAS
24
-
The PowerPAD should be soldered to the analog ground. If possible, use thermal vias to connect to a PCB
ground plane for improved power dissipation.
PowerPAD™
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6 Specifications
6.1 Absolute Maximum Ratings
MIN(1)
–0.3
–0.3
–0.3
–1
MAX
60
UNIT
VIN, EN/UVLO, VISNS, VOSNS, ISNS(+), ISNS(–)
BIAS
40
FB, SS, DITH, RT/SYNC, SLOPE, COMP
SW1, SW2
3.6
60
SW1, SW2 (20 ns transient)
VCC, MODE, PGOOD
65
–5.0
–0.3
–0.3
–0.3
–0.3
–0.3
-0.3
8.5
8.5
8.5
8.5
68
V
LDRV1, LDRV2
BOOT1, HDRV1 with respect to SW1
BOOT2, HDRV2 with respect to SW2
BOOT1, BOOT2
ISNS(+) with respect to ISNS(-)
CS, CSG
0.3
0.3
150
150
–0.3
–40
-65
Operating junction temperature
Storage temperature, Tstg
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 2
±2000
V(ESD) Electrostatic discharge
V
All pins
±500
±750
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level C4B
Corner pins
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
4.2
NOM
MAX
55
UNIT
VIN
Input bias voltage
VISNS
2.5
55
Input power stage voltage with external bias (BIAS ≥5 V
or VIN ≥4.5 V)
BIAS
Bias supply voltage range (when VCC in regulation)
Output voltage range
8
0.8
0
36
55
V
VOSNS
EN/UVLO
ISNS(+), ISNS(-)
TJ
Enable voltage range
55
Average current sense common mode range
Operating temperature range(2)
Operating frequency range
0
55
150
600
°C
–40
100
Fsw
kHz
(1) Recommended Operating Conditions are conditions under the device is intended to be functional. For specifications and test
conditions, see 节6.5 .
(2) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
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6.4 Thermal Information
LM5176-Q1
THERMAL METRIC(1)
PWP (HTSSOP)
UNIT
28 PINS
32.6
21.4
8.2
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
RθJC(top)
RθJB
°C/W
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJT
8.3
ψJB
RθJC(bot)
1.0
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 125°C junction temperature
range unless otherwise stated. VIN = 24 V unless otherwise stated.(1)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE (VIN)
IQ
VIN shutdown current
VIN operating current
VEN/UVLO = 0 V
2.6
2
10
4
µA
VEN/UVLO = 2 V, VFB = 0.9 V
mA
VCC
VVCC(VIN)
VUV(VCC)
Regulation voltage
VBIAS = 0 V, VCC open
VCC increasing
6.95
3.11
7.35
3.27
176
7.88
3.43
V
VCC Undervoltage lockout
Undervoltage hysteresis
VCC current limit
mV
mA
Ω
IVCC
VVCC = 0 V
65
ROUT(VCC)
BIAS
VCC regulator output impedance
IVCC = 30 mA, VIN = 4 V
8
8
16
VBIAS(SW)
EN/UVLO
VEN(STBY)
IEN(STBY)
VEN(OP)
ΔIHYS(OP)
SS
BIAS switchover voltage
VIN = 24 V
7.25
8.75
V
Standby threshold
EN/UVLO rising
VEN/UVLO = 1.1 V
EN/UVLO rising
VEN/UVLO = 1.5 V
0.55
1
0.82
2
0.97
3
V
µA
V
Standby source current
Operating threshold
1.17
2.15
1.22
3.15
1.29
4.25
Operating hysteresis current
µA
ISS
Soft-start pull up current
SS clamp voltage
FB to SS offset
VSS = 0 V
SS open
VSS = 0 V
3.75
5
1.21
-18
6.35
µA
V
VSS(CL)
VFB - VSS
mV
EA (ERROR AMPLIFIER)
VREF
Feedback reference voltage
Error amplifier gm
FB = COMP
0.788
0.800
1.31
280
20
0.812
V
gmEA
mS
µA
ISINK/ISOURCE COMP sink/source current
VFB=VREF ± 300 mV
ROUT
Amplifier output resistance
Unity gain bandwidth
MΩ
MHz
nA
BW
2
IBIAS(FB)
FREQUENCY
fSW(1)
Feedback pin input bias current
FB in regulation
25
Switching Frequency 1
Switching Frequency 2
175
350
200
390
225
430
RT = 40 kΩ
RT = 20 kΩ
kHz
fSW(2)
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Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 125°C junction temperature
range unless otherwise stated. VIN = 24 V unless otherwise stated.(1)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
DITHER
IDITHER
Dither source/sink current
Dither high threshold
Dither low threshold
11
1.27
1.16
µA
V
VDITHER
SYNC
VSYNC
Sync input high threshold
Sync input low threshold
2.1
50
V
1.2
PWSYNC
Minimum sync input pulse width
ns
CURRENT LIMIT
VCS(BUCK)
Buck current limit threshold (Valley)
VIN = VVISNS = 24 V, VVOSNS = 12 V,
VSLOPE = 0 V
66
80
94
mV
µA
VCS(BOOST)
IBIAS(CS/CSG)
Boost current limit threshold (Peak)
CS/CSG pin bias current
VIN = VVISNS = 12 V, VVOSNS = 18 V,
VSLOPE = 0 V
100
120
-80
140
VCS = VCSG = 0 V
VCS = VCSG = 0 V
IOFFSET(CS/CSG) CSG pin bias current
19
57
CONSTANT CURRENT LOOP
VSNS
Average current loop regulation target
VISNS(-) = 24 V, sweep ISNS(+), VSS
0.8 V
=
43
50
3
mV
µA
ISNS
Gm
VISNS(+) = VISNS(–) = VIN = 24 V
ISNS(+)/ISNS(–) pin bias currents
gm of soft-start pull down amplifier
V
V
ISNS(+)–VISNS(–) = 55 mV, VSS = 0.5
1
mS
SLOPE
ISLOPE
Buck adaptive slope current
Boost adaptive slope current
Slope compensation amplifier gm
VIN = VVISNS = 24 V, VVOSNS = 12 V,
VSLOPE = 0 V
24
13
30
35
21
µA
µS
VIN = VVISNS = 12 V, VVOSNS = 18 V,
VSLOPE = 0 V
17
2
gmSLOPE
MODE
IMODE
Source current out of MODE pin
CCM with hiccup threshold
CCM no hiccup threshold
17
1.18
2.22
20
1.28
2.4
23
1.38
2.6
µA
V
VCCM_HIC
VCCM
V
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Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 125°C junction temperature
range unless otherwise stated. VIN = 24 V unless otherwise stated.(1)
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
PGOOD
VPGD
PGOOD trip threshold for falling FB
PGOOD trip threshold for rising FB
Hysteresis
Measured with respect to VREF
Measured with respect to VREF
%
%
–9
10
2.5
%
ILEAK(PGD)
ISINK(PGD)
OUTPUT OVP
VOVP
PGOOD leakage current
PGOOD sink current
100
6.5
nA
mA
VPGOOD = 0.4 V
2
4.2
Output overvoltage threshold at FB pin
Hysteresis
Measured with respect to VREF
10
%
%
2.5
NMOS DRIVERS
IHDRV1,2
Driver peak source current
VBOOT - VSW = 7 V
VBOOT - VSW = 7 V
1.8
2.2
1.8
2.2
1.8
1.1
3.4
150
1.7
1.3
45
Driver peak sink current
A
ILDRV1,2
Driver peak source current
Driver peak sink current
RHDRV1,2
VUV(BOOT1,2)
RLDRV1,2
Driver pull up resistance
VBOOT - VSW = 7 V
VBOOT - VSW = 7 V
HDRV1,2 shut off
Ω
Driver pull down resistance
BOOT1,2 to SW1,2 UVLO threshold
BOOT1,2 to SW1,2 UVLO hysteresis
Driver pull up resistance
V
HDRV1,2 start switching
mV
Ω
Driver pull down resistance
Dead time HDRV1,2 off to LDRV1,2 on
Dead time LDRV1,2 off to HDRV1,2 on
tDT1
tDT2
ns
45
THERMAL SHUTDOWN
TSD
Thermal shutdown temperature
Thermal shutdown hysteresis
165
15
°C
TSD(HYS)
(1) All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and
applying statistical process control.
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6.6 Typical Characteristics
At TA = 25°C, unless otherwise stated.
99
98
97
96
95
94
93
100
96
92
88
84
80
VIN = 9V
VIN = 12V
VIN = 24V
0
1
2
3
4
LOAD CURRENT (A)
5
6
5
10
15
20
25
VIN (V)
30
35
40
45
50
D008
D009
VOUT = 12 V
Fsw = 300 kHz
L1 = 4.7 μH
VOUT = 12 V
Fsw = 300 kHz
IOUT = 5 A
L1 = 4.7 μH
图6-2. Efficiency vs Load
图6-1. Efficiency vs VIN
600
500
400
300
200
100
0
8
6
4
2
0
0
10
20
30
40
50
60
70
80
90
100
2
4
6
VIN (V)
8
10
12
RT (kW)
D004
D002
图6-3. Oscillator Frequency
图6-4. VCC vs VIN
3.0
2.6
2.2
1.8
1.4
1.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-40 èC
25 èC
125 èC
BIAS = 0V
BIAS = 12V
0
10
20
30
VIN (V)
40
50
60
0
10
20
30
VIN (V)
40
50
60
D007
D010
图6-5. IIN Operating vs VIN
图6-6. IIN Shutdown vs VIN
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1.30
1.26
1.22
1.18
1.14
1.10
110
100
90
80
70
60
50
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
TEMPERATURE (èC)
TEMPERATURE (èC)
D013
D014
图6-7. ENABLE/UVLO Rising Threshold vs
图6-8. Buck Current Limit vs Temperature
Temperature
150
140
130
120
110
100
90
SW1
SW2
IL1
-40
-20
0
20
40
60
80
100 120 140
TEMPERATURE (èC)
VOUT = 12 V
VIN = 6 V
D015
图6-9. Boost Current Limit vs Temperature
图6-10. Forced CCM Operation (Boost)
SW1
SW1
SW2
SW2
IL1
IL1
VOUT = 12 V
VIN = 11 V
VOUT = 12 V
VIN = 12 V
图6-11. Forced CCM Operation (Buck-Boost)
图6-12. Forced CCM Operation (Buck-Boost)
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SW1
SW1
SW2
SW2
IL1
IL1
VOUT = 12 V
VIN = 13 V
VOUT = 12 V
VIN = 24 V
图6-13. Forced CCM Operation (Buck-Boost)
图6-14. Forced CCM Operation (Buck)
VOUT
500 mV/div
VOUT
500 mV/div
IOUT
2 A/div
IOUT
2 A/div
500 µs/div
500 µs/div
VIN = 6 V
VOUT = 12 V
Load 3 A to 6 A
VIN = 12 V
VOUT = 12 V
Load 3 A to 6 A
图6-15. Load Step (Boost)
图6-16. Load Step (Buck-Boost)
VOUT
500 mV/div
VIN
10 V/div
IOUT
2 A/div
VOUT
1 V/div
IL
5 A/div
500 µs/div
1 ms/div
IOUT = 3 A
VIN = 24 V
VOUT = 12 V
Load 3 A to 6 A
VIN = 8 V to 24 V
VOUT = 12 V
图6-17. Load Step (Buck)
图6-18. Line Transient
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15
12
9
Overload
released
VOUT
5 V/div
6
3
IL
0
20 ms/div
Hiccup Enabled
5 A/div
0
1
2
3
IOUT (A)
4
5
6
D021
VIN = 24 V
VOUT = 12 V
VIN = 24 V
RSNS = 10 mΩ
图6-19. Hiccup Mode Current Limit
图6-20. Constant Current Constant Voltage (CCCV)
Operation
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7 Detailed Description
7.1 Overview
The LM5176-Q1 is a wide input voltage four-switch buck-boost controller IC with integrated drivers for N-channel
MOSFETs. It operates in buck mode when VIN is greater than VOUT and in boost mode when VIN is less than
VOUT. When VIN is close to VOUT, the device operates in a proprietary transition buck or boost mode. The control
scheme provides smooth operation for any input/output combination within the specified operating range. The
buck or boost transition control scheme provides a low ripple output voltage when VIN equals VOUT without
compromising the efficiency.
The LM5176-Q1 integrates four N-Channel MOSFET drivers including two low-side drivers and two high-side
drivers, eliminating the need for external drivers or floating bias supplies. The internal VCC regulator supplies
internal bias rails as well as the MOSFET gate drivers. The VCC regulator is powered either from the input
voltage through the VIN pin or from the output or an external supply through the BIAS pin for improved efficiency.
The PWM control scheme is based on valley current mode control for buck operation and peak current mode
control for boost operation. The inductor current is sensed through a single sense resistor in series with the low-
side MOSFETs. The sensed current is also monitored for cycle-by-cycle current limit. The behavior of the
LM5176-Q1 during an overload condition is dependent on the MODE pin programming (see the 节 7.4.2
section). If hiccup mode fault protection is selected, the controller turns off after a fixed number of switching
cycles in cycle-by-cycle current limit and restarts after another fixed number of clock cycles. The hiccup mode
reduces the heating in the power components in a sustained overload condition. If hiccup mode is disabled
through the MODE pin, the controller remains in a cycle-by-cycle current limit condition until the overload is
removed.
In addition to the cycle-by-cycle current limiting, the LM5176-Q1 also provides an optional average current
regulation loop that can be configured for either input or output current limiting. This is useful for battery charging
or other applications where a constant current behavior may be required.
The soft-start time of LM5176-Q1 is programmed by a capacitor connected to the SS pin to minimize the inrush
current and overshoot during start-up.
The precision EN/UVLO pin supports programmable input undervoltage lockout (UVLO) with hysteresis. The
output overvoltage protection (OVP) feature turns off the high-side drivers when the voltage at the FB pin
exceeds the output overvoltage threshold (VOVP). The PGOOD output indicates when the FB voltage is inside
the PGOOD regulation window centered at VREF
.
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7.2 Functional Block Diagram
VIN
BIAS
∆IHYS(OP)
+
-
EN/UVLO
VCC
VEN(OP)
OPERATING
EN & BIAS
LOGIC
IEN(STBY)
THERMAL
SHUTDOWN
+
-
VEN(STBY)
STANDBY
45 mV
1.2 V
PGOOD
-
+
ISS
SS
1.1VREF
FB
OV
-
-
+
VOVP
ISNS(+)
ISNS(-)
+
-
+
-
+
1 mA/V
0.91VREF
CONSTANT
CURRENT LOOP
BOOT1
HDRV1
3.3V
GM ERROR
AMPLIFIER
PWM
COMPARATOR
1.6V
VREF
+
+
SS
FB
+
-
SW1
-
VCC
LDRV1
COMP
CS AMPLIFIER
CLK
BUCK-BOOST CONTROLLER
LOGIC
BOOT2
HDRV2
CS
+
ACS=5
ꢀ
ILIMIT
COMPARATOR
CSG
-
SW2
+
-
VCC
LDRV2
VISNS
VOSNS
SLOPE
V
ILIM
SLOPE COMP
MODE
HICCUP CURRENT
LIMIT
RT/SYNC
DITH
OSC/SYNC
CLK
PGND
AGND
7.3 Feature Description
7.3.1 Fixed Frequency Valley/Peak Current Mode Control with Slope Compensation
The LM5176-Q1 implements a fixed frequency current mode control of both the buck and boost switches. The
output voltage, scaled down by the feedback resistor divider, appears at the FB pin and is compared to the
internal reference (VREF) by an internal error amplifier. The error amplifier produces an error voltage by driving
the COMP pin. An adaptive slope compensation signal based on VIN, VOUT, and the capacitor at the SLOPE pin
is added to the current sense signal measured across the CS and CSG pins. The result is compared to the
COMP error voltage by the PWM comparator.
The LM5176-Q1 regulates the output using valley current mode control in buck mode and peak current mode
control in boost mode. For valley current mode control, the high-side buck MOSFET controlled by HDRV1 is
turned on by the PWM comparator at the valley of the inductor ripple current and turned off by the oscillator clock
signal. Valley current mode control is advantageous for buck converters where the PWM controller must resolve
very short on-times. For peak current mode control in the boost mode, the low-side boost MOSFET controlled by
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LDRV2 is turned on by the clock signal in each switching cycle and turned off by the PWM comparator at the
peak of the inductor ripple current.
The low-side gate drive LDRV1, complementary to the HDRV1 drive signal, controls the synchronous
rectification MOSFET of the buck stage. The high-side gate drive HDRV2, complementary to the low-side gate
drive LDRV2, controls the high-side synchronous rectifier of the boost stage. For operation with VIN close to
VOUT, the LM5176-Q1 uses a proprietary buck or boost transition scheme to achieve smooth, low ripple
transition zone behavior.
Peak and valley current mode controllers require slope compensation for stable current loop operation at duty
cycle greater than 50% in peak current mode control and less than 50% in valley current mode control. The
LM5176-Q1 provides a SLOPE pin to program optimum slope for any VIN and VOUT combination using an
external capacitor.
7.3.2 VCC Regulator and Optional BIAS Input
The VCC regulator provides a regulated bias supply to the gate drivers. When EN/UVLO is above the standby
threshold (VEN(STBY)), the VCC regulator is turned on. For VIN less than the VCC regulation target, the VCC
voltage tracks VIN with a small voltage drop as shown in 图 6-4. If the EN/UVLO input is above the operating
threshold (VEN(OP)) and VCC exceeds the VCC UV threshold (VUV(VCC)), the controller is enabled and switching
begins.
The VCC regulator draws power from VIN when there is no supply voltage connected to the BIAS pin. If the BIAS
pin is connected to an external voltage source that exceeds VCC by one diode drop, the VCC regulator draws
power from the BIAS input instead of VIN. Connecting the BIAS pin to VOUT in applications with VOUT greater
than 8.5 V improves the efficiency of the regulator in the buck mode.
For low VIN operation, ensure that the VCC voltage is sufficient to fully enhance the MOSFETs. Use an external
bias supply if VIN dips below the voltage required to sustain the VCC voltage. For these conditions, use a series
blocking diode between the input supply and the VIN pin (图 7-1). This prevents VCC from back-feeding into VIN
through the body diode of the VCC regulator.
A ceramic capacitor of 16 V or higher voltage rating and a value between 1 µF and 4.7 µF is required to supply
the VCC regulator load transients. The VCC bypass capacitor should be connected between VCC and PGND
pins.
Series Blocking Diode
VIN
VIN
CVIN
LM5176
Optional
Bias Supply/ VOUT
BIAS
CBIAS
VCC
CVCC
图7-1. VCC Regulator and Optional BIAS
7.3.3 Enable/UVLO
The LM5176-Q1 has a dual function enable and undervoltage lockout (UVLO) circuit. The EN/UVLO pin has
three distinct voltage ranges: shutdown, standby, and operating (see the 节 7.4.1 section). When the EN/UVLO
pin is below the standby threshold, VEN(STBY), the converter is held in a low power shutdown mode. When EN/
UVLO voltage is greater than the standby threshold, VEN(STBY) but less than the operating threshold, VEN(OP), the
internal bias rails and the VCC regulator are enabled but the soft-start (SS) pin is held low and the PWM
controller is disabled. A pullup current IEN(STBY) is sourced out of the EN/UVLO pin in standby mode to provide
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hysteresis between the shutdown mode and the standby mode. When EN/UVLO is greater than the operating
threshold VEN(OP) and VCC is above the undervoltage threshold VUV(VCC), the controller starts operation. A
hysteresis current, ΔIHYS(OP), is sourced out of the EN/UVLO pin when the EN/UVLO input exceeds the
operating threshold to provide hysteresis that prevents on/off chattering in the presence of noise with a slowly
changing input voltage.
The VIN UVLO threshold is typically set by a resistor divider from VIN to AGND (图 7-2). The turnon threshold
VIN(UV) is calculated using 方程式 1 where RUV2 is the upper resistor and RUV1 is the lower resistor in the EN/
UVLO resistor divider:
≈
’
÷
◊
RUV2
RUV1
V
= VEN(OP) ì 1+
-RUV2 ìIEN(STBY)
∆
IN(UV)
«
(1)
The hysteresis between the UVLO turnon threshold and turnoff threshold is set by the upper resistor in the EN/
UVLO resistor divider and is given by:
DVHYS(UV) = DIHYS(OP) ìRUV2
(2)
VIN
LM5176
RUV2
EN/UVLO
RUV1
图7-2. UVLO Threshold Programming
7.3.4 Soft-Start
The LM5176-Q1 soft-start time is programmed using a soft-start capacitor from the SS pin to AGND. When the
converter is enabled, an internal current source (ISS) charges the soft-start capacitor. When the SS pin voltage is
below the feedback reference voltage VREF, the soft-start pin controls the regulated FB voltage. Once SS
exceeds VREF, the soft-start interval is complete and the error amplifier is referenced to VREF. The soft-start time
is given by 方程式3:
CSS ì VREF
ISS
tss
=
(3)
The soft-start capacitor is internally discharged when the converter is disabled because of EN/UVLO falling
below the operating threshold or VCC falling below the VCC UV threshold. The soft-start pin is also discharged
when the converter is in hiccup mode current limiting or in thermal shutdown. When average input or output
current limiting is active, the soft-start capacitor is discharged by the constant current loop transconductance
(gm) amplifier to limit either input or output current.
7.3.5 Overcurrent Protection
The LM5176-Q1 provides cycle-by-cycle current limit to protect against overcurrent and short circuit conditions.
In buck operation, the sensed valley voltage across the CSG and CS pins is limited to VCS(BUCK). The high-side
buck switch skips a cycle if the sensed voltage does not fall below this threshold during the buck switch off time.
In boost operation, the maximum peak voltage across CS and CSG is limited to VCS(BOOST). If the peak current in
the low-side boost switch causes the voltage across CS and CSG to exceed this threshold voltage, the boost
switch is turned off for the remainder of the clock cycle.
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Applying the appropriate voltage to the MODE pin of the LM5176-Q1 enables hiccup mode fault protection (see
节 7.4.2). In the hiccup mode, the controller shuts down after detecting cycle-by-cycle current limiting for 128
consecutive cycles and the soft-start capacitor is discharged. The soft-start capacitor is automatically released
after 4000 oscillator clock cycles and the controller restarts. If hiccup mode protection is not enabled through the
MODE pin, the LM5176-Q1 will operate in cycle-by-cycle current limiting as long as the overload condition
persists.
7.3.6 Average Input/Output Current Limiting
The LM5176-Q1 provides optional average current limiting capability to limit either the input or the output current
of the DC/DC converter. The average current limiting circuit uses an additional current sense resistor connected
in series with the input supply or output voltage of the converter. A current sense gm amplifier with inputs at the
ISNS(+) and ISNS(-) pins monitors the voltage across the sense resistor and compares it with an internal 50-mV
reference. If the drop across the sense resistor is greater than 50 mV, the gm amplifier gradually discharges the
soft-start capacitor. When the soft-start capacitor discharges below the feedback reference voltage, VREF, the
output voltage of the converter decreases to limit the input or output current. The average current limiting feature
can be used in applications requiring a regulated current from the input supply or into the load. The target
constant current is given by 方程式4:
50 mV
ICL(AVG)
=
RSNS
(4)
A filter network as shown in 图 8-1 is often used across ISNS(+) and ISNS(-) pins to filter the ripple in the
average current sense signal.
The average current loop can be disabled by shorting the ISNS(+) and ISNS(-) pins together to AGND.
7.3.7 Operation Above 40-V Input
For an application where input voltage is higher than 40 V, a 2-kΩ resistor in series with the VISNS pin is
required as shown in 图8-1.
7.3.8 CCM Operation
The LM5176-Q1 works in continuous conduction mode (CCM). In CCM operation, the inductor current can flow
in either direction and the controller switches at a fixed frequency regardless of the load current. The CCM
operation is useful for noise-sensitive applications where a fixed switching eases filter design.
7.3.9 Frequency and Synchronization (RT/SYNC)
The LM5176-Q1 switching frequency can be programmed between 100 kHz and 600 kHz using a resistor from
the RT/SYNC pin to AGND. The RT resistor is related to the nominal switching frequency (Fsw) by the 方程式5:
≈
∆
«
’
÷
1
-190 ns
F
sw ◊
RT =
116 pF
(5)
图 6-3 in the 节 6.6 shows the relationship between the programmed switching frequency (Fsw) and the RT
resistor.
The RT/SYNC pin can also be used for synchronizing the internal oscillator to an external clock signal. The
external synchronization pulse is ac-coupled using a capacitor to the RT/SYNC pin. The external synchronization
pulse frequency range is 75% to 125% of the resistor programmed frequency. A 50% duty cycle is acceptable for
external SYNC.
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LM5176
RT/SYNC
external SYNC
CSYNC
RT
图7-3. Using External SYNC
7.3.10 Frequency Dithering
The LM5176-Q1 provides an optional frequency dithering function that is enabled by connecting a capacitor from
DITH to AGND. 图 7-4 illustrates the dithering circuit. A triangular waveform centered at 1.22 V is generated
across the CDITH capacitor. This triangular waveform modulates the oscillator frequency by 10% of the nominal
frequency set by the RT resistor. The CDITH capacitance value sets the rate of the low frequency modulation. A
lower CDITH capacitance will modulate the oscillator frequency at a faster rate than a higher capacitance. For the
dithering circuit to effectively reduce peak EMI, the modulation rate must be much less than the oscillator
frequency (Fsw). 方程式 6 calculates the DITH pin capacitance required to set the modulation frequency, FMOD
.
Connecting the DITH pin directly to AGND disables frequency dithering, and the internal oscillator operates at a
fixed frequency set by the RT resistor. Dither is disabled when external SYNC is used.
10 mA
FMOD ì0.24 V
CDITH
=
(6)
1.22 V + 5%
1.22 V
LM5176
1.22 V - 5 %
DITH
CDITH
图7-4. Dither Operation
7.3.11 Output Overvoltage Protection (OVP)
The LM5176-Q1 provides an output overvoltage protection (OVP) circuit that turns off the gate drives when the
feedback voltage is above the output overvoltage threshold, VOVP. Switching resumes once the feedback voltage
falls below the OVP threshold. There is a small hysteresis to prevent chattering.
7.3.12 Power Good (PGOOD)
PGOOD is an open-drain output that is pulled low when the voltage at the FB pin is outside -9%/+10% of the
nominal VREF. The PGOOD internal N-Channel MOSFET pulldown strength is typically 4.2 mA. This pin can be
connected to a voltage supply of up to 8 V through a pullup resistor.
7.3.13 Gm Error Amplifier
The LM5176-Q1 has a gm error amplifier for loop compensation. The gm amplifier output (COMP) range is 0.3 V
to 3 V. Connect an Rc1-Cc1 compensation network between COMP and ground for type II (PI) compensation (see
图 8-1). Another pole is usually added using Cc2 to suppress higher frequency noise and switching frequency
ripple.
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The COMP output voltage (VCOMP) range limits the possible VIN and IOUT range for a given design. In buck
mode, the maximum VIN for which the converter can regulate the output at no load is when VCOMP reaches 0.3 V.
方程式7 gives VCOMP as a function of VIN at no load in CCM buck mode:
2 mS∂ V - V
+ 6 mA
VOUT
(
)
sw
IN
OUT
VCOMP(BUCK) = 1.6 V - ACS ∂RSENSE
∂
∂ 1-D
(
-
∂ 1-D
(
BUCK
)
)
BUCK
2∂L1∂F
CSLOPE ∂F
sw
(7)
Where DBUCK in 方程式7 is the buck duty cycle given by:
VOUT
DBUCK
=
V
IN
(8)
A larger L1, lower slope ripple (higher CSLOPE), smaller sense resistor (RSENSE), and higher frequency can
increase the maximum VIN range for buck operation.
For boost mode, the minimum VIN for which the converter can regulate the output at full load is when VCOMP
reaches 3 V. 方程式9 gives VCOMP as a function of VIN in boost mode:
2mS∂ V
- V + 5mA
IN
≈
’
÷
◊
VOUT
V
(
)
OUT
IN
VCOMP(BOOST) = 1.6V + ACS ∂RSENSE ∂ I
∂
+
∂DBOOST
+
∂DBOOST
∆
OUT
V
2∂L1∂F
CSLOPE ∂F
sw
«
IN
sw
(9)
Where DBOOST in the 方程式9 is the boost duty cycle given by:
V
IN
DBOOST = 1-
VOUT
(10)
A larger L1, lower slope ripple (higher CSLOPE), smaller sense resistor (RSENSE), and higher frequency can
extend the minimum VI N range for boost operation.
7.3.14 Integrated Gate Drivers
The LM5176-Q1 provides four N-channel MOSFET gate drivers: two floating high-side gate drivers at the
HDRV1 and HDRV2 pins, and two ground referenced low-side drivers at the LDRV1 and LDRV2 pins. Each
driver is capable of sourcing 1.8 A and sinking 2.2-A peak current. In buck operation, LDRV1 and HDRV1 are
switched by the PWM controller while HDRV2 remains continuously on. In boost operation, LDRV2 and HDRV2
are switched while HDRV1 remains continuously on.
The low-side gate drivers are powered from VCC and the high-side gate drivers HDRV1 and HDRV2 are
powered from bootstrap capacitors CBOOT1 (between BOOT1 and SW1) and CBOOT2 (between BOOT2 and
SW2), respectively. The CBOOT1 and CBOOT2 capacitors are charged through external Schottky diodes connected
to the VCC pin as shown in 图8-1.
In most applications, ceramic capacitors of 16 V or higher voltage rating and values between 0.1 µF and 0.22 µF
are sufficient for CBOOT1 and CBOOT2
.
7.3.15 Thermal Shutdown
The LM5176-Q1 is protected by a thermal shutdown circuit that shuts down the device when the internal junction
temperature exceeds 165°C (typical). The soft-start capacitor is discharged when thermal shutdown is triggered
and the gate drivers are disabled. The converter automatically restarts when the junction temperature drops by
the thermal shutdown hysteresis of 15°C below the thermal shutdown threshold.
7.4 Device Functional Modes
Refer to the 节7.3.3 section for the description of EN/UVLO pin function. The 节7.4.1 section lists the shutdown,
standby, and operating modes for LM5176-Q1 as a function of EN/UVLO and VCC voltages.
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7.4.1 Shutdown, Standby, and Operating Modes
EN/UVLO
VCC
DEVICE MODE
EN/UVLO < VEN(STBY)
VEN(STBY) < EN/UVLO < VEN(OP)
EN/UVLO > VEN(OP)
EN/UVLO > VEN(OP)
Shutdown: VCC off, No switching
Standby: VCC on, No switching
Standby: VCC on, No switching
Operating: VCC on, Switching enabled
—
—
VCC < VUV(VCC)
VCC > VUV(VCC)
7.4.2 MODE Pin Configuration
The MODE pin is used to select hiccup mode current limit. The MODE selection is based on the voltages at the
MODE pin. The MODE voltage is decided by the programming resistor RMODE between MODE and AGND, and
the source current out of the MODE pin (IMODE). MODE is latched during start-up.
MODE PIN CONNECTION
HICCUP FAULT PROTECTION
No Hiccup
RMODE to AGND = 200 kΩor connect
MODE to VCC
Hiccup Enabled
RMODE to AGND = 93.1 kΩ
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8 Application and Implementation
Note
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The LM5176-Q1 is a four-switch buck-boost controller. A quick-start tool on the LM5176-Q1 product webpage
can be used to design a buck-boost converter using the LM5176-Q1. Alternatively, Webench® software can
create a complete buck-boost design using the LM5176-Q1 and generate bill of materials, estimate efficiency,
solution size, and cost of the complete solution. The 节 8.2 describes a detailed step-by-step design procedure
for a typical application circuit.
8.2 Typical Application
A typical application example is a buck-boost converter operating from a wide input voltage range of 6 V to 50 V
and providing a stable 12-V output voltage with current capability of 6 A.
RSNS
0 Ω
VIN
VOUT
0.1 µF
CVIN
CIN
CIN
COUT
10 µF
x5
COUT
2 kΩ
RUV2
4.7 µF
x5
180 µF
x2
68 µF
10 Ω
100 Ω
1 µF
100 Ω
249 kΩ
RUV1
QH1
QH2
59.0 kΩ
EN/UVLO
VISNS
VIN
ISNS(-)
ISNS(+)
HDRV1
L1
10 kΩ
VCC
BOOT1
VCC
PGOOD
4.7 µH
QL1
CBOOT1
0.1 µF
QL2
RMODE
SW1
MODE
93.1 kΩ
LDRV1
100 Ω
RT/SYNC
CS
CSYNC
1 nF
RSENSE
47 pF
8 mΩ
RT
CSG
27.4 kΩ
LM5176
100 Ω
SS
CSS
0.1 µF
LDRV2
BOOT2
VOUT
BIAS
VCC
CBIAS
CBOOT2
0.1 µF
0.1 µF
SW2
AGND
PGND
HDRV2
VOSNS
VCC
DITH
COMP
SLOPE
FB
CVCC
1 µF
CSLOPE
220 pF
Cc1
RRB2
33 nF
RRB1
280 kΩ
Cc2
560 pF
20 kΩ
Rc1
10 kΩ
图8-1. LM5176-Q1 Four-Switch Buck Boost Application Schematic
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8.2.1 Design Requirements
For this design example, the following are used as the input parameters.
DESIGN PARAMETER
Input Voltage Range
Output
EXAMPLE VALUE
6 V to 50 V
12 V
Load Current
6 A
Switching Frequency
Mode
300 kHz
CCM, Hiccup
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design with WEBENCH Tools
Click here to create a custom design using the LM5176-Q1 device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real
time pricing and component availability.
4. In most cases, you will also be able to:
• Run electrical simulations to see important waveforms and circuit performance,
• Run thermal simulations to understand the thermal performance of your board,
• Export your customized schematic and layout into popular CAD formats,
• Print PDF reports for the design, and share your design with colleagues.
5. Get more information about WEBENCH tools at www.ti.com/webench.
8.2.2.2 Frequency
The switching frequency of LM5176-Q1 is set by an RT resistor connected from RT/SYNC pin to AGND. The RT
resistor required to set the desired frequency is calculated using 方程式 5 or 图 6-3 . A 1% standard resistor of
27.4 kΩ is selected for Fsw = 300 kHz.
8.2.2.3 VOUT
The output voltage is set using a resistor divider to the FB pin. The internal reference voltage is 0.8 V. Normally
the bottom resistor in the resistor divider is selected to be in the 1-kΩ to 100-kΩ range. Select
RFB1 = 20 kW
(11)
(12)
The top resistor in the feedback resistor divider is selected using 方程式12:
VOUT - 0.8 V
0.8 V
RFB2
=
ìRFB1 = 280 kW
8.2.2.4 Inductor Selection
The inductor selection is based on consideration of both buck and boost modes of operation. For buck mode,
inductor selection is based on limiting the peak-to-peak current ripple, ΔIL, to approximately 40% of the
maximum inductor current at the maximum input voltage. The target inductance for buck mode is:
(VIN(MAX) - VOUT)ì VOUT
LBUCK
=
= 12.7mH
0.4ìIOUT(MAX) ìFsw ì V
IN(MAX)
(13)
For boost mode, the inductor selection is based on limiting the peak to peak current ripple, ΔIL, to approximately
30% of the maximum inductor current at the minimum input voltage. The target inductance for the boost mode is:
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VI2N(MIN) ì(VOUT - V
0.3 ìIOUT(MAX) ìFsw ì VO2UT
)
IN(MIN)
LBOOST
=
= 2.8 mH
(14)
In this particular application, the buck inductance is larger. Choosing a larger inductance reduces the ripple
current but also increases the size of the inductor. A larger inductor also reduces the achievable bandwidth of
the converter by moving the right half plane zero to lower frequencies. Therefore, a judicious compromise should
be made based on the application requirements. For this design, a 4.7-µH inductor is selected. With this inductor
selection, the inductor current ripple is 6.5 A, 4.3 A, and 2.1 A, at VIN of 50 V, 24 V, and 6 V, respectively.
The maximum average inductor current occurs at the minimum input voltage and maximum load current:
VOUT ìIOUT(MAX)
IL(MAX)
=
= 13.3 A
0.9ì V
IN(MIN)
(15)
where
• 90% efficiency is assumed
The peak inductor current occurs at minimum input voltage and is given by:
V
IN(MIN) ì(VOUT - V
)
IN(MIN)
IL(PEAK) = IL(MAX)
+
= 14.4 A
2ìL1ìF ì VOUT
sw
(16)
To ensure sufficient output current, the current limit threshold must be set to allow the maximum load current in
boost operation. The inductor peak current during overload depends on the current limit resistor, RSENSE (refer to
the subsection on selecting RSENSE). The peak inductor current in current limit when in boost mode is given by:
120 mV
IL(PEAK, ILIMIT, BOOST)
=
RSENSE
(17)
The peak inductor current in current limit when in buck mode happens at high input voltage and is given by:
V
IN(MAX) - VOUT
≈
’
(
)
VOUT
80 mV
IL(PEAK, ILIMIT, BUCK)
=
+
ì
∆
∆
«
÷
÷
◊
RSENSE
L1ìF
V
IN(MAX)
sw
(18)
The peak inductor current in current limit is 15 A and 16.5 A in boost mode and buck mode, respectively. The
inductor should be selected to handle this current.
8.2.2.5 Output Capacitor
In the boost mode, the output capacitor conducts high ripple current. The output capacitor RMS ripple current is
given by 方程式19 where the minimum VIN corresponds to the maximum capacitor current.
VOUT
ICOUT(RMS) = IOUT
ì
-1
V
IN
(19)
In this example, the maximum output ripple RMS current is ICOUT(RMS) = 6 A. A 5-mΩ output capacitor ESR
causes an output ripple voltage of 60 mV as given by:
IOUT ì VOUT
DVRIPPLE(ESR)
=
ìESR
V
IN(MIN)
(20)
A 400-µF output capacitor causes a capacitive ripple voltage of 25 mV as given by:
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V
≈
’
÷
◊
IN(MIN)
IOUT ì 1-
∆
VOUT
«
DVRIPPLE(COUT)
=
COUT ìF
sw
(21)
Typically a combination of ceramic and bulk capacitors is needed to provide low ESR and high ripple current
capacity. The complete schematic in 图8-1 shows a good starting point for COUT for typical applications.
8.2.2.6 Input Capacitor
In buck mode, the input capacitor supplies high ripple current. The RMS current in the input capacitor is given
by:
ICIN(RMS) = IOUT Dì(1-D)
(22)
The maximum RMS current occurs at D = 0.5, which gives ICIN(RMS) = IOUT / 2 = 3 A. A combination of ceramic
and bulk capacitors should be used to provide short path for high di/dt current and to reduce the output voltage
ripple. The complete schematic in 图8-1 is a good starting point for CIN for typical applications.
8.2.2.7 Sense Resistor (RSENSE
)
The current sense resistor between the CS and CSG pins should be selected to ensure that current limit is set
high enough for both buck and boost modes of operation. For the buck operation, the current limit resistor is
given by:
80 mV
RSENSE(BUCK)
=
= 13 mW
IOUT(MAX)
(23)
(24)
For the boost mode of operation, the current limit resistor is given by:
120 mV
RSENSE(BOOST)
=
= 8.3 mW
IL(PEAK)
The closest standard value of RSENSE = 8 mΩ is selected based on the boost mode operation.
The maximum power dissipation in RSENSE happens at VIN(MIN)
:
2
V
≈
’
÷
◊
≈
∆
«
’
÷
120mV
IN(MIN)
P
=
∂RSENSE ∂ 1-
= 0.9W
∆
RSENSE(MAX)
RSENSE ◊
VOUT
«
(25)
Therefore, a sense resistor with 2-W power rating will be sufficient for this application.
For some application circuits, it can be required to add a filter network to attenuate noise in the CS and CSG
sense lines. See 图8-1 for typical values. The filter resistance should not exceed 100 Ω.
8.2.2.8 Slope Compensation
For stable current loop operation and to avoid subharmonic oscillations, the slope capacitor should be selected
based on 方程式26:
L1
4.7 mH
8 mWì5
CSLOPE = gmSLOPE
ì
= 2 mSì
= 235 pF
RSENSE ì ACS
(26)
This slope compensation results in “dead-beat” operation, in which the current loop disturbances die out in
one switching cycle. Theoretically, a current mode loop is stable with half the “dead-beat” slope (twice the
calculated slope capacitor value in 方程式 26). A smaller slope capacitor results in larger slope signal which is
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better for noise immunity in the transition region (VIN~VOUT). A larger slope signal, however, restricts the
achievable input voltage range for a given output voltage, switching frequency, and inductor. For this design,
CSLOPE = 220 pF is selected for better transition region behavior while still providing the required VIN range. This
selection of slope capacitor, inductor, switching frequency, and inductor satisfies the COMP range limitation
explained in the 节7.3.13 section.
8.2.2.9 UVLO
The UVLO resistor divider must be designed for turnon below 6 V. Selecting RUV2 = 249 kΩ gives a UVLO
hysteresis of 0.8 V based on 方程式2. The lower UVLO resistor is the selected using 方程式27:
RUV2 ì VEN(OP)
RUV1
=
V
+IEN(STBY) ìRUV2 - VEN(OP)
IN
UV
(27)
A standard value of 59.0 kΩis selected for RUV1
.
When programming the UVLO threshold for lower input voltage operation, it is important to choose MOSFETs
with gate (Miller) plateau voltage lower than the minimum VIN.
8.2.2.10 Soft-Start Capacitor
The soft-start time is programmed using the soft-start capacitor. The relationship between CSS and the soft-start
time is given by:
CSS ì VREF
ISS
tss
=
(28)
CSS = 0.1 µF gives a soft-start time of 16 ms.
8.2.2.11 Dither Capacitor
The dither capacitor sets the modulation frequency of the frequency dithering around the nominal switching
frequency. A larger CDITH results in lower modulation frequency. For proper operation, the modulation frequency
(FMOD) must be much lower than the switching frequency. Use 方程式 29 to select CDITH for the target
modulation frequency.
10 mA
FMOD ì0.24 V
CDITH
=
(29)
For the current design dithering is not being implemented. Therefore a 0-Ω resistor from the DITH pin to AGND
disables this feature.
8.2.2.12 MOSFETs QH1 and QL1
The input side MOSFETs QH1 and QL1 need to withstand the maximum input voltage of 50 V. In addition, they
must withstand the transient spikes at SW1 during switching. Therefore, QH1 and QL1 should be rated for 60 V
or higher. The gate plateau voltages of the MOSFETs should be smaller than the minimum input voltage of the
converter, otherwise the MOSFETs may not fully enhance during startup or overload conditions.
The power loss in QH1 in the boost mode of operation is approximated by:
2
≈
’
÷
VOUT
V
PCOND(QH1) = I
∂
∂RDSON(QH1)
∆
OUT
«
IN ◊
(30)
The power loss in QH1 in the buck mode of operation consists of both conduction and switching loss
components given by 方程式31 and 方程式32, respectively:
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≈
∆
«
’
÷
VOUT
V
PCOND(QH1)
=
∂I
2 ∂RDSON(QH1)
OUT
IN ◊
(31)
(32)
1
2
PSW(QH1)
=
∂ VIN ∂IOUT ∂ t + t ∂F
r f sw
(
)
The rise (tr) and the fall (tf) times are based on the MOSFET datasheet information or measured in the lab.
Typically a MOSFET with smaller RDSON (smaller conduction loss) will have longer rise and fall times (larger
switching loss).
The power loss in QL1 in the buck mode of operation is shown in 方程式33:
≈
’
÷
VOUT
V
PCOND(QL1) = 1-
∂I
2 ∂RDSON(QL1)
OUT
∆
«
IN ◊
(33)
8.2.2.13 MOSFETs QH2 and QL2
The output side MOSFETs QH2 and QL2 see the output voltage of 12 V and additional transient spikes at SW2
during switching. Therefore, QH2 and QL2 should be rated for 20 V or more. The gate plateau voltages of the
MOSFETs should be smaller than the minimum input voltage of the converter, otherwise the MOSFETs may not
fully enhance during start-up or overload conditions.
The power loss in QH2 in the buck mode of operation is approximated by:
PCOND(QH2) = IOUT2 ∂RDSON(QH2)
(34)
The power loss in QL2 in the boost mode of operation consists of both conduction and switching loss
components given by 方程式35 and 方程式36, respectively:
2
≈
’ ≈
’
÷
V
VOUT
IN
PCOND(QL2) = 1-
∂ I
÷ ∆ OUT
∂
∂RDSON(QL2)
∆
VOUT ◊ «
V
«
IN ◊
(35)
(36)
≈
’
÷
VOUT
V
1
PSW(QL2)
=
∂ VOUT ∂ I
∂
∂ t + t ∂F
r f sw
(
)
∆
«
OUT
2
IN ◊
The rise (tr) and the fall (tf) times can be based on the MOSFET datasheet information or measured in the lab.
Typically a MOSFET with smaller RDSON (lower conduction loss) has longer rise and fall times (larger switching
loss).
The power loss in QH2 in the boost mode of operation is shown in 方程式37:
2
≈
’
÷
V
VOUT
IN
PCOND(QH2)
=
∂ I
∂
∂RDSON(QH2)
∆
OUT
VOUT «
V
IN ◊
(37)
8.2.2.14 Frequency Compensation
This section presents the control loop compensation design procedure for the LM5176-Q1 buck-boost controller.
The LM5176-Q1 operates mainly in buck or boost modes, separated by a transition region, and therefore, the
control loop design is done for both buck and boost operating modes. Then, a final selection of compensation is
made based on the mode that is more restrictive from a loop stability point of view. Typically for a converter
designed to go deep into both buck and boost operating regions, the boost compensation design is more
restrictive due to the presence of a right half plane zero (RHPZ) in the boost mode.
The boost power stage output pole location is given by:
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ƒp1(boost)
where
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≈
∆
’
÷
1
2
=
= 398 Hz
2p ROUT ìCOUT ◊
«
(38)
• ROUT = 2 Ω corresponds to the maximum load of 6 A
The boost power stage ESR zero location is given by:
≈
∆
’
÷
1
1
ƒz1
=
= 79.6 kHz
2p RESR ìCOUT ◊
«
(39)
(40)
The boost power stage RHP zero location is given by:
2
≈
’
ROUT ì(1-DMAX
L1
)
1
ƒRHP
=
= 16.9 kHz
∆
∆
«
÷
÷
◊
2p
where
• DMAX is the maximum duty cycle at the minimum VIN
The buck power stage output pole location is given by:
≈
∆
’
÷
1
1
ƒp1(buck)
=
= 199 Hz
2p ROUT ìCOUT ◊
«
(41)
The buck power stage ESR zero location is the same as the boost power stage ESR zero.
It is clear from 方程式40 that RHP zero is the main factor limiting the achievable bandwidth. For a robust design,
the crossover frequency should be less than 1/3 of the RHP zero frequency. Given the position of the RHP zero,
a reasonable target bandwidth in boost operation is around 4 kHz:
ƒbw = 4 kHz
(42)
For some power stages, the boost RHP zero might not be as restrictive. This happens when the boost maximum
duty cycle (DMAX) is small, or when a really small inductor is used. In those cases, compare the limits posed by
the RHP zero (fRHP / 3) with 1/20 of the switching frequency and use the smaller of the two values as the
achievable bandwidth.
The compensation zero can be placed at 1.5 times the boost output pole frequency. Keep in mind that this
locates the zero at three times the buck output pole frequency which results in approximately 30 degrees of
phase loss before crossover of the buck loop and 15 degrees of phase loss at intermediate frequencies for the
boost loop:
ƒ
= 600 Hz
zc
(43)
If the crossover frequency is well below the RHP zero and the compensation zero is placed well below the
crossover, the compensation gain resistor Rc1 is calculated using the approximation:
2pì ƒbw RFB1 +RFB2 ACS ìRSENSE ìCOUT
Rc1
=
ì
ì
= 9.49 kW
gmEA
RFB1
1-DMAX
(44)
where
• DMAX is the maximum duty cycle at the minimum VIN in boost mode
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• ACS is the current sense amplifier gain
The compensation capacitor Cc1 is then calculated from:
1
Cc1
=
= 27.9 nF
2ì pì ƒzc ìRc1
(45)
The standard values of compensation components are selected to be Rc1 = 10 kΩ and Cc1 = 33 nF.
A high frequency pole (fpc2) is placed using a capacitor (Cc2) in parallel with Rc1 and Cc1. Set the frequency of
this pole at seven to ten times of fbw to provide attenuation of switching ripple and noise on COMP while avoiding
excessive phase loss at the crossover frequency. For a target fpc2 = 28 kHz, Cc2 is calculated using 方程式46:
1
Cc2
=
= 568 pF
2ì p ì ƒpc2 ìRc1
(46)
Select a standard value of 560 pF for Cc2. These values provide a good starting point for the compensation
design. Each design should be tuned in the lab to achieve the desired balance between stability margin across
the operating range and transient response time.
8.2.3 Application Curves
100
96
92
88
84
80
99
98
97
96
95
94
93
VIN = 9V
VIN = 12V
VIN = 24V
0
1
2
3
4
LOAD CURRENT (A)
5
6
5
10
15
20
25
VIN (V)
30
35
40
45
50
D008
D009
图8-2. Efficiency vs Load
图8-3. Efficiency vs Input Voltage
VIN = 24 V
VIN
10 V/div
VIN = 12 V
VIN = 6 V
VOUT
1 V/div
IL
5 A/div
1 ms/div
200 mV/div
5 µs/div
图8-5. Line Transient Response (8 V - 24 V, IOUT = 2
图8-4. Output Voltage Ripple
A)
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9 Power Supply Recommendations
The LM5176-Q1 is a power management device. The power supply for the device is any dc voltage source
within the specified input range. The supply should also be capable of supplying sufficient current based on the
maximum inductor current in boost mode operation. The input supply should be bypassed with additional
electrolytic capacitor at the input of the application board to avoid ringing due to parasitic impedance of the
connecting cables.
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10 Layout
10.1 Layout Guidelines
The basic PCB board layout requires separation of sensitive signal and power paths. This checklist must be
followed to get good performance for a well-designed board.
• Place the power components including the input filter capacitor CIN, the power MOSFETs QL1 and QH1, and
the sense resistor RSENSE close together to minimize the loop area for input switching current in buck
operation.
• Place the power components including the output filter capacitor COUT, the power MOSFETs QL2 and QH2,
and the sense resistor RSENSE close together to minimize the loop area for output switching current in boost
operation.
• Use a combination of bulk capacitors and smaller ceramic capacitors with low series impedance for the input
and output capacitors. Place the smaller capacitors closer to the IC to provide a low impedance path for high
di/dt switching currents.
• Minimize the SW1 and SW2 loop areas as these are high dv/dt nodes.
• Layout the gate drive traces and return paths as directly as possible. Layout the forward and return traces
close together, either running side by side or on top of each other on adjacent layers to minimize the
inductance of the gate drive path.
• Use Kelvin connections to RSENSE for the current sense signals CS and CSG and run lines in parallel from
the RSENSE terminals to the IC pins. Avoid crossing noisy areas such as SW1 and SW2 nodes or high-side
gate drive traces. Place the filter capacitor for the current sense signal as close to the IC pins as possible.
• Place the CIN, COUT, and RSENSE ground pins as close as possible with thick ground trace and/or planes on
multiple layers.
• Place the VCC bypass capacitor close to the controller IC, between the VCC and PGND pins. A 1-µF ceramic
capacitor is typically used.
• Place the BIAS bypass capacitor close to the controller IC, between the BIAS and PGND pins. A 0.1-µF
ceramic capacitor is typically used.
• Place the BOOT1 bootstrap capacitor close to the IC and connect directly to the BOOT1 to SW1 pins.
• Place the BOOT2 bootstrap capacitor close to the IC and connect directly to the BOOT2 to SW2 pins.
• Bypass the VIN pin to AGND with a low ESR ceramic capacitor located close to the controller IC. A 0.1-µF
ceramic capacitor is typically used. When using external BIAS, use a diode between input rails and VIN pins
to prevent reverse conduction when VIN < VCC.
• Connect the feedback resistor divider between the COUT positive terminal and AGND pin of the IC. Place the
components close to the FB pin.
• Use care to separate the power and signal paths so that no power or switching current flows through the
AGND connections which can either corrupt the COMP, SLOPE, or SYNC signals, or cause dc offset in the
FB sense signal. The PGND and AGND traces can be connected near the PGND pin, near the VCC
capacitor PGND connection, or near the PGND connection of the CS, CSG pin current sense resistor.
• When using the average current loop, divide the overall capacitor (CIN or COUT) between the two sides of the
sense resistor to ensure small cycle-by-cycle ripple. Place the average current loop filter capacitor close to
the IC between the ISNS(+) and ISNS(-) pins.
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10.2 Layout Example
L1
SW1
SW2
VOUT
VIN
QL1
QL2
QH1
QH2
RISNS
COUT
CIN
CIN
RSENSE
COUT
LM5176
GND
GND
图10-1. LM5176-Q1 Power Stage Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
11.1.2 Development Support
11.1.2.1 Custom Design with WEBENCH Tools
Click here to create a custom design using the LM5176-Q1 device with the WEBENCH® Power Designer.
1. Start by entering your VIN, VOUT and IOUT requirements.
2. Optimize your design for key parameters like efficiency, footprint and cost using the optimizer dial and
compare this design with other possible solutions from Texas Instruments.
3. WEBENCH Power Designer provides you with a customized schematic along with a list of materials with real
time pricing and component availability.
4. In most cases, you will also be able to:
• Run electrical simulations to see important waveforms and circuit performance,
• Run thermal simulations to understand the thermal performance of your board,
• Export your customized schematic and layout into popular CAD formats,
• Print PDF reports for the design, and share your design with colleagues.
5. Get more information about WEBENCH tools at www.ti.com/webench.
11.2 Documentation Support
11.2.1 Related Documentation
Please visit TI homepage for latest technical document including application notes, user guides, and reference
designs.
Texas Instruments, Semiconductor and IC Package Thermal Metrics
11.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.5 Trademarks
PowerPAD™ is a trademark of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
Webench®, WEBENCH® and are registered trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
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11.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: LM5176-Q1
重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
15-Jan-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM5176QPWPRQ1
LM5176QPWPTQ1
ACTIVE
ACTIVE
HTSSOP
HTSSOP
PWP
PWP
28
28
2000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
-40 to 125
LM5176Q1
LM5176Q1
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
15-Jan-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Sep-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5176QPWPRQ1
HTSSOP PWP
28
2000
330.0
16.4
6.9
10.2
1.8
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Sep-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP PWP 28
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
LM5176QPWPRQ1
2000
Pack Materials-Page 2
PACKAGE OUTLINE
PWP0028C
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
0
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX
AREA
SEATING
PLANE
26X 0.65
28
1
2X
9.8
9.6
8.45
NOTE 3
14
15
0.30
0.19
28X
4.5
4.3
B
0.1
C A B
SEE DETAIL A
(0.15) TYP
2X 0.95 MAX
NOTE 5
14
15
2X 0.2 MAX
NOTE 5
0.25
GAGE PLANE
1.2 MAX
5.18
4.48
THERMAL
PAD
0.15
0.05
0.75
0.50
0 -8
A
20
DETAIL A
TYPICAL
1
28
3.1
2.4
4223582/A 03/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
PWP0028C
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
(3.1)
METAL COVERED
BY SOLDER MASK
SYMM
28X (1.5)
1
28X (0.45)
28
SEE DETAILS
(R0.05) TYP
(5.18)
(0.6)
26X (0.65)
SYMM
(9.7)
NOTE 9
SOLDER MASK
DEFINED PAD
(1.2) TYP
(
0.2) TYP
VIA
14
15
(1.2) TYP
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4223582/A 03/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
PWP0028C
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.1)
BASED ON
0.125 THICK
STENCIL
28X (1.5)
METAL COVERED
BY SOLDER MASK
1
28X (0.45)
28
(R0.05) TYP
26X (0.65)
SYMM
(5.18)
BASED ON
0.125 THICK
STENCIL
15
14
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 8X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.47 X 5.79
3.10 X 5.18 (SHOWN)
2.83 X 4.73
0.125
0.15
0.175
2.62 X 4.38
4223582/A 03/2017
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他 TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款 (https:www.ti.com.cn/zh-cn/legal/termsofsale.html) 或 ti.com.cn 上其他适用条款/TI 产品随附的其他适用条款
的约束。TI 提供这些资源并不会扩展或以其他方式更改 TI 针对 TI 产品发布的适用的担保或担保免责声明。IMPORTANT NOTICE
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