LM8323_技术文档

July 19, 2010

LM8323

Mobile I/O Companion Supporting Keyscan, I/O Expansion,

PWM, and ACCESS.bus Host Interface

Key events, errors, and dedicated hardware interrupts

request host service by asserting the IRQ output.

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1.0 General Description

The LM8323 key-scan controller is a dedicated device to un-

The correct reception of a command may be assumed, if

■

burden a host from scanning a matrix-addressed keypad. In

no error is reported from the LM8323 after receiving it.

addition, the LM8323 provides general-purpose I/O expan-

sion, a rotary encoder interface and PWM outputs useful for

dynamic LED brightness modulation.

Wake-up from Halt mode on any matrix key-scan event,

any use of the SF keys, or any activity on the ACCESS.bus

■

interface, or any change in the rotary encoder counter

It communicates with the host through an I²C-compatible

value (if enabled).

ACCESS.bus interface. An interrupt output is available for

signaling key-press and key-release events. Communication

frequencies up to 400 kHz (Fast-mode) bus speed are sup-

ported. The LM8323 supports a predefined set of commands.

These commands enable a host device to keep control over

all functions.

Host-Controlled Functions

Three PWM outputs

■

Period of inactivity that triggers entry into Halt mode

Debounce time for reliable key event polling

Configuration of general-purpose I/O ports

Various initialization options (keypad size, etc.)

2.0 Features

Key Features

Key Device Characteristics

01.8V ± 180 mV single-supply operation

■

Supports keypad matrices of up to 8 × 12 keys plus 8

■

On-chip power-on reset (POR)

special-function (SF) keys for a total of 104 keys. SF keys

pull keypad scan inputs directly to ground, rather than

connecting to a keypad scan output.

Watchdog timer

Dedicated slow clock input for 32 kHz

Supports I²C-compatible ACCESS.bus interface in slave

mode up to 400 kHz (Fast-mode).

-40°C to +85°C industrial temperature range

■

36-pin MICRO-ARRAY package

Three host-programmable PWM outputs useful for smooth

LED brightness modulation.

■

Applications

Cordless phones

■

Supports general-purpose I/O expansion on pins not

otherwise used for keypad or rotary encoder interface.

■

Smart handheld devices

Key-scan event storage in a FIFO buffer for up to 15

events.

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300211

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3.0 Block Diagram

30021120

4.0 Ordering Information

NSID

Spec.*

Firmware*

No. of Pins

Package Type

Temperature

Package Method

LM8323JGR8

NOPB

FW4

36

Micro-Array

-40°C +85°C

1000 pcs Tape &

Reel

LM8323JGR8X

LM8323JGR8AXM

LM8323JGR8AXMX

NOPB

FW4

FW6

36

Micro-Array

-40°C +85°C

3500 pcs Tape &

Reel

1000 pcs Tape &

Reel

3500 pcs Tape &

Reel

*Note: NOPB = No PB (No Lead)

Firmware version FW6 will replace FW4.

Firmware version FW4 is not recommended for new designs.

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5.0 Pin Assignments

30021121

Top View

36-Pin MICRO-ARRAY Package

See NS Package Number GRA36A

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Table of Contents

1.0 General Description ......................................................................................................................... 1

2.0 Features ........................................................................................................................................ 1

3.0 Block Diagram ................................................................................................................................ 2

4.0 Ordering Information ........................................................................................................................ 2

5.0 Pin Assignments ............................................................................................................................. 3

6.0 Signal Descriptions .......................................................................................................................... 6

6.1 TERMINATION OF UNUSED SIGNALS ...................................................................................... 7

7.0 Application Example ........................................................................................................................ 8

7.1 FEATURES ............................................................................................................................. 8

8.0 Clocks ........................................................................................................................................... 9

8.1 INTERNAL EXECUTION CYCLE ............................................................................................... 9

8.2 BUFFERED CLOCK ................................................................................................................. 9

8.3 CLOCK CONFIGURATION ..................................................................................................... 10

9.0 Reset ........................................................................................................................................... 11

9.1 EXTERNAL RESET ................................................................................................................ 11

9.2 POWER-ON RESET (POR) ..................................................................................................... 11

9.3 PIN CONFIGURATION AFTER RESET .................................................................................... 11

9.4 DEVICE CONFIGURATION AFTER RESET .............................................................................. 12

9.5 CONFIGURATION INPUTS ..................................................................................................... 12

9.6 INITIALIZATION ..................................................................................................................... 12

9.7 INITIALIZATION EXAMPLE ..................................................................................................... 14

10.0 Halt Mode ................................................................................................................................... 15

10.1 ACCESS.bus ACTIVITY ........................................................................................................ 15

11.0 Keypad Interface ......................................................................................................................... 16

11.1 EVENT CODE ASSIGNMENT ................................................................................................ 16

11.2 KEYPAD SCAN CYCLES ...................................................................................................... 16

11.2.1 Timing Parameters ..................................................................................................... 17

11.2.2 Multiple Key Pressings ................................................................................................ 17

11.3 EXAMPLE KEYPAD CONFIGURATION .................................................................................. 18

12.0 General-Purpose I/O Ports ............................................................................................................ 19

12.1 USING THE CONFIG_X PINS FOR GPIO ............................................................................... 19

12.2 USING THE ROT_IN_X PINS FOR GPIO ................................................................................ 19

12.3 GPIO TIMING ...................................................................................................................... 19

13.0 Rotary Encoder Interface .............................................................................................................. 21

14.0 PWM Output Generation ............................................................................................................... 23

14.1 COMMAND QUEUE ............................................................................................................. 23

14.2 PWM TIMER OPERATION .................................................................................................... 23

14.3 PWM SCRIPT COMMANDS .................................................................................................. 24

14.4 RAMP COMMAND ............................................................................................................... 25

14.5 SET_PWM COMMAND ......................................................................................................... 25

14.6 GO_TO_START COMMAND ................................................................................................. 25

14.7 BRANCH COMMAND ........................................................................................................... 25

14.8 END COMMAND .................................................................................................................. 26

14.9 TRIGGER COMMAND .......................................................................................................... 26

14.10 PWM SCRIPT EXAMPLE .................................................................................................... 26

14.10.1 PWM Channel 0 Script .............................................................................................. 27

14.10.2 PWM Channel 1 Script .............................................................................................. 27

14.10.3 PWM Channel 2 Script .............................................................................................. 27

14.11 SELECTABLE SCRIPT EXAMPLE ........................................................................................ 28

15.0 Digital Multiplexers ....................................................................................................................... 29

16.0 Host Interface ............................................................................................................................. 29

16.1 START AND STOP CONDITIONS .......................................................................................... 29

16.2 CONTINUOUS COMMAND STRINGS .................................................................................... 29

16.3 DEVICE ADDRESS .............................................................................................................. 30

16.4 HOST WRITE COMMANDS .................................................................................................. 30

16.5 HOST READ COMMANDS .................................................................................................... 30

16.6 INTERRUPTS ...................................................................................................................... 31

16.7 INTERRUPT CODE .............................................................................................................. 31

16.8 ERROR CODE ..................................................................................................................... 32

16.9 WAKE-UP FROM HALT MODE .............................................................................................. 32

17.0 Host Commands .......................................................................................................................... 33

17.1 READ_ID COMMAND ........................................................................................................... 34

17.2 WRITE_CFG COMMAND ...................................................................................................... 34

17.3 READ_INT COMMAND ......................................................................................................... 35

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17.4 RESET COMMAND .............................................................................................................. 35

17.5 WRITE_PULL_DOWN COMMAND ......................................................................................... 35

17.6 WRITE_PORT_SEL COMMAND ............................................................................................ 36

17.7 WRITE_PORT_STATE COMMAND ........................................................................................ 36

17.8 READ_PORT_SEL COMMAND ............................................................................................. 36

17.9 READ_PORT_STATE COMMAND ......................................................................................... 36

17.10 READ_FIFO COMMAND ..................................................................................................... 37

17.11 RPT_READ_FIFO COMMAND ............................................................................................. 37

17.12 SET_ACTIVE COMMAND ................................................................................................... 37

17.13 READ_ERROR COMMAND ................................................................................................. 38

17.14 READ_ROTATOR COMMAND ............................................................................................. 38

17.15 SET_DEBOUNCE COMMAND ............................................................................................. 38

17.16 SET_KEY_SIZE COMMAND ................................................................................................ 38

17.17 READ_KEY_SIZE COMMAND ............................................................................................. 38

17.18 READ_CFG COMMAND ..................................................................................................... 39

17.19 WRITE_CLOCK COMMAND ................................................................................................ 39

17.20 READ_CLOCK COMMAND ................................................................................................. 39

17.21 PWM_WRITE COMMAND ................................................................................................... 39

17.22 PWM_START COMMAND ................................................................................................... 40

17.23 PWM_STOP COMMAND ..................................................................................................... 40

18.0 Absolute Maximum Ratings ........................................................................................................... 41

19.0 DC Electrical Characteristics ......................................................................................................... 41

20.0 AC Electrical Characteristics ......................................................................................................... 42

21.0 Physical Dimensions .................................................................................................................... 43

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6.0 Signal Descriptions

A6

A5

F1

Function

KP-X0

I/O

Input

I/O

Description

Wake-up input/Keyboard scanning input 0

Wake-up input/Keyboard scanning input 1

Wake-up input/Keyboard scanning input 2

Wake-up input/Keyboard scanning input 3

General-purpose I/O port 13

Wake-up input/Keyboard scanning input 4

General-purpose I/O port 12

Wake-up input/Keyboard scanning input 5

General-purpose I/O port 11

Wake-up input/Keyboard scanning input 6

General-purpose I/O port 10

Wake-up input/Keyboard scanning input 7

General-purpose I/O port 9

Keyboard scanning output 0

Keyboard scanning output 1

Keyboard scanning output 2

Keyboard scanning output 3

General-purpose I/O port 8

Keyboard scanning output 4

General-purpose I/O port 7

Keyboard scanning output 5

General-purpose I/O port 6

Keyboard scanning output 6

General-purpose I/O port 5

Keyboard scanning output 7

General-purpose I/O port 4

Keyboard scanning output 8

32.768 kHz clock output

KP-X1

KP-X2

KP-X3

F2

A2

B3

A3

B4

GPIO_13

KP-X4

Input

I/O

GPIO_12

KP-X5

Input

I/O

GPIO_11

KP-X6

Input

I/O

GPIO_10

KP-X7

Input

Output

I/O

GPIO_09

KP_Y0

C6

C5

B6

KP-Y1

KP-Y2

KP-Y3

B5

B2

A1

B1

C2

GPIO_08

KP-Y4

Output

I/O

GPIO_07

KP-Y5

Output

I/O

GPIO_06

KP-Y6

Output

I/O

GPIO_05

KP-Y7

Output

I/O

GPIO_04

KP-Y8

Output

I/O

E3

D5

E6

F6

SLOWCLKOUT

GPIO_03

KP-Y9

General-purpose I/O port 3

Keyboard scanning output 9

Multiplexer 2 input 1

Output

Input

I/O

MUX2_IN1

GPIO_02

KP-Y10

General-purpose I/O port 2

Keyboard scanning output 10

Multiplexer 2 input 2

Output

Input

I/O

MUX2_IN2

GPIO_01

KP-Y11

General-purpose I/O port 1

Keyboard scanning output 11

Multiplexer 2 output

Output

I/O

MUX2_OUT

GPIO_00

ACB_SDA

ACB_SCL

PWM_0

MUX_IN1

PWM_1

MUX_IN2

PWM_2

MUX1_OUT

CONFIG_2

GPIO_15

General-purpose I/O port 0

ACCESS.bus data signal

E2

E1

I/O

ACCESS.bus clock signal

Output

Input

Output

Input

Output

Input

I/O

Pulse-width modulated output 0

Multiplexer 1 input 1

E4

F5

Pulse-width modulated output 1

Multiplexer 1 input 2

Pulse-width modulated output 2

Multiplexer 1 output

E5

Slave address select input 2

General-purpose I/O port 15

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D6

D1

D2

Function

CONFIG_1

GPIO_14

XTAL_OUT

SLOWCLK

XTAL_IN

IRQ

I/O

Input

I/O

Description

Slave address select input 1

General-purpose I/O port 14

32.768 kHz crystal output

32.768 kHz clock

32.768 kHz crystal input

Interrupt request output

Reset Input

Output

Input

Output

Input

N/A

F3

C1

RESET

A4, F4

VCC

V_CC

C3, C4,

D3, D4

GND

N/A

Ground

6.1 TERMINATION OF UNUSED SIGNALS

TABLE 1. Termination of Unused Signals

Termination

Signal

RESET

Connect to VCC if not driven from an external Supervisory circuit.

Connect to VCC or GND through a pullup or pulldown resistor because the slave address is

selected by the level on this pin. This pin cannot be left unconnected.

CONFIG_1

XTAL_IN

This pin is a high-impedance input and must be connected to VCC or GND if it is unused.

This pin has a weak pullup and can be left open-circuit if it is unused.

XTAL_OUT

These pins are dedicated keypad pins. In the minimum configuration, these pins are keypad inputs

with weak pullups.

KP-X[2:0]

KP-X[7:3]

These pins are in high-impedance mode after power-on initialization. There are two ways to handle

these pins if unused:

•

Connect to VCC or GND.

Program as inputs with weak pullups or outputs.

Care must be taken when connecting to VCC or GND. Erroneous parameters sent with the

WRITE_PORT_SEL or WRITE_PORT_STATE commands could cause excessive current

consumption. A better approach is to leave unused keyboard inputs open-circuit and use the

WRITE_PORT_SEL and WRITE_PORT_STATE commands to configure the pins as inputs with

weak pullups or outputs.

KP-X7 can only be an input. This pin should be programmed as an input with a weak pullup.

These pins are dedicated keypad pins. In the minimum configuration, these pins are keypad outputs

driven low.

KP-Y[2:0]

These pins are in high-impedance mode after power-on initialization. There are two ways to handle

these pins if unused:

•

Connect to V_CCor GND.

Program as inputs with weak pullups or outputs

KP-Y[11:3]

Care must be taken when connecting to VCC or GND. Erroneous parameters sent with the

WRITE_PORT_SEL or WRITE_PORT_STATE commands could cause excessive current

consumption. A better approach is to leave unused keyboard inputs open-circuit and use the

WRITE_PORT_SEL and WRITE_PORT_STATE commands to configure the pins as inputs with

weak pullups or outputs.

PWM_0,

PWM_1

These pins must be connected to VCC or GND if they are not used for any optional function

described in the datasheet.

PWM_2/

CONFIG_2

Connect to VCC or GND through a pullup or pulldown resistor because the slave address is

selected by the level on this pin. This pin cannot be left unconnected.

IRQ

This pin must be connected.

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7.0 Application Example

30021101

FIGURE 1. Typical Application

7.1 FEATURES

and CONFIG_2) could be used as an additional PWM

driver port to control a third external LED.

The application example shown in Figure 1 supports the fol-

•

Rotary encoder interface shares pins with KP-Y9, KP-Y10,

and KP-Y11. For larger keyboard configurations (such as

QWERTY layouts), the rotary encoder interface is not

available.

ACCESS.bus address is selected by the CONFIG_1 and

CONFIG_2 inputs. These pins may also be used as GPIO

pins after reset initialization has occurred. If extra GPIO

pins are not needed, CONFIG_1 and CONFIG_2 may be

tied directly to VCC and GND.

Crystal pins XTAL_IN and XTAL_OUT may be used to

connect to an external 32.768 kHz crystal or receive an

external 32.768 kHz clock input for running the PWM

peripheral. By default, the PWM is clocked by an on-chip

clock source.

lowing features:

•

8 x 9 standard keys.

8 special function keys (SF keys) with wake-up capability

by forcing a WAKE_INx pin to ground. Pressing a SF key

overrides any other key in the same row.

•

ACCESS.bus (I²C-compatible) interface for

communication with the host.

Hardware IRQ interrupt to host to signal keypad, rotary

encoder, error, and status events. By default, this is an

open-drain output, so an external pullup resistor may be

required to avoid false assertion. The host can program

this output for push-pull mode, in which case the pullup

might not be required, if the host can ignore a false

assertion before the LM8323 has been programmed.

•

Two LEDs driven by PWM outputs with programmable

ramp-up and ramp-down. PWM_2 (shared with GPIO_15

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Execution Clock. This clock is close to 32 kHz which is in

a good range to source the PWM function block as an

alternative to an external clock source.

External 32.768 kHz Clock — driven into the SLOWCLK

input. May be used internally as the timebase for the PWM

and driven on the SLOWCLKOUT output.

External 32.768 kHz Crystal — connected across the

XTAL_IN and XTAL_OUT pins (XTAL_IN is an alternate

function of the SLOWCLK pin). May be used internally as

the timebase for the PWM and driven on the

SLOWCLKOUT output.

8.0 Clocks

•

System Clock (mclk) — The system clock is in the range

of about 21 MHz (±7%) typical. This clock is used to drive

the I²C-compatible serial ACCESS bus and is the input

clock for other function blocks.

•

Processing and Command Execution Clock (t_C) — The

internal processing is based on a 2MHz clock. This clock

is derived from the System Clock.

Internal PWM Clock — The internal PWM clock is a fixed

scaled down clock (÷ 64) of the Processing and Command

30021102

FIGURE 2. Clock Architecture

8.1 INTERNAL EXECUTION CYCLE

8.2 BUFFERED CLOCK

The Processing - and Command - execution clock is about

2MHz. This clock is stopped in Halt mode, which only occurs

under control of the LM8323. However, the host can set the

period of inactivity which causes the device to enter Halt

mode.

The timebase for the PWM comes from any of three sources:

•

Prescaled internal Execution clock.

External 32.768 kHz clock received on the SLOWCLK

input.

•

On-chip oscillator with an external crystal connected

across XTAL_IN and XTAL_OUT.

Exit from Halt mode can be triggered by any of these events:

•

Occurrence of a key-press or key-release event.

A Start condition driven by the host on the ACCESS.bus

interface.

Any of these sources may be buffered and driven on the

SLOWCLKOUT output. The clock buffer is enabled with the

WRITE_CLOCK command.

•

Any change to the rotary encoder counter value (if the

interface is enabled).

If XTAL_IN is not used it must be terminated to VCC or GND.

•

Assertion of the RESET input.

After reset, the default timebase for the PWM outputs is the

internal execution clock divided by 64.

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8.3 CLOCK CONFIGURATION

mand. The WRITE_CLOCK command must be issued only

once during system initialization. This command is used to

override the default settings.

Table 2 shows the clock configurations available by loading

the clock configuration register with the WRITE_CLOCK com-

TABLE 2. Clock Configuration Register

7

6

5

4

3

2

1

0

SLOWCLKOUT

0

SLOWCLKEN

0

RCPWM

Bit

Value

Description

0

Disable SLOWCLKOUT buffer.

Enable SLOWCLKOUT buffer.

SLOWCLKOUT

1

0

External 32.768 kHz crystal is installed between the XTAL_IN and XTAL_OUT pins.

SLOWCLKEN

External 32.768 kHz clock is received on the SLOWCLK pin, or no 32.768 kHz clock

is required.

1

00

01

10

11

On-chip RC clock divided by 64 drives the PWM and clock buffer.

Reserved

RCPWM

Reserved

External 32.768 kHz clock or crystal drives the PWM and clock buffer.

The SLOWCLKOUT signal is an alternate function of the pin

used for the KP-Y8 scanning output and the GPIO_03 port. If

the SLOWCLKOUT function is enabled, these other functions

of the pin are unavailable.

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When the RESET pin goes high, the LM8323 comes out of

the reset state within about 1400 ns.

9.0 Reset

The LM8323 may be reset by either an external reset, RE-

SET command, or an internally generated power-on reset

(POR) signal. The RESET input must not be allowed to float.

If the external RESET input is not used, it must be connected

to VCC, either directly or through a pull-up resistor.

9.2 POWER-ON RESET (POR)

The POR circuit is always enabled. When V_CCrises above the

POR threshold voltage V_POR(about 1.2–1.5V), an on-chip re-

set signal is asserted. The V_CCrise time must be greater than

20 µs and less than 10 ms, otherwise the on-chip reset signal

may deassert before V_CCreaches the minimum operating

voltage. While V_CCis below V_POR, the LM8323 is held in reset

and a timer clocked by the on-chip RC clock is preset with

0xFF (256 clock cycles). When V_CCreaches a value greater

than V_POR, the timer starts counting down. When it under-

flows, the on-chip reset signal is deasserted and the LM8323

begins operation.

9.1 EXTERNAL RESET

The device enters a reset state immediately when the RE-

SET input is driven low. RESET must be held low for a

minimum of 700 ns to guarantee a valid reset. If RESET is

asserted at power-on, it must be held low until V_CCrises above

the minimum operating voltage (1.62V). If an RC circuit is

used to drive RESET, it must have a time constant 5 times

(5×) greater than the V_CCrise time to this level.

9.3 PIN CONFIGURATION AFTER RESET

When RESET goes low, the I/O ports are initialized immedi-

ately, any observed delay being only propagation delay.

Table 3 shows the pin configuration after reset.

TABLE 3. Pin Configuration After Reset

Pins

KP-X00

KP-X01

KP-X02

KP-X03

KP-X04

KP-X05

KP-X06

KP-X07

KP-Y00

KP-Y01

KP-Y02

KP-Y03

KP-Y04

KP-Y05

KP-Y06

KP-Y07

KP-Y08

KP-Y09

KP-Y10

KP-Y11

CONFIG_1

CONFIG_2

IRQ

After Reset

After LM8323 Initialization

High-impedance mode.

Input mode with an on-chip pullup enabled.

High-impedance mode, until host configures them as keypad inputs

or GPIO.

High-impedance mode.

Active drive low.

High-impedance mode, until host configures them as keypad outputs

or GPIO.

High-impedance mode.

The ACCESS.bus slave address must be selected with external

pullup or pulldown resistors or direct connections to VCC or GND.

High-impedance mode.

Active drive low.

PWM_0

PWM_1

PWM_2

ACB_SDA

ACB_SCL

XTAL_IN

XTAL_OUT

RESET

High-impedance mode.

Open-drain mode.

High-impedance mode.

Weak pullup device.

High-impedance mode. Terminate to VCC or GND if not used.

Weak pullup device.

High-impedance mode.

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9.4 DEVICE CONFIGURATION AFTER RESET

After the LM8323 has completed its reset initialization, it will

have the following internal configuration:

•

PWM Clock: The PWM clock source is the on-chip clock

divided by 64. This remains in effect until changed by a

host command.

•

Keypad Size: 3 × 3.

Rotary Encoder Interface: disabled.

Digital Multiplexers: disabled.

IRQ: enabled, active low.

NOINIT Bit : set.

Debounce Time: 3 scan cycles (about 12 milliseconds).

Active Time: 500 milliseconds.

Note: When FW6 version devices receive a RESET com-

mand the IRQ line is set high and held high for 60 ms and then

pulled low to show the device was successfully reset and is

ready to be used.

9.5 CONFIGURATION INPUTS

The states sampled from the CONFIG_1 and CONFIG_2 in-

puts during reset select the ACCESS.bus address used by

the LM8323, as shown in Table 4. The address occupies the

high seven bits of the first byte of a bus transaction, with the

LSB (shown as X below) indicating the direction of transfer.

TABLE 4. Bus Address Selection

CONFIG_1

CONFIG_2

Bus Address

1000 010X

1000 011X

1000 100X

1000 101X

0

1

0

1

0

1

30021103

FIGURE 3. LM8323 Initialization Behavior

When these pins are used as GPIO ports, the design must

ensure that they have the desired states during reset. For ex-

ample, a 100-kΩ resistor to ground can impose a logic 0

during reset without interfering with normal operation as a

GPIO port.

Figure 4 shows the timing of IRQ relative to a RESET or POR

event and the WRITE_CFG command. 100 µs after a RE-

SET or POR event, IRQ is asserted and any READ_INT

command will return an interrupt code with the NOINIT bit set.

90 µs after a WRITE_CFG command is received, IRQ is de-

asserted.

9.6 INITIALIZATION

The LM8323 waits for a WRITE_CFG command from the

host. During this time, IRQ is asserted to request service from

the host. Figure 3 describes the behavior of the LM8323 fol-

lowing reset.

30021104

FIGURE 4. IRQ Reset Timing

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After sending the WRITE_CFG command, the host must send

a series of commands to configure the LM8323, as shown in

Figure 5. (See left hand side.)

quest received from the LM8323 during operation. Such

requests will be made from the LM8323 as a result of key

pressed events, the detection of an error, the termination of

a PWM cycle and others.

This Flow - diagram illustrates also the basic host communi-

cation steps which the host must execute upon an IRQ re-

30021105

FIGURE 5. Host-Side LM8323 Initialization

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9.7 INITIALIZATION EXAMPLE

Most of these settings can be verified by executing com-

mands such as READ_CONF, READ_PORT_SEL,

READ_CLOCK, etc.

In the following example, the LM8323 is configured as:

•

Keypad matrix configuration is 8 × 4.

Rotary encoder interface enabled.

GPIO_03 through GPIO_07 are available to use as GPIO

pins.

ALL GPIO pin states can be read using the

READ_PORT_STATE command, without regard to whether

the pin is an input or an output.

An open-drain signal can be created by alternating between

input mode and driving the output low.

•

GPIO_03 is an output driven low.

GPIO_4 and GPIO_5 are outputs driven high.

GPIO_06 and GPIO_07 are inputs with weak pulldowns.

GPIO_14 and GPIO_15 are inputs with weak pullups.

The PWM clock source is the internal execution clock

divided by 64 (about 32 kHz).

All GPIOs can sink and source 16 mA when configured as an

output.

Command

Encoding Parameter 1 Parameter 2

Description

Selects 36-pin package and disables the two digital

multiplexers.

WRITE_CFG

0x81

0x40

SLOWCLKOUT disabled, no external 32.768 kHz clock

required, PWM clock source is internal.

WRITE_CLK

SET_KEY_SIZE

SET_ACTIVE

0x93

0x90

0x8B

0x08

0x84

0x4B

Selects a keypad matrix size of 8 × 4.

Sets the active time to about 300 milliseconds (75 × 4

milliseconds).

Sets the key debouncing time to about 12 milliseconds

(3 × 4 ms). This is actually the default and would not have

to be performed.

SET_DEBOUNCE

0x8F

0x85

0x03

0x00

Configure GPIO_03, GPIO_04, and GPIO_05 as

outputs. Configure GPIO_06, GPIO_07, GPIO_14, and

GPIO_15 as inputs.

WRITE_PORT_SEL

0x38

0x3F

0xF0

Set the direction for the pullup/pulldown devices on

GPIO_06 and GPIO_07 to pulldown. Set the direction for

the pullup/pulldown devices on GPIO_14 and GPIO_15

to pullup.

WRITE_PULL_DOWN

WRITE_PORT_STATE

0x84

0x86

0x00

0xC0

Set GPIO_04 and GPIO_05 to drive high. Enable the

pullups on GPIO_06, GPIO_07, GPIO_14, and

GPIO_15.

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14

Halt mode is entered when no key-press event, key-release

event, change in the rotary encoder counter value or

ACCESS.bus activity is detected for a certain period of time

(by default, 500 ms). The mechanism for entering Halt mode

is always enabled in hardware, but the host can program the

period of inactivity which triggers entry into Halt mode.

10.0 Halt Mode

The fully static architecture of the LM8323 allows stopping the

internal RC clock in Halt mode, which reduces power con-

sumption to the minimum level. Figure 6 shows the current in

Halt mode at the maximum V_CC(1.98V) from 25°C to +85°C.

Note: When FW4 version devices enter the Halt mode there

is approximately a 33% chance the device may miss key

events during the period of 3ms before entering Halt mode

until 3ms after entering Halt mode resulting in lost key events.

This was corrected in FW6 devices so that 100% of all key

events are captured, even as the device is entering Halt

mode.

10.1 ACCESS.bus ACTIVITY

When the LM8323 is in Halt mode, any activity on the

ACCESS.bus interface will cause the LM8323 to exit from

Halt mode. However, the LM8323 will not be able to acknowl-

edge the first bus cycle immediately following wake-up from

Halt mode. It will respond with a negative acknowledgement,

and the host should then repeat the cycle.

The LM8323 will be prevented from entering Halt mode if it

shares the bus with peripherals that are continuously active.

For lowest power consumption, the LM8323 should only

share the bus with peripherals that require little or no bus ac-

tivity after system initialization.

30021106

FIGURE 6. Halt Current vs. Temperature at 1.98V

15

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mode to minimize power consumption (typically <9 µA stand-

by current).

11.0 Keypad Interface

Table 5 lists the codes assigned to the matrix positions en-

coded by the hardware. Key-press events are assigned the

codes listed in Table 5, but with the MSB set. When a key is

released, the MSB of the code is clear.

11.1 EVENT CODE ASSIGNMENT

After power-on reset and host initialization, the LM8323 starts

scanning the keypad. It stays active for a default time of about

500 ms after the last key is released, after which it enters Halt

TABLE 5. Keypad Matrix Code Assignments

KP-Y0 KP-Y1 KP-Y2 KP-Y3 KP-Y4 KP-Y5 KP-Y6 KP-Y7 KP-Y8 KP-Y9 KP-Y10 KP-Y11 SF Keys

KP-X0

KP-X1

KP-X2

KP-X3

KP-X4

KP-X5

KP-X6

KP-X7

0x01

0x11

0x21

0x31

0x41

0x51

0x61

0x71

0x02

0x12

0x22

0x32

0x42

0x52

0x62

0x72

0x03

0x13

0x23

0x33

0x43

0x53

0x63

0x73

0x04 0x05 0x06

0x14 0x15 0x16

0x24 0x25 0x26

0x34 0x35 0x36

0x44 0x45 0x46

0x54 0x55 0x56

0x64 0x65 0x66

0x74 0x75 0x76

0x07

0x17

0x27

0x37

0x47

0x57

0x67

0x77

0x08

0x18

0x28

0x38

0x48

0x58

0x68

0x78

0x09

0x19

0x29

0x39

0x49

0x59

0x69

0x79

0x0A

0x1A

0x2A

0x3A

0x4A

0x5A

0x6A

0x7A

0x0B

0x1B

0x2B

0x3B

0x4B

0x5B

0x6B

0x7B

0x0C

0x1C

0x2C

0x3C

0x4C

0x5C

0x6C

0x7C

0x0F

0x1F

0x2F

0x3F

0x4F

0x5F

0x6F

0x7F

When the rotary encoder interface is enabled, KP-Y9, KP-

Y10, and KP-Y11 (bolded in Keypad Matrix Code Assign-

ments) become unavailable for keypad scanning, which limits

the keypad to a maximum size of 8 × 9 + 8 SF keys.

The codes are loaded into the FIFO buffer in the order in

which they occurred. Table 6 shows an example sequence of

events, and Figure 7 shows the resulting sequence of event

codes loaded into the FIFO buffer.

TABLE 6. Example Sequence of Events

Event on Input Driven Output

KP-X4 KP-Y4

Event Number

Event Code

0xC5

Description

Key is pressed

1

2

3

4

5

6

7

8

0xB2

KP-X3

KP-X4

KP-X3

KP-X0

KP-X5

KP-X0

N/A

KP-Y1

KP-Y4

KP-Y1

KP-Y0

N/A

Key is pressed

0x45

Key is released

0x32

Key is released

0x81

Key is pressed

0x5F

SF Key is released

Key is released

0x01

KP-Y0

N/A

0x00

Indicates end of stored events

30021107

FIGURE 7. Example Event Codes Loaded in FIFO Buffer

11.2 KEYPAD SCAN CYCLES

The LM8323 starts new scan cycles at fixed time intervals of

about 4 milliseconds. If a change in the state of the keypad is

detected, the keypad is rescanned after a debounce delay.

When the state change has been reliably captured, it is en-

coded and written to the FIFO buffer.

Figure 8 shows the relationship between a KP-Yx output and

a KP-Xx input over multiple scan cycles during a key press

event. Between scan cycles, the KP-Yx outputs that are spec-

ified by the SET_KEY_SIZE command (0x90) for keypad

scanning are driven low.

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16

The SF keys connect KP-Xx inputs directly to ground. There

can be up to eight SF keys. If any of these keys are pressed,

other keys that use the same KP-Xx pin are ignored.

11.2.1 Timing Parameters

Two timing parameters affect scanning of the keypad:

•

Debounce Time — minimum delay between detecting a

keypad event and confirming the event before asserting

IRQ. The default debounce time is 3 scan cycles (about

12 milliseconds), but the host can set values in the range

1–255 cycles (4–1020 milliseconds).

•

Active Time — period without detecting a state change in

the keypad or rotary encoder that triggers entry into Halt

mode, during which keypad scanning is suspended. The

default active time is 500 milliseconds, but the host can set

it values in the range 4–1020 milliseconds. The active time

must be greater than the debounce time.

30021108

FIGURE 8. Keypad Scan Cycles

11.2.2 Multiple Key Pressings

During a scan cycle, only one KP-Yx output pin will be driven

low at any time, while the others are driven high or undriven.

At the time scale used in Figure 8, the low phase of a KP-Yx

output during a scan cycle is not visible. The KP-Xx input pins

are pulled high by weak pullups.

If more than two keys are pressed at the same time, the

LM8323 stores all key pressed and released events in the

FIFO buffer in the sequence in which they were decoded.

For multiple key pressings the following circumstances have

to be respected:

There are capacitive loads on the KP-Xx inputs and KP-Yx

outputs due to protection circuits, wiring, etc. The LM8323 in-

serts delays to allow complete charging or discharging of

these loads before sampling the input levels on the KP-Xx

inputs. The maximum parasitic load capacitance on the KP-

Xx inputs is 5nF.

•

A multiple key-press event is given if two or more key-

press events are reported but no corresponding key-

release event.

With the activity time set between the minimum and

maximum time (4 ms to 1 second) it is not safe to detect

two simultaneous key pressings in one input row (see

Figure 9 on the left hand side.)

If all key pressings (two or more) are located in different

input rows (see Figure 9 on the right hand side) then the

key pressed events will be correctly found in the FIFO

buffer without any restriction.

•

After detecting a key-press or key-release event, the de-

bounce time specified by the SET_DEBOUNCE command

(0x8F) sets the minimum time for confirming the event before

the IRQ output is asserted.

•

If more than two keys are pressed simultaneously, the pattern

of key closures may be ambiguous, in which case the the in-

terrupt code indicates an error and the IRQ output is asserted

(if enabled).

30021109

FIGURE 9. Simultaneous Keys Pressed

•

In order to securely detect and store the key codes of

simultaneous key pressings in the same input row the

following precautions must be taken from the host side:

the host must send the SET_ACTIVE Command again with

the parameter setting the desired duration for the active time.

This will enable the LM8323 to enter low power HALT mode

once the activity time has passed without detecting any

events.

As soon as the host device has detected a key pressed event

the host must send the SET_ACTIVE Command with the pa-

rameter set to “00”. This will prevent the LM8323 from enter-

ing HALT mode. If all keyboard events are resolved (no

remaining key pressed status in the LM8323 anymore) then

•

Once one or more key (pressed and/or released) events

have been read from the host with the help of the READ

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FIFO command there are two conditions cleaning the

FIFO buffer contents:

scanning outputs (KP-Y0 through KP-Y3). The remaining

scanning outputs KP-Y4 through KP-Y11 are available for use

as GPIO pins. Enabling the rotary encoder interface reduces

the number of available GPIO pins to KP-Y4 through KP-Y8.

A second execution of the READ FIFO Command or,

A new key event detected from the LM8323.

—

11.3 EXAMPLE KEYPAD CONFIGURATION

Figure 10 shows an 8 × 4 keypad matrix. This configuration

occupies all scanning inputs (KP-X0 through KP-X7) and four

30021110

FIGURE 10. Keypad Interface Example

In the example above, three keys (Up, Down, and Select) are

connected as SF keys (connected directly to ground). Al-

though they could have shared the KP-Xx inputs used with

the scanned keys, the advantage of placing them on their own

KP-Xx inputs is that it allows scanning the keypad while an

SF key is pressed. If an SF key shares a KP-Xx input with any

scanned keys, pressing the SF key prevents the LM8323 from

reading the scanned keys.

specify the number of KP-Xx inputs, and the lower 4 bits

specify the number of KP-Yx outputs. The minimum number

of inputs and outputs is 3. Therefore, the minimum keypad

configuration supports 3 × 3 + 3 SF keys (total of 12 keys).

The maximum number of KP-Xx inputs is 8, and the maximum

number of KP-Yx pins is 12. All KP-Xx and KP-Yx pins not

used for the keyboard interface can be used for general-pur-

pose I/O.

The SET_KEY_SIZE command includes a data byte that

specifies the keypad size. The upper 4 bits of the data byte

For the example shown in Figure 10, the SET_KEY_SIZE

command would specify 8 KP-Xx inputs and 4 KP-Yx outputs.

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18

put selects between a high-impedance input or an input with

a pullup or pulldown device. The selection between pullup or

pulldown devices is controlled by the parameter bytes to the

WRITE_PULL_DOWN (0x84) command. Clear bits in the pa-

rameter bytes select pullup devices, while set bits select

pulldown devices.

12.0 General-Purpose I/O Ports

Any unused KP-Xx and KP-Yx pins may be used as general-

purpose I/O (GPIO) port pins. The WRITE_PORT_SEL

(0x85) command selects the port direction, in which a clear

bit in the parameter to the command selects the input direction

and a set bit selects the output direction.

Table 7 shows the GPIO port configurations selected by the

bits in the WRITE_PORT_SEL, WRITE_PORT_STATE, and

WRITE_PULL_DOWN command parameters.

The WRITE_PORT_STATE (0x86) command selects either

the port level when configured as output (by the

WRITE_PORT_SEL command) or when configured as an in-

TABLE 7. GPIO Port Control Bits

WRITE_PORT_SEL

WRITE_PORT_STATE

WRITE_PULL_DOWN

Description

High-Impedance Input

0

1

0

1

0

1

x

0

1

x

Input with Pullup Device

Input with Pulldown Device

Output, Drive Low

Output, Drive High

Any pins used as GPIO ports must be configured after the

peripheral configuration has been initialized with the

WRITE_CFG command (0x81) and the keypad configuration

has been initialized with the SET_KEY_SIZE command

(0x90). The default keypad configuration after reset is a 3 × 3

keyboard matrix. The default GPIO configuration is an input

with the pullup disabled.

WRITE_CFG command (0x81), in which case it will not be

available as a GPIO pin. It can also be configured as a PWM

output, which also would override its use as a GPIO pin.

12.2 USING THE ROT_IN_X PINS FOR GPIO

The rotary encoder interface uses alternate functions of KP-

Y9, KP-Y10, and KP-Y11. The maximum keypad size is au-

tomatically reduced to a 8 × 9 matrix if the rotary encoder

interface is enabled.

12.1 USING THE CONFIG_X PINS FOR GPIO

The CONFIG_1 and CONFIG_2 pins are available for use as

GPIO pins after power-on or reset. However, stable states

must be provided on these pins during power-on or reset to

select the I²C-compatible ACCESS.bus address.

12.3 GPIO TIMING

When a WRITE_PORT_STATE command (0x86) is received,

the GPIO outputs do not change to their new states immedi-

ately or simultaneously. The first one changes 54 µs after the

command is acknowledged, and the others change at inter-

vals of 7.3 µs, as shown in Figure 11.

External pullup or pulldown resistors can be used to pull either

CONFIG_x pin low, while retaining the ability to drive it to an-

other state when used as a GPIO pin.

CONFIG_2 has two alternate functions, in addition to GPIO.

It can be configured as a multiplexer output using the

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30021111

FIGURE 11. GPIO Port State Change Timing

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20

are alternate functions of certain keypad scanning pins. The

ROT_IN_x inputs are bidirectional signals used to test the

status of switches in an external rotary encoder, as shown in

Figure 12.

13.0 Rotary Encoder Interface

A three-wire interface is provided for an external rotary en-

coder. Setting the ROTEN bit with the WRITE_CFG com-

mand enables the interface and the ROT_IN_x inputs, which

30021122

FIGURE 12. Rotary Encorder External Interface

The ROT_IN_x inputs are alternate functions of KP-Y9, KP-

Y10, and KP-Y11. When the rotary encoder interface is en-

abled, these keypad scanning outputs are not available for

keypad interface.

counter, as shown in the example sequence in Table 8. The

READ_ROTATOR command returns a data byte which indi-

cates the accumulated count since the counter was last read.

Steps which correspond to clockwise rotation increment a

counter, while counterclockwise steps decrement the

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TABLE 8. Rotary Encoder Example Sequence

Switch 1-2

Closed

Open

Switch 2-3

Closed

Open

Switch 3-1

Open

Action

Counter

00000000

00000001

00000010

00000011

00000100

00000011

00000010

00000001

00000000

11111111

11111110

11111101

Increment

No Change

Increment

No Change

Increment

No Change

Increment

No Change

Increment

No Change

Decrement

No Change

Decrement

No Change

Decrement

No Change

Decrement

No Change

Decrement

No Change

Decrement

No Change

Decrement

Open

Closed

Open

Closed

Open

Closed

Open

Closed

Open

Closed

Open

Closed

Open

Closed

Open

Closed

Open

Closed

Open

Closed

Open

Closed

The value of the data byte is in two’s complement form, in

which positive values indicate clockwise rotation and negative

values indicate counterclockwise rotation. This is shown in

the example when the counter decrements below zero.

A rotary encoder event will only wake up the LM8323 from

Halt mode if it changes the counter value.

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•

PWM_WRITE — load one word into the script command

file at a specified address.

14.0 PWM Output Generation

Three pulse-width modulated (PWM) outputs are provided

with advanced capabilities for ramp-up and ramp-down of the

PWM duty cycle and execution of simple to complex com-

mand sequences. These capabilities are supported by three

independent script-execution engines capable of au-

tonomous operation after setup and launch by the host.

Figure 13 shows the architecture of a script-execution engine.

•

PWM_START — start execution of the script.

PWM_STOP — stop execution of the script.

Please note: The PWM_STOP command might not take im-

mediate effect if the current command being executed is a

command with long execution time. If a PWM_STOP com-

mand is sent when the PWM engine is running a long RAMP

command, the PWM will only stop after the RAMP is com-

pleted.

The script commands have their own fixed-length 16-bit for-

mat and encoding unrelated to the variable-length, byte-

based format used for host commands. A script command is

sent by the host to the LM8323 as a parameter to the

PWM_WRITE command. Another parameter to the

PWM_WRITE command specifies an address in the script

command file for receiving the command.

14.1 COMMAND QUEUE

After the host issues a PWM_START command, script com-

mands are read from the script command file into a command

queue which consists of a command file output register, com-

mand buffer, and active command register. This allows one

command to be active while another command is queued in

the command buffer, which allows seamless back-to-back

command execution.

A command loaded into the command file output register is

synchronized to the 32.768 kHz clock and stored in the com-

mand buffer. If no command is currently active, the command

passes through to the active command register. In this case,

another command can be read from the script command file,

which is queued in the command buffer. On completion of the

currently active command, the contents of the command

buffer are transferred to the active command register, and the

command buffer may then receive a new command.

The host does not have direct access to any of the registers

in the command queue. The operations which read script

commands from the script command file occur automatically

after the host issues the PWM_START command.

Script execution stops when the host sends a PWM_STOP

command or when the script engine executes an END com-

mand. Executing an END command asserts IRQ to the host.

30021112

14.2 PWM TIMER OPERATION

FIGURE 13. PWM Script Execution Engine

The timers implement a fixed 256-cycle period with a pro-

grammable duty cycle and programmable ramp-up/ramp-

down of the duty cycle. Figure 14 shows the architecture of a

PWM timer.

The host has three commands for interfacing to the script ex-

ecution engine. The following commands are always associ-

ated with one particular PWM channel:

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30021113

FIGURE 14. PWM Timer

The period counter is a free running 8-bit up-counter which

starts counting when the script command file issues the first

RAMP command. An END command stops the period

counter.

of the 32.768 kHz clock. The ramp counter saturates at either

0x00 or 0xFF depending on the ramp direction.

The number of increment or decrement steps is specified by

the INCREMENT field of the RAMP command, which is load-

ed into the step counter. Even if the ramp counter hits its

saturation value, the requested number of steps will be per-

formed. An option enables assertion of the IRQ output to the

host after the last step is performed.

The duty cycle of the PWM output is controlled by the ramp

counter. If the PWM period counter is active, the PWM output

signal is asserted while the period counter has a value less

than or equal to the value of the ramp counter.

The ramp counter can increment or decrement at a rate con-

trolled by the prescaler and step time counter. The prescaler

selects a factor of 16 or 512 for dividing down the frequency

14.3 PWM SCRIPT COMMANDS

Table 9 summarizes the script commands.

TABLE 9. PWM Script Commands

Command

15

0

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PRES

CALE

RAMP

STEPTIME

0

SIGN

INCREMENT

PWMVALUE

SET_PWM

GO_TO_

START

0

1

0

BRANCH

1

0

1

0

1

LOOPCOUNT

0

ADDRESS

RES

ET

END

0

TRIGGER

WAITTRIGGER

SENDTRIGGER

0

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14.4 RAMP COMMAND

which supports both very fast and very slow ramps. The IN-

CREMENT field specifies the number of steps to be executed

by the command. The maximum value is 126, which corre-

sponds to half of full scale.

The RAMP command generates a duty-cycle ramp starting

from the current value. At each step, the ramp counter is in-

cremented or decremented by one, unless it has reached its

its saturation value (0xFF for increment, or 0x00 for decre-

ment). The time for one step is controlled by the PRESCALE

bit and STEPTIME field. The minimum time for one step is

0.49 milliseconds. and the maximum time is about 1 second,

There are two special cases in the instruction encoding. If all

bits and fields are 0, it is interpreted as the GO TO START

command. If the STEPTIME field is 0 but any other bit or field

is non-zero, it is interpreted as the SET_PWM command.

15

14

13 12 11 10

9

8

7

6

5

4

3

2

1

0

PRESCALE

STEPTIME

SIGN

INCREMENT

Bit or Field

PRESCALE

STEPTIME

SIGN

Value

Description

0

1

Divide the 32.768 kHz clock by 16

Divide the 32.768 kHz clock by 512

Number of prescaled clock cycles per step

Increment ramp counter

1–63

0

1

Decrement ramp counter

INCREMENT

1–126

Number of steps executed by this instruction

14.5 SET_PWM COMMAND

lished by initializing the duty cycle to either 100% or 0%

followed by a RAMP command.

The SET_PWM command loads the ramp counter from the

8-bit DUTYCYCLE field in the instruction.

Please note: Only 0x00 and 0xFF are valid values for the duty

cycle in SET_PWM command. Other values can be estab-

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

DUTYCYCLE

Bit or Field

Value

0

Description

Duty cycle is 0%.

DUTYCYCLE

255

Duty cycle is 100%.

14.6 GO_TO_START COMMAND

The GO_TO_START command jumps to the first command

in the script command file.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

14.7 BRANCH COMMAND

The BRANCH command jumps to the specified command in

the script command file, with the option of looping for a spec-

ified number of repetitions. Nested loops are not allowed.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

1

LOOPCOUNT

0

ADDRESS

Field

Value

0

Description

Loop until a STOP PWM SCRIPT command is issued by the host.

Number of repetitions to perform, biased by -1. The range is 0–62 repetitions.

LOOPCOUNT

1–63

Branch destination address in the script command file. If this field is greater than 59, no

looping will be performed.

ADDRESS

0–59

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14.8 END COMMAND

Please note: If a PWM channel is waiting for the trigger (last

executed command was "TRIGGER") and the script execu-

tion is halted then the "END" command can’t be executed

because the previous command is still pending. This is an

exception - in this case the IRQ signal will not be asserted.

The END command terminates script execution and asserts

an interrupt to the host if the RESET bit is set to “1” or “0”.

If the END command is executed with the RESET bit set to

“1” , the PWM output will be disabled. If the RESET bit is “0”

when executing the END command, the PWM channel re-

mains active with the fixed duty cycle it was last set to.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

0

RESET

0

Bit

RESET

14.9 TRIGGER COMMAND

Value

Description

0

1

PWM_x output is active when script execution terminates.

PWM_x output is Tristate when script execution terminates.

Then, it will clear the trigger(s) and continue to the next com-

mand.

Triggers are used to synchronize operations between PWM

channels. A TRIGGER command that sends a trigger takes

sixteen 32.768 kHz clock cycles, and a command that waits

for a trigger takes at least sixteen 32.768 kHz clock cycles.

When a trigger is sent, it is stored by the receiving channel

and can only be cleared when the receiving channel executes

a TRIGGER command that waits for the trigger.

A TRIGGER command that waits for a trigger (or triggers) will

stall script execution until the trigger conditions are satisfied.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

1

WAITTRIGGER

SENDTRIGGER

0

Field

Value

000xx1

000x1x

0001xx

000xx1

000x1x

0001xx

Description

Wait for trigger from channel 0

Wait for trigger from channel 1

Wait for trigger from channel 2

Send trigger to channel 0

WAITTRIGGER

SENDTRIGGER

Send trigger to channel 1

Send trigger to channel 2

14.10 PWM SCRIPT EXAMPLE

This example shows a complex ramping sequence that uses

triggers for synchronization. Three scripts implement the ex-

ample. Figure 15 shows the PWM outputs for this example.

30021114

FIGURE 15. PWM Outputs

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14.10.1 PWM Channel 0 Script

Script

PWM_WRITE PWM_WRITE PWM_WRITE

Script

Command

Address

Description

Parameter 1

Parameter 2

Parameter 3

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x01

0x05

0x09

0x0D

0x11

0x15

0x19

0x1D

0x40

0xE2

0x07

0xA1

0xC8

0x00

0x7E

0xFE

0x82

0x00

SET_PWM Initialize channel for 0% duty cycle

TRIGGER Wait for trigger from channel 2

RAMP

BRANCH

END

Ramp up by 126 steps

Ramp down by 126 steps

Loop 2 times starting at address 0x02

Terminate script and assert IRQ to host

14.10.2 PWM Channel 1 Script

Script

PWM_WRITE PWM_WRITE PWM_WRITE

Script

Command

Address

Description

Parameter 1

Parameter 2

Parameter 3

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x02

0x06

0x0A

0x0E

0x12

0x16

0x1A

0x1E

0x22

0x40

0xE2

0x0F

0xA2

0xE0

0xC8

0xFF

0x00

0xFE

0x7E

0x02

0x08

0x00

SET_PWM Initialize channel for 100% duty cycle

TRIGGER Wait for trigger from channel 2

RAMP

Ramp down by 126 steps

Ramp up by 126 steps

RAMP

Ramp up by 126 steps

BRANCH

Loop 3 times starting at address 0x02

TRIGGER Send trigger to channel 2

END

Terminate script and assert IRQ to host

14.10.3 PWM Channel 2 Script

Script

PWM_WRITE PWM_WRITE PWM_WRITE

Script

Command

Address

Description

Parameter 1

Parameter 2

Parameter 3

0x00

0x01

0x02

0x03

0x04

0x03

0x07

0x0B

0x0F

0x13

0x40

0x03

0x00

0x7E

0xFE

SET_PWM Initialize channel for 0% duty cycle

RAMP

Ramp up by 126 steps

Ramp down by 126 steps

Send triggers to channels 0 and 1,

wait for trigger from channel 1

0x05

0x17

0xE1

0x06

TRIGGER

0x06

0x07

0x08

0x09

0x0A

0x1B

0x1F

0x23

0x27

0x2B

0x03

0xC8

0x7E

0xFE

0x00

RAMP

END

Ramp up by 126 steps

Ramp down by 126 steps

Terminate script and assert IRQ to host

27

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14.11 SELECTABLE SCRIPT EXAMPLE

Multiple scripts can be placed in a single buffer. The script

which is executed is selected by the address in the parameter

to the PWM_START command (0x96).

Script

Command

Address

PWM_WRITE

Parameter 1

PWM_WRITE PWM_WRITE

Script

Description

Parameter 2

Parameter 3 Command

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x01

0x05

0x09

0x0D

0x11

0x15

0x19

0x1D

0x21

0x25

0x29

0x2D

0x40

0x0F

0xC0

0x40

0x0F

0xC0

0x40

0x07

0xA5

0x00

0x33

0x00

0xFF

0xD5

0x00

0x7E

0xFE

0x07

Set PWM_0 to 0% duty cycle

Ramp up 51 steps

Script 1

Script 2

Keep channel at 20% duty cycle

Set PWM_0 to 100% duty cycle

Ramp down 85 steps

Keep channel at 66.6% duty cycle

Set PWM_0 to 0% duty cycle

Ramp up 126 steps

Script 3

Script 4

Ramp down 126 steps

Loop ten times to script address 0x07

Switch PWM_0 off (script 3 automatically

enters here)

0x0C

0x31

0xC8

0x00

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

.....

0x35

0x39

0x3D

0x41

0x45

0x49

0x4D

0x51

0x40

0x07

0xC0

0x40

0x01

0x3F

0xA0

0x00

0x25

0x00

0x40

0x7E

0xFE

0x12

Set PWM_0 to 0% duty cycle

Ramp up 37 steps

Script 5

Script 6

Keep channel at 14.5% duty cycle

Set PWM_0 to 0% duty cycle

Ramp up 64 steps

(Alternates

between 25%

and 75% duty

cycle)

Ramp up 126 steps

Ramp down 126 steps

Always branch to script address 0x12

Script 7

0x3B

To set a fixed duty cycle on a PWM channel requires 3 steps

(see script 1 for duty cycles from 0% to 49% and script 2 for

duty cycles from 51% to 100%).

Script 7 can be finished by two commands:

•

PWM_STOP command with parameter 0x01

PWM_START command with parameter 0x31 (start

PWM_0 from address 0x0C to run script 4)

To keep a PWM channel active providing a fixed duty cycle

on its output, the script must terminate with the END com-

mand leaving the RESET bit clear. To switch this channel off,

the host must send another PWM_START command (0x96

followed by the parameter bytes) triggering the single com-

mand described in script 4. This END command will set the

RESET bit and the dedicated PWM output will be disabled.

The script address is the physical address to be used from

BRANCH instructions inside the script file buffer. The param-

eter 1 byte contains the same address with the 2 channel bits

appended and will be associated with the PWM_START com-

mand.

Script 3 will automatically enter into this command when the

10 loops of ramping up and down are executed.

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28

The data select inputs for the multiplexers are controlled by

the MUX1SEL and MUX2SEL bits, which are written by the

WRITE_CFG command. If it is important to avoid momentarily

passing an incorrect input to the output, the select bit must be

loaded with a first WRITE_CFG command before sending a

second WRITE_CFG command to set the enable bit. The

truth table for the multiplexers is shown in Table 10.

15.0 Digital Multiplexers

Two 2:1 multiplexers are provided for host-controlled digital

switching. Setting the MUX1EN or MUX2EN bits with the

WRITE_CFG command enables the corresponding multi-

plexer and its input and output signals, which overrides any

other functions which may use these pins. The MUX1 signals

are alternate functions of the PWM_x outputs. The MUX2

signals are alternate functions of three KP-Yx pins shared

with the rotary encoder interface, so MUX2 is unavailable

when the interface is used.

TABLE 10. Digital Multiplexer Function Table

MUXxEN Bit

MUXxSEL

Bit

MUXx_IN2

MUXx_IN1

MUXx_OUT

1

0

1

X

0

1

0

1

0

1

0

1

X

MUXx_OUT

not enabled

0

X

TABLE 11. Minimal Command String

16.0 Host Interface

Command

Description

The two-wire ACCESS.bus interface is used to communicate

with a host. The ACCESS.bus interface is compatible with the

I²C bus standard. The LM8323 operates as a bus slave at 400

kHz (Fast mode).

Read vendor ID and software

version

READ_ID

Check if NOINT bit is set in

interrupt register

READ_INT

All communication with the LM8323 over the ACCESS.bus

interface is initiated by the host, usually in response to an in-

terrupt request (IRQ low) asserted by the LM8323. The

LM8323 may request service from the host by asserting the

IRQ interrupt output.

WRITE_CFG

Configure the LM8323

SET_KEY_SIZE

Set the size of the keypad

Set the clock mode for the PWM

unit

WRITE_CLK

16.1 START AND STOP CONDITIONS

WRITE_PORT_SEL Set port direction for GPIO pins

WRITE_PORT_STATE Set port states of GPIO pins

Every transfer is preceded by a Start condition or a Repeated

Start condition. The latter occurs when a command follows

immediately upon another command without an intervening

Stop condition. A Stop condition indicates the end of trans-

mission. Every byte is acknowledged by the receiver.

A more comprehensive command string may include the ad-

ditional commands shown in Table 12.

TABLE 12. Additional Commands

Command

SET_DEBOUNCE

SET_ACTIVE

READ_CLK

Description

Set debounce time

Set active time

Verify PWM clock settings

Verify configuration setting

Read all port states (physical levels

READ_CFG

READ_PORT_STATE on pins)

30021115

Note: Very long continuous command strings exceeding 30

milliseconds could overrun the ability of the LM8323 to pro-

cess commands if the time from the last clock cycle of a

command until the next Start condition or Repeated Start

condition is always shorter than 60 µs. A very long command

chain could prevent the LM8323 from performing any watch-

dog service and consequently could trigger a physical

RESET to the device.

FIGURE 16. Start and Stop Conditions

16.2 CONTINUOUS COMMAND STRINGS

A host device may send a continuous string of commands

using the Repeated Start condition, which would block an-

other ACCESS.bus device from gaining control of the bus.

After Power-On the host device must send multiple com-

mands to initialize the LM8323 device. A minimal command

string will include the commands shown in Table 11.

To avoid overrunning the LM8323, the host should provide a

1ms break between long (>30 ms) command sequences for

SCL frequencies > 100 kHz.

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16.3 DEVICE ADDRESS

16.4 HOST WRITE COMMANDS

The device address is controlled by states sampled on the

CONFIG_1 and CONFIG_2 pins, as shown in Table 13. In the

first byte of a bus transaction, a 7-bit address plus a direction

bit are broadcast by the bus master to all bus slaves.

Some host commands include one or more data bytes written

to the LM8323. Figure 17 shows a SET_KEY_SIZE com-

mand, which consists of an address byte, a command byte,

and one data byte.

The first byte is composed of a 7-bit slave address in bits 7:1

and a direction bit in bit 0. The state of the direction bit is 0 on

writes from the host to the slave and 1 on reads from the slave

to the host.

TABLE 13. Device Address Selection

CONFIG_1

CONFIG_2

Device Address

1000 010X

0

1

0

1

0

1

The second byte sends the command. The SET_KEY_SIZE

command is 0x90.

1000 011X

1000 100X

The third byte sends the data, in this case specifying the

number of rows and columns for the keypad.

1000 101X

CONFIG_1 and CONFIG_2 pins should be connected to

GND or V_CCusing pulldown or pullup resistors. The pins can-

not be left unconnected.

30021116

FIGURE 17. Host Write Command

16.5 HOST READ COMMANDS

The bus master can send any number of Repeated Start con-

ditions without releasing control of the bus. This technique

can be used to implement atomic transactions, in which the

bus master sends a command and then reads a register with-

out allowing any other device to get control of the bus between

these events.

Some host commands include one or more data bytes read

from the LM8323. Figure 18 shows a READ_PORT_SEL

command which consists of an address byte, a command

byte, a second address byte, and two data bytes.

The first address byte is sent with the direction bit driven low

to indicate a write transaction of the command to the LM8323.

The second address byte is sent with the direction bit undriven

(pulled high) to indicate a read transaction of the data from

the LM8323.

The data is sent from the slave to the host in the fourth and

fifth bytes. The fifth byte ends with a negative acknowledge-

ment (NACK) to indicate the end of the data.

The Repeated Start condition must be repeated whenever the

slave address or the direction bit is changed. In this case, the

direction bit is changed.

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30

30021117

FIGURE 18. Host Read Command

16.6 INTERRUPTS

The IRQ output may be asserted on these conditions:

16.7 INTERRUPT CODE

The interrupt code is read and acknowledged with the

READ_INT command (0x82). This command clears the code

and deasserts the IRQ output. Table 14 shows the format of

the interrupt code.

•

Any new key-event after the last interrupt was asserted but

not yet acknowledged by reading the interrupt code.

•

Any change in the state of the rotary encoder inputs.

Termination of a PWM script (END command).

Any error condition, which is indicated by the error code.

TABLE 14. Interrupt Code

7

6

5

4

3

2

1

0

PWM2END

PWM1END

PWM0END

NOINIT

ERROR

0

ROTATOR

KEYPAD

Bit

Description

PWM2END

PWM1END

PWM0END

NOINIT

An END script command was executed by PWM channel 2.

An END script command was executed by PWM channel 1.

An END script command was executed by PWM channel 0.

The LM8323 is waiting for an initialization sequence.

An error condition occurred.

ERROR

ROTATOR

KEYPAD

A state change was detected in the rotary encoder inputs.

A key-press or key-release event occurred.

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16.8 ERROR CODE

If the LM8323 reports an error, the READ_ERROR command

(0x8C) is used to read the error code. This command clears

the error code. Table 15 shows the format of the error code.

TABLE 15. Error Code

7

6

5

4

3

2

1

0

FIFOOVR

0

KEYOVR

CMDUNK

BADPAR

Bit

Description

FIFOOVER

KEYOVR

CMDUNK

BADPAR

Event occurred while the FIFO was full.

More than two keys were pressed simultaneously.

Not a valid command.

Bad command parameter.

16.9 WAKE-UP FROM HALT MODE

terminates without being acknowledged (shown as NACK in

Figure 19). The host then aborts the transaction by sending

a Stop condition. After aborting the bus cycle, the host may

then retry the bus cycle. On the second attempt, the LM8323

will be able to acknowledge the slave address, because it will

be in Active mode.

Alternatively, the I²C specification allows sending a START

byte (00000001), which will not be acknowledged by any de-

vice. This byte can be used to wake up the LM8323 from Halt

mode.

Any bus transaction initiated by the host may encounter the

LM8323 device in Halt mode or busy with processing data,

such as controlling the FIFO buffer or executing interrupt ser-

vice routines.

LM8323 shows the case in which the host sends a command

while the LM8323 is in Halt mode (Internal execution clock is

stopped). Any activity on the ACCESS.bus wakes up the

LM8323, but it cannot acknowledge the first bus cycle imme-

diately after wake-up.

The LM8323 may also stall the bus transaction by pulling the

SCL low, which is a valid behavior defined by the I²C speci-

fication.

The host drives a Start condition followed by seven address

bits and a R/W bit. The host then releases SDA for one clock

period, so that it can be driven by the LM8323.

If the LM8323 does not drive SDA low during the high phase

of the clock period immediately after the R/W bit, the bus cycle

30021118

FIGURE 19. LM8323 Responds with NACK, Host Retries Command

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17.0 Host Commands

Function

Cmd

0x80

0x81

Dir

R

Data Bytes

nnnn nnnn

pppp pppp

nnnn nnnn

Description

Read the manufacturer code (nnnn nnnn) and the device

revision number (pppp pppp).

READ_ID

WRITE_CFG

W

Write the hardware configuration register.

Read the interrupt code, deassert the IRQ output, and clear

the code. (If the NOINIT bit is set, it remains set and IRQ

remains asserted until a WRITE_CFG command is

received.)

READ_INT

0x82

R

nnnn nnnn

RESET

0x83

0x84

W

nnnn nnnn

pppp pppp

nnnn nnnn

pppp pppp

nnnn nnnn

Reset the LM8323. Error if nnnn nnnn is not 0xAA.

Select pullup (0) or pulldown (1) direction for the

corresponding general-purpose I/O (GPIO) port pins.

WRITE_PULL_DOWN

Select input (0) or output (1) for the corresponding general-

purpose I/O (GPIO) port pins.

WRITE_PORT_SEL

WRITE_PORT_STATE

READ_PORT_SEL

0x85

0x86

0x87

W

R

For pins configured as inputs, 0 selects high-impedance

mode and 1 enables a weak pullup. For pins configured as

outputs, each bit specifies the logic level driven on the pin.

pppp pppp

nnnn nnnn

pppp pppp

nnnn nnnn

pppp pppp

Read the direction of the corresponding GPIO port pins.

Read the state on the corresponding GPIO port pins.

READ_PORT_STATE

READ_FIFO

0x88

0x89

0x8A

R

Up to 15 event Read an event from the FIFO.

codes

Maximum of 14 event codes stored in the FIFO.

Up to 15 event Repeats a FIFO read without advancing the FIFO pointer,

RPT_READ_FIFO

codes

for example to retry a read after an error.

Set the time during which the LM8323 stays active before

entering Halt mode. The active time must be greater than

the debounce time. The default time is 500 milliseconds.

The valid range is 1255. Active time = n × 4 milliseconds.

SET_ACTIVE

0x8B

W

nnnn nnnn

READ_ERROR

0x8C

0x8E

R

nnnn nnnn

Read and clear the error code.

READ_ROTATOR

Read accumulated rotation steps since previous read.

Set the time for rescanning the keypad after detecting a

key-press or key-release event to verify the event. The

default time is 12 milliseconds. The valid range is 1255.

Debounce time = n × 4 milliseconds and must not exceed

active time.

SET_DEBOUNCE

0x8F

W

nnnn nnnn

SET_KEY_SIZE

READ_KEY_SIZE

READ_CFG

0x90

0x91

0x92

0x93

0x94

W

R

nnnn pppp

nnnn nnnn

Set keypad size. nnnn = KP-Xx pins, pppp = KP-Yx pins

Read keypad size. nnnn = KP-Xx pins, pppp = KP-Yx pins

Read the hardware configuration register.

Write the clock configuration register.

R

WRITE_CLOCK

READ_CLOCK

W

R

Read the clock configuration register.

Write a command to the PWM script command file.

nn = PWM channel number (01, 10, or 11)

aaaaaa = address in script command file (0-59)

pppp pppp = high byte of script command

qqqq qqqq = low byte of script command

PWM_WRITE

0x95

W

aaaa aann

pppp pppp

qqqq qqqq

Start script on channel nn (01, 10, or 11) at address

aaaaaa.

PWM_START

PWM_STOP

0x96

0x97

W

aaaa aann

0000 00nn

Stop script on channel nn (01, 10, or 11).

33

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Please note: The data bytes which follow the command can

be reads (toward the host) or writes (toward the LM8323). In

the case of the READ_FIFO and RPT_READ_FIFO com-

mands, the number of data bytes is variable, with the last

transaction indicated by returning a negative acknowledge-

ment (NACK).

17.1 READ_ID COMMAND

The READ_ID command consists of a command byte (0x80)

from the host and two data bytes from the LM8323.

The first data byte returns the manufacturer code, and the

second byte returns the device revision level.

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

MANUFACTURER

REVISION

17.2 WRITE_CFG COMMAND

into the hardware configuration register. The default state of

this register is 0x80.

The WRITE_CFG command consists of a command byte

(0x81) and a data byte from the host. The data byte is loaded

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

IRQPST

ROTEN

0

MUX2EN

MUX2SEL

MUX1EN MUX1SEL

Bit

Value

Description

0

1

0

IRQ is an open-drain output.

IRQ is a push-pull output.

IRQPST

Rotary encoder interface disabled.

ROTEN

Rotary encoder interface enabled. This selection enables the ROT_IN_x inputs which

are alternate functions of certain KP-Yx pins.

1

0

1

0

1

0

1

0

1

MUX2_OUT output disabled.

MUX2EN

MUX2_OUT output enabled. This overrides any other function available on this pin.

If the MUX2 EN bit is 1, the MUX2_IN1 input drives the MUX2_OUT output.

If the MUX2 EN bit is 1, the MUX2_IN2 input drives the MUX2_OUT output.

MUX1_OUT output disabled.

MUX2SEL

MUX1EN

MUX1SEL

MUX1_OUT output enabled. This overrides any other function available on this pin.

If the MUX1 EN bit is 1, the MUX1_IN1 input drives the MUX1_OUT output.

If the MUX1 EN bit is 1, the MUX1_IN2 input drives the MUX1_OUT output.

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34

17.3 READ_INT COMMAND

interrupt code. An exception to this behavior occurs if the

NOINIT bit is set, in which case IRQ will not be deasserted

and the interrupt code will not be cleared until a WRITE_CFG

command is received.

The READ_INT command consists of a command byte (0x82)

from the host and a data byte from the LM8323. The data byte

is the interrupt code. Reading the interrupt code acknowl-

edges the interrupt (which deasserts IRQ) and clears the

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

PWM2END PWM1END PWM0END NOINIT ERROR

0

ROTATOR KEYPAD

Bit

Value

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No interrupt from PWM channel 2.

PWM2END

PWM1END

PWM0END

NOINIT

An END script command was executed by PWM channel 2.

No interrupt from PWM channel 1.

An END script command was executed by PWM channel 1.

No interrupt from PWM channel 0.

An END script command was executed by PWM channel 0.

Normal operation.

LM8323 is waiting for the initialization sequence.

No error condition is indicated.

ERROR

An error condition occurred.

No state change in the rotary encoder inputs is indicated.

A state change was detected in the rotary encoder inputs.

No key-press or key-release event is indicated.

A key-press or key-release event occurred.

ROTATOR

KEYPAD

17.4 RESET COMMAND

Note: When FW6 version devices receive a RESET com-

mand the IRQ line is set high and held high for 60 ms, then

pulled low to show the device was successfully reset and is

ready to be used.

The RESET command consists of a command byte (0x83)

and one data byte from the host. The command causes a re-

set, identical to an external reset. The data byte must be

0xAA, otherwise no reset will occur and an error condition will

be signalled.

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

0

1

0

17.5 WRITE_PULL_DOWN COMMAND

responding general-purpose I/O ports as pullups (0) or pull-

downs (1). The first data byte controls ports GPIO_15 through

GPIO_08, and the second byte controls ports GPIO_07

through GPIO_00.

The WRITE_PORT_SEL command consists of a command

byte (0x84) and two data bytes from the host. The data bytes

configure the pullup/pulldown device (if enabled) for the cor-

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

Bit

GPIO_xx

Value

Description

GPIO port pin pullup/pulldown device is a pullup.

GPIO port pin pullup/pulldown device is a pulldown.

0

1

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17.6 WRITE_PORT_SEL COMMAND

puts (0) or outputs (1). The first data byte controls ports

GPIO_15 through GPIO_08, and the second byte controls

ports GPIO_07 through GPIO_00.

The WRITE_PORT_SEL command consists of a command

byte (0x85) and two data bytes from the host. The data bytes

configure the corresponding general-purpose I/O ports as in-

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

Bit

GPIO_xx

Value

Description

0

1

GPIO port pin is an input.

GPIO port pin is an output.

The GPIO_09 port pin can only be configured as an input with

weak pullup/pulldown device.

general-purpose I/O ports configured as inputs, the data

bytes select whether the inputs are high-impedance (0) or

have a weak pullup (1). For ports configured as outputs, the

data bytes control the state driven on the output. The first data

byte controls ports GPIO_15 through GPIO_08, and the sec-

ond byte controls ports GPIO_07 through GPIO_00.

17.7 WRITE_PORT_STATE COMMAND

The WRITE_PORT_STATE command consists of a com-

mand byte (0x86) and two data bytes from the host. For

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

Bit

Value

Description

If the GPIO port pin is an input, pullup device is disabled. If the GPIO port pin is an

output, it is driven low.

0

GPIO_xx

If the GPIO port pin is an input, pullup device is enabled. If the GPIO port pin is an

output, it is driven high.

1

17.8 READ_PORT_SEL COMMAND

the corresponding ports, either input (0) or output (1). The first

data byte controls ports GPIO_15 through GPIO_08, and the

second byte controls ports GPIO_07 through GPIO_00.

The READ_PORT_SEL command consists of a command

byte (0x87) from the host and two data bytes from the

LM8323. The data bytes indicate the direction configured for

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

Bit

Value

Description

0

1

GPIO port pin is an input.

GPIO port pin is an output.

GPIO_xx

17.9 READ_PORT_STATE COMMAND

sponding ports. The first data byte controls ports GPIO_15

through GPIO_08, and the second byte controls ports

GPIO_07 through GPIO_00.

The READ_PORT_STATE command consists of a command

byte (0x88) from the host and two data bytes from the

LM8323. The data bytes indicate the states on the corre-

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

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Bit

Value

Description

If the GPIO port pin is an input, pullup is disabled. If the GPIO port pin is an

output, it is driven low.

0

GPIO_xx

If the GPIO port pin is an input, pullup is enabled. If the GPIO port pin is an

output, it is driven high.

1

17.10 READ_FIFO COMMAND

the FIFO is empty. The last data byte is indicated by its value

(0x00) and a negative acknowledgement (NACK) on the

ACCESS.bus interface. The data bytes correspond to key-

press and key-release events, as described in Table 5.

The READ_FIFO command consists of a command byte

(0x89) sent from the host and a variable number of data bytes

received from the LM8323. The LM8323 will provide data until

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

FIFODATA

0x00

Field

Value

Description

0xxxxxxx

1xxxxxxx

Key-release event.

Key-press event.

FIFODATA

17.11 RPT_READ_FIFO COMMAND

data as a previous READ_FIFO command, but without ad-

vancing the FIFO pointer. It may be used to recover from an

error encountered during a READ_FIFO command.

The RPT_READ_FIFO command consists of a command

byte (0x8A) and from the host and a variable number of data

bytes from the LM8323. This command provides the same

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

FIFODATA

0x00

Field

Value

Description

0xxxxxxx

1xxxxxxx

Key-release event.

Key-press event.

FIFODATA

17.12 SET_ACTIVE COMMAND

press, key-release or rotary encoder event before entering

Halt mode. The default active time is 500 milliseconds. The

host can program ACTIVETIME from 4–1020 milliseconds

with a granularity of 4 milliseconds.

The SET_ACTIVE command consists of a command byte

(0x8B) and a data byte from the host. This command sets the

time that the LM8323 stays active without detecting a key-

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

ACTIVETIME

Field

Value

Description

0

Halt mode is disabled.

Active time = n × 4 milliseconds.

ACTIVETIME

1–255

37

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17.13 READ_ERROR COMMAND

reading an interrupt code that indicates an error condition, this

command is used to read an error code that indicates the

cause of the error condition.

The READ_ERROR command consists of a command byte

(0x8C) from the host and a data byte from the LM8323. After

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

FIFOOVR

0

KEYOVR CMDUNK

BADPAR

Bit

Value

Description

0

1

0

1

0

1

0

1

No FIFO overrun occurred.

FIFOOVR

KEYOVR

CMDUNK

BADPAR

Event occurred while the FIFO was full.

No keypad overrun occurred.

More than two keys were pressed simultaneously.

No invalid command was encountered.

Not a valid command.

No bad parameter was encountered.

Bad command parameter.

17.14 READ_ROTATOR COMMAND

dicates the accumulated number of rotation steps of an ex-

ternal rotary encoder since the last time the READ_ROTA-

TOR command was executed.

The READ_ROTATOR command consists of a command

byte (0x8E) from the host and a data byte from the LM8323.

The data byte is a signed two's complement value which in-

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

ROTATION

Field

Value

Description

Clockwise rotation is indicated by a positive value. Counterclockwise

movement is indicated by a negative value.

ROTATION

17.15 SET_DEBOUNCE COMMAND

−128 to +127

bounce time is 12 milliseconds. The host can program DE-

BOUNCETIME from 4–1020 milliseconds with a granularity

of 4 milliseconds. The DEBOUNCETIME must not exceed the

active time set with the SET_ACTIVE command.

The SET_DEBOUNCE command consists of a command

byte (0x8F) and a data byte from the host. This command sets

the time that the LM8323 waits before rescanning the keypad

to confirm a key-press or key-release event. The default de-

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

DEBOUNCETIME

Field

Value

Description

DEBOUNCETIME

1–255

Active time = n × 4 milliseconds.

17.16 SET_KEY_SIZE COMMAND

The maximum number of KP-Xx inputs is 8, and the maximum

number of KP-Yx outputs is 12. If the digital multiplexer MUX2

or the rotary encoder interface is used, the maximum number

of KP-Yx outputs is 9. If the SLOWCLKOUT pin is used, the

maximum number is 8.

The SET_KEY_SIZE command consists of a command byte

(0x90) and a data byte from the host. This command specifies

the keypad size in terms of the number of KP-Xx inputs and

KP-Yx outputs which are used. Any unused KP-Xx and KP-

Yx pins may be used for general-purpose I/O. The minimum

value for either field is 3, which corresponds to a keypad con-

figuration that supports 3 × 3 + 3 SF keys (total of 12 keys).

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

KP-X

KP-Y

Field

KP-X

KP-Y

Value

3–8

Description

Number of KP-Xx inputs.

Number of KP-Yx outputs.

3–12

17.17 READ_KEY_SIZE COMMAND

The host can issue the command at any time to read the con-

figuration of the keypad.

The READ_KEY_SIZE command consists of a command

byte (0x91) from the host and a data byte from the LM8323.

www.national.com

38

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

KP-X

KP-Y

Field

KP-X

KP-Y

Value

3–8

Description

Number of KP-Xx inputs.

Number of KP-Yx outputs.

3–12

17.18 READ_CFG COMMAND

data byte returns the settings in the hardware configuration

register. The default state of this register is 0x80.

The READ_CFG command consists of a command byte

(0x92) from the host and a data byte from the LM8323. The

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

ROTEN

0

Bit

Value

Description

0

Rotary encoder interface disabled.

ROTEN

Rotary encoder interface enabled. This selection enables the ROT_IN_x inputs, which

are alternate functions of certain KP-Yx pins.

1

0

1

0

1

0

1

0

1

MUX2_OUT output disabled.

MUX2EN

MUX2_OUT output enabled. This overrides any other function available on this pin.

If the MUX2 EN bit is 1, the MUX2_IN1 input drives the MUX2_OUT output.

If the MUX2 EN bit is 1, the MUX2_IN2 input drives the MUX2_OUT output.

MUX1_OUT output disabled.

MUX2SEL

MUX1EN

MUX1SEL

MUX1_OUT output enabled. This overrides any other function available on this pin.

If the MUX1 EN bit is 1, the MUX1_IN1 input drives the MUX1_OUT output.

If the MUX1 EN bit is 1, the MUX1_IN2 input drives the MUX1_OUT output.

17.19 WRITE_CLOCK COMMAND

The WRITE_CLOCK command consists of a command byte

(0x93) and a data byte from the host. This command sets the

clock configuration, as described in Table 2.

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

CONFIGURATION

17.20 READ_CLOCK COMMAND

command reads bits 7:2 of the clock configuration, as de-

scribed in Table 2 , Section 8.3 CLOCK CONFIGURATION.

The READ_CLOCK command consists of a command byte

(0x94) from the host and a data byte from the LM8323. This

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

CONFIGURATION

1

0

17.21 PWM_WRITE COMMAND

writes a 16-bit script command into a specified address in the

script command file of the specified PWM channel.

The PWM_WRITE command consists of a command byte

(0x95) and three data bytes from the host. The command

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5 4 3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

1

ADDRESS

CH

COMMAND

Bit

Value

Description

ADDRESS

0–59

01

Location in the PWM script command file.

PWM channel 0.

CH

10

PWM channel 1.

11

PWM channel 2.

39

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17.22 PWM_START COMMAND

execution of the script command file at the specified address

for the specified channel.

The PWM_START command consists of a command byte

(0x96) and a data byte from the host. This command starts

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

ADDRESS

CH

Bit

Value

0–59

01

Description

ADDRESS

Start address in the PWM script command file.

PWM channel 0.

CH

10

PWM channel 1.

11

PWM channel 2.

17.23 PWM_STOP COMMAND

The PWM_STOP command consists of a command byte

(0x97) and a data byte from the host. This command stops

execution of the script command file for the specified channel.

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

1

0

CH

Bit

Value

01

Description

PWM channel 0.

PWM channel 1.

PWM channel 2.

CH

10

11

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40

Maximum Input Current Without

Latchup

18.0 Absolute Maximum Ratings (Note

±100 mA

1)

ESD Protection Level

(Human Body Model)

(Machine Model)

(Charge Device Model)

2 kV

200V

750V

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

If Military/Aerospace specified devices are required, please

contact the National Semiconductor Sales Office/Distributors

for availability and specifications.

Total Current into V_CCPin (Source)

Total Current out of GND Pin (Sink)

Storage Temperature Range

100 mA

−65°C to +140°C

Supply Voltage (V_CC

Voltage at Any Pin

)

2V

-0.3V to V_CC+0.3V

19.0 DC Electrical Characteristics

(Temperature: -40°C ≤ T_A≤ +85°C, unless otherwise specified)

Data sheet specification limits are guaranteed by design, test, or statistical analysis.

Symbol

V_CC

Parameter

Conditions

Min

Typ

Max

Units

Operating Voltage

1.62

1.98

V

I_DD

Supply Current (Note 2)

Internal Clock,

No loads on pins,

1.9

<9

3.0

40

mA

V_CC= 1.9V, T_C= 0.5 µs (Note 3)

I_HALT

V_IL

Standby Mode Current (Note 4)

Logical 0 Input Voltage (Note 5)

Logical 1 Input Voltage (Note 5)

Typical:

V_CC= 1.9V, T_A= 25°C

µA

V

0.3 x

V_CC

V_IH

0.7 x

V_CC

V

Hi-Z Input Leakage (TRI-STATE Output)

Port Input Hysteresis (Note 5, Note 6)

Weak Pull-Up/Pull-Down Current

V_CC= 1.8V

-2

2

µA

mV

µA

100

400

1.6V<V_CC< 2.0V

150

-16

Output Current Source (Push-Pull Mode)

Output Current Sink (Push-Pull Mode)

Allowable Sink and Source Current per Pin (Note 7)

Input/Output Capacitance (Note 6)

V_CC= 1.62V, V_OH= 0.7 x V_CC

V_CC= 1.62V, V_OL= 0.3 x V_CC

mA

pF

16

5

C_PAD

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics tables.

Note 2: Supply current is measured with inputs connected to V_CCand outputs driven low but not connected to a load.

Note 3: Command execution cycle = 0.5 µs.

Note 4: In standby mode, the internal clock is switched off. Supply current in standby mode is measured with inputs connected to V_CCand outputs driven low but

not connected to a load.

Note 5: Applied to all digital pins (including RESET) except for SLOWCLK when configured for an external clock.

Note 6: Guaranteed by design, not tested.

Note 7: The sum of all I/O sink/source current must not exceed the maximum total current into V_CCand out of GND as specified in the absolute maximum ratings.

41

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20.0 AC Electrical Characteristics

(Temperature: -40°C ≤ T_A≤ +85°C)

Data sheet specification limits are guaranteed by design, test, or statistical analysis.

Parameter

System Clock Frequency

Conditions

Min

Typ

Max

Units

Internal RC

21

MHz

System Clock Period (mclk)

48

ns

1.62V ≤ V_CC≤ 1.98V

Processing and Command Execution Cycle (t_C)

0.5

μs

System Clock, Processing and Command Execution

Cycle Variation

7

%

General-Purpose I/O (GPIO)

Output Rise Time(Note 8)

Output Fall Time(Note 8)

C_LOAD= 50 pF

15

ns

ACCESS.bus Input Signals

Bus Free Time Between Stop and Start Condition

(tBUFi) (Note 8)

16

mclk

SCL Setup Time (tCSTOsi) (Note 8)

SCL Hold Time (tCSTRhi) (Note 8)

Before Stop Condition

After Start Condition

Before Start Condition

Before SCL Rising Edge (RE)

Before SCL RE

8

mclk

SCL Setup Time (tCSTRsi) (Note 8)

Data High Setup Time (tDHCsi) (Note 8, Note 9)

Data Low Setup Time (tDLCsi) (Note 8, Note 9)

SCL Low Time (tSCLlowi) (Note 8)

8

2

After SCL Falling Edge (FE)

After SCL RE

12

0

SCL High Time (tSCLhighi) (Note 8, Note 9)

SDA Hold Time (tSDAhi) (Note 8)

After SCL FE

SDA Setup Time (tSDAsi) (Note 8, Note 9)

Before SCL RE

2

ACCESS.bus Output Signals

SCL Hold Time (tSDAho) (Note 8)

After SCL FE

7

mclk

Note 8: Guaranteed by design, not tested.

Note 9: The ACCESS.bus interface implements and meets the timing necessary for interface to the I²C and SMBus protocol at logic levels. The bus drivers are

designed with open-drain output for bidirectional operation. Due to System Clock (mclk) Variation, this specification may not meet the AC timing and current/

voltage drive requirements of the full bus specifications.

30021119

FIGURE 20. ACB Start and Stop Condition Timing

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42

21.0 Physical Dimensions inches (millimeters) unless otherwise noted

Micro Array Package

Order Number LM8323GGR8

NS Package Number GRA36A

43

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型号：	LM8323
厂家：	TEXAS INSTRUMENTS
描述：	LM8323 Mobile I/O Companion Supporting Keyscan, I/O Expansion, PWM, and ACCESS.bus Host Interface LM8323移动I / O伴侣支持键盘扫描， I / O扩展，PWM和ACCESS总线主机接口
文件：	总46页 (文件大小：597K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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