LM8335TLE/NOPB [TI]
LM8335 General Purpose Output Expander with MIPI® RFFE Host Interface; LM8335通用输出扩展器，带有MIPI® RFFE主机接口
| 型号： | LM8335TLE/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LM8335 General Purpose Output Expander with MIPI® RFFE Host Interface |
| 文件： | 总16页 (文件大小：1206K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM8335
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SNVS840 –JUNE 2012
LM8335 General Purpose Output Expander with MIPI® RFFE Host Interface
Check for Samples: LM8335
1
FEATURES
2
•
•
•
MIPI RFFE Interface Version 1.10 Compliant
KEY SPECIFICATIONS
Supports Output Expansion
•
•
•
•
•
•
•
1.8 ± 0.15V MIPI RFFE Operation (VIO)
1.8 ± 0.15V Core Supply (VDD
1.65 to 3.6V GPO Supply (VDDIO
Host Interface Address Select Pin:
)
–
–
ADR=GND, USID[3:0]=0001
ADR=VDD, USID[3:0]=1001
)
Low Standby and Active Current
On-Chip Power-On Reset (POR)
−30 to +85°C Ambient Temperature Range
16-Bump DSBGA Package
•
•
Pin-Configurable Initial State: VIO
–
CFG=GND, GPO High-z, with Weak Internal
Pull-Down Resistor Enabled;
GPO_OUT_DATA is Unmasked
–
1.965 mm x 1.965 mm x 0.6 mm, 0.5 mm
Pitch (Nominal)
–
CFG=VDD, GPO High-z, with Weak Internal
Pull-Down Resistor Enabled;
GPO_OUT_DATA is Masked
DESCRIPTION
Three Sources for Chip Reset:
The LM8335 General Purpose Output Expander is a
dedicated device to provide flexible and general
purpose, host programmable output expansion
functions. This device communicates with a host
processor through a MIPI® RFFE Interface (Mobile
Industry Processor Interface RF Front-End).
–
–
–
VIO Input Pin
POR
Software-Commanded Reset
APPLICATIONS:
Eight general purpose outputs (GPO) can be
configured by the host controller as drive
high/low/high-z. Weak pull-ups (PU) or weak pull-
downs (PD) can be enabled.
•
•
Smart Handheld Devices
RF Transceiver Applications
Upon power-on, the LM8335 default configuration is
for all GPO to be set based on the state of the CFG
pin.
After startup, any changes to the default configuration
must be sent from the host via the MIPI RFFE host
interface..
The LM8335 is available in a 16-bump lead-free
DSBGA package of size 1.965 mm x 1.965 mm x 0.6
mm (0.5 mm pitch).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCT PREVIEW information concerns products in the
formative or design phase of development. Characteristic data and
other specifications are design goals. Texas Instruments reserves
the right to change or discontinue these products without notice.
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LM8335
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Single RFFE Slave Application Block Diagram
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Dual RFFE Slave Application Block Diagram
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Connection Diagram and Package Mark Information
2
1
3
4
VDD
VIO
SCLK
SDATA
A
VDDIO
GPO_6
GND
ADR
CFG
GPO_0
GPO_1
B
C
D
GPO_7
GPO_5
GPO_4
GPO_3
GPO_2
Top View
Note: This is a preliminary pinout (pin sequence not fixed)
Figure 1. 16-Bump DSBGA Pinout
1.965mm x 1.965mm x 0.6mm (nom), 0.5mm pitch
See Package Number YZR0016
PIN A1
IDENTIFIER
Figure 2. A1 Pin Identifier
PIN DESCRIPTIONS
Pin Number
Name
Description
8
1
1
GPO_0 through GPO_7 General purpose outputs
SCLK
RFFE clock input
SDATA
RFFE data input
RFFE chip address input
ADR = VDD: USID[3:0] = b1001
ADR = GND: USID[3:0] = b0001
Initial configuration select
1
ADR
CFG
CFG = VDD: GPO high-z with weak internal pull-down resistor enabled,
GPO_OUT_DATA masked
1
CFG = GND: GPO high-z, with weak internal pull-down resistor enabled,
GPO_OUT_DATA unmasked
1
1
1
1
VIO
VDD
MIPI RFFE VIO (1.8V ± 0.15V)
Core supply VDD (1.8V ± 0.15V)
GPO supply VDDIO (1.65V to 3.6V)
Ground
VDDIO
GND
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ADR INPUT PIN
The state of the ADR pin determines the MIPI RFFE USID as described in the table above. This enables two
devices to be used on the same RFFE bus thereby doubling the number of GPOs available in the system (see
Dual RFFE Slave Application Block Diagram).
DEFAULT GPO_x PIN CONFIGURATION
Upon power-on all GPOs will default based on the state of the CFG pin.
CFG INPUT PIN = GND
The CFG0 mode is an automatic initialization mode. It allows the host to not have to first configure any registers
before writing the GPO_OUT_DATA register to set the GPOs high or low. In this mode, the GPOs will default as
high-z with weak pull-down resistors enabled and the GPO_OUT_DATA will be unmasked. When the host writes
the GPO_OUT_DATA register, the weak pull-down resistor will be disabled. The output driver will immediately be
enabled and will drive high or low based on the value written to the GPO_OUT_DATA register. In configuration
mode CFG0 the GPO data mask function is available but the GPO pull resistor, and high-z functions cannot be
changed. Writing to the GPO_PULL_DIR, GPO_PULL_ENABLE, and GPO_OUT_HIGH_CFG registers will have
no effect. If control of the GPO pull resistor or output configuration is required then the CFG1 mode must be
used.
CFG INPUT PIN = VDD
The CFG1 mode is a more general purpose mode where the outputs must be configured during initialization prior
to use. In this mode, the GPOs will default as high-z with internal pull-down resistors enabled and
GPO_OUT_DATA will be masked. During initialization, the host must first write to the GPO_OUT_DATA register
(Note: this will transition all of the GPOs from high-z with internal pull-down to Full-Buffer driven low with internal
pull-down regardless of the value written to the GPO_OUT_DATA register). The host must then write to the
GPO_PULL_DIR, GPO_PULL_ENABLE, & GPO_OUT_HIGH_CFG registers to configure each GPO into the
desired output configuration. Once that is complete, the host then writes the GPO_DATA_MASK and
GPO_OUT_DATA registers to set the GPO outputs in the desired state. Refer to Figure 8.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)(2)
Absolute Maximum Ratings
RFFE Supply Voltage (VIO)
−0.3V to 2.2V
−0.3V to 2.2V
Core Supply Voltage (VDD)
GPO Supply Voltage (VDDIO)
DC Input Voltage for SCLK & SDATA pins
DC Input Voltage for ADR & CFG pins
DC Output Voltage for GPO pins
Storage Temperature Range
−0.3V to 4.0V
−0.3V to (VIO+0.3V)
−0.3V to (VDD+0.3V)
−0.3V to (VDDIO+0.3V)
−40°C to +125° C
−0°C to +85°C
Operating Ambient Temperature (TA)
Lead Temperature (TL)
(Soldering, 10 sec.)
260°C
ESD Rating
(CZAP=120 pF, RZAP=1500Ω)
(3)
Human Body Model
1000V
250V
Charge Device Model:
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not specified. For specifications and test conditions, see the
Electrical Characteristics tables.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF
capacitor discharged directly into each pin.
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Operating Ratings
Min
Max
1.95
25
Unit
RFFE Supply Voltage (VIO)
RFFE Supply Noise (VIO)
1.65
V
mVpp
V
Core Supply Voltage (VDD
Core Supply Noise (VDD
GPO Supply Voltage (VDDIO
GPO Supply Noise (VDDIO
)
1.65
1.65
1.95
25
)
mVpp
V
)
3.60
50
)
mVpp
DC Electrical Characteristics: General (ADR, CFG)(1)(2)
TA: −30°C to +85°C, VIO = 1.8V ± 0.15V, VDD = 1.8V ± 0.15V, VDDIO = 3.3V ± 0.3V (unless otherwise specified).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Minimim high-level input voltage
(ADR, CFG)
VIH
VIL
IIH
0.7 * VDD
VDD+ 0.2
0.3 * VDD
2
V
Maximum low-level input voltage
(ADR, CFG)
−0.2
−2
Logic high-level input current
(ADR, CFG)
VIN = VDD
µA
Logic low-level input current (ADR,
CFG)
IIL
VIN = GND
(1) All voltages are with respect to the GND pin.
(2) Min and Max Limits are specified by design, test, or statistical analysis. Typical (Typ.) numbers are not specified, but do represent the
most likely norm. Unless otherwise specified conditions for typical specifications are: VDD = 1.8V, VDDIO = 3.3V, VIO = 1.8V, TA = +25°C.
DC Electrical Characteristics: GPO (GPO_x, VDD, VDDIO)(1)(2)
TA: −30°C to +85°C, VIO = 1.8V ± 0.15V, VDD = 1.8V ± 0.15V; VDDIO = 3.3V ± 0.3V (unless otherwise specified).
Symbol
Parameter
Conditions
IOH = −12 mA
(VDDIO = 3.3V ± 0.3V)
Minimum high-level output voltage IOH = −4 mA
(VDDIO = 1.8V ± 0.15V)
Min
Typ
Max
Units
0.7 * VDDIO
VDDIO − 0.2
VOH
V
IOH = −10 µA
IOL = 12 mA
(VDDIO = 3.3V ± 0.3V)
0.4
VOL
Maximum low-level output voltage IOL = 4 mA
V
0.4
0.2
(VDDIO = 1.8V ± 0.15V)
IOL = 10 µA
(VDDIO = 3.3V ± 0.3V)
(VDDIO = 1.8V ± 0.15V)
(VDDIO = 3.3V ± 0.3V)
(VDDIO = 1.8V ± 0.15V)
0 < VPIN < VDDIO
−12
−4
IOH
Logic high-level output current
mA
12
4
IOL
IOZ
IPU
Logic low-level output current
High-Z leakage current
Pull-Up current
mA
µA
µA
−2
−60
−9
60
9
2
(VDDIO = 3.3V ± 0.3V)
(VDDIO = 1.8V ± 0.15V)
(VDDIO = 3.3V ± 0.3V)
(VDDIO = 1.8V ± 0.15V)
−200
-60
200
60
IPD
Pull-Down current
µA
µA
ISTBY
VDD supply standby current
TA = 25°C, VIO = 1.8V,
VDD = 1.8V, VDDIO = 3.3V,
GPO_X = high-z, PU & PD
disabled
2.5
ISTBYIO
VDDIO supply standby current
2.5
SCLK = Low
(1) All voltages are with respect to the GND pin.
(2) Min and Max Limits are specified by design, test, or statistical analysis. Typical (Typ.) numbers are not specified, but do represent the
most likely norm. Unless otherwise specified conditions for typical specifications are: VDD = 1.8V, VDDIO = 3.3V, VIO = 1.8V, TA = +25°C.
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DC Electrical Characteristics: GPO (GPO_x, VDD, VDDIO)(1)(2) (continued)
TA: −30°C to +85°C, VIO = 1.8V ± 0.15V, VDD = 1.8V ± 0.15V; VDDIO = 3.3V ± 0.3V (unless otherwise specified).
Symbol
IVDD
Parameter
VDD supply current
Conditions
Min
Typ
Max
Units
TA = 25°C, VDD = 1.8V
225
400
µA
TA = 25°C
VDDIO = 3.3V
IVDDIO
VDDIO supply current
200
450
DC Electrical Characteristics: RFFE (SCLK, SDATA, VIO)(1)(2)
TA: −30°C to +85°C, VIO = 1.8V ± 0.15V, VDD = 1.8V ± 0.15V; VDDIO = 3.3V ± 0.3V (unless otherwise specified).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Input pin capacitance
(SCLK, SDATA)(2)
CIN
2.5
pF
Positive edge threshold voltage
(SCLK, SDATA)
VTP
0.4 * VIO
0.3 * VIO
0.1 * VIO
0.7 * VIO
0.6 * VIO
0.4 * VIO
Negative edge threshold voltage
(SCLK, SDATA)
VTN
V
Input hysteresis voltage
(SDATA)
VHYST
RFFE I/O voltage reset voltage
level
VIORST
IINVIO
IIN
VIO toggled low
0.2
1
Input current (VIO)
0 < VIO < 0.2V
−1
−1
Input current
(SCLK, SDATA)
VIO = Max,
0.2 * VIO < VIN < 0.8 * VIO
1
µA
VIO = 1.8,
RFFE write only mode
IVIO
VIO supply input current
100
(1) All voltages are with respect to the GND pin.
(2) Min and Max Limits are specified by design, test, or statistical analysis. Typical (Typ.) numbers are not specified, but do represent the
most likely norm. Unless otherwise specified conditions for typical specifications are: VDD = 1.8V, VDDIO = 3.3V, VIO = 1.8V, TA = +25°C.
AC Electrical Characteristics: Internal POR, VIO, GPO_x, SCLK(1)(2)
TA: −30°C to +85°C, VIO = 1.8V ± 0.15V, VDD = 1.8V ± 0.15V; VDDIO = 3.3V ± 0.3V (unless otherwise specified).
Symbol
tPORC1
tPORC2
tREADY
Parameter
Conditions
VDD ramp rate = 100 µS
VDDIO ramp rate = 100 µS
Min
Typ
Max
1
Units
VDD POR reset complete
VDDIO POR reset complete
mS
1
VIO input signal reset delay time VIO = 1.65V, SCLK, SDATA = Low,
tPORC1, tPORC2 = complete
120
26
nS
MHz
nS
fSCLK
tD
SCLK frequency
0.032
GPO_x output delay time
VDDIO = 1.8V ± 0.15V,
CLOAD = 10 pf
25
(1) All voltages are with respect to the GND pin.
(2) Min and Max Limits are specified by design, test, or statistical analysis. Typical (Typ.) numbers are not specified, but do represent the
most likely norm. Unless otherwise specified conditions for typical specifications are: VDD = 1.8V, VDDIO = 3.3V, VIO = 1.8V, TA = +25°C.
D1
D0
P
SDATA
SCLK
VTP Max
tD
VOH Min
VOL Max
GPO_x
Figure 3. GPO Delay Timing
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MIPI RFFE INTERFACE
The LM8335 provides RFFE compatible slave access to the device specific and RFFE defined registers on a
single master bidirectional serial bus interface. The LM8335 uses the three interface signals SCLK, SDATA, and
VIO as defined in MIPI RFFE Version 1.10 – 26 July 2011. The VIO voltage supply provides power to the
LM8335 RFFE Interface and doubles as an asynchronous enable and reset. Whenever VIO is low the SCLK and
SDATA lines must be held low. When the VIO voltage is applied, the LM8335 enables the slave interface and
resets the user defined slave registers to the default settings. The LM8335 enters the power down mode via the
asynchronous VIO signal. The LM8335 does not support read access.
The LM8335 contains fewer than 28 user defined registers but supports the Extended Register Write Command
to allow a burst write of configuration registers during initialization. Any write outside of the range from 0x00 to
0x1F will have no effect on device operation.
The LM8335 recognizes the broadcast Slave Identifier (SID) of 0000b and is configured internally with a Unique
Slave Identifier (USID) and a Group Slave Identifier (GSID). The USID is set based on the state of the ADR pin
and the GSID is set to 0000b. The USID may be reprogrammed via the RFFE Interface by performing the
Register Write USID Command Sequence.
The LM8335 supports only the 1.8V VIO supply levels. The LM8335 utilizes a power-detect reset circuit that
resets the RFFE interface and internal registers when VIO is removed.
SCLK
SDATA
SA3
SA2
SA1
SA0
1
D6
D5
D4
D3
D2
D1
D0
P
0
Parity
Bus
Park
SSC
Slave Address
Data
Signal driven by Master.
Signal not driven; pull-down only.
For reference only.
Figure 4. Register 0 Write Command Sequence
Figure 5. Register Write Command Sequence
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Figure 6. Extended Register Write Command Sequence
INTERNAL POR OPERATION
There are two internal POR circuits: one on the VDD supply and one on the VDDIO supply that initialize the
LM8335 when power is applied. The duration of the reset is an RC delay which is based on the ramp rate and
not a threshold voltage of the VDD/VDDIO supply. VIO can be activated as soon as VDD and VDDIO have
reached their minimum respective voltage levels however the LM8335 may still be in reset due to the internal
POR timing. When VIO is asserted after VDD and VDDIO tPORC Max, the device reset will be released based on
the VIO tREADY timing.
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VDD or
VDDIO
VIO
V
VIO-RST
POR
(Internal)
t
RAMP
t
Min
PORC
t
Max
PORC
t
Max
READY
Figure 7. Internal VDD or VDDIO POR Timing
Register Information
Table 1. Register Listing
Register Name
Addr
Bit
Default
Description
Software reset register
Bit 0 = 0, no effect
CNTL_REG
0x00
7:0
0x00
Bit 0 = 1, reset registers to default values (self-clearing)
GPO pin pull resistor direction
0 = pull-down
1 = pull-up
GPO_PULL_DIR
0x01
0x02
7:0
0x00
0xFF
Note: When CFG = GND, writing to this register has no effect.
The pull-down resistor will be disabled after the first write to
the GPO_OUT_DATA register.
GPO pin internal pull resistor enable
0 = disabled
1 = enabled
GPO_PULL_ENABLE
0xFF
Note: GPO_PULL_DIR register selects if the resistor is a pull-
up or a pull-down. When CFG = GND, writing to this register
has no effect. The pull-down resistor will be disabled after the
first write to the GPO_OUT_DATA register.
GPO output high state (full buffer or high-z).
0 = full buffer
1 = high-z (open-drain behavior)
GPO_OUT_HIGH_CFG
0x03
7:0
0xFF
Note: When CFG = GND, writing to this register has no effect.
The pull-down resistor will be disabled, and all GPO outputs
will be in the actively driven state (not high-z) after the first
write to the GPO_OUT_DATA register.
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Table 1. Register Listing (continued)
Register Name
Addr
Bit
Default
Description
GPO output data mask
0 = GPO_OUT_DATA masked
1 = GPO_OUT_DATA unmasked
0xFF
(CFG=0) or
0x00
Note: Only the GPO_OUT_DATA register write is affected by
the GPO_OUT_MASK register. When the GPO_OUT_MASK
bit is set low (masked), writing to GPO_OUT_DATA register
will leave the pin state unchanged. When the
GPO_OUT_MASK
0x04
7:0
(CFG=1)
GPO_OUT_MASK bit is set high (unmasked), the GPO output
will be updated when the GPO_OUT_DATA is written (only
GPOs that are unmasked will be changed).
GPO output data
0 = pin set low
1 = pin set high
GPO_OUT_DATA
0x05
7:0
0x00
Note: GPO_OUT_HIGH_CFG register selects if the pin is
driven or high-z. The pin state will follow GPO_OUT_DATA
only if the corresponding bit is unmasked in the
GPO_OUT_MASK register.
MIPI RFFE power mode and trigger register
Bits 7:6 = PWR_MODE
PM_TRIG
PROD_ID
0x1C
0x1D
7:0
7:0
0x00
0xC4
Bits 5:0 = TRIG_REG
This is a MIPI RFFE reserved read only register and can not
be read since readback is not supported on this device.
Bits 7:0 = PRODUCT_ID [7:0]
The product ID is provided as information only to support the
RFFE USID programming feature.
This is a MIPI RFFE reserved read-only register and can not
be read since readback is not supported on this device.
MAN_ID
0x1E
7:0
0x02
Bits 7:0 = MANUFACTURER_ID [7:0]
The manufacturer ID is provided as information only to support
the RFFE USID programming feature.
0x11
(ADR=0)
This MIPI RFFE reserved register
or
Bits 7:6 = SPARE
0x19
Bits 5:4 = MANUFACTURER_ID [9:8] = 1
Bits 3:0 = Programmable Unique Slave Identifier
— ADR=Low, USID[3:0]=0001
(ADR=1)
USID_REG
0x1F
7:0
— ADR=High, USID[3:0]=1001
Note: The USID is initially set based on the state of the ADR
pin (default value when ADR=Low shown). This register can
not be read since readback is not supported on this device.
USID_REG[5:4] are provided as information only to support
the RFFE USID programming feature.
Table 2. General Bit Field Layout for GPO_x Registers
7
6
5
4
3
2
1
0
GPO_7
GPO_6
GPO_5
GPO_4
GPO_3
GPO_2
GPO_1
GPO_0
Table 3. CNTL_REG Register Bit Fields
7
6
5
4
3
2
1
0
rsvd
rsvd
rsvd
rsvd
rsvd
rsvd
rsvd
SW_RESET
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Figure 8. CFG1 MODE Recommended Initialization Sequence
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Figure 9. Update GPO Pin State Sequence
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PACKAGE OPTION ADDENDUM
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24-Jan-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
(1)
(2)
(3)
(4)
LM8335TLE
PREVIEW
PREVIEW
ACTIVE
16
16
16
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-30 to 85
-30 to 85
LM8335TLE NOPB
LM8335TLE/NOPB
DSBGA
DSBGA
YZR
YZR
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
8335
LM8335TLX
PREVIEW
ACTIVE
16
16
TBD
Call TI
Call TI
-30 to 90
LM8335TLX/NOPB
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
8335
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
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Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Only one of markings shown within the brackets will appear on the physical device.
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Addendum-Page 1
MECHANICAL DATA
YZR0016xxx
D
0.600±0.075
E
TLA16XXX (Rev C)
D: Max = 2.01 mm, Min = 1.91 mm
E: Max = 2.01 mm, Min = 1.91 mm
4215051/A
12/12
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
NOTES:
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