LM98722 [TI]
具有 LVDS/CMOS 输出和集成 CCD/CIS 传感器定时发送器的 3 通道 16 位 45 MSPS AFE;型号: | LM98722 |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有 LVDS/CMOS 输出和集成 CCD/CIS 传感器定时发送器的 3 通道 16 位 45 MSPS AFE CD 传感器 |
文件: | 总151页 (文件大小:5301K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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LM98722
SNAS487B –SEPTEMBER 2009–REVISED MARCH 2015
LM98722 3 Channel, 16-Bit, 45 MSPS Analog Front End with LVDS/CMOS Output,
Integrated CCD/CIS Sensor Timing Generator, and Spread Spectrum Clock Generation
1 Features
3 Description
The LM98722 is a fully integrated, high performance
16-Bit, 45 MSPS signal processing solution for digital
color copiers, scanners, and other image processing
applications. High-speed signal throughput is
achieved with an innovative architecture utilizing
Correlated Double Sampling (CDS), typically
employed with CCD arrays, or Sample and Hold
(S/H) inputs (for higher speed CCD or CMOS image
sensors). The signal paths utilize 8 bit Programmable
Gain Amplifiers (PGA), a +/-9-Bit offset correction
DAC and independently controlled Digital Black Level
correction loops for each input. The PGA and offset
DAC are programmed independently allowing unique
values of gain and offset for each of the three analog
inputs. The signals are then routed to a 45-MHz high
performance analog-to-digital converter (ADC). The
1
•
•
LVDS/CMOS Outputs
LVDS/CMOS/Crystal Clock Source with PLL
Multiplication
•
Integrated Flexible Spread Spectrum Clock
Generation
•
•
CDS or S/H Processing for CCD or CIS sensors
Independent Gain/Offset Correction for Each
Channel
•
Automatic per-Channel Gain and Offset
Calibration
•
•
Programmable Input Clamp Voltage
Flexible CCD/CIS Sensor Timing Generator
2 Applications
fully
differential
processing
channel
shows
exceptional noise immunity, having a very low noise
floor of -74dB. The 16-bit ADC has excellent dynamic
performance making the LM98722 transparent in the
image reproduction chain.
•
•
•
•
•
Multi-Function Peripherals
High-speed Currency/Check Scanners
Flatbed or Handheld Color Scanners
High-speed Document Scanners
Key Specifications:
A very flexible integrated Spread Spectrum Clock
Generation (SSCG) modulator is included to assist
with EM compliance and reduce system costs.
–
Maximum Input Level:
–
1.2-V or 2.4-V Modes (Both with + or -
Polarity Option)
Device Information
ORDER NUMBER
PACKAGE
BODY SIZE
–
–
–
–
ADC Resolution: 16-Bit
LM98722
TSSOP (56)
14.0 mm x 6.10 mm
ADC Sampling Rate: 45 MSPS
INL: +18/-25 LSB (typ)
Simplified Schematic
Channel Sampling Rate: 22.5/22.5/15 MSPS
(1ch/2ch/3ch)
CCD/CIS Sensor
Analog Front End
SPI
–
–
–
–
–
–
–
–
–
–
PGA Gain Steps: 256 Steps
Image Processor/
ASIC
LM98722
PGA Gain Range: 0.64 to 8.3x
Data Output
CLK
CCD Timing
Generator
Sensor Drivers
Analog DAC Resolution: +/-9 Bits
Analog DAC Range: +/-307 mV or +/-614 mV
Digital DAC Resolution: +/-6 Bits
Digital DAC Range: -2048 LSB to + 2016 LSB
SNR: -74dB (at 0dB PGA Gain)
Power Dissipation: 630 mW (LVDS)
Operating Temp: 0 to 70°C
Motor
Controllers
SSCG
Supply Voltage: 3.3-V Nominal (3.0-V to 3.6-V
Range)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM98722
SNAS487B –SEPTEMBER 2009–REVISED MARCH 2015
www.ti.com
Table of Contents
7.1 Overview ................................................................. 13
7.2 Functional Block Diagrams ..................................... 14
7.3 Feature Description................................................. 16
7.4 Device Functional Modes........................................ 25
7.5 Registers Maps ....................................................... 91
Layout ................................................................. 141
8.1 Layout Example .................................................... 141
Device and Documentation Support................ 142
9.1 Device Support...................................................... 142
9.2 Trademarks........................................................... 142
9.3 Electrostatic Discharge Caution............................ 142
9.4 Glossary................................................................ 142
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings.............................................................. 6
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information.................................................. 7
6.5 Electrical Characteristics........................................... 7
6.6 AC Timing Requirements........................................ 11
Detailed Description ............................................ 13
8
9
10 Mechanical, Packaging, and Orderable
7
Information ......................................................... 142
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (April 2013) to Revision B
Page
•
Added, updated, or revised the following sections in accordance with new datasheet standards: Description; Pin
Configuration and Functions; Specifications; Detailed Description; Application and Implementation; Device and
Documentation Support; and Mechanical, Packaging, and Ordering Information.................................................................. 1
Changed "29" to "33" for Pin 32 INCLK+ in Pin Functions table............................................................................................ 4
Deleted "Boldface limits apply..." statement in Electrical Characteristics and AC Timing Requirements ............................. 7
•
•
•
Changed "external" to "internal" and changed "internal" to "external" under "SH_R Capture Clock Select (Page 0,
Register 0x00, Bit 5)" bullet point in Clock Sources - Additional Settings and Flexibility..................................................... 19
•
•
•
•
•
Changed 25 MHz to 15 MHz in Table 4 .............................................................................................................................. 26
Changed 50 MHz to 45 MHz in Table 4............................................................................................................................... 26
Changed "Page 2" to "Page 0" in CCD Timing Generator Master/Slave Modes and Master Timing Generator Mode....... 64
Added "Note" to Serial Interface .......................................................................................................................................... 86
Changed "1100 0000" to "1100 0010" for Page 0, Addr 2 ................................................................................................ 104
Changes from Original (April 2013) to Revision A
Page
•
Changed layout of National Data Sheet to TI format ............................................................................................................. 1
2
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LM98722
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SNAS487B –SEPTEMBER 2009–REVISED MARCH 2015
5 Pin Configuration and Functions
56-Pin TSSOP
Package DGG056A
(Top View)
PHIC2
PHIC1
SH1
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
SH5
2
SH4
3
PHIB2
PHIB1
CE
4
CAL
5
V
C
6
DGND
PHIA2
PHIA1
CP
RESET
SH_R
7
SDI
SDO
SCLK
SEN
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
RS
SH3
CLKOUT/SH2
V
A
AGND
V
V
C
56 Pin TSSOP
(not to scale)
V
A
D
VREFB
VREFT
DGND
DOUT0/TXOUT0-
DOUT1/TXOUT0+
DOUT2/TXOUT1-
DOUT3/TXOUT1+
DOUT4/TXOUT2-
DOUT5/TXOUT2+
DOUT6/TXCLK-
DOUT7/TXCLK+
INCLK-
V
A
AGND
VCLP
V
A
IBIAS
AGND
OS
R
AGND
OS
INCLK+
G
AGND
OS
DVB
CPOFILT1
B
CPOFILT2
DGND
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LM98722
SNAS487B –SEPTEMBER 2009–REVISED MARCH 2015
www.ti.com
Pin Descriptions(1)
PIN
I/O
TYP
RES
DESCRIPTION
NO.
NAME
PHIC2
1
2
3
O
O
O
D
D
D
PU
PD
PU
Configurable high speed sensor timing output.
Configurable high speed sensor timing output.
Configurable low speed sensor timing output.
Chip Serial Interface Address Setting Input
PHIC1
SH1
CE LEVEL
VD
ADDRESS
4
CE
I
D
01
10
00
Float
DGND
5
6
7
8
9
CAL
I
I
D
D
D
D
D
D
D
P
P
P
A
A
P
P
PD
PU
PD
PD
Initiate calibration sequence. Leave unconnected or tie to DGND if unused.
Active-low master reset. NC when function not being used.
External request for an SH interval.
RESET
SH_R
SDI
I
I
Serial Interface Data Input.
SDO
SCLK
SEN
O
I
Serial Interface Data Output.
10
11
12
13
14
15
16
17
18
PD
PU
Serial Interface shift register clock.
I
Active-low chip enable for the Serial Interface.
VA
Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND.
Analog ground return.
AGND
VA
Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND.
Bottom of ADC reference. Bypass with a 0.1μF capacitor to ground.
Top of ADC reference. Bypass with a 0.1μF capacitor to ground.
Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND.
Analog ground return.
VREFB
VREFT
VA
O
O
AGND
Input Clamp Voltage. Normally bypassed with a 0.1μF , and a 4.7μF capacitor to
AGND. An external reference voltage may be applied to this pin.
19
VCLP
IO
A
20
21
22
23
24
25
26
27
VA
P
A
P
A
P
A
P
A
Analog power supply. Bypass voltage source with 4.7μF and pin with 0.1μF to AGND.
Bias setting pin. Connect a 9.0 kΩ 1% resistor to AGND.
Analog ground return.
IBIAS
AGND
OSR
O
I
Analog input signal. Typically sensor Red output AC-coupled thru a capacitor.
Analog ground return.
AGND
OSG
I
Analog input signal. Typically sensor Green output AC-coupled thru a capacitor.
Analog ground return.
AGND
OSB
I
Analog input signal. Typically sensor Blue output AC-coupled thru a capacitor.
Charge Pump Filter Capacitor. Bypass this supply pin with a 0.1μF capacitor to
CPOFILT1.
28
29
30
31
CPOFILT2
DGND
A
P
A
D
Digital ground return.
Charge Pump Filter Capacitor. Bypass this supply pin with a 0.1μF capacitor to
CPOFILT2.
CPOFILT1
DVB
O
I
Digital Core Voltage bypass. Not an input. Bypass with 0.1μF capacitor to DGND.
Clock Input. Non-Inverting input for LVDS clocks or CMOS clock input. CMOS clock is
selected when pin 33 is held at DGND, otherwise clock is configured for LVDS
operation.
32
INCLK+
D
33
34
INCLK-
DOUT7/
TXCLK+
DOUT6/
TXCLK-
I
D
D
Clock Input. Inverting input for LVDS clocks, connect to DGND for CMOS clock.
Bit 7 of the digital video output bus in CMOS Mode, LVDS Frame Clock+ in LVDS
Mode.
O
Bit 6 of the digital video output bus in CMOS Mode, LVDS Frame Clock- in LVDS
Mode.
35
O
D
(1) (I=Input), (O=Output), (IO=Bi-directional), (P=Power), (D=Digital), (A=Analog), (PU=Pull Up with an internal resistor), (PD=Pull Down
with an internal resistor.).
4
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SNAS487B –SEPTEMBER 2009–REVISED MARCH 2015
Pin Descriptions(1) (continued)
PIN
NAME
I/O
O
TYP
D
RES
DESCRIPTION
NO.
DOUT5/
TXOUT2+
DOUT4/
TXOUT2-
DOUT3/
TXOUT1+
DOUT2/
TXOUT1-
DOUT1/
TXOUT0+
DOUT0/
TXOUT0-
DGND
Bit 5 of the digital video output bus in CMOS Mode, LVDS Data Out2+ in LVDS
Mode.
36
37
38
39
40
Bit 4 of the digital video output bus in CMOS Mode, LVDS Data Out2- in LVDS Mode.
O
D
Bit 3 of the digital video output bus in CMOS Mode, LVDS Data Out1+ in LVDS
Mode.
O
D
Bit 2 of the digital video output bus in CMOS Mode, LVDS Data Out1- in LVDS Mode.
O
D
Bit 1 of the digital video output bus in CMOS Mode, LVDS Data Out0+ in LVDS
Mode.
O
D
Bit 0 of the digital video output bus in CMOS Mode, LVDS Data Out0- in LVDS Mode.
41
42
O
O
D
D
PD
Configurable sensor control output.
Power supply for the digital circuits. Bypass this supply pin with 0.1μF capacitor. A
single 4.7μF capacitor should be used between the supply and the VD, VR and VC
pins.
43
VD
P
Power supply for the sensor control outputs. Bypass this supply pin with 0.1μF
capacitor.
44
45
VC
P
D
Output clock for registering output data when using CMOS outputs, or a configurable
low speed sensor timing output.
CLKOUT/SH2
O
46
47
48
49
50
51
SH3
O
O
O
O
O
D
D
D
D
D
P
Configurable low speed sensor timing output.
Configurable high speed sensor timing output.
Configurable high speed sensor timing output.
Configurable high speed sensor timing output.
Configurable high speed sensor timing output.
Digital ground return.
RS
CP
PHIA1
PHIA2
DGND
Power supply for the sensor control outputs.
Bypass this supply pin with 0.1μF capacitor.
52
VC
P
53
54
55
56
PHIB1
PHIB2
SH4
O
O
O
O
D
D
D
D
Configurable high speed sensor timing output.
Configurable high speed sensor timing output.
Configurable low speed sensor timing output.
Configurable low speed sensor timing output.
SH5
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SNAS487B –SEPTEMBER 2009–REVISED MARCH 2015
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6 Specifications
6.1 Absolute Maximum Ratings(1)(2)(3)(4)
MIN
MAX
4.2
UNIT
V
Supply Voltage (VA, VR, VD, VC)
Voltage on Any Input Pin (not to exceed 4.2 V)
Voltage on Any Output Pin (except DVB and not to exceed 4.2 V)
DVB Output Pin Voltage
−0.3
−0.3
VA + 0.3
VA + 0.3
2.0
V
V
V
Input Current at any pin other than Supply Pins(5)
Package Input Current (except Supply Pins)(5)
Maximum Junction Temperature (TA)
Package Dissipation at TA = 25°C(6)
±25
mA
mA
°C
W
±50
150
>1.89
+150
Storage Temperature, Tstg
–65
°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions. Operation of the device beyond the Operating Ratings is not
recommended.
(2) All voltages are measured with respect to AGND = DGND = 0V, unless otherwise specified.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(4) Soldering process must comply with Texas Instrument’s Reflow Temperature Profile specifications. Refer to www.ti.com/packaging
Reflow temperature profiles are different for lead-free and non-lead-free packages.
(5) When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > VA or VD), the current at that pin should be
limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can simultaneously safely exceed the
power supplies with an input current of 25 mA to two.
(6) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX,RθJA and the ambient temperature,
TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX – TA)/RθJA. The values for maximum power dissipation
listed above will be reached only when the device is operated in a severe fault condition, (for example, when input or output pins are
driven beyond the power supply voltages, or the power supply polarity is reversed). Such conditions should always be avoided.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(2)
±2500
V(ESD)
Electrostatic discharge(1)
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(3)
±250
(1) Human body model is 100 pF capacitor discharged through a 1.5-kΩ resistor. Machine model is 220 pF discharged through 0 Ω.
(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2500 V may actually have higher performance.
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±250 V may actually have higher performance.
6.3 Recommended Operating Conditions(1)(2)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
0 ≤ TA ≤ +70
+3.6
UNIT
°C
Operating Temperature Range
All Supply Voltage
+3.0
V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions. Operation of the device beyond the Operating Ratings is not
recommended.
(2) All voltages are measured with respect to AGND = DGND = 0V, unless otherwise specified.
6
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SNAS487B –SEPTEMBER 2009–REVISED MARCH 2015
6.4 Thermal Information
TSSOP
UNIT
THERMAL METRIC(1)
56 TERMINALS
RθJA
Junction-to-ambient thermal resistance
<66
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
The following specifications apply for VA = VD = VC = 3.3 V, CL = 10 pF, and fINCLK = 15 MHz unless otherwise specified. All
other limits TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN(1)
TYP(2) MAX(1)(3)
UNIT
CMOS DIGITAL INPUT DC SPECIFICATIONS (RESETb, SH_R, SCLK, SENb)
VIH
Logical “1” Input Voltage
Logical “0” Input Voltage
Logic Input Hysteresis
2.0
V
V
VIL
0.8
VIHYST
0.6
VIH = VD:
RESET, SEN
100
65
nA
IIH
Logical “1” Input Current
Logical “0” Input Current
SH_R, SCLK, SDI, CAL
μA
CE
30
VIL = DGND
RESET, SEN,
SH_R, SCLK, SDI, CAL
CE
-65
-100
-30
μA
nA
μA
IIL
CMOS DIGITAL OUTPUT DC SPECIFICATIONS (SH1 to SH5, RS, CP, PHIA, PHIB, PHIC)
VOH
VOL
Logical “1” Output Voltage
Logical “0” Output Voltage
IOUT = -0.5 mA
IOUT = 1.6 mA
VOUT = DGND
VOUT= VD
3.0
V
V
0.21
18
-25
20
IOS
Output Short Circuit Current
mA
nA
VOUT = DGND
VOUT = VD
CMOS Output TRI-STATE
Current
IOZ
-25
CMOS DIGITAL OUTPUT DC SPECIFICATIONS (CMOS DATA OUTPUTS)
VOH
VOL
Logical “1” Output Voltage
Logical “0” Output Voltage
IOUT = -0.5 mA
IOUT = 1.6 mA
VOUT = DGND
VOUT= VD
2.3
0.12
12
V
V
IOS
Output Short Circuit Current
mA
nA
-14
20
VOUT = DGND
VOUT = VD
CMOS Output TRI-STATE
Current
IOZ
-25
(1) Test limits are ensured to TI's AOQL (Average Outgoing Quality Level).
(2) Typical figures are at TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured.
(3) The analog inputs are protected as shown in Figure 1. Input voltage magnitudes beyond the supply rails will not damage the device,
provided the current is limited per Note 4 under the Absolute Maximum Ratings table. However, input errors will be generated If the
input goes above VA and below AGND.
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Electrical Characteristics (continued)
The following specifications apply for VA = VD = VC = 3.3 V, CL = 10 pF, and fINCLK = 15 MHz unless otherwise specified. All
other limits TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN(1)
TYP(2) MAX(1)(3)
UNIT
LVDS/CMOS CLOCK RECEIVER DC SPECIFICATIONS (INCLK+ and INCLK- PINS)
Differential LVDS Clock
VIHL
200
mV
mV
V
High Threshold Voltage
Differential LVDS Clock
Low Threshold Voltage
CMOS Clock
RL = 100 Ω, VCM (LVDS Input Common Mode
Voltage)= 1.25 V
VILL
VIHC
VILC
IIHL
-200
2.0
High Threshold Voltage
CMOS Clock
INCLK- = DGND
0.8
V
Low Threshold Voltage
CMOS Clock
230
260
μA
μA
Input High Current
CMOS Clock
IILC
-135
-120
Input Low Current
LVDS OUTPUT DC SPECIFICATIONS
VOD
VOS
IOS
Differential Output Voltage
LVDS Output Offset Voltage
Output Short Circuit Current
280
390
1.20
8.5
490
mV
V
RL = 100 Ω
1.08
1.33
VOUT = 0 V, RL = 100 Ω
mA
POWER SUPPLY SPECIFICATIONS
LVDS Output Data Format
139
3.1
137
50
162
4.5
161
65
mA
mA
mA
mA
mA
IA
ID
VA Analog Supply Current
LVDS Output Data Format (Powerdown)
CMOS Output Data Format (40 MHz)
LVDS Output Data Format
LVDS Output Data Format (Powerdown)
5.5
8
VD Digital Output Driver Supply
Current
CMOS Output Data Format
(ATE Loading of CMOS Outputs > 50 pF)
(40 MHz)
48
1
62
4
mA
Typical sensor outputs:
SH1-SH5, PHIA, PHIB, PHIC, RS, CP
(ATE Loading of CMOS
VC CCD Timing Generator
Output Driver Supply Current
IC
mA
Outputs > 50pF)
LVDS Output Data Format
LVDS Output Data Format (Powerdown)
630
28
736
32
mW
mW
PWR
Average Power Dissipation
CMOS Output Data Format
(ATE Loading of CMOS Outputs > 50 pF)
(40 MHz)
600
740
mW
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Electrical Characteristics (continued)
The following specifications apply for VA = VD = VC = 3.3 V, CL = 10 pF, and fINCLK = 15 MHz unless otherwise specified. All
other limits TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN(1)
TYP(2) MAX(1)(3)
UNIT
INPUT SAMPLING CIRCUIT SPECIFICATIONS
CDS Gain=1x, PGA Gain=1x
CDS Gain=2x, PGA Gain= 1x
2.3
VIN
Input Voltage Level
Vp-p
1.22
Source Followers Off
CDS Gain = 1x
OSX = VA (OSX = AGND)
19
25
(-103)
(-152)
(-250)
μA
(-95)
Source Followers Off
CDS Gain = 2x
OSX = VA (OSX = AGND)
Sample and Hold Mode Input
Leakage Current
33
50
IIN_SH
μA
(-141)
Source Followers On
CDS Gain = 2x
OSX = VA (OSX = AGND)
20
250
nA
(-50)
Sample/Hold Mode
Equivalent Input Capacitance
CDS Mode
CDS Gain = 1x
CDS Gain = 2x
2.5
4
pF
pF
CSH
Source Followers Off
OSX = VA (OSX = AGND)
10
250
IIN_CDS
RCLPIN
(-250)
nA
(-50)
Input Leakage Current
CLPIN Switch Resistance (OSX
to VCLP Node)
16
55
Ω
VCLP REFERENCE CIRCUIT SPECIFICATIONS
VCLP Voltage 000
VCLP Voltage 001
VCLP Voltage 010
VCLP Voltage 011
VCLP Voltage 100
VCLP Voltage 101
VCLP Voltage 110
VCLP Voltage 111
VCLP Voltage Setting = 000
0.85VA
0.9VA
V
V
V
V
V
V
V
V
VCLP Voltage Setting = 001
VCLP Voltage Setting = 010
VCLP Voltage Setting = 011
VCLP Voltage Setting = 100
VCLP Voltage Setting = 101
VCLP Voltage Setting = 110
VCLP Voltage Setting = 111
0.95VA
0.6VA
VVCLP
0.55VA
0.4VA
0.35VA
0.15VA
VCLP DAC Short Circuit Output
Current
ISC
30
mA
BLACK LEVEL OFFSET DAC SPECIFICATIONS
Resolution
10
Bits
Monotonicity
Ensured by characterization
CDS Gain = 1x
Minimum DAC Code = 0x000
Maximum DAC Code = 0x3FF
CDS Gain = 2x
-614
614
mV
Offset Adjustment Range
Referred to AFE Input
Minimum DAC Code = 0x000
Maximum DAC Code = 0x3FF
Minimum DAC Code = 0x000
Maximum DAC Code = 0x3FF
CDS Gain = 1x
-307
307
mV
-17500
+16130
-16130
+17500
Offset Adjustment Range
Referred to AFE Output
LSB
mV
(LSB)
LSB
1.2
(32)
DAC LSB Step Size
Referred to AFE Output
DNL
INL
Differential Non-Linearity
Integral Non-Linearity
-0.85 +0.74/ -0.37
-2.5 +0.72/ -0.56
+2.4
+2.5
LSB
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Electrical Characteristics (continued)
The following specifications apply for VA = VD = VC = 3.3 V, CL = 10 pF, and fINCLK = 15 MHz unless otherwise specified. All
other limits TA = 25°C.
PARAMETER
PGA SPECIFICATIONS
TEST CONDITIONS
MIN(1)
TYP(2) MAX(1)(3)
UNIT
Gain Resolution
Monotonicity
8
Bits
Ensured by characterization
CDS Gain = 1x
7.7
17.7
0.58
-4.7
8.3
18.4
0.64
-4.2
8.8
18.9
0.70
-3.5
V/V
dB
Maximum Gain
Minimum Gain
PGA Function
CDS Gain = 1x
CDS Gain = 1x
V/V
dB
CDS Gain = 1x
Gain (V/V) = (180/(277-PGA Code))
Gain (dB) = 20LOG10(180/(277-PGA Code))
Minimum PGA Gain
3%
Channel Matching
Maximum PGA Gain
12.7%
ADC SPECIFICATIONS
VREFT
VREFB
Top of Reference
2.07
0.89
V
V
Bottom of Reference
Differential Reference Voltage
VREFT
VREFB
-
1.06
1.18
1.30
V
Overrange Output Code
Underrange Output Code
65535
0
DIGITAL OFFSET “DAC” SPECIFICATIONS
Resolution
7
Bits
Digital Offset DAC LSB Step
Size
Referred to AFE Output
32
LSB
Offset Adjustment Range
Referred to AFE Output
Min DAC Code =7b0000000
Mid DAC Code =7b1000000
Max DAC Code = 7b1111111
-2048
0
LSB
+2016
FULL CHANNEL PERFORMANCE SPECIFICATIONS
(4)
DNL
INL
Differential Non-Linearity
Integral Non-Linearity
See
See
-0.999
-75
+0.8/-0.7
+18/-25
-76
2.5
75
LSB
LSB
dB
(4)
Minimum PGA Gain(4)
LSB
RMS
10
-56
96
26
SNR
Total Output Noise
Maximum PGA Gain(4)
dB
LSB
RMS
Mode 3
Mode 2
26
17
Channel to Channel Crosstalk
LSB
(4) This parameter ensured by design and characterization.
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6.6 AC Timing Requirements
The following specifications apply for VA = VD = VC = 3.3 V, CL = 10 pF, and fINCLK = 15 MHz unless otherwise specified. All
other limits TA = 25°C.(1)
PARAMETER
TEST CONDITIONS
MIN(2)
TYP(3)
MAX(2) UNIT
INPUT CLOCK TIMING SPECIFICATIONS
0.66
15 (Mode 3)
INCLK = PIXCLK
(Pixel Rate Clock)
1
22.5 (Mode 2) MHz
22.5 (Mode 1)
45 (Mode 3)
1
fINCLK
Input Clock Frequency
Input Clock Duty Cycle
2
INCLK = ADCCLK
(ADC Rate Clock)
2
2
45 (Mode 2) MHz
22.5 (Mode 1)
60/40%
Tdc
40/60%
50/50%
FULL CHANNEL LATENCY SPECIFICATIONS
PIXPHASE0
PIXPHASE1
PIXPHASE2
PIXPHASE3
PIXPHASE0
PIXPHASE1
PIXPHASE2
PIXPHASE3
PIXPHASE0
PIXPHASE1
PIXPHASE2
PIXPHASE3
24
23.5
23
3 Channel Mode Pipeline Delay
See Figure 50 (LVDS)
See Figure 55 (CMOS)
tLAT3
tLAT2
tLAT1
TADC
TADC
TADC
22.5
21
2 Channel Mode Pipeline Delay
See Figure 51 (LVDS)
See Figure 56 (CMOS)
20.5
20
19.5
19
1 Channel Mode Pipeline Delay
See Figure 52 (LVDS)
See Figure 57 (CMOS)
18.5
18
17.5
SH_R TIMING SPECIFICATIONS (see Figure 40)
tSHR_S
tSHR_H
SH_R Setup Time
SH_R Hold Time
2
2
ns
ns
LVDS OUTPUT TIMING SPECIFICATIONS (see Figure 49)
TXpp0
TXpp1
TXpp2
TXpp3
TXpp4
TXpp5
TXpp6
TXCLK to Pulse Position 0
TXCLK to Pulse Position 1
TXCLK to Pulse Position 2
TXCLK to Pulse Position 3
TXCLK to Pulse Position 4
TXCLK to Pulse Position 5
TXCLK to Pulse Position 6
-0.26
1.50
3.26
5.03
6.80
8.56
10.32
0
1.76
3.53
5.29
7.06
8.82
10.58
0.26
2.02
3.79
5.55
7.32
9.08
10.84
ns
ns
ns
ns
ns
ns
ns
(1) The analog inputs are protected as shown in Figure 1. Input voltage magnitudes beyond the supply rails will not damage the device,
provided the current is limited per Note 4 under the Absolute Maximum Ratings table. However, input errors will be generated If the
input goes above VA and below AGND.
(2) Test limits are ensured to TI's AOQL (Average Outgoing Quality Level).
(3) Typical figures are at TA = 25°C, and represent most likely parametric norms at the time of product characterization. The typical
specifications are not ensured.
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AC Timing Requirements (continued)
The following specifications apply for VA = VD = VC = 3.3 V, CL = 10 pF, and fINCLK = 15 MHz unless otherwise specified. All
other limits TA = 25°C.(1)
PARAMETER
TEST CONDITIONS
MIN(2)
TYP(3)
MAX(2) UNIT
CMOS OUTPUT TIMING SPECIFICATIONS
fINCLK = 40MHz
CLKOUT Rising Edge to CMOS Output Data
Transition
tCRDO
INCLK = ADCCLK
(ADC Rate Clock)
2
4.5
9
ns
SERIAL INTERFACE TIMING SPECIFICATIONS
fSCLK <= fINCLK
INCLK = PIXCLK
(Pixel Rate Clock)
Mode 3/2/1
15/22.5/22.5 MHz
45/45/22.5 MHz
fSCLK
Input Clock Frequency
fSCLK <= fINCLK
INCLK = ADCCLK
(ADC Rate Clock)
Mode 3/2/1
SCLK Duty Cycle
50/50
ns
ns
tIH
Input Hold Time
1.5
2.5
1.5
2.5
6
tIS
Input Setup Time
ns
tSENSC
tSCSEN
SCLK Start Time After SEN Low
SEN High after last SCLK Rising Edge
ns
ns
INCLK present(4)(5)
INCLK stopped(4)(5)
TINCLK
ns
tSENW
SEN Pulse Width
50
tOD
tHZ
Output Delay Time
11
14
ns
Data Output to High Z
0.5 TSCLK
(4) If the input INCLK is divided down to a lower internal clock rate via the PLL, the parameter tSENW will be increased by the same factor.
(5) When the Spread Spectrum Clock Generation feature is enabled, tSENW should be increased by 1.
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7 Detailed Description
7.1 Overview
The LM98722 is a 16-bit, three-input, complete Analog Front End (AFE) for digital color copier and Multi-Function
Peripheral (MFP) applications. The system block diagram of the LM98722, shown in LM98722 Overall Chip
Block Diagram highlights the main features of the device. Each input has its own Input Bias and Clamping
Network which are routed through a selectable Sample/Hold (S/H) or Correlated Double Sampler (CDS)
amplifier. A +/-9-Bit Offset DAC applies independent offset correction for each channel. A -3 to 17.9dB
Programmable Gain Amplifier (PGA) applies independent gain correction for each channel. The LM98722 also
provides independent Digital Black Level Correction Feedback Loops for each channel. The Black Level
Correction Loop can be configured to run in Manual Mode (where the user inputs their own values of DAC offset)
or in Automatic Mode where the LM98722 calculates each channel’s Offset DAC value during optical black pixels
and then adjusts the Offset register accordingly. The signals are routed to a single high performance 16-bit, 45-
MHz analog-to-digital converter.
The analog inputs are protected as shown in Figure 1. Input voltage magnitude up to 500 mV beyond the supply
rails will not damage this device. However, input errors will be generated if the input goes above VA and below
AGND.
VA
I/O
To Internal Circuitry
AGND
Figure 1.
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7.2 Functional Block Diagrams
7.2.1 LM98722 Overall Chip Block Diagram
SH5
SH4
SH3
SH1
RS
CP
PHIC2
PHIC1
PHIB2
PHIB1
PHIA2
PHIA1
SH_R
VREFT
VREFB
VCLP
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Functional Block Diagrams (continued)
7.2.2 System Block Diagram
CCD/CIS Sensor
Analog Front End
SPI
Image Processor/
ASIC
LM98722
Data Output
CLK
CCD Timing
Generator
Sensor Drivers
Motor
Controllers
SSCG
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7.3 Feature Description
7.3.1 Modes of Operation Introduction
The LM98722 can be configured to operate in several different operating modes. The following sections are a
brief introduction to these modes of operation. A more rigorous explanation of the operating modes is contained
in Device Functional Modes, including input sampling diagrams for each mode as well as a description of the
operating conditions.
7.3.2 Mode 3 - Three Channel Input/Synchronous Pixel Sampling
OSB, OSG, and OSR inputs are sampled synchronously at a pixel rate. The sampled signals are processed with
each channel’s offset and gain adjusted independently via the control registers. The order in which pixels are
processed from the input to the ADC is fully programmable and is synchronized by the SH pulse. In this mode,
the maximum channel speed is 15MSPS per channel with the ADC running at 45MSPS yielding a three color
throughput of 45MSPS.
7.3.3 Mode 2 - Two Channel Input/Synchronous Pixel Sampling
Mode 2 is useful for CCD sensors with a Black and White mode with Even and Odd outputs. In its default
configuration, Mode 2 samples the Even output via the OSB channel input, and the Odd output via the OSG
channel input. Sampling of the Even and Odd pixels is performed synchronously at a maximum sample rate of
22.5MSPS per input with the ADC running at 45MSPS
7.3.4 Mode 1 - One Channel Input
In Mode 1, all pixels are processed through a single input (OSR, OSG, or OSB) chosen through the control
register setup. This mode is useful in applications where only one input channel is used. The selected input is
programmable through the control register.
7.3.5 CIS Lamp and Coefficient Modes
In additional to Modes 3, 2, and 1 above, two different CIS sensor modes (CISa and CISb) can be enabled.
These allow color sequential lamp control, as well as synchronized color sequential gain/offset coefficient usage
for multi-output color sequential sensors.
7.3.6 Clock Sources
7.3.6.1 User Provided Clock Signal
When XTALEN = 0 (Page 0, Register 0, Bit 2) the clock input to the LM98722 can be a differential LVDS clock
on the INCLK+ and INCLK- pins or a CMOS level clock applied to the INCLK+ pin with the INCLK- pin connected
to DGND. The external clock signal format is auto sensed internally.
7.3.6.2 Crystal Oscillator Driver On-Chip
When XTALEN = 1 (Page 0, Register 0, Bit 2), an on-chip crystal oscillator driver circuit can be paired with an
external crystal. Terminal 2 of the crystal should connect to INCLK+ and terminal 1 of the crystal should connect
to INCLK-. 18 pF capacitors should connect from each terminal of the crystal to ground.
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Feature Description (continued)
7.3.6.3 Clock Multiplication - Basic
For any of the available clock sources, the input clock can be applied at the Pixel frequency (PIXCLK) or at the
ADC frequency (ADCCLK). The LM98722 can perform internal clock multiplication when a Pixel frequency clock
is applied, or no multiplication when an ADC frequency clock is applied. The internal configuration registers need
to be written to perform the proper setup of the input clock. The available input clock configurations for each
operating mode is outlined in Table 1.
Table 1. Input Clock Configurations for Operating Modes
INTERNAL
MULTIPLIER
CONFIGURATION REGISTER
SETTINGS
AFE MODE
INPUT CLOCK TYPE
INCLK MAX FREQ.
INCLK = Pixel Freq. (PIXCLK)
INCLK = ADC Freq. (ADCCLK)
INCLK = Pixel Freq. (PIXCLK)
INCLK = ADC Freq. (ADCCLK)
INCLK = Pixel Freq. = ADC Freq
(ADCCLK = PIXCLK in Mode 1)
3x
1x
2x
1x
15 MHz
45 MHz
22.5 MHz
45 MHz
TBD
TBD
TBD
TBD
Mode 3
Mode 2
Mode 1
1x
22.5 MHz
TBD
7.3.6.4 Clock Multiplication - Flexible
There are a variety of situations where it is desirable to multiply the base frequency by a selected amount to
achieve the proper pixel frequency for a given application and set of system conditions.
•
•
Applications using the onchip Crystal Oscillator driver will have much more flexibility of pixel frequencies.
Reducing the input MCLK frequency can significantly reduce the EMI generated by the MCLK signals being
sent up the cable from the host board to the imaging board.
To ease this task a flexible multiplying PLL architecture is incorporated. When the 2 PLL architecture is enabled
(Page 2, Register 0x1Bh, Bit 1=0) the source clock frequency is multiplied by the ratio M/N. Two registers are
used to set these values:
•
•
•
•
•
•
M = Value(Page 2, Register 0x1Ch) + 1
N = Value(Page 2, Register 0x1Dh) + 1
N(max) = 64
M/N(max) = 64
M/N(min) = 1/64
Note: Since the 8 bit register values can be from 0 to 255, the resulting Numerator and Denominator values
could be from 1 to 256. However, the maximum recommended multiply or divide ratios are 64x or x/64. In
addition, the maximum recommended value for N is 64.
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Clock
Receiver
INCLK+
Fin
Fout
SSCG LVDS Only, 2
PLL Mode
PLL1
Fout = Fin x (M/N)
Crystal or
INCLK from Host
Crystal
Oscillator
Driver
Clock to CCDTG
and AFE
M
U
X
INCLK-
Spread All, 1 PLL Mode
Data from AFE
SSCG
Enable
2 PLLs – Use M/N, Use M/N
and SSCG All, SSCG LVDS
Only
M
U
X
PLL2
SSCG modulation
21
1 PLL – No M/N and SSCG
All, No M/N and no SSCG
FIFO
21
M
U
X
Use FIFO
LVDS
Serializer
Clock/Data to Host
Bypass FIFO
Clock System Configuration Options
Source
INCLK
INCLK
INCLK
INCLK
INCLK
PLL (Dual/Single)
Single
Single
Spreading (On/Off)
ON
SpreadMode (LVDS/All)
ALL
N/A
OFF
ON
Dual (Use M/N)
Dual (Use M/N)
Dual (Use M/N)
LVDS*
ALL
N/A
ON
OFF
XTAL
XTAL
XTAL
XTAL
XTAL
Single
Single
ON
ALL
N/A
OFF
ON
Dual (Use M/N)
Dual (Use M/N)
Dual (Use M/N)
LVDS*
ALL
N/A
ON
OFF
*If SpreadMode is LVDS, then FIFO is used to move data from CCDTG/AFE clock domain to LVDS clock domain.
Figure 2. Clock System Block Diagram
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7.3.7 Clock Sources - Additional Settings and Flexibility
To support the new crystal oscillator feature, some additional flexibility was added. In Crystal Oscillator mode, the
master clock source is now on the AFE (rather than in the system ASIC or main processor). If Slave Timing
Mode (see Device Functional Modes) is still needed (to synchronize the AFE to the line timing of the system), the
external SH_R signal must now be captured with the internal clock source. The SH_R Capture Clock Select bit
has been added to support this case.
In addition, in these systems, it may be difficult to adjust the host SH_R timing to get the best Setup and Hold
times with respect to the internal CLK. The SH_R, INCLK Monitor Override and SH_R Capture Edge Select
controls have been added to support these needs. The INCLK Monitor Override allows the internal SH_R and
CLK signals to be monitored, to aid in selected the best edge (rising or falling) of CLK to latch the SH_R signal.
•
•
•
SH_R Capture Clock Select (Page 0, Register 0x00, Bit 5)
–
–
0 - Use internal INCLK source to latch SH_R
1 - Use external CLK source to latch SH_R
SH_R Capture Edge Select (Page 0, Register 0x00, Bit 4)
–
–
0 - Use rising edge of selected clock source
1 - Use falling edge of selected clock source
SH_R and INCLK Monitor Override (Page 0, Register 0x14, Bit 6)
–
–
0 - Timing monitor selections unaltered
1 - Timing monitors for CLAMPB and SAMPB are replaced with monitor of SH_R_Internal and SH_R
Capture_Clock_Internal.
7.3.8 Spread Spectrum Clock Generation (SSCG)
NOTE
When using SSCG, ensure that INCLK = ADCCLK is selected at Page 0, Register
0x02, Bit 2 = 0. Then set the flexible clock multiplication PLL settings to achieve the
desired internal clock frequency from the applied clock.
EMI is a problem faced by any system designer. In a typical imaging system, data must be sent over a relatively
long cable to the main system board. To minimize the amount of measured EMI caused by system clocking and
data transmission, a flexible Spread Spectrum Clock Generation system is included in the LM98722.
The spread spectrum feature is configured by the registers at Page 2, Registers 0x1Ah, 0x1Bh and 0x1Eh.
The following key SSCG modes of operation and features are provided:
•
Spread output data/clock only (Internal FIFO used to transfer data between clock domains) or spread internal
system clock as well as output data/clock
•
•
•
•
•
•
Spread synchronized to CCD line length (SH period or frequency) or unsychronized.
Spread widths of 0.625, 1.25, 2.5 and 5% selectable
Spread gain of 1x to 2x can double the selected spread widths
3 selectable modulation frequency multipliers to increase the spreading modulation frequency
Spread “boost” provides a cleaner spread for 1 channel and 2 channel modes of AFE operation
Spread MaxRate allows the most effective spreading modulation for Output Only spreading. When this bit is
set, the spreading waveform is NOT synchronized to the CCD line timing.
•
•
Spreading modulation waveform and FIFO reset by SH_R event. (Page 8, Register 0x1Eh, Bit 7) This
ensures that the spread- ing waveform is synchronized to the CCD line timing, even if SH_R to SH_R period
is varied by system ASIC.
Spreading SH_R Reset can be delayed from SH_R event by a “Holldoff” amount. (Page 8, Register 0x1Eh,
Bits6:0)
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7.3.9 Typical EMI Cases and Recommended SSCG Settings
Case 1: Majority of EMI coming from LVDS outputs
Usage: Spread output data/clock only. FIFO used to move data between non-spread and spread clock domains.
If Slave Mode is also used, ensure that the Line Length and Line Length Multiplier settings correspond to the
SH_R period. If the SH_R period may vary, then set FIFO Reset (Page 2, Register 0x1Bh, Bit 6 =1) to ensure
the FIFO counters are reset every SH Interval.
Case 2: EMI from LVDS outputs and CCD timing signals - Master Mode Application
Usage: Spread internal system clock as well as output data/clock. Synchronize spread waveform to SH Interval.
Best to use Master mode timing to ensure spread waveform is always smoothly synchronized to the SH Interval
timing.
Case 3: EMI from LVDS outputs and CCD timing signals - Slave Mode Application
Usage: Spread internal system clock as well as output data/clock. Use minimal amount of spreading to reduce
CCD timing emissions, in combination with data scrambling to further reduce data cable emissions. The small
amount of spreading minimizes effects on image data, therefore, spreading is not required to be synchronized
with SH Intervals.
7.3.10 Recommended Master/Slave, Clock Source and SSCG Combinations and Settings
7.3.10.1 Master Mode Operation (LM98722 Controls Line Timing)
(These are easiest cases to implement SSCG)
Clock From Host Board
1. Use SSCG - Spread All
2. Use SSCG - Spread LVDS Only
3. No SSCG
Clock From Local Crystal
1. Use SSCG - Spread All
2. Use SSCG - Spread LVDS Only
3. No SSCG
7.3.10.2 Slave Mode Operation (Host FPGA or ASIC Controls Line Timing)
(These SSCG cases are more challenging as received LVDS data timing will not be synchronous with the clock
of the FPGA/ASIC. Clock from host board. If a local clock is present on the FPGA/ASIC, an internal FIFO must
be implemented to transfer the received data from the spread LVDS clock domain, to the internal FPGA/ASIC
clock domain. If the AFE LVDS clock is used as the system clock, care must be taken to ensure that settings are
not loaded which disable this clock, and therefore lock up the system.)
1. Use SSCG - Spread All - Need spreading start to be SH gated, and SH period to be consistent to ensure
consistent capture of SH_R by the spread INCLK.
2. Use SSCG - Spread LVDS Only - In this case ensure that Line Length Register is set to same number of
pixels as that or SH_R period. In addition, if SH_R period will vary, set FIFO Reset (Page 2, Register 0x1Bh,
Bit 6 = 1) to reset FIFO at SH Interval.
3. No SSCG
Clock from local crystal (Not recommended, difficult to meet CLK to SH_R setup and hold times. Use Master
Mode instead)
1. Use SSCG - Spread All
2. Use SSCG - Spread LVDS Only
3. No SSCG
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7.3.10.3 SSCG Configuration/Usage Flow
•
•
•
•
•
•
Unlock Registers (Page 0, Register 0, Bit 0 = 0)
Ensure PIXCLK/ADCCLK Configuration is set to ADCCLK. Page 0, Register 0x02, Bit 2 = 0.
Set Override PLL2 Lock Detector (Page 2, Register 0x1B, Bit 4) = 1
Set PLL2 Charge Pump Current Control (Page 2, Register 0x19, Bits 4:3) = 00
Set PLL2 Filter Bandwidth Control (Page 2, Register 0x19, Bits 2:0) = 111
Set SSCG Spread Boost (Page 2, Register 0x1A, Bit 5) = 0 or 1 (0 = default, recommended for most
applications)
•
•
Set SSCG Spread Gain (Page 2, Register 0x1A, Bit 4) = 0 or 1 (0 = default, recommended for most
applications)
Set SSCG Spread Width (Page 2, Register 0x1A, Bits 3:2) = 0.625% to 2.5% (Beyond 2.5% most LVDS
deserializers will not track the clock properly)
•
•
Set SSCG SH Sync Enable (Page 2, Register 0x1A, Bit 1) = 0 or 1 (Set to 1 for Spread All)
Set PLL Mode Select (Page 2, Register 0x1B, Bits 1:0) = 00, 01 or 11. Spread Output Only or Spread All
Clocks
•
If PLL Clock Multiplication Enabled, Set Clock Mult M (Page 2, Register 0x1C) and N (Page 2, Register 0x1D)
to desired values. If a pixel rate clock is applied, set the PLL multiplication to the same factor as the AFE
Mode selected at Page 0, Register 0x03, Bits 7:6. ie. The multiplication factor should be 3x for Mode 3, 2x for
Mode 2 and 1x for Mode 1.
•
•
•
Set SSCG Enable (Page 2, Register 0x1A, Bit 0) = 1 (enable spreading, load spreading state machines)
Lock Registers (Page 0, Register 0, Bit 0 = 1)
If spreading is synchronized to SH interval, the spreading function will wait until the next SH Interval before
beginning.
7.3.10.4 Changing SSCG Settings
To change SSCG settings:
•
•
•
•
•
Un-Lock Registers ((Page 0, Register 0, Bit 0 = 0)
Set SSCG Enable = 0 (disable spreading)
Change desired SSCG settings.
Set SSCG Enable = 1 (enable spreading, reload spreading state machines)
Lock Registers (Page 0, Register 0, Bit 0 = 1)
Table 2. SSCG and Clock Multiplication Register Settings
PAGE
REGISTER
DEFAULT
BITS
NAME
DESCRIPTION
Master PLL Range Setting for PLL1 and
PLL2 when
2
24
18
1111 1000
[7:5]
Autorange is off. Set to 111.
[4:3]
PLL1 Charge Pump Current Control
Default = 11
PLL Control 1
[2:0]
[7:5]
PLL1 Filter Bandwidth Control
Default = 000
2
25
19
0001 1000
Reserved
Default = 000
[4:3]
[2:0]
PLL2 Charge Pump Current Control
Default = 11
PLL Control 2
Set to 00 when using SSCG.
PLL2 Filter Bandwidth Control
Default = 000
Set to 111 when using SSCG.
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Table 2. SSCG and Clock Multiplication Register Settings (continued)
PAGE
REGISTER
DEFAULT
BITS
NAME
DESCRIPTION
Spread Rate Multiplier
2
26
1A
0000 0000
[7:6]
(Increases modulation frequency in low
pixel frequency applications)
00 1x - Default
01 2x
10 4x
11 Reserved
[5]
SSCG Spread Boost
0 Normal, PLL divide step is 1/28
1 Boost, PLL divide step is 1/56.
Narrower and cleaner spread for 1ch
and 2ch modes, but limits max pixel freq
to 25 MHz.
[4]
SSCG Spread Gain
0 Spread widths as specified in [3:2]
1 Spread widths are 2x [3:2] settings
SSCG Control 1
SSCG Spread Width (Fmod =
Fcenter+/- Width/2)
[3:2]
00 5%
01 2.5%
10 1.25%
11 0.625%
[1]
[0]
SSCG SH Sync Enable
0 Spread unsynched, once SSCG
Enable and Register Lock Control are
set, SSCG will begin immediately.
1 Spread synched to SH interval, once
SSCG Enable is set, the SSCG will
begin at the first SH Interval.
SSCG Enable
0 Spread off
1 Spread on
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Table 2. SSCG and Clock Multiplication Register Settings (continued)
PAGE
REGISTER
DEFAULT
BITS
NAME
DESCRIPTION
2
27
1B
0000 0010
[7]
Load SSCG state machine
(SSCG Enable 0->1 also performs this
function)
0 Normal
1 Load state machine (self clearing)
[6]
FIFO Reset at SH_R
0 FIFO is only reset when SSCG started
1 FIFO is reset at SH_R. Only useful in
Slave Mode with Spread LVDS Only set.
Ensures that FIFO counters are
centered if SH_R period is consistenly
shorter or longer than Line Length
settings.
[5]
[4]
Spread Waveform Reset at SH_R
0 Spread waveform not reset by SH_R
1 Spread waveform reset by SH_R
Override PLL2 Lock Detector
0 PLL2 Lock Detector Normal
1 Force PLL2 Lock Detect = 1. Set to 1
when using SSCG.
SSCG Control 2
[3]
Override PLL1 Lock Detector
0 PLL1 Lock Detector Normal
1 Force PLL1 Lock Detect = 1. Useful
only if using a large multiplication factor
and a lot of jitter is present in the source
clock.
[2]
Spread MaxRate
0 Spread Normal
1 Force Spreading to highest modulation
frequency instead of tied to Line Length
Setting.
[1:0]
PLL Mode Select
11 Spread All System Clocks, No
Multiplication
10 PLLs and SSCG Disabled - Default
01 Spread All System Clocks,
Multiplication Enabled
00 Spread Output Clocks Only,
Mutiplication Enabled
Multiplying PLL. Fout = Fin x M/N M =
mmmmmmmm + 1 (1 to 256)
2
2
28
29
1C
1D
0000 0000
0000 0000
Clock Mult M
Clock Mult N
Multiplying PLL. Fout = Fin x M/N N =
nnnnnnnn + 1 (1 to 256)
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Table 2. SSCG and Clock Multiplication Register Settings (continued)
PAGE
REGISTER
DEFAULT
BITS
NAME
DESCRIPTION
2
30
1E
0000 0000
[7]
FIFO Reset
0 FIFO normal operating
1 Force reset of FIFO (self clearing)
FIFO and Spread Waveform SH_R
Reset Holdoff
[6:0]
SSCG Control 3
Delay reset of FIFO and Spread
Waveform from 0 to
127 ADC clock cycles after the internal
synchronized SH_R. To allow this event
to occur during SH Interval after all valid
pixels in the pipeline have been pro-
cessed.
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7.4 Device Functional Modes
7.4.1 Mode 3 - Three Channel Input/Synchronous Pixel Sampling
In Mode 3, the OSR, OSG, and OSB input channels are sampled synchronously. The sampled input signals are
then processed in parallel through their respective channels with each channel offset and gain adjusted by their
respective control registers. The signals are then routed through a 3-1 MUX to the ADC. The order in which
pixels are processed through the MUX to the ADC is programmable (OSR-OSG-OSB, or OSB-OSG-OSR) and is
synchronized by the SH pulse.
Black
Level
COLOR1DAC[9:0]
COLOR1PGA[7:0]
Offset
DAC
CDS
or
Input Bias/
Clamping
OSR
OSG
OSB
PGA
PGA
PGA
Sample/Hold
Amplifier
Black
COLOR2PGA[7:0]
Level
Offset
DAC
COLOR2DAC[9:0]
CDS
or
Input Bias/
Clamping
3:1
MUX
Sample/Hold
Amplifier
Black
COLOR3PGA[7:0]
Level
Offset
DAC
COLOR3DAC[9:0]
CDS
or
Input Bias/
Clamping
Sample/Hold
Amplifier
Figure 3. Synchronous Three Channel Pixel Mode Signal Routing
Table 3. Mode 3 Operating Details
DETAIL
OSB & OSG & OSR
15
3 channel synchronous pixel
sampling.
Channels Active
Channel Sample Rate
ADC Sample Rate
MSPS per Channel (max)
MSPS (max)
45
3:1
1:1
Internal 3x Clock Selected
Internal 1x Clock Selected
fINCLK = 25 MHz (max)
fINCLK = 75 MHz (max)
fADC: fINCLK
SH Signal --> R-G-B-R-G-B-R-G-B→
Output Sequencing
or
SH Signal --> B-G-R-B-G-R-B-G-R→
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7.4.2 Mode 2 - Two Channel Input/Synchronous Pixel Sampling
Mode 2 is useful for CCD sensors with a Black and White line with Even and Odd pixels. In its default
configuration, Mode 2 samples Even sensor pixels via the Blue Channel Input, and Odd sensor pixels via the
Green Channel Input. The selection of Even/Odd inputs can be changed through the serial interface registers.
Sampling of the Even and Odd inputs is performed synchronously.
Black
Level
COLOR1DAC[9:0]
COLOR1PGA[7:0]
Offset
DAC
CDS
or
Input Bias/
Clamping
OSR
OSG
OSB
PGA
PGA
PGA
Sample/Hold
Amplifier
Black
COLOR2PGA[7:0]
Level
Offset
DAC
COLOR2DAC[9:0]
CDS
or
Input Bias/
Clamping
3:1
MUX
Sample/Hold
Amplifier
Black
COLOR3PGA[7:0]
Level
Offset
DAC
COLOR3DAC[9:0]
CDS
or
Input Bias/
Clamping
Sample/Hold
Amplifier
Figure 4. Mode 2 Signal Routing
Table 4. Mode 2 Operating Details
DETAIL
OSG and OSB (Default)
Two inputs synchronously
processed as Even and Odd
Pixels. Channel inputs are
configurable.
or
OSR and OSG
or
Channels Active
OSB and OSR
22.5
Channel Sample Rate
ADC Sample Rate
MSPS per Channel (max)
MSPS (max)
45
2:1
1:1
Internal 2x Clock Selected
Internal 1x Clock Selected
fINCLK = 15 MHz (max)
fINCLK = 45 MHz (max)
fADC: fINCLK
SH Signal --> Even-Odd-Even-Odd-Even-Odd-Even→
Output Sequencing
or
SH Signal --> Odd-Even-Odd-Even-Odd-Even-Odd→
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7.4.3 Mode 1 - One Channel Input
In Mode 1a, all pixels are processed through a single input (OSR, OSG, or OSB) chosen through the control
register setup. This mode is useful in applications where only one input channel is used. The selected input is
programmable through the control register. In this mode, the maximum channel speed is 22.5MSPS per channel
with the ADC running at 22.5MSPS.
Black
Level
COLOR1DAC[9:0]
COLOR1PGA[7:0]
Offset
DAC
CDS
or
Input Bias/
Clamping
OSR
OSG
OSB
PGA
PGA
PGA
Sample/Hold
Amplifier
Black
COLOR2PGA[7:0]
Level
Offset
DAC
COLOR2DAC[9:0]
CDS
or
Input Bias/
Clamping
3:1
MUX
Sample/Hold
Amplifier
Black
COLOR3PGA[7:0]
Level
Offset
DAC
COLOR3DAC[9:0]
CDS
or
Input Bias/
Clamping
Sample/Hold
Amplifier
Figure 5. Mode 1a Signal Routing
Table 5. Mode 1 Operating Details
DETAIL
Channels Active
Channel Sample Rate
ADC Sample Rate
fADC: fINCLK
OSR or OSG or OSB
22.5
One color active for all lines.
MSPS per Channel (max)
MSPS (max)
22.5
1:1
Internal 1x Clock Selected
fINCLK = 25MHz (max)
Output Sequencing
SH Signal → Color 1→Color 1→Color 1→Color 1→Color 1→
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Table 6. Modes of Operation Register Settings Table
OPERATING
MODE
SAMPLING
INPUT(S)
SIGNAL
PATH(S)
OUTPUT SEQUENCING MODE 3 and 2 = PIXEL SEQ
PixelR→PixelG→PixelB→
Mode3-RGB
Forward
RGB
OSR||OSG||OSB
OSR||OSG||OSB
Mode3-RGB
Reverse
RGB
PixelB→PixelG→PixelR→
Mode2-RG Forw.
Mode2-RG Rev.
OSR||OSG
OSR||OSG
RG
RG
PixelR→PixelG→
PixelG→PixelR→
Mode2-GB Forw.
Mode2-GB Rev.
OSG||OSB
OSG||OSB
GB
GB
PixelG→PixelB→
PixelB→PixelG→
Mode2-RB Forw.
Mode2-RB Rev.
OSR||OSB
OSR||OSB
RB
RB
PixelR→PixelB→
PixelB→PixelR
Mode1-R Mono
Mode1-G Mono
Mode1-B Mono
CISa
OSR
OSG
R
G
Color Line Seq: R→R→R→R→
Color Line Seq: G→G→G→G→
Color Line Seq: B→B→B→B→
OSB
B
Mode 1 or 2 or 3
Any
2, 3, or 4 lines in sequence
Gain and Offset are channel specific.
LM98714 style CB bits indicate channel used to process data. Additional CB
bits can be used to identify current line in sequence.
CISb
Mode 1 or 2 or 3
Any
2 or 3 lines in sequence
Gain and Offset for all channels are common, and change from line to line
based on current color in sequence.
LM98714 style CB bits indicate channel used to process data. Additional CB
bits can be used to identify current line in sequence.
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7.4.4 Input Bias and Clamping
VA
Input Bias Enable
Configuration 3, Bit[6]
VBIAS
SAMPLE
20kΩ
OSR or
OSG or
OSB
Source Follower Enable
Configuration 3, Bit[7]
CS
20kΩ
Auto CLPIN Enable
Configuration 4, Bit[5]
SAMPLE
CLPIN
AGND
HOLD
VA
CLPIN Gating Enable
Configuration 4, Bit[4]
VBIAS
CLAMP
VCLP
CS
VCLP Reference Select
Configuration 4, Bits[3:0]
VCLP
Sampling Mode Select
(CDS or Sample/Hold Mode)
Configuration 2, Bit[1]
Pixel rate switches to sample OS signal and reference voltages.
Optional line rate switch to clamp OS input to VCLP node.
Static switches controlled by Configuration Registers
SAMPLE, CLAMP, HOLD, CLPIN are internally generated timing signals.
Figure 6. Input Bias and Clamping Diagram
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7.4.4.1 Input Bias and Clamping - AC Coupled Applications
The inputs to the LM98722 are typically AC coupled through a film capacitor and can be sampled in either
Sample and Hold Mode (S/ H Mode) or Correlated Double Sampling Mode (CDS Mode). In either mode, the DC
bias point for the LM98722 side of the AC coupling capacitor is set using the circuit of Figure 6 which can be
configured to operate in a variety of different modes. A typical CCD waveform is shown in Figure 7. Also shown
in Figure 7 is an internal signal “SAMPLE” which can be used to “gate” the CLPIN signal so that it only occurs
during the “signal” portion of the CCD pixel waveform.
SH
Invalid
Pixels
Dummy Pixels
Optical Black Pixels
Valid Pixels
OSX
Auto CLPIN Start Register
Page 2, Reg. 6, Bits[7:0]
Auto CLPIN End Register
Page 2, Reg. 7, Bits[7:0]
CLPIN
SAMPLE
CLPINGATED
Figure 7. Typical CCD Waveform and LM98722 Input Clamp Signal (CLPIN)
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7.4.5 Sample/Hold Mode
SAMPLE
OSR or
OSG or
OSB
CS
CPAR
HOLD
CLAMP
VCLP
CS
CPAR
Figure 8. Sample and Hold Mode Simplified Input Diagram
Proper DC biasing of the CCD waveform in Sample and Hold mode is critical for realizing optimal operating
conditions. In Sample/ Hold mode, the Signal Level of the CCD waveform is compared to the DC voltage on the
VCLP pin. In order to fully utilize the range of the input circuitry, it is desirable to cause the Black Level signal
voltage to be as close to the VCLP voltage as possible, resulting in a near zero scale output for Black Level
pixels.
In Sample/Hold Mode, the DC bias point of the input pin is typically set by actuating the input clamp switch (see
Figure 8) during optical black pixels which connects the input pins to the VCLP pin DC voltage. The signal
controlling this switch is an auto-generated pulse, CLPIN. CLPIN is generated with a programmable pixel delay
with respect to the SH Interval and a programmable # of pixels Duration. These parameters are available through
the serial interface control registers.
Actuating the input clamp will force the average value of the CCD waveform to be centered around the VCLP DC
voltage. During Optical Black Pixels, the CCD output has roughly three components. The first component of the
pixel is a “Reset Noise” peak followed by the Reset (or Pedestal) Level voltage, then finally the Black Level
voltage signal. Taking the average of these signal components will result in a final “clamped” DC bias point that
is close to the Black Level signal voltage.
To provide a more precise DC bias point (that is, a voltage closer to the Black Level voltage), the CLPIN pulse
can be “gated” by the internally generated SAMPLE clock. This resulting CLPINGATED signal is the logical
“AND” of the SAMPLE and CLPIN signals as shown in Figure 7. By using the CLPINGATED signal, the higher
Reset Noise peak will not be included in the clamping period and only the average of the Reset Level and Black
Level components of the CCD waveform will be centered around VCLP.
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7.4.6 DC Coupled Applications
In some applications, particularly with CIS sensors, the output voltage is within a voltage range that will allow DC
coupling of the signal. When using Sample/Hold mode, DC coupling eliminates any problems with signal droop
across the line caused by voltage changes across the coupling capacitor. When DC coupling, the Auto CLPIN
should be disabled.
There are two ways of setting the proper DC levels in this type of application. If the sensor has a Vref output pin,
this can be connected to the VCLP pin of the LM98722. The internal VCLP generation should be disabled to
allow this external reference to set the Black Level for the chip close to the black pixel level of the sensor.
Many CIS sensors will not have a Vref output. In these applications, the internal VCLP voltage of the LM98722
can be set to the level that is closest to the black pixel level of the sensor.
OSR or
OSG or
OSB
fPIXEL
CSH
VCLP
Figure 9. Equivalent Input Switched Capacitance S/H Mode
In Sample and Hold Mode, the impedance of the analog input pins is dominated by the switched capacitance of
the CDS/Sample and Hold amplifier. The amplifier switched capacitance, shown as CS in Figure 8, and internal
parasitic capacitances can be estimated by a single capacitor switched between the analog input and the VCLP
reference pin for Sample and Hold mode. During each pixel cycle, the modeled capacitor, CSH, is charged to the
OSX-VCLP voltage then discharged. The average input current at the OSX pin can be calculated knowing the
input signal amplitude and the frequency of the pixel. If the application requires AC coupling of the CCD output to
the LM98722 analog inputs, the Sample and Hold Mode input bias current may degrade the DC bias point of the
coupling capacitor. To overcome this, Input Source Follower Buffers are available to isolate the larger Sample
and Hold Mode input bias currents from the analog input pin (as discussed in Input Source Follower Buffers). As
shown in CDS Mode section, the input bias current is much lower for CDS mode, eliminating the need for the
source follower buffers.
7.4.7 Input Source Follower Buffers
The OSR, OSG, OSB inputs each have an optional Source Follower Buffer which can be selected with Main
Configuration Register 3 at Page 0, Register 3, Bit[7]. These source followers provide a much higher impedance
seen at the inputs. In some configurations, such as Sample and Hold Mode with AC coupled inputs, the DC bias
point of the input nodes must remain as constant as possible over the entire length of the line to ensure a
uniform comparison to reference level (VCLP in this case). The Source Followers effectively isolate the AC input
coupling capacitor from the switched capacitor network internal to the LM98722’s Sample and Hold/ CDS
Amplifier. This results in a greatly reduced charge loss or gain on the AC Input coupling capacitor over the length
of a line, thereby preserving its DC bias point.
The Source Followers should only be used in the 1.2 V input range (i.e. Gain Mode Register at Page 1, Register
0, Bit[0] = 1, CDS Gain = 2x). Using the Source Followers in the 2.4 V (that is, Gain Mode Register at Page 1,
Register 0, Bit[0] = 0, CDS Gain = 1x). Input range will result in a loss of performance (mainly linearity
performance at the high and low ends of the input range).
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7.4.8 CDS Mode
SAMPLE
OSR or
OSG or
OSB
CS
CPAR
HOLD
CLAMP
CS
CPAR
Figure 10. CDS Mode Simplified Input Diagram
Correlated Double Sampling mode does not require as precise a DC bias point as does Sample and Hold mode.
This is due mainly to the nature of CDS itself, that is, the Video Signal voltage is referenced to the Reset Level
voltage instead of the static DC VCLP voltage. The common mode voltage of these two points on the CCD
waveform have little bearing on the resulting differential result. However, the DC bias point does need to be
established to ensure the CCD waveform’s common mode voltage is within rated operating ranges.
The CDS mode biasing can be performed in the same way as described in Sample/Hold Mode, or, an alternative
method is available which precludes the need for a CLPIN pulse. Internal resistor dividers can be switched in
across the OSR, OSG, and/or OSB inputs to provide the DC bias voltage.
SAMPLE
IBIAS
OSR or
OSG or
OSB
CS
CPAR
HOLD
CLAMP
CS
CPAR
Figure 11. CDS Mode Input Bias Current
Unlike in Sample and Hold Mode, the input bias current in CDS Mode is relatively small. Due to the architecture
of CDS switching, the average charge loss or gain on the input node is ideally zero over the duration of a pixel.
This results in a much lower input bias current, whose main source is parasitic impedances and leakage
currents.
As a result of the lower input bias current in CDS Mode, maintaining the DC Bias point the input node over the
length of a line will require a much smaller AC input coupling capacitor.
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7.4.9 VCLP DAC
The VCLP pin provides the reference level for incoming signals in Sample and Hold Mode. The pin’s voltage can
be set by writing to the VCLP Configuration Register on register page 0. By default, the VCLP pin voltage is
established by an internal resistor divider which sets the voltage to 0.85 VA.
The VCLP buffer can also be disconnected and the pin driven externally by the another voltage in the
application, such as Vref from some CIS sensors.
Table 7. VCLP Voltage Setting
VCLP CONFIGURATION PAGE 0,
REGISTER 0x04, BITS[2:0]
TYPICAL VCLP OUTPUT
(FINAL SILICON TARGETS)
000
001
010
011
100
101
110
111
0.85VA (Default)
0.9VA
0.95VA
0.6VA
0.55VA
0.4VA
0.35VA
0.15VA
7.4.10 Gain and Offset Correction
Each input channel has individual settings for offset (DAC) and gain (PGA and CDS/SH gain).
7.4.10.1 Analog Offset
Analog offset (DAC) settings are individually adjustable for each color. In addition, there are (optionally) separate
settings for Even and Odd pixels being processed through each color channel. This feature is designed to
support specific CCD sensors that have two CCD transfer arrays per color, which may introduce different offset
for the Even versus Odd pixels.
COLOR1PGA[7:0]
COLOR1EVENDAC[9:0]
COLOR1ODDDAC[9:0]
Black
Level
Offset
DAC
M
U
X
CDS
or
Input Bias/
Clamping
PGA
OS
R
Sample/Hold
Amplifier
Figure 12. Analog Offset Applied Prior to PGA
The Black Level Offset DACs are set with a 9 bit plus sign value. This gives an approximate adjustment range of
+/- 300 mV or +/- 600mV when the CDS/SH Gain is set to 1x or 2x.
The analog offset registers are found at Page 1, Registers 0x04h to 0x0Fh.
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7.4.10.2 Digital Offset
In addition, digital offset can be added to color data at the output of the ADC in the Digital Offset block. The
digital offsets are a +/- 6 bit value. This value is summed with the upper 11 bits of the ADC output. Therefore, the
effective offset range is from +2016 to -2048 lsbs of the ADC output.
The digital offset registers are found at Page 1, Registers 0x10h to 0x15h.
16 Bit ADC
16
Digital
Offset
Figure 13. Digital Offset Applied to ADC Output
7.4.10.3 Even/Odd Offset Coefficients
Certain CCD sensors may have different offset voltages for the Even versus the Odd pixels. To optimize the
image processing of these pixels, separate coefficients can be stored, and applied for the Even and Odd pixels.
The Even/Odd offset feature is enabled by setting Page 0, Register 0x02h, Bit 0 = 1. Bimodal correction,
discussed below, is automatically disabled when Even/Odd offset coefficients are enabled.
Color 1 Even Offset
Color 2 Even Offset
Color 3 Even Offset
Color 1 Odd Offset
Color 1 Odd Offset
Color 1 Odd Offset
Figure 14.
•
•
Analog Gain
The gain of each input channel can be adjusted at two points in the signal chain.
CDS/SH Gain - Page 1, Register 0x00h
–
–
–
A 1x or 2x gain setting is available in the CDS/SH amplifier.
By default, one common CDS/SH gain setting setting is used for all input channels. If desired, individual
CDS/SH gain settings can be used for each input. To enable this feature, set Page 1, Register 0x00h, Bit
2 = 1.
•
PGA Gain - Page 1, Registers 0x01h, 0x02h, 0x03h
–
An 8 bit PGA (Programmable Gain Amplifier) is also available. The PGA gain curve is non-linear for
optimal performance in imaging applications, and is shown on Figure 15. The approximate gain equation
is:
Gain (V/V) = 180/(277-PGA_Code), Gain (dB) = 20log10(180/(277-PGA_Code))
(1)
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The gain setting registers are found at Page 1, Registers 0x00h, 0x01h, 0x02h and 0x03h.
18
17
16
15
14
13
Gain (V/V) =
(180/(277-PGA Code))
12
11
10
9
Gain (dB) =
20LOG10(180/(277-PGA Code))
8
7
6
5
4
3
2
1
0
0
32
64
96
128
160
192
224
-1
-2
-3
-4
PGA Register Value
Overall Gain (dB) Overall Gain (V/V)
Figure 15. PGA Gain vs. PGA Gain Code
Dual Gain Mode - Page 1, Register 0x00h, Bit 1, and Registers 0x16h, 0x17h, 0x18h
•
–
In many scanning systems, the system illumination and optics characteristics will result in a much higher
optical efficiency in the pixels near the middle of the sensor, compared with the pixels at the beginning
and end of the sensor. If a single gain setting is used for all pixels, the middle pixels will be near clipping,
while the ones at the edges can be at 1/2 scale or lower. This results in lower signal to noise for the edge
pixels. To combat this problem, the LM98722 incorporates an optional Dual Gain system. When enabled,
the system provides a second set of PGA gain registers to set the “high” gain for each input channel. The
“normal” gain settings will be applied during the “active/white” pixels, while the “high” gain settings will be
applied for all pixels before and after the “active/white” pixels (see Figure 16).
–
The Dual Gain enable bit is found at Page 1, Register 0x00h, Bit 1. The High Gain PGA settings are found
at Page 1, Registers 0x16h to 0x18h.
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7.4.11 LM98722 Typical Line Timing and Pixel Gain Regions
Figure 16. Typical Line Timing and Pixel Gain Regions
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7.4.12 Automatic Black and White Level Calibration Loops
7.4.12.1 Calibration Overview
The offset and gain settings in the AFE will normally be set to optimize the range of the sensor output signal
within the ADC input range. These settings can be calculated in a host ASIC and loaded into the AFE during the
calibration procedure. To reduce the processing required to do these calculations, the LM98722 has built in
feedback or calibration loops that will automatically adjust the offset and gain settings. A number of register
values must be initially set to optimize the calibration for the particular application.
7.4.12.2 Different Modes for Different Needs
The calibration features of the LM98722 are not intended to be used during active scanning, but rather before
scanning begins, or in the page gap between images. Generally, more time is available to perform the initial
calibration before scanning begins. Page gap calibration must be necessariliy short to ensure the process
finishes in the limited number of scan lines available.
The Black and White Fine Tuning, and Black Calibration Only modes can be used during the page gap to adjust
for small differences in offset/gain that occur over time.
Black and White Full Calibration should be run before the initial scanning process, or periodically between major
jobs to take care of larger shifts in offset/gain of the input signal.
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7.4.12.3 Calibration Initiation
Once these settings have been made, the Register Lock Control bit (Page 0, Register 0, Bit 0) should be set to
begin converting pixels. Once the sensor data from the test image is stable the calibration process can be started
by either setting the CAL register bit at Page 0, Register 0x01h, Bit 5, or by applying a logic high to the CAL input
pin. (Both of these inputs are active when the Register Lock Control is set.) The CAL input pin is particularly
useful for implementing page gap calibration.
7.4.12.4 Key Calibration Settings
Table 8. Key Calibration Settings
General Settings
Calibration Mode
Page 2, Register 0, Bits[1:0]
Black Calibration Only
Black and White Full Calibration
Black and White Fine Tuning:
Number of Lines
00
01
10
Page 2, Register 1
Black Loop Specific Settings
# Black Pixels Averaged
Black Target
Page 2, Register 2, Bits[1:0]
Page 2, Register 3
Black Pixels Start
Page 2, Register 8
ADAC Scaling
Page 2, Register 2, Bits[3:2]
Page 2, Register 2, Bits[5:4]
Page 2, Register 0, Bit 2
DDAC Scaling
DDAC enable/disable
White Loop Specific Settings
White Target
Page 2, Register 5
White Loop Tolerance
White Pixel Averaging Window Size
Active/White Pixels Start
Active/White Pixels End
Page 2, Register 4, Bits[6:3]
Page 2, Register 4, Bits[2:0]
Page 2, Registers 0x09h, 0x0Ah
Page 2, Registers 0x0Bh, 0x0Ch
The calibration loops are intended to be used prior to scanning the page or between pages being scanned. The
black loop calibrates the channel offset such that the ADC outputs the desired code for Optical Black Pixels. The
white loop calibrates the channel gain such that the ADC outputs the desired maximum white value when
scanning a white target image.
The Black Loop and White loop will both update until the # Lines setting is met. Settings of 1 to 254 lines will
cause the loops to run for that many lines, and then stop. A setting of 255 will cause the calibration loops to run
indefinitely.
While using the Auto Black Level Correction Loop, the DAC registers are re-written as required every line the
loop is running.
While using the Auto White Level Correction Loop, the PGA registers are re-written as required every line the
loop is running.
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7.4.12.5 General Black Loop Operation
During calibration, the following general process is performed:
Beginning at Black Pixels Start, the selected number of black pixels are averaged.
This Black Average value is compared with the Black Target to give the Black Error value.
In general, if the Black Average>> Black Target, the new DAC values will be lower than the previous ones. If the
Black Average < Black
Target the new DAC values will be higher than the previous ones.
The ADAC Scaling and DDAC Scaling values are used to balance the speed of convergence against the
tolerance for noise in the data. The smallest (1/8) scaling values will give slower convergence, but will make the
system respond more slowly to noisy data. The highest (1/2) will result in the fastest convergence, but will
respond more quickly to noisy data. The DDAC scaling factor of Linear - 1LSB adjust will result in a maximum
change of one LSB of the DDAC value, regardless of how great the difference between Black Average and Black
Target
The number of Black Pixels to be processed by the algorithm is set at Page 2, Register 2, Bits[1:0]. 4, 8, 16 or 32
pixels can be averaged together to determine the current Black Value. Averaging the highest number of pixels
possible for the sensor in use will improve the accuracy and repeatability of the Black Average value.
The delay from the end of the SH Interval to the first Black Pixel to be processed is set at Page 2, Register 8. A
delay of up to 255 pixels can be set.
7.4.12.6 ADAC/DDAC Convergence
At the beginning of the calibration process, the ADAC will be used to reduce the Black Error as much as
possible. Once further adjustments of the ADAC can no longer reduce the Black Error, the ADAC adjustments
will stop and the DDAC will be used. *If users would rather apply digital offset corrections in their ASIC, the
DDAC corrections can be omitted by setting the DDAC disable bit at Page 2, Register 0x00h, Bit 2.
Figure 17. Black Loop Timing
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7.4.12.7 General White Loop Operation
The White Peak value is determined by a moving window average done throughout the Active/White pixels
region of the line (see to Figure 16). The size of the moving window is set at Page 2, Register 4, Bits[2:0]. 4, 8,
16 or 32 (default) pixels are averaged together at a time and compared with the previous Peak White value. If
the new White Average is greater than the previous Peak White value, then the Peak White value is set equal to
the White Average. The window is then shifted over to the next group of pixels (one window width) and a new
average is calculated. This process is repeated until the Active/White Pixels End value is reached. The final Peak
White value is then compared with the White Target value (Page 2, Register 5). The gain settings are then
adjusted to make the Peak White value closer to the White Target value.
7.4.12.8 White Loop Modes
•
White Full Calibration (Cold start or Pre-Job): In this mode, the gain settings are completely reset to
default at the beginning of the loop. The first change or gain decision is whether the CDS/SH gain setting will
be 1x or 2x. Subsequent decisions are made to adjust the PGA setting to the provide the Peak White value
that is closest to the White Target value
•
White Fine Tuning (Page Gap Calibration): In this mode, the previous gain settings are used as the starting
point. The CDS/ SH gain setting will not be changed. The PGA gain will be increased or decreased by one
step at a time, to fine tune the gain. This mode is normally used where only minor changes in the white level
are expected.
7.4.12.9 Bimodal (Automatic) Correction
Due to the architecture of the ADC used in the LM98722, it is possible that a small offset in the resulting data will
be present between the Even and Odd pixels processed by the device. This offset is referred to as a Bimodal
distribution in the data. It can occur because the signals being processed go through two different paths to
achieve the required throughput. Each of these paths can give a slightly different signal offset, resulting in the
bimodal distribution in output data, for a given fixed input voltage.
When the automatic Black Level (offset) correction circuit is engaged, a portion of that circuitry automatically
corrects the bimodal distribution. The bimodal correction applied is stored at Page 1, Registers 0x1Ch, 0x1Dh,
and 0x1Eh. The stored value is divided by two. Half is added to the Even pixels, and half is subtracted from the
Odd pixels.
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7.4.13 Coarse Pixel Phase Alignment
Precise placement of the CCD video signal sampling point is a critical aspect in any typical imaging application.
Many factors such as logic gate propagation delays and signal skew increase the difficulty in properly aligning
the CCD pixel output signals with the AFE input sampling points. The LM98722 provides two powerful features to
aid the system level designer in properly sampling the CCD video signal under a large range of conditions. The
first feature, discussed in this section, is the Coarse Pixel Phase Alignment block. As the name implies, this block
provides a very coarse range of timing adjustment to align the phase of the CCD Pixel output with the phase of
the LM98722 sample circuit. The second feature, discussed in Internal Sample Timing, is the block which is
designed for fine tuning of the sampling points within the selected Coarse Pixel Alignment Phase. A small portion
of a typical imaging application is shown in Figure 18.
SH
φ1Α
LM98724 CCD
Timing Generator
Outputs
φ2Α
OS3
CCD/CIS
Sensor
OS2
LM98724
Output Data Bus
OS1
Input Clock
(INCLK)
Figure 18. Typical AFE/CCD Interface
As shown in Figure 18, the LM98722 provides the timing signals to drive the CCD using external logic gates to
drive the high capacitance CCD clock pins. The pixels are shifted out of the CCD, thru the emitter follower
buffers and received by the LM98722 inputs for processing.
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In an ideal application, depicted in Figure 19, the Pixel output signal would be in phase with the timing signals
that drove the CCD. The LM98722 input sampling clocks (CLAMP and SAMPLE) are adjustable within a pixel
period. By default, the pixel period (or pixel “phase”) is defined to be in line with the input clock. As shown in the
ideal case, Figure 19, CLAMP and SAMPLE can be properly adjusted to their ideal positions within the pixel
phase, shown in Figure 19 at the stable region near the end of the pedestal and data phases.
Figure 19. Clock Alignment in an Ideal Application
However, in a real system, propagation delays exist in all stages of the signal chain. These propagation delays
will lead to a shift in the CCD Pixel outputs with respect to the LM98722 input clock. The phase shift of the CCD
Pixel output, demonstrated in Figure 20, can lead to significant sample timing issues if not properly corrected.
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Figure 20. CCD Output Phase Shift in a Real Application
In the default mode, the LM98722 sampling is performed during a clock period whose phase is aligned with the
input clock (ignoring any clock tree skew for the moment). The actual sampling clocks are adjustable within the
clock period, as shown in Figure 21 (shown for CDS mode in Figure 20) and further described in Internal Sample
Timing . As shown in Figure 20, the delay of the CCD Pixel output is shifted far enough that the fine CLAMP and
SAMPLE clocks cannot be placed in a stable portion of the waveform. To remedy this situation, the LM98722’s
Coarse Pixel Phase Alignment feature allows the designer to shift the entire phase of the analog front end with
respect to the input clock. This allows the designer to choose one of four sampling phases which best matches
the delay in the external circuitry. Once the “Coarse Pixel Phase” has been chosen, the designer can then fine
tune the sampling clocks using the fine adjustment (see Internal Sample Timing).
The four available Coarse Pixel Phases (PIXPHASE0 - PIXPHASE3) are depicted in Figure 21 (Mode 3),
Figure 22 (Mode 2) and Figure 23 (Mode 1). Also shown in the diagrams are the external input clock (INCLK)
and a typical CCD output delayed from the input clock.
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Figure 21. Mode 3 Coarse Pixel Adjustment
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Figure 22. Mode 2 Coarse Pixel Phase Adjustment
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Figure 23. Mode 1 Coarse Pixel Phase Adjustment
7.4.14 Internal Sample Timing
A typical CCD input signal is depicted in Figure 24 and Figure 25. Also shown are the internally generated
SAMPLE and CLAMP pulses. These signals provide the sampling points of the input signal (OSX). The timing of
SAMPLE and CLAMP is derived from an internal system clock (SYSCLK).
The pixel’s reference level input (depicted as VREF) is captured by the falling edge of the CLAMP pulse. In
Sample/Hold Mode the VREF input is a sample of the VCLP DC voltage. In CDS Mode the CLAMP pulse samples
the pedestal Level of the CCD output waveform.
The pixel’s signal level input (depicted as VSIG) is captured by the SAMPLE pulse. In either Sample/Hold or CDS
Mode, the VSIG input is the signal level of the CCD output waveform.
The LM98722 provides fine adjustment of the CLAMP and SAMPLE pulse placement within the pixel period. This
allows the user to program the optimum location of the CLAMP and SAMPLE falling edges. The available fine
tuning locations for CLAMP and SAMPLE are shown in Figure 25 and Figure 27 for each sampling mode (CDS
or S/H) and channel mode (3, 2, or 1 Channel).
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Figure 24. Pixel Sampling in CDS Mode
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Figure 25. Pixel Sampling in S/H Mode
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TPIXCLK
PIXPHASE
SYSCLK
TSYSCLK = TPIXCLK / 21 (In Mode 3)
CLAMP Start and CLAMP Stop can be individually programmed
Valid programming range as follows:
CLAMP Start 0 to 38
OSX CLAMP
Control =
CLAMP Stop 4 to 42
CLAMP Start
CLAMP Stop
CLAMP
ΔCLAMP= TSYSCLK / 2
OSX
SAMPLE Start and SAMPLE Stop can be individually programmed
Valid programming range as follows:
SAMPLE Start 0 to 38
SAMPLE
Control =
SAMPLE Stop 4 to 42
SAMPLE Start
SAMPLE Stop
SAMPLE
ΔSAMPLE= TSYSCLK / 2
Figure 26. 3 Channel (Mode 3) CLAMP and SAMPLE Timing
Figure 27. 1 or 2 Channel (Mode 1, Mode 2) CLAMP and SAMPLE Timing
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7.4.14.1 CCD Timing Generation
A flexible internal timing generator is included to provide clocking signals to CCD and CIS sensors. A block
diagram of the CCD Timing Generator is shown in Figure 28.
l o r t n o C t r e v n I
e c n e u q e S l a v r e t n I l e x i P
Figure 28. CCD Timing Generator Block Diagram
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Examples of the various operating modes and settings are shown in Figure 29 through Figure 32. The detailed
pixel timing is somewhat dependent on the operating modes of the AFE circuitry regarding the number of
adjustment points for the on and off points of the different timing outputs.
Note: In addition to the timing adjustments shown, the polarity of all sensor clock signals can be adjusted by
register control.
Figure 29. Pixel Timing - 42 Timing Points Per Pixel in Mode 3
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Figure 30. Pixel Timing - 28 Timing Points Per Pixel in Mode 2 and Mode 1
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Figure 31. Pixel Timing - Normal or 1/2 Rate Timing for High Resolution Sensors
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Figure 32. Pixel Timing - Independent Inversion of Each Output
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7.4.14.2 SH Interval Details - Multiple States Defined within SH Interval
In the LM98722, each SH Interval (the period when the high speed pixel timing is stopped) can have a selected
number of “States”, with each “State” having a specified duration. In the most common usage, each SH Interval
is the same, and there can be as many as 31 defined States within the SH Interval. During each State, the logic
level of each output signal can be defined as 1 or 0. The duration of the State, and the logic levels of the signals
are defined in configuration registers on register pages 3, 4 and 5.
Each State basic duration can be from 1 to 255 pixel periods. There is also a multiplier of 2x, 4x, 8x or 16x (Page
2, Register 0x17) that will increase SH State durations for sensors that require long SH pulse widths
If less than the maximum number of states are required, the first 0 duration State in the SH Interval will terminate
processing.
At the end of the SH Interval, a glitchless transition to pixel timing will occur. Similarly, at the end of the pixel
timing, a glitchless transition to the first state in the SH Interval will occur.
Some more complex sensors require different SH Interval timing in some sequence. The LM98722 can support
up to 4 different SH Interval Timings. The available 31 states are divided as follows when higher numbers of SH
Intervals are used:
Table 9. States within SH Interval Details
AVAILABLE STATES
# of SH Intervals
SH Interval 1
0 to 30
SH Interval 2
n/a
SH Interval 3
n/a
SH Interval 4
1
2
3
4
n/a
n/a
0 to 14
15 to 30
10 to 19
7 to 14
n/a
0 to 9
20 to 30
15 to 22
n/a
0 to 6
23 to 30
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Figure 33. Sensor Timing SH Interval Details - Single SH Interval
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An example showing a 4 SH Interval sequence is shown on Figure 34 through Figure 37.
Figure 34. Sensor Timing SH Interval Details - Multiple SH Intervals - 1 of 4
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Figure 35. Sensor Timing SH Interval Details - Multiple SH Intervals - 2 of 4
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Figure 36. Sensor Timing SH Interval Details - Multiple SH Intervals - 3 of 4
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Figure 37. Sensor Timing SH Interval Details - Multiple SH Intervals - 4 of 4
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7.4.14.3 SH Outputs - Low Speed Line Timing Usage
While the PHI, RS and CP outputs generate high speed timing during the pixel portion of the line, the SH outputs
can be used to generate low frequency signals during this period. This can be useful to generate “mode” or
“resolution” control signals for certain sensors.
Each SH output has a programmed ON and OFF point within the line. These points are programmed with a 16
bit value that sets the pixel number where the transition occurs.
Programming ON and OFF in different orders will allow pulses that are normally low or normally high, always
high, always low, etc. A common 1x, 2x, or 4x multiplier (Page 2, Register 0x15) can be used to increase the
range (and reduce the resolution) of these ON/ OFF points, as well as the White/Active and Line Length pixels
settings.
SH Interval
Waveform set by SH
Interval Sequence
ON < OFF
ON > OFF
ON
OFF
ON
OFF
ON < OFF
ON
ON
OFF
ON < OFF, OFF = 0xFFFFFFFF
ON > OFF, ON = 0xFFFFFFFF
ON = 0, OFF = 0xFFFFFFFF
OFF = 0, ON = 0xFFFFFFFF
OFF
ON
OFF
Figure 38. Sensor Timing SH ON/OFF Details - Example Settings and Waveforms
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7.4.14.4 Controlled Inversion
When using multiple SH Intervals, it is possible to invert the pixel portion of the line for any of the output signals
in any of the 4 Lines in the sequence. There is one bit per signal (or pair of signals for PHIA, PHIB and PHIC),
for each of the 1 to 4 lines in the sequence. Setting the bit for a particular output and line in the sequence will
cause the pixel portion of that line to be inverted. The transition to the next line in the sequence occurs at the
end of the SH Interval. Inversion can affect both the high speed timing signals (PHIx, RS, CP) and the low speed
ON/OFF behavior of the SH signals.
Figure 39 is an example of Polarity Override with a 2 Line sequence. Note that the PHIA1, SH1, SH2 and SH3
signals are inverted in Line 2, while all other signals are at the default polarity for both lines.
SH Interval 1
Line 1
SH Interval 2
Line 2
SH Interval 1
RS
PHIA1
SH1
SH2
SH3
SH4
SH5
0
0
0
0
0
0
0
0
1
1
1
0
0
0
Polarity
Override
Settings
Polarity
Override
Settings
SH Interval signal levels are set by SH Interval Information
Polarity for pixel portion of lines can be adjusted by Polarity Override Settings – Page 7, Registers 0x14 to 0x1D
Figure 39. Sensor Timing Mode Pin Output Details - Active Programmed Transition
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7.4.15 CCD Timing Generator Master/Slave Modes
The internal Sensor Timing generator is capable of operating in Master Mode or in Slave Mode. The
Master/Slave operation is configured with the Master Mode Select bit (Page 0, Register 0x00, bit 1). In either
Master or Slave Mode, control bit data can be included in the LM98722 output data to indicate when each new
scan is starting as well as pixel information such as color, type (active, black, dummy, etc.), and the beginning of
each line.
7.4.15.1 Master Timing Generator Mode
In Master Timing Mode (Page 0, Register 0x00, bit 1 = 1), the LM98722 controls the entire CCD Timing
Generation based on INCLK and the Register Lock Bit (Page 0, Register 0, Bit 0) state. The Register Lock bit is
set by the user to initiate a new scan. The LM98722 controls when each new line of the scan begins and ends
based on the CCD Timing Generator register settings. Scanning is enabled as long as the Register Lock bit = 1.
The period of the line (integration time) is controlled by the SH Interval State Length settings (Page 3 Registers)
and the Line Length setting (Page 3, Registers 0x0D and 0x0E) as well as the Pixel Multiplier Factor (Page 2,
Register 0x0F) and SH State Length Multiplier (Page 2, Register 0x11) .
The line period from end of one SH Interval to the end of the next SH Interval is equal to:
Line Period = (Sum of SH Interval States x SH State Length Multiplier) + (Line Length Setting x Pixel Multiplier Factor)
pixels
(2)
7.4.15.2 Slave Timing Generator Mode
In Slave Timing Mode (Page 2, Register 0x00, bit 1 = 0), the LM98722 CCD Timing Generator is controlled by
the external SH_R pin. Each new line of a scan is initiated by an SH_R pulse. The period of the line (integration
time) is mainly controlled by the period of the incoming SH_R signal. The minimum period between SH_R pulses
should be at least the SH Interval duration as calculated in Equation 2, plus the number of pixels to be clocked
out of the CCD or CIS sensor.
Figure 40. SH_R to INCLK (PIXCLK or ADCCLK) Timing
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7.4.15.3 Multiple SH Intervals
Multiple SH Intervals are supported for those CCD sensors that has different waveform and timing requirements
during successive SH Intervals. Up to 4 different SH Intervals are supported.
In the Multiple SH Interval mode, the Line Period can be different for each line, due to the possible different
settings for SH Interval duration. In that case the Line Periods would be calculated as follows:
Line Period1 = (Sum of SH Interval States1 x SH State Length Multiplier) + (Line Length Setting x Pixel Multiplier
Factor) pixels
Line Period2 = (Sum of SH Interval States2 x SH State Length Multiplier) + (Line Length Setting x Pixel Multiplier
Factor) pixels
Line Period3 = (Sum of SH Interval States3 x SH State Length Multiplier) + (Line Length Setting x Pixel Multiplier
Factor) pixels
Line Period4 = (Sum of SH Interval States4 x SH State Length Multiplier) + (Line Length Setting x Pixel Multiplier
Factor) pixels
In multiple SH Interval mode, the SH Interval States are subdivided as follows:
Table 10. Multiple SH Intervals Table
# SH INTERVALS
SH INTERVAL 1 STATES SH INTERVAL 2 STATES SH INTERVAL 3 STATES SH INTERVAL 4 STATES
1
2
3
4
0 to 30
0 to 14
0 to 9
0 to 6
15 to 30
10 to 19
7 to 14
20 to 30
15 to 22
23 to 30
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7.4.15.4 Support for CIS Sensors
In CIS Sensor modes, the SH (LampR), SH2 (LampG), SH3 (LampB) and SH4 (LampIR) outputs are configured
as Lamp illumination control outputs. In CIS mode, the number of lines/colors in the lamp sequence is selected
by the Multiple SH Interval setting at Page 2, Register 10h, Bits 1:0. Sequences of 2, 3 or 4 lines/colors are
supported in CIS mode. By definition, the standard CCD timing mode is equivalent to a CIS mode with length =
1.
Two different CIS modes are supported (CISa and CISb, selected at Page 2, Register 0x10h, Bits 4:3):
In CISa, there can be 2, 3 or 4 colors in the sequence, to support sensors with as many as 4 different lamp
colors. In this mode, the PGA and DAC settings are controlled by the channel settings, regardless of what line in
the sequence is being processed.
Figure 41. Mode 3, 3 Color Sequence, CISa Default
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Figure 42. Mode 3, 3 Color Sequence, CISb
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In CISb, when a 2 line sequence is selected, it is necessary to choose which coefficients are used during the 2
different lines in the sequence. this selection is made with the CISb Color Coefficient Select at Page 2, Register
10h, Bits 6:5. Following is an example of a 2 color sequence, where Red and Green are the selected colors:
(1) Use Page 2, Register 10h, Bits 6:5 to choose which SHx Lampx outputs are used, and which coefficients are used in
CISb 2 color sequence.
Figure 43. Mode 3, 2 Color Sequence, CISb
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To support monochrome scanning with an RGB CIS, select Mode 3, and a 1 line sequence. The LampR, LampG
and LampB On/Off times will apply for every line. The On/Off times and relative channel gains can both be
adjusted to achieve the desired white balance. Lamps can be on either simultaneously if the CIS and power
budget allow, or sequentially.
(1) Lamps can be on simultaneously , or sequentially within each line
Figure 44. Mode 3, Mono – 1 Color CCD Timing
7.4.15.5 LVDS Output Format - LM98714 Mode
7 Bit Frame
TXCLK
TXOUT2
TXOUT1
TXOUT0
DB[12]
DB[4]
DB[11]
DB[7]
DB[10]
DB[3]
DB[9]
DB[2]
DB[15]
DB[8]
DB[14]
DB[7]
DB[13]
DB[6]
DB[12]
DB[5]
DB[11]
DB[4]
DB[10]
DB[3]
DB[9]
DB[2]
n-1
n-1
n-1
n-1
n
n
n
n
n
n
n
n-1
n-1
n-1
n-1
n
n
n
n
n
n
n
CB[3]
CB[2]
CB[1]
CB[0]
DB[1]
DB[0]
CB[4]
CB[3]
CB[2]
CB[1]
CB[0]
n
n-1
n-1
n-1
n-1
n
n
n
n
n
n
Pixel “n-1”
Pixel “n”
Figure 45. LVDS Output Bit Alignment and Data Format
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7.4.16 LVDS Control Bit Coding - LM98714 Mode
The 5 control bits included in the LVDS data stream are coded as follows:
The "active" and "black" pixel tags are programmable tags that the LM98722 provides in order to identify how
many pixels have been processed since the falling edge of SH.
Which pixels are given "Active" and "Black" CB tags is controlled by Page 2, Registers 0x02, 0x08-0x0C, and
0x0F. (# Black Pixels Averaged, Black Pixels Start, Active/White Pixels Start, Active/White Pixels End, and Line
Length Multiplier).
The LM98722 counts the number of pixel periods after the SH Interval: If the number of pixel periods after the
SH Interval is greater than (Black Pixels Start) and less than (Black Pixels Start + # Black Pixels Averaged) the
CB bits will indicate that the pixel is a Black pixel. If the number of pixel periods after the falling edge of SH is
between Active/White Pixels Start and Active/White Pixels End, the CB bits will indicate that the pixel is an Active
pixel.
7.4.16.1 Latency Compensation of CB Bits
By default, the CB bits will be compensated for the latency through the AFE signal chain. This compensation can
be turned off by setting Page 8, Register 0x08, Bit 2 = 1.
Table 11. Latency Compensation of CB Bits
BITS
DESCRIPTION
CB[4]
0
Not the beginning of line
1
Beginning of Line (This bit is high during the SH Interval)
CB[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1111
Dummy Pixels
Red Active Pixels
Green Active Pixels
Blue Active Pixels
IR1 Active Pixels
IR2 Active Pixels
Red Black Pixels
Green Black Pixels
Blue Black Pixels
IR1 Black Pixels
IR2 Black Pixels
Beginning of Scan (This bit is high during the SH Interval of the first
line after the Lock Bit transitions from low to high)
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7.4.17 Flexible LVDS Formatting Mode: Mapping
7 Bit Frame
TXCLK
TXOUT2
TXOUT1
TXOUT0
DB[12]
DB[4]
DB[11]
DB[7]
DB[10]
DB[3]
DB[9]
DB[2]
DB[15]
DB[8]
DB[14]
n
DB[13]
DB[6]
DB[12]
DB[5]
DB[11]
DB[4]
DB[10]
DB[3]
DB[9]
DB[2]
n-1
n-1
n-1
n-1
n
n
n
n
n
n
DB[7]
n
n-1
n-1
n-1
n-1
n
n
n
n
n
n
CB[3]
CB[2]
CB[1]
CB[0]
DB[1]
DB[0]
n
CB[4]
CB[3]
CB[2]
CB[1]
CB[0]
n
n-1
n-1
n-1
n-1
n
n
n
n
n
Pixel “n-1”
Pixel “n”
Figure 46. LVDS Output Bit Alignment and Data Format
In Flexible LVDS Formatting Mode, the values highlighted in red can be substituted with other CB tag
information. Table 12 shows the different CB information that can be selected:
Table 12. Selectable CB Tag Information
SETTING
0000
CB TAG INFORMATION
Original CB or Data
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
CBO0 from LM98714 definition
CBO1 from LM98714 definition
CBO2 from LM98714 definition
CBO3 from LM98714 definition
CBO4 from LM98714 definition
R - High for a red channel pixel
G - High for a green channel pixel
B - High for a blue channel pixel
Parity - 21 bit if TXOUT0 Enabled, 14 bit if TXOUT0 Disabled
Ping - High for pixels processed by the Ping section of a channel, low for Pong
Line# lsb - Line = 0 to 3 for lines 0 to 3 in multiline sequences
Line# msb
Black Loop Pixels - High for pixels processed by the Black Loop
White Loop Pixels - High for pixels process by the White Loop
CLP Pixels - High for pixels where the input CLP switch is closed
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7.4.17.1 TXOUT0 Disable
The TXOUT0 data pair can be disabled. In combination with the new Flexible LVDS Formatting Mode, this can
support applications where only the upper 14 MSB of data are required. This will save one pair of LVDS wires in
the cable, and reduce the LM98722 slightly.
In addition, if fewer than 14 bits are required, the D2 and D3 bits can be replaced with the desired CB
information, selected from Table 12.
7.4.17.2 Parity
A parity bit is available for use as one of the CB bits. Parity is calculated based on all bits being sent via the 21
or 14 bit LVDS link except:
•
•
If any bit is selected to transmit CB Parity, it will not be used in the calculation
If any bit is transmitting a scrambler key bit when scrambler mode 2 is selected, it will not be used in the
calculation.
The total parity across the 21 or 14 output bits (excluding any scrambler key bit) will be even.
7.4.17.3 Latency Compensation of CB Bits
By default, the CB bits will be compensated for the latency through the AFE signal chain. This compensation can
be turned off by setting Page 8, Register 0x08, Bit 2 = 1.
7.4.18 LVDS Data Randomization for EMI Reduction
While LVDS transmissions will inherently reduce the amount of electromagnetic energy, further reductions can be
achieved by randomizing the data being sent over the link. A built in “scrambler” feature provides a number of
different modes to suit different applications and host processing capabilities. One key part of the scrambler is a
linear feedback shift register (LFSR) implementation to provide pseudo-random sequence “keys” to randomize
the image data. The basic implementation of an LFSR is shown in Figure 47:
XOR
...
20 19 18
2
1
0
Figure 47. Basic Implementation of an LFSR
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The LFSR algorithm used in the LM98722 is an n=21 maximal length right-shift implementation as shown in
Figure 47. As a reference for FPGA and ASIC developers, the sequence is the same as that created by the
Synopsys DW component DW03_lfsr_load with inverted outputs. The preload or starting value for the sequence
is 0x000001h.
If the prs (serial-type) output is selected (MODE = 01, SUB_MODE = 0X), the 21 bits of the LFSR are shifted one
position to the right on each TXCLK.
For clarity, the first 11 values in the prs sequence are:
0x000001h
0x100000h
0x080000h
0x040000h
0x020000h
0x010000h
0x008000h
0x004000h
0x002000h
0x001000h
0x000800h
If the pprs (parallel-type) output is selected (MODE = 01, SUB_MODE = 1X), the next 21 coefficients of the shift-
in term are calculated in parallel, and the LFSR is loaded with these coefficients: the effect is equivalent to
clocking the LFSR 21 times in serial mode. For clarity, the first 11 values in the pprs sequence are:
0x000001h
0x080001h
0x020001h
0x0A8001h
0x002001h
0x082801h
0x022201h
0x0AAA81h
0x000021h
0x080029h
0x120023h
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A summary and description of each of the modes and submodes is shown in Table 13.
Table 13. Mode and Submode Summary
MODE
Page 0, Register 0x05
Bits 4:3
SUB_MODE
Page 0, Register 0x05
Bits 2:1
DESCRIPTION
00
Scrambler Disabled
Full Scrambler Enabled. Sub-mode Settings Select:
00
01
10
11
send lvds_data[20:0] bitwise XOR with prs[20:0]
send prs[20:0]
01
send lvds_data[20:0] bitwise XOR with pprs[20:0]
send pprs[20:0]
1 bit scrambler with key of prs[0] send lvds_data[20:0] bitwise XOR with prs[0], with lvds_data[k] = 0 send
prs[0] on lvds_out[k] k is selected with following settings:
k = 0 (DB0 in CMOS and 714 modes, CB0 in flexible,
16 bit mode)
00
10
01 (TXOUT0 Disable = 0)
k = 5 (DB0 (LSB) in flexible, 16 bit mode)
k = 7 (DB2 (LSB) in flexible, 14 bit mode)
k = 16 (CB0 in 714 mode)
01 (TXOUT0 Disable = 1)
10
11
k = 20 (CB4 in 714 mode)
1 bit scrambler with key of lvds_data[k]. send lvds_data[20:0] bitwise XOR with lvds_data[k] with lvds_out[k] =
lvds_data[k]:
k = 0 (DB0 in CMOS and 714 modes, CB0 in flexible,
16 bit mode)
00
11
01 (TXOUT0 Disable = 0)
k = 5 (DB0 (LSB) in flexible, 16 bit mode)
k = 7 (DB2 (LSB) in flexible, 14 bit mode)
k = 16 (CB0 in 714 mode)
01 (TXOUT0 Disable = 1)
10
11
k = 20 (CB4 in 714 mode)
7.4.18.1 Mode 00: Scrambler Disabled
Mode 00: Scrambler Disabled
7.4.18.2 Mode 01: Full Scrambler Using The Full 21-bit Pseudo Random Sequence
There are 4 sub-modes: (a) the 21-bit output will be bit-wise XORed with the 21-bit serial pseudo-random
sequence. i.e. lvds_data[20:0] ^ prs[20:0]; (b) the 21-bit serial pseudo random sequence will be output directly;
(c) the 21-bit output will be bit-wise XORed with the 21-bit parallel pseudo-random sequence. i.e. lvds_data[20:0]
^ pprs[20:0]; (d) the 21-bit parallel pseudo random sequence will be output directly. In all sub-modes, the
sequences start m clock cycles after the de-assertion of the bol where m is defined as the analog latencies in 1-
ch, 2-ch and 3-ch modes. In other words, the output starts the same way as the up-count test pattern mode.
Unlike the up-count test pattern mode, the 21-bit pseudo-random sequence runs at the ADC (same as TXCLK)
rate, not pixel or line rate.
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7.4.18.3 Mode 10: One bit scrambler using the prs shift bit only, sending this bit out on a CB bit
Each bit of lvds_data[20:0] is XORed with prs[0]. One selected bit, lvds_data[k] is replaced with 0 before the
XOR procedure. The resulting output lvds_out[20:0] has bit k replaced by prs[0]. The bit k selection is flexible to
support different mappings of lvds_out depending on output settings as follows:
•
•
•
LVDS Mapping - 714 Default Mode versus Flexible Mode (Since the location of CB bits changes depending
on which is selected) Mapping select is at Page 8, Register 8, Bit 0.
CMOS Mode versus LVDS Mode (since only lvds_out[15:0] are available in CMOS mode) CMOS/LVDS mode
select at Page 0, Register 5, Bit 7.
LVDS 3 Pair Mode versus LVDS 2 Pair Mode (Since TXOUT0 pair is disabled in 2 Pair Mode(txout0_dis=1))
TXOUT0 Disable at Page 8, Register 8, Bit 1.
Figure 48. LVDS_out[20:0] Mapping In Different Modes
If an output bit is replaced with the scrambler key, that bit position/value is excluded from the calculation of the
parity.
7.4.18.4 Mode 11: “LSB” scrambler
The “LSB” selected from lvds_data[k] is used to scramble the output. The lvds_data[20:0] key bit k, as selected
in Mode 10 above is used (as the “LSB”) to XOR the other bits. The key bit itself is not replaced.
7.4.18.5 Scrambler Inhibit Bit Select
This feature allows individual bits in the LVDS output stream to be non-scrambled. This can be used as a setup
and debugging aid during initial system development, or as a permanent feature to simplify the data decoding
task. The tradeoff will be somewhat compromised EMI reduction over a fully scrambled LVDS data stream.
The controls for this feature are located as follows:
Scrambler Inhibit 0 - Page 8, Register 0x12h, Bits 6:0 - LVDS[6:0]
Scrambler Inhibit 1 - Page 8, Register 0x13h, Bits 6:0 - LVDS[13:7]
Scrambler Inhibit 2 - Page 8, Register 0x14h, Bits 6:0 - LVDS[20:14]
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7.4.19 LVDS Drive Strength Adjust
The LVDS outputs may be decreased in strength to reduce EMI generation, or increased in strength to improve
noise immunity.
Page 8, Register 8, Bits 5:4 can be adjusted as follows (in terms of VOD into 100 Ω termination):
Table 14. LVDS Strength
00 -
01 -
10 -
11 -
Decrease of approximately 100 mV
Decrease of approximately 50 mV
Default - Approximately 350 mV
Increase of approximately 50 mV
7.4.20 LVDS Output Timing Details
INCLK
t
IDO
7 Bit Frame Period
TXCLK
(single ended)
Pixel “n-1”
Pixel “n”
TXOUT2
(single ended)
CB[1]
CB[0]
DB[9]
DB[15]
DB[14]
CB[4]
CB[3]
CB[2]
CB[1]
n
CB[0]
DB[9]
DB[15]
DB[8]
DB[14]
DB[7]
n-1
n-1
n-1
n-1
n-1
n
n
n
n
n
n
n
TXOUT1
(single ended)
DB[10]
DB[3]
DB[8]
DB[7]
DB[13]
DB[12]
DB[5]
DB[11]
DB[4]
DB[10]
n
n-1
n-1
n-1
n
n
n
n
n
TXOUT0
(single ended)
DB[2]
DB[1]
TX
DB[0]
DB[6]
DB[3]
n
DB[2]
DB[1]
DB[0]
n
n-1
n-1
n-1
n-1
n
n
n
n
n
TX
pp0
pp1
TX
pp2
TX
pp3
TX
pp4
TX
pp5
TX
pp6
Figure 49. LVDS Data Output Mode Specification Diagram
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7.4.20.1 Optional TXCLK Delay
The LM98722 includes a selectable (off by default) delay of TXCLK. This delay can be enabled (Page 8, Register
0x08, Bit 3) to improve timing margin between the TXCLK and TXOUTx signals when using certain LVDS
deserializers. The default/off setting is intended to be compatible with the LM98714 LVDS timing.
7.4.21 LVDS Data Latency Diagrams
Figure 50. Mode 3 LVDS Data Latency
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Figure 51. Mode 2 LVDS Data Latency
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Figure 52. Mode 1 LVDS Data Latency
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7.4.22 Data Test Patterns
The data test patterns present different data to the input of the LVDS serializer block. There are two basic groups
of test patterns:
•
•
LVDS Output Pattern Modes - These patterns are applicable to all 21 bits of the LVDS interface.
AFE Output Pattern Modes (Default) - These patterns are applicable to the 16 bit AFE data sent to the LVDS
interface.
•
All Test Pattern Modes are selected at Page 0, Register 6.
7.4.22.1 LVDS Output Pattern Modes
7.4.22.1.1 Worst Case Transitions (Alternating 0x2A/0x55 on Each LVDS Pair)
This test mode provides an LVDS output with the maximum possible transitions. This mode is useful for system
EMI evaluations, and for ATE timing tests.
The effective data values are an alternating pattern between 21’b101010101010101010101 (0x155555) and
21’b010101010101010101010 (0x0AAAAA). This test pattern resets to 0x155555 at the selected event (BOL or
BOS).
Figure 53. Worst Case Transitions (Alternating 0x2A/0x55 on Each LVDS Pair)
7.4.22.1.2 Fixed Output Data
This mode sends a fixed repeating data pattern to each of the indicated LVDS output pairs. This is useful for
system debugging of the LVDS link and receiver circuitry. There are 4 different choices within this mode:
•
•
•
•
0x2A (0101010b) (All 3 data pairs)
0x55 (1010101b) (All 3 data pairs)
0x00 (0000000b) (*All 3 data pairs + clock pair)
0x7F (1111111b) (*All 3 data pairs + clock pair)
*Since the 0x00 and 0x7F patterns also affect the clock pair, they cannot be used for deserializer and
downstream testing. They are useful for DC measurements of the LVDS outputs.
7.4.22.2 AFE Output Pattern Modes
There are 3 different types of AFE Output Patterns:
•
•
•
Normal ADC/AFE output (Default)
Up-Counter Data
Fixed AFE Patterns
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7.4.22.2.1 Up-Counter Data
The counter will be reset to 0xFFFF during the BOS (Beginning Of Scan) SH Interval. When the AFE up-counter
is selected, the ramp begins at the BOS, and increments by 1 at either the pixel rate or at the line rate (every
BOL). This data can be useful as it can provide a grayscale image that increases in intensity down the “page”.
Alternately, it can provide data that increments at the pixel rate. Either of these forms can be very useful in
debugging the downstream data processing system.
7.4.22.2.2 Fixed AFE Pattern
The fixed AFE patterns allow the CB coding information to be sent normally, while specific data is used to
replace the AFE output. This can be useful in debugging portions of the downstream data processing system.
•
•
•
•
•
•
0xFF00 (0x1111111100000000b) fixed data
0xAA55 (0x1010101001010101b) fixed data
0x0000 (0x0000000000000000b) fixed data
0xFFFF (0x1111111111111111b) fixed data
0x00FF (0x0000000011111111b) fixed data
0x55AA (0x0101010110101010b) fixed data
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7.4.23 CMOS Output Format
Figure 54. CMOS Data Output Format (Mode 3 Shown)
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7.4.24 CMOS Output Data Latency Diagrams
INCLK =
ADCCLK
tLAT3
tLAT3
tLAT3
tLAT3
PIXPHASE0
PIXPHASE1
PIXPHASE2
PIXPHASE3
OSR
OSG
OSB
CLKOUT
DOUTx
MSB
LSB
Data latency shown is for Mode 3 in relation to PIXPHASE0 with the processing order set to OSRDOSGDOSB. If the incoming pixels are not aligned with
PIXPHASE0, one of the remaining PIXPHASEs can be selected as the sampling phase without effecting the output data location.
Figure 55. Mode 3 CMOS Output Latency
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INCLK =
ADCCLK
tLAT2
tLAT2
tLAT2
tLAT2
PIXPHASE0
PIXPHASE1
PIXPHASE2
PIXPHASE3
OSR
OSG
OSB
CLKOUT
DOUTx
MSB
LSB
Data latency shown is for Mode 2 in relation to PIXPHASE0 with the processing order set to OSGDOSB. If the incoming pixels are not aligned with
PIXPHASE0, one of the remaining PIXPHASEs can be selected as the sampling phase without effecting the output data location.
Figure 56. Mode 2 CMOS Output Latency
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INCLK =
ADCCLK
tLAT1
tLAT1
tLAT1
tLAT1
PIXPHASE0
PIXPHASE1
PIXPHASE2
PIXPHASE3
OSR
OSG
OSB
CLKOUT
DOUTx
MSB
LSB
Data latency shown is for Mode 1 in relation to PIXPHASE0 with the processing channel configured to OSR. If the incoming pixels are not aligned with
PIXPHASE0, one of the remaining PIXPHASEs can be selected as the sampling phase without effecting the output data location.
Figure 57. Mode 1 CMOS Output Latency
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7.4.25 Serial Interface
A serial interface is used to write and read the configuration registers. The interface is a four wire interface using
SCLK, SEN, SDI and SDO connections. SDI and SDO can be connected together to support the same format
and connectivity as previous LM98714 designs. The CE pin should be tied to GND to support LM98714
compatible communications. This will set the device address bits to 00.
Table 15. Serial Interface "CE" Pin Definition
CE LEVEL
VD
ADDRESS
01
10
00
Float
GND
The main input clock (INCLK) to the LM98722 can be active or stopped when accessing the Serial Interface.
Care should be taken to avoid stopping or starting the INCLK during Serial Interface communication.
NOTE
After either starting or stopping INCLK, or after Software Reset (Register Page 0, Address
1, [4:3]), users should wait for 50 ms to allow the internal PLL and logic to stabilize before
resuming Serial Interface communications.
7.4.25.1 Serial Interface Operating Modes
•
LM98714 Compatible Mode (Default): By default the serial interface is compatible with the LM98714
interface, allowing SDI and SDO to be connected and driving by a single pin on the host.
•
LM98722 4 Wire 16+ Clock Mode (Default): The 4 Wire 16+ Clock Mode is essentially the same as the
LM98714 Compatible Mode, but using all 4 wires, with separate SDO and SDI signals between the Host and
Slave. This requires additional wires, but removes the need for a bidirectional signal. A valid transaction is
recognized after a minimum of 16 SCLK while SEN is low.
•
LM98722 25+ Clock Mode (Selected when Page 0, Register 0x01h, Bit 7=1: This mode forces the serial
interface logic to only process a transaction with 25 or more SCLK while SEN is low. This mode can be used
with either 3 or 4 wire connections. In all of the above cases, the final 16 bits on SDI (before the rising edge
of SEN) are processed by the serial interface logic. Any earlier information on SDI is ignored.
•
•
Serial Interface in Absence of MCLK
Clockless (MCLK stopped) Mode (always enabled if MCLK stopped): When the input MCLK is stopped,
Data Read operation is exactly the same as MCLK present mode. The Data Write operation no longer
provides a free readback of the previously written data. See Figure 60 and Figure 63.
7.4.25.2 Serial Interface in Absence of MCLK
Clockless (MCLK stopped) Mode (always enabled if MCLK stopped) - When the input MCLK is stopped, Data
Read operation is exactly the same as MCLK present mode. The Data Write operation no longer provides a free
readback of the previously written data. See Figure 60 and Figure 62.
7.4.25.3 Writing to the Serial Registers
To write to the serial registers, the timing diagram shown in Figure 58 must be met. First, SEN is toggled low.
The *previously addressed device assumes control of the SDO pin during the first eight clocks of the command.
During this period, data is clocked out of the device at the rising edge of SCLK. At the rising edge of ninth clock,
the LM98722 releases control of the SDO pin. At the falling edge of the ninth clock period, the master should
assume control of the SDI pin and begin issuing the new command. SDI is clocked into the LM98722 at the
rising edge of SCLK. The remaining bits are composed of the “write” command bit (a zero), two device address
bits (00, 01 or 10 for the LM98722), five bit register address to be written, and the eight bit register value to be
written. When SEN toggles high, the register is written to, and the LM98722 now functions with this new data.
The previously addressed device could be another device on a shared serial interface or this device. If the
previous command was to this device, and was a read, then the SDO pin will be driven during the first eight
clocks. If the previous command was to this device and was a write, then the SDO pin will only be driven if the
serial interface is in “MCLK active” mode.
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7.4.25.4 Reading The Serial Registers
To read to the serial registers, the timing diagram shown Figure 59 must be met. First, SEN is toggled low. The
LM98722 assumes control of the SDO pin during the first eight clocks of the command. During this period, data
is clocked out of the device at the rising edge of SCLK. The eight bit value clocked out is the contents of the
previously addressed register, regardless if the previous command was a read or a write. At the rising edge of
ninth clock, the LM98722 releases control of the SDO pin. At the falling edge of the ninth clock period, the
master should assume control of the SDI pin and begin issuing the new command. SDI is clocked into the
LM98722 at the rising edge of SCLK. The remaining bits are composed of the “read” command bit (a one), two
device address bits (zeros for the LM98722), five bit register address to be read, and the eight bit “don’t care”
bits. When SEN toggles high, the register is not written to, but its contents are staged to be outputted at the
beginning of the next command.
Examples of Serial Writes and Reads in the various modes are shown in Figure 58 through Figure 64.
7.4.25.5 LM98714 Compatible 3 Wire Serial Signaling
1
9
n-15
n
SCLK
SEN
SDO
DO DO DO DO DO DO DO DO
[7] [6] [5] [4] [3] [2] [1] [0]
DO DO DO DO DO DO DO DO
[7] [6] [5] [4] [3] [2] [1] [0]
Device outputting register contents from this
write command if MCLK is present.
If MCLK is not present, no data output will occur.
Previously addressed slave
outputting register contents from
previous command.
(W)
0
CE CE
0
DI DI DI DI DI DI DI DI
[7] [6] [5] [4] [3] [2] [1] [0]
X
X
X
X
X
X
X
X
X
X
X
X
A4 A3 A2 A1 A0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SDI
1
Master issues “write” bit (0), 2 “chip enable” bits (00, 01 or 10), five bit
register address, and eight bit register value to be written.
Only final 16 bits of SDI data before rising edge of /SEN are processed.
Figure 58. Serial Write - LM98714 Compatible Connection
1
9
n-15
n
SCLK
SEN
DO DO DO DO DO DO DO DO
[7] [6] [5] [4] [3] [2] [1] [0]
CE CE
0
DI DI DI DI DI DI DI DI
[7] [6] [5] [4] [3] [2] [1] [0]
DO DO DO DO DO DO DO DO
[7] [6] [5] [4] [3] [2] [1] [0]
X
X
1
A4 A3 A2 A1 A0
X
X
SDIO
1
(R)
Previously addressed slave
outputting register contents from
previous command.
Master issues “read” bit (1), 2 “chip enable” bits (00, 01 or 10), five bit register
address, and eight “don’t care” bits. Register contents are not altered.
Only final 16 bits of SDI data before rising edge of /SEN are processed.
Device outputting register contents
addressed in read command.
Figure 59. Serial Read - LM98714 Compatible Connection
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7.4.25.6 LM98722 4 Wire Serial Signaling
1
9
n-15
n
SCLK
SEN
SDO
DO DO DO DO DO DO DO DO
[7] [6] [5] [4] [3] [2] [1] [0]
DO DO DO DO DO DO DO DO
[7] [6] [5] [4] [3] [2] [1] [0]
Device outputting register contents from this
write command if MCLK is present.
If MCLK is not present, no data output will occur.
Previously addressed slave
outputting register contents from
previous command.
(W)
0
CE CE
0
DI DI DI DI DI DI DI DI
[7] [6] [5] [4] [3] [2] [1] [0]
X
X
X
X
X
X
X
X
X
X
X
X
A4 A3 A2 A1 A0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SDI
1
Master issues “write” bit (0), 2 “chip enable” bits (00, 01 or 10), five bit
register address, and eight bit register value to be written.
Only final 16 bits of SDI data before rising edge of /SEN are processed.
Figure 60. Serial Write - 4 Wire Connection - 25+ Clock Mode
1
9
n-15
n
SCLK
SEN
SDO
DO DO DO DO DO DO DO DO
[7] [6] [5] [4] [3] [2] [1] [0]
DO DO DO DO DO DO DO DO
[7] [6] [5] [4] [3] [2] [1] [0]
Device outputting register contents
addressed in read command.
Previously addressed slave
outputting register contents from
previous command.
CE CE
0
X
X
X
X
X
X
X
X
X
X
X
X
1
A4 A3 A2 A1 A0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SDI
1
(R)
Master issues “read” bit (1), 2 “chip enable” bits (00, 01 or 10), five bit register
address, and eight “don’t care” bits. Register contents are not altered.
Only final 16 bits of SDI data before rising edge of /SEN are processed.
Figure 61. Serial Read - 4 Wire Connection - 25+ Clock Mode
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1
n-15
9
n
SCLK
SEN
SDO
DO DO DO DO DO DO DO DO
[7] [6] [5] [4] [3] [2] [1] [0]
DO DO DO DO DO DO DO DO
[7] [6] [5] [4] [3] [2] [1] [0]
Previously addressed slave outputting
register contents from last command.
Device outputting register contents from this write
command if MCLK is present.
If MCLK is not present, no data output will occur.
(W)
CE CE
0
DI DI DI DI DI DI DI DI
[7] [6] [5] [4] [3] [2] [1] [0]
0
A4 A3 A2 A1 A0
X
X
X
X
X
X
X
X
X
X
X
X
SDI
1
Master issues “write” bit (0), 2 “chip enable” bits (00, 01 or 10), five bit
register address, and eight bit register value to be written.
Only final 16 bits of SDI data before rising edge of /SEN are processed.
Figure 62. Serial Write - 4 Wire Connection - 16+ Clock Mode
1
n-15
9
n
SCLK
SEN
SDO
DO DO DO DO DO DO DO DO
[7] [6] [5] [4] [3] [2] [1] [0]
DO DO DO DO DO DO DO DO
[7] [6] [5] [4] [3] [2] [1] [0]
Previously addressed slave outputting
register contents from last command.
Device outputting register contents
addressed in read command.
CE CE
0
DI DI DI DI DI DI DI DI
[7] [6] [5] [4] [3] [2] [1] [0]
1
A4 A3 A2 A1 A0
X
X
X
X
X
X
X
X
X
X
X
X
SDI
1
(R)
Master issues “read” bit (1), 2 “chip enable” bits (00, 01 or 10), five bit register
address, and eight “don’t care” bits. Register contents are not altered.
Only final 16 bits of SDI data before rising edge of /SEN are processed.
Figure 63. Serial Read - 4 Wire Connection - 16+ Clock Mode
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7.4.25.7 Serial Interface Timing Details
tSENSC
tSCSEN
tIS
SCLK
tHZ
tOD
tIH
SEN
SDIO
(R)
1
DO DO DO DO DO DO
[7] [6] [5] [4] [3] [2]
DO DO DO DO DO DO DO DO
[7] [6] [5] [4] [3] [2] [1] [0]
CE CE
[1] [0]
A4 A3 A2 A1 A0
x
x
x
x
x
x
x
x
tSENW
INCLK
Figure 64. Serial Interface Specification Diagram
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7.5 Registers Maps
7.5.1 Configuration Registers
The LM98722 operation is very flexible to support a wide variety of sensors and system designs. This flexibility is
controlled through configuration registers which are first summarized, then described in full in the register tables.
Because the serial interface only allows 5 address bits, a register paging system is used to support the larger
number of required registers.
The page register is present at the highest address (1Fh or 11111b) of the currently selected page. The power
on default setting of the page register is 00. Writing other values to this register allows the other pages to be
accessed.
Once all registers are written, the Register Lock Control bit (Page 0, Register 0, Bit 0) is set to 1 to start the state
machines and initiate the converting of pixels. If Slave mode is selected, SH_R pulses must also be input to
trigger this process.
NOTE
When Register Lock Control = 1, many registers are locked to prevent state machines
from becoming corrupted, while others are accessible to allow control of necessary
functions. The registers and bits that are still writable are indicated in Boldface print in the
Bits and Register Description columns of the Register Definition Details table.
Operational Setup Sequence:
Ensure Lock Bit (Page 0, Register 0, Bit 0) = 0 for following setting writes
Apply either no INCLK or a stable INCLK to ensure accurate serial communications
Page 0
•
•
•
•
•
•
Set AFE mode (# of input channels)
Set output data format
Enable data outputs
Set AFE biasing
Set AFE Clamp and Sample timing
Setup Slave or Master Mode
Page 1
•
•
•
•
Set Gain Mode (Single or Dual)
Set CDS/SH Gain
Set PGA
Set DAC settings
Page 2
•
•
•
•
•
•
•
Set Input Clamping Settings
Set Black Pixel Start and # Black Pixels Averaged
Set Active White Pixels Start and End
Set Line Length (Master Mode Only)
Set # Pixel Multiplier, SH Line Sequence # and SH State Length Multiplier
Set PHI, RS, CP On and Off delay settings
Set Spread Spectrum control settings
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Registers Maps (continued)
Page 3
•
Set SH State Length settings
Page 4
•
Set SH Interval State Settings for PHI, RS, CP
Page 5
•
Set SH Interval State Settings for SH1 to SH5
Page 6
•
Set PHI, RS, CP pattern bit fields and rate (normal or 1/2 rate)
Page 7
•
•
Set SHx On, Off settings if needed
Set CLK invert settings for multi-line sequences if needed
Page 8
•
•
•
•
Set CLK output activity, polarity, enable
Set LVDS output format
Set CB coding
Set PHI, RS, CP, SH unlock output state
Begin Scanning:
•
•
•
Ensure stable INCLK applied and PLL is locked (read back Page 0, Register 0, Bit 7)
Set Register Lock Control bit = 1
In Master Mode, conversions will begin after the Lock Bit is set. In Slave Mode, SH_R pulses can begin after
the Lock Bit is set. SH Intervals will be generated in response to the SH_R input pulses.
•
Registers and Bits marked in Boldface print may be adjusted while scanning is in progress. More major
changes (i.e.: color mode, CCDTG details) should be done by writing a 0 to the Register Lock Control Bit to
pause scanning.
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Registers Maps (continued)
Table 16. Register Summary Table
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
REGISTER TITLE
PAGE 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0010 0000
Main Configuration 0
Main Configuration 1
Main Configuration 2
Main Configuration 3
Main Configuration 4
Main Configuration 5
Configuration 6
1
1
0100 0000
1100 0000
1000 0010
0011 0000
0000 0000
0000 0000
0000 0000
0000 0000
0001 0000
0000 0000
0001 0000
0000 0000
0001 0000
0001 0110
0010 0110
0001 0110
0010 0110
0001 0110
0010 0110
0000 0000
0000 0000
2
2
3
3
4
4
5
5
6
6
7
7
Configuration 7
8
8
OSR CLAMP Start Edge
OSR CLAMP Stop Edge
OSG CLAMP Start Edge
OSG CLAMP Stop Edge
OSB CLAMP Start Edge
OSB CLAMP Stop Edge
OSR SAMPLE Start Edge
OSR SAMPLE Stop Edge
OSG SAMPLE Start Edge
OSG SAMPLE Stop Edge
OSB SAMPLE Start Edge
OSB SAMPLE Stop Edge
Sample & Clamp Monitor 0
Sample & Clamp Monitor 1
Reserved
9
9
10
11
12
13
14
15
16
17
18
19
20
21
A
B
C
D
E
F
10
11
12
13
14
15
22 to 29
30
16 to 1D
1E
XX00 0011
0000 0000
Revision
31
1F
Page Register
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Registers Maps (continued)
Table 16. Register Summary Table (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
REGISTER TITLE
PAGE 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0000 0000
Gain Mode
1
1
0110 0001
0110 0001
0110 0001
1000 0000
0000 0000
1000 0000
0000 0000
1000 0000
0000 0000
1000 0000
0000 0000
1000 0000
0000 0000
1000 0000
0000 0000
0100 0000
0100 0000
0100 0000
0100 0000
0100 0000
0100 0000
0110 0001
0110 0001
0110 0001
0100 0000
0100 0000
0100 0000
0000 0000
Red PGA
2
2
Green PGA
3
3
Blue PGA
4
4
Red Even DAC MSB
Red Even DAC LSB
5
5
6
6
Green Even DAC MSB
Green Even DAC LSB
Blue Even DAC MSB
Blue Even DAC LSB
Red Odd DAC MSB
Red Odd DAC LSB
7
7
8
8
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
28
29
30
31
A
B
C
Green Odd DAC MSB
Green Odd DAC LSB
Blue Odd DAC MSB
Blue Odd DAC LSB
Red Even Digital Offset
Green Even Digital Offset
Blue Even Digital Offset
Red Odd Digital Offset
Green Odd Digital Offset
Blue Odd Digital Offset
Red High Gain PGA
Green High Gain PGA
Blue High Gain PGA
Red Channel Bimodal
Green Channel Bimodal
Blue Channel Bimodal
Page Register
D
E
F
10
11
12
13
14
15
16
17
18
1C
1D
1E
1F
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Registers Maps (continued)
Table 16. Register Summary Table (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
REGISTER TITLE
PAGE 2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
0
0
0000 0000
Calibration Mode
Calibration # Lines
Black Cal Config
Black Target
1
1
0000 0000
0001 0100
0100 0000
0100 0011
1000 0000
0000 0100
0000 1100
0001 0000
0000 0000
0001 0100
0001 0000
0000 0000
0001 0000
0100 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
2
2
3
3
4
4
White Cal Config
White Target
5
5
6
6
AutoCLPIN Start
AutoCLPIN End
Black Loop Start
7
7
8
8
9
9
Active/White Pixels Start - MSB
Active/White Pixels Start - LSB
Active/White Pixels End - MSB
Active/White Pixels End - LSB
Line Length MSB
Line Length LSB
10
11
12
13
14
15
16
17
18
19
A
B
C
D
E
F
Line Length Multiplier
Line Mode
10
11
12
13
SH State Length Multiplier
PHIA/B/C Delays
RS/CP Delays
20 to 23
24
14 to 17
18
Reserved
1111 1000
0001 1000
0000 0000
0000 0010
0000 0000
0000 0000
0000 0000
PLL Control 1
25
19
PLL Control 2
26
1A
SSCG Control 1
27
1B
SSCG Control 2
28
1C
Clock Mult M
29
1D
Clock Mult N
30
1E
SSCG Control 3
31
1F
Page Register
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Registers Maps (continued)
Table 16. Register Summary Table (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
REGISTER TITLE
PAGE 3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
0
0
0000 0000
SH State 0 Length
SH State 1 Length
SH State 2 Length
SH State 3 Length
SH State 4 Length
SH State 5 Length
SH State 6 Length
SH State 7 Length
SH State 8 Length
SH State 9 Length
SH State 10 Length
SH State 11 Length
SH State 12 Length
SH State 13 Length
SH State 14 Length
SH State 15 Length
SH State 16 Length
SH State 17 Length
SH State 18 Length
SH State 19 Length
SH State 20 Length
SH State 21 Length
SH State 22 Length
SH State 23 Length
SH State 24 Length
SH State 25 Length
SH State 26 Length
SH State 27 Length
SH State 28 Length
SH State 29 Length
SH State 30 Length
Page Register
1
1
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
A
B
C
D
E
F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
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Registers Maps (continued)
Table 16. Register Summary Table (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
REGISTER TITLE
PAGE 4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
0
0
0000 0000
SH State 0 PHI, RS, CP
1
1
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
SH State 1 PHI, RS, CP
SH State 2 PHI, RS, CP
SH State 3 PHI, RS, CP
SH State 4 PHI, RS, CP
SH State 5 PHI, RS, CP
SH State 6 PHI, RS, CP
SH State 7 PHI, RS, CP
SH State 8 PHI, RS, CP
SH State 9 PHI, RS, CP
SH State 10 PHI, RS, CP
SH State 11 PHI, RS, CP
SH State 12 PHI, RS, CP
SH State 13 PHI, RS, CP
SH State 14 PHI, RS, CP
SH State 15 PHI, RS, CP
SH State 16 PHI, RS, CP
SH State 17 PHI, RS, CP
SH State 18 PHI, RS, CP
SH State 19 PHI, RS, CP
SH State 20 PHI, RS, CP
SH State 21 PHI, RS, CP
SH State 22 PHI, RS, CP
SH State 23 PHI, RS, CP
SH State 24 PHI, RS, CP
SH State 25 PHI, RS, CP
SH State 26 PHI, RS, CP
SH State 27 PHI, RS, CP
SH State 28 PHI, RS, CP
SH State 29 PHI, RS, CP
SH State 30 PHI, RS, CP
Page Register
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
A
B
C
D
E
F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
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Registers Maps (continued)
Table 16. Register Summary Table (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
REGISTER TITLE
PAGE 5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
0
0
0000 0000
SH State 0 SH1-SH5
SH State 1 SH1-SH5
SH State 2 SH1-SH5
SH State 3 SH1-SH5
SH State 4 SH1-SH5
SH State 5 SH1-SH5
SH State 6 SH1-SH5
SH State 7 SH1-SH5
SH State 8 SH1-SH5
SH State 9 SH1-SH5
1
1
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
A
SH State 10 SH1-SH5
SH State 11 SH1-SH5
SH State 12 SH1-SH5
SH State 13 SH1-SH5
SH State 14 SH1-SH5
SH State 15 SH1-SH5
SH State 16 SH1-SH5
SH State 17 SH1-SH5
SH State 18 SH1-SH5
SH State 19 SH1-SH5
SH State 20 SH1-SH5
SH State 21 SH1-SH5
SH State 22 SH1-SH5
SH State 23 SH1-SH5
SH State 24 SH1-SH5
SH State 25 SH1-SH5
SH State 26 SH1-SH5
SH State 27 SH1-SH5
SH State 28 SH1-SH5
SH State 29 SH1-SH5
SH State 30 SH1-SH5
Page Register
B
C
D
E
F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
98
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Registers Maps (continued)
Table 16. Register Summary Table (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
REGISTER TITLE
PAGE 6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
0
0
0000 0000
PHIA0
PHIA1
PHIA2
PHIA3
PHIA4
PHIA5
PHIB0
PHIB1
PHIB2
PHIB3
PHIB4
PHIB5
PHIC0
PHIC1
PHIC2
PHIC3
PHIC4
PHIC5
RS0
1
1
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
A
B
C
D
E
F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
RS1
RS2
RS3
RS4
RS5
CP0
CP1
CP2
CP3
CP4
CP5
HSPIX Rate Select
Page Register
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Registers Maps (continued)
Table 16. Register Summary Table (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
REGISTER TITLE
PAGE 7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
0
0
0000 0000
SH1 PIXEL ON MSB
SH1 PIXEL ON LSB
SH1 PIXEL OFF MSB
SH1 PIXEL OFF LSB
SH2 PIXEL ON MSB
SH2 PIXEL ON LSB
SH2 PIXEL OFF MSB
SH2 PIXEL OFF LSB
SH3 PIXEL ON MSB
SH3 PIXEL ON LSB
SH3 PIXEL OFF MSB
SH3 PIXEL OFF LSB
SH4 PIXEL ON MSB
SH4 PIXEL ON LSB
SH4 PIXEL OFF MSB
SH4 PIXEL OFF LSB
SH5 PIXEL ON MSB
SH5 PIXEL ON LSB
SH5 PIXEL OFF MSB
SH5 PIXEL OFF LSB
1
1
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
A
B
C
D
E
F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
PHIA Polarity Override
PHIB Polarity Override
PHIC Polarity Override
RS Polarity Override
CP Polarity Override
SH1 Polarity Override
SH2 Polarity Override
SH3 Polarity Override
SH4 Polarity Override
SH5 Polarity Override
Reserved
Page Register
100
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Registers Maps (continued)
Table 16. Register Summary Table (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
REGISTER TITLE
PAGE 8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
0
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0000 0000
PHIA1, PHIA2 Polarity / State
1
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0010 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
PHIB1, PHIB2 Polarity / State
PHIC1, PHIC2 Polarity / State
RS, CP Polarity / State
SH1, SH2 Polarity / State
SH3, SH4 Polarity / State
SH5 Polarity / State
2
3
4
5
6
7
Reserved
8
LVDS Configuration
9
CB1/CB0 CB Mapping
10
11
12
13
14
15
CB3/CB2 CB Mapping
D2/CB4 CB Mapping
D4/D3 CB Mapping
D5 CB Mapping
Unlock State Output Values PHIA, PHIB, PHIC, RS, CP
Unlock State Output Values SH1, SH2, SH3, SH4, SH5
Reserved
16 to 17
18
10 to 11
12
Scrambler Inhibit 0 (LVDS[6:0])
Scrambler Inhibit 1 (LVDS[13:7])
Scrambler Inhibit 2 (LVDS[20:14])
Reserved
19
13
20
14
16 to 30
31
15 to 1E
1F
Page Register
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The following section describes all available registers in the LM98722 register bank, and their functions.
***Registers and/or Bits Marked in Boldface are Writeable when Register 0, Bit 0 = 1, all others are “Locked”.***
Table 17. Register Definition, Page 0
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
BITS
REGISTER TITLE
REGISTER DESCRIPTION
PAGE 0
0010 0000
[7]
PLL Locked (READ ONLY) Status Bit
0 PLL is not locked
1 PLL is locked
[6]
[5]
Not Used
SH_R Capture Clock Select
0 Use internal CLK from XTAL source.
1 Use external INCLK source.
[4]
SH_R Capture Edge Select
0 Use rising edge of selected Clock source.
1 Use falling edge of selected Clock source.
Main
Configuration
0
[3]
[2]
Not Used
XTALEN
0
0
0
0 Use autodetecting CMOS/LVDS clock
receiver
1 Enable crystal driver. INCLK+ is output,
INCLK- is input.
[1]
[0]
Master Mode Select Bit
0 Slave/SH_R
1 Master/Line Length
Register Lock Control
0 Registers are unlocked (i.e. writeable) and
CCDTG state machines are stopped
1 Registers are locked (default) and CCDTG
state machines are operating
102
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Table 17. Register Definition, Page 0 (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
BITS
[7]
REGISTER TITLE
REGISTER DESCRIPTION
0
1
1
0100 0000
Serial Interface Mode Select
0 16+ Clock Mode [Default]
1 25+ Clock Mode
[6]
[5]
[4]
Enable PLL Range Autocalibration
0 PLL Range Autocal OFF
1 PLL Range Autocalibrates (Default)
Calibrate Gain/Offset (self clearing)
0 Calibration is off
1 Calibration is active
Main
Software Reset - FSM
Configuration
Set to 1 to reset all state machines. Self
clearing.
1
[3]
Software Reset - FSM + Registers
Set to 1 to reset all state machines and
registers. Self clearing.
[2]
[1]
[0]
Power Down CDS/SH Amplifier
Reference Buffer Power Down
Master Power Down
0 Master Power Down Disable
1 Master Power Down Enable
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Table 17. Register Definition, Page 0 (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
BITS
REGISTER TITLE
REGISTER DESCRIPTION
0
2
2
1100 0010
[7:6]
Mode Select Bits
11 Mode 3 (Default) (3 Channel Mode)
10 Mode 2 (2 Channel Mode)
01 Mode 1 (1 Channel Mode)
00 Not Used
Color Select Bits. Used to determine the inputs
sampled during a scan.
[5:4]
11 Reserved
10 Mode 2 = OSR & OSB Mode 1 = OSB
01 Mode 2 = OSG & OSB Mode 1 = OSG
00 Mode 2 = OSR & OSG Mode 1 = OSR
Color Order. Configures the sequence of the
pixel processing
[3]
[2]
0 Forward (default)
1 Reverse
Main
PIXCLK/ADCCLK Configuration. Selects
appropriate multiplier for given input clock
frequency
Configuration
2
Mode 3: ADC Frequency = 3x Pixel Frequency
Mode 2: ADC Frequency = 2x Pixel Frequency
Mode 1: ADC Frequency = 1x Pixel Frequency
0 User supplies ADC rate clock, LM98722
performs no multiplication.
1 User supplies Pixel rate clock, LM98722
performs clock multiplication.
[1]
[0]
Sampling Mode Select
0 Sample and Hold Mode
1 Correlated Double Sampling Mode (Default)
Even/Odd CCD Sensor Enable
Dedicated Even and Odd DACs and Digital
Offsets would be applied to every other pixels.
104
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Table 17. Register Definition, Page 0 (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
BITS
[7]
REGISTER TITLE
REGISTER DESCRIPTION
0
3
3
1000 0010
Source Follower Enable.
0 Disable
1 Enable (Default)
Input Bias Enable. Enables the Input Bias
Resistor ladder.
[6]
0 Disable (Default)
1 Enable
Main
Bit CLP mode enable (black clamping done in
reference portion of every pixel of line)
[5]
[4:2]
[1]
Configuration
3
0 Disabled (Default)
1 Enable
Pixel Phase Clock Select. Coarse adjustment
for Pixel phase relative to INCLK. Useful in
systems where Pixel inputs arrive with
significant delay relative to INCLK.
Sensor Polarity Select
0 Voltage increases with increasing white
level
1 Voltage decreases with increasing white
level
[0]
Reserved
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Table 17. Register Definition, Page 0 (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
BITS
[7]
REGISTER TITLE
REGISTER DESCRIPTION
0
4
4
0011 0000
Reserved
[6]
Enable VCLP Buffer
0 Use resistor divider voltages directly
1 Use buffered resistor divider voltage
[5]
[4]
Auto CLPIN Enable
0 Auto CLPIN Disabled
1 Auto CLPIN Enabled - (Default) - CLPIN
generated according to Start and End position
settings at Page 2, Registers 0x06 and 0x07
CLPIN Gating Enable
0 Auto CLPIN not gated by the SAMPLE pulse
timing
1 Auto CLPIN gated by the SAMPLE pulse timing
(Default)
[3]
Main
Configuration
4
VCLP Power Down
0 VCLP Normal Operation
1 No circuit is tied to the VCLP output and no
current is drawn
[2:0]
VCLP Voltage Setting/Source
000 0.85VA (Default)
001 0.9VA
010 0.95VA
011 0.6VA
100 0.55VA
101 0.4VA
110 0.35VA
111 0.15VA
106
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Table 17. Register Definition, Page 0 (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
BITS
REGISTER TITLE
REGISTER DESCRIPTION
0
5
5
0000 0000
[7]
Output Format
0 LVDS (Default)
1 CMOS
[6]
[5]
Output Enable. Enables the Data Output pins.
0 Disabled (Default)
1 Enable
CMOS Data CLK Override Enable
0 - SH2 output as normal
1 - CMOS Data CLK on SH2
[4:3]
Data Scrambler Enable/Mode
00 - Scrambler Disabled
01, 10, 11 - Scrambler Enabled see 1:0
description below for details:
[2:1]
Data Scrambler Submode
If Scrambler Mode = 01, Full scrambler enabled
as follows:
00 Send lvds_data[20:0]^prs[20:0]
01 Send prs[20:0]
10 Send lvds_data[20:0]^pprs[20:0]
11 Send pprs[20:0]
If Scrambler Mode = 10, 1 bit scrambler with key
of prs[0]
Main
Send lvds_data[20:0]^prs[0], with lvds_data[k] = 0
Configuration
00 k = 0 (DBO in CMOS and 714 modes, CB0 in
flexible, 16 bit mode)
5
01, txout0 disable = 0, k = 5 (DB0(lsb) in flexible,
16 bit mode)
01, txout0 disable = 1, k = 7 (DB2(lsb) in flexible,
14 bit
mode)
10 k = 16 (CB0 in 714 mode)
11 k = 20 (CB4 in 714 mode)
If Scrambler Mode = 11, 1 bit scrambler with key
of lvds_data[k].
Send lvds_data[20:0]^lvds_data[k], with
lvds_out[k] =
lvds_data[k]
00 k = 0 (DBO in CMOS and 714 modes, CB0 in
flexible, 16 bit mode)
01, txout0 disable = 0, k = 5 (DB0(lsb) in flexible,
16 bit mode)
01, txout0 disable = 1, k = 7 (DB2(lsb) in flexible,
14 bit mode)
10 k = 16 (CB0 in 714 mode)
11 k = 20 (CB4 in 714 mode)
[0]
Reserved
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Table 17. Register Definition, Page 0 (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
BITS
REGISTER TITLE
REGISTER DESCRIPTION
0
6
6
0000 0000
[7]
LVDS Test Pattern Synchronization Select
0 Synchronizes at (held at initial state during)
BOL & BOS
1 Synchronizes at (held at initial state during)
BOS
only
[6:4]
LVDS Output Pattern Select
000 Select AFE output (normal operation) (Must
be 00 for AFE Test Patterns)
001 Select 0x2A & 0x55 alternating patterns (all 3
pairs)
010 Selects 0x2A (all 3 pairs)
011 Selects 0x55 (all 3 pairs)
100 Selects 0x00 (all 4 pairs) (Differential 0 on all
outputs)
101 Selects 0x7F (all 4 pairs) (Differential 1 on all
outputs)
[3]
AFE Test Pattern - Up-count Rate Select
0 Up-count at pixel rate
Configuration
6
1 Up-count at BOL
Test Pattern - AFE Data Select - (Bits 6:4 must
be 000 for AFE Test Patterns)
[2:0]
000 Selects ADC output (normal operation)
001 Selects up-counter output
010 Selects 0xFF00 - fixed data
011 Selects 0xAA55 - fixed data
100 Selects 0x0000 - fixed data
101 Selects 0xFFFF - fixed data
110 Selects 0x00FF - fixed data
111 Selects 0x55AA - fixed data
108
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Table 17. Register Definition, Page 0 (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
BITS
REGISTER TITLE
REGISTER DESCRIPTION
0
7
7
0000 0000
Timing Generator Output Driver Strength
[5]
[4]
[3]
[2]
[1]
PHIA1, PHIA2 - 0 = Normal, 1 = High
PHIB1, PHIB2 - 0 = Normal, 1 = High
PHIC1, PHIC2 - 0 = Normal, 1 = High
RS - 0 = Normal, 1 = High
Configuration
7
CP - 0 = Normal, 1 = High
SH1, SH2, SH3, SH4, SH5 - 0 = Normal, 1 =
High
[0]
0
0
0
0
0
0
0
0
0
0
0
8
8
9
0000 0000
0001 0000
0000 0000
0001 0000
0000 0000
0001 0000
0001 0110
0010 0110
0001 0110
0010 0110
0001 0110
[7:6]
OSR CLAMP Start
Edge
Not Used
[5:0]
[7:6]
CLAMP_R Start Edge - Default = 0d
Not Used
9
OSR CLAMP Stop
Edge
[5:0]
[7:6]
CLAMP_R Stop Edge - Default = 16d
Not Used
10
11
12
13
14
15
16
17
18
A
OSG CLAMP Start
Edge
[5:0]
[7:6]
CLAMP_G Start Edge - Default = 0d
Not Used
B
OSG CLAMP Stop
Edge
[5:0]
[7:6]
CLAMP_G Stop Edge - Default = 16d
Not Used
C
OSB CLAMP Start
Edge
[5:0]
[7:6]
CLAMP_B Start Edge - Default = 0d
Not Used
D
OSB CLAMP Stop
Edge
[5:0]
[7:6]
CLAMP_B Stop Edge - Default = 16d
Not Used
E
OSR SAMPLE Start
Edge
[5:0]
[7:6]
SAMPLE_R Start Edge - Default = 22d
Not Used
F
OSR SAMPLE Stop
Edge
[5:0]
[7:6]
SAMPLE_R Stop Edge - Default = 38d
10
11
12
OSG SAMPLE Start Not Used
Edge
[5:0]
[7:6]
SAMPLE_G Start Edge - Default = 22d
OSG SAMPLE Stop
Edge
Not Used
[5:0]
[7:6]
SAMPLE_G Stop Edge - Default = 38d
Not Used
OSB SAMPLE Start
Edge
[5:0]
[7:6]
SAMPLE_B Start Edge - Default = 22d
OSB SAMPLE Stop
Edge
Not Used
0
19
13
0010 0110
[5:0]
SAMPLE_B Stop Edge - Default = 38d
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Table 17. Register Definition, Page 0 (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
BITS
[7]
REGISTER TITLE
REGISTER DESCRIPTION
0
20
14
0000 0000
Not Used
SH_R Capture Monitor Override
[6]
0 SAMPB=SAMPB, CLAMPB=CLAMPB -
Default
1 SAMPB = INCLK, CLAMPB = SH_R
[5:3]
Selection bits for RS (user test mode)
000 Normal output
001 SAMPR Output
010 SAMPG Output
011 SAMPB Output
100 CLAMPR Output
101 CLAMPG Output
Sample & Clamp
Monitor 0
110 CLAMPB Output
111 PIXPHASE Output
[2:0]
Selection bits for CP (user test mode)
000 Normal output
001 SAMPR Output
010 SAMPG Output
011 SAMPB Output
100 CLAMPR Output
101 CLAMPG Output
110 CLAMPB Output
111 PIXPHASE Output
110
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Table 17. Register Definition, Page 0 (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
BITS
[7:6]
[5:3]
REGISTER TITLE
REGISTER DESCRIPTION
0
21
15
0000 0000
Not Used
Selection bits for SH2 (user test mode)
000 Normal output
001 SAMPR Output
010 SAMPG Output
011 SAMPB Output
100 CLAMPR Output
101 CLAMPG Output
110 CLAMPB Output
111 PIXPHASE Output
Sample & Clamp
Monitor 1
[2:0]
Selection bits for SH3 (user test mode)
000 Normal Output
001 SAMPR Output
010 SAMPG Output
011 SAMPB Output
100 CLAMPR Output
101 CLAMPG Output
110 CLAMPB Output
111 PIXPHASE Output
0
0
22 to 29
30
16 to 1D 0000 0000
Reserved
Revision
1E
1F
XX00 0011
0000 0000
[7:0]
Page Register
Used to select desired page of registers being
accessed
0
31
[3:0]
0000 Page 0
0001 Page 1
0010 Page 2
0011 Page 3
0100 Page 4
0101 Page 5
0110 Page 6
0111 Page 7
1000 Page 8
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Table 18. Register Definition, Page 1
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
BITS
REGISTER TITLE
Gain Mode
REGISTER DESCRIPTION
1
0
0
0000 0000
[7]
[6]
[5]
CDS/SH Gain Blue - 0 = 1x Gain, 1 = 2x Gain
CDS/SH Gain Green - 0 = 1x Gain, 1 = 2x Gain
CDS/SH Gain Blue - 0 = 1x Gain, 1 = 2x Gain
[4:3]
[2]
Not used
Individual CDS/SH Gain Enable
0 Use Bit 0 for CDS/SH Gain
1 Use Bits 7:5 for CDS/SH Gains
[1]
[0]
Dual Gain Mode Enable
0 Single Gain Setting Within Each Line
1 Two Gain Settings Within Each Line
Gain Select
0 1x CDS/SH Gain - Default
1 2x CDS/SH Gain
1
1
1
1
1
2
3
4
1
2
3
4
0110 0001
0110 0001
0110 0001
1000 0000
[7:0]
[7:0]
[7:0]
[7:0]
Red PGA
Green PGA
Blue PGA
Default = 97d for Gain = 1
Default = 97d for Gain = 1
Default = 97d for Gain = 1
Red Even DAC MSB DAC[9:2]
Red Even DAC LSB Not Used
1
5
5
0000 0000
[7:2]
[1:0]
[7:0]
DAC[1:0]
1
1
6
7
6
7
1000 0000
0000 0000
Green Even DAC MSB DAC[9:2]
[7:2]
Green Even DAC LSB Not Used
[1:0]
[7:0]
DAC[1:0]
1
1
8
9
8
9
1000 0000
0000 0000
Blue Even DAC MSB DAC[9:2]
[7:2]
Blue Even DAC LSB Not Used
DAC[1:0]
[1:0]
[7:0]
1
1
10
11
A
B
1000 0000
0000 0000
Red Odd DAC MSB
Red Odd DAC LSB
DAC[9:2]
Not Used
DAC[1:0]
[7:2]
[1:0]
[7:0]
1
1
12
13
C
D
1000 0000
0000 0000
Green Odd DAC MSB DAC[9:2]
[7:2]
[1:0]
[7:0]
[7:2]
Green Odd DAC LSB Not Used
DAC[1:0]
1
1
14
15
E
F
1000 0000
0000 0000
Blue Odd DAC MSB DAC[9:2]
Blue Odd DAC LSB
Not Used
[1:0]
[7]
DAC[1:0]
Not Used
1
1
16
17
10
11
0100 0000
0100 0000
Red Even Digital
Offset
[6:0]
[7]
Digital Offset
Not Used
Green Even Digital
Offset
[6:0]
Digital Offset
112
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Table 18. Register Definition, Page 1 (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
BITS
[7]
REGISTER TITLE
REGISTER DESCRIPTION
1
1
1
1
1
18
19
20
21
22
12
13
14
15
16
0100 0000
0100 0000
0100 0000
0100 0000
0110 0001
Blue Even Digital
Offset
Not Used
[6:0]
[7]
Digital Offset
Not Used
Red Odd Digital
Offset
[6:0]
[7]
Digital Offset
Not Used
Green Odd Digital
Offset
[6:0]
[7]
Digital Offset
Not Used
Blue Odd Digital
Offset
[6:0]
[7:0]
Digital Offset
Red High Gain PGA PGA setting during high gain portion of line
when dual gain mode is enabled
Default = 97d for Gain = 1
1
1
1
1
1
1
23
24
28
29
30
31
17
18
1C
1D
1E
1F
0110 0001
0110 0001
0100 0000
0100 0000
0100 0000
0000 0000
[7:0]
[7:0]
Green High Gain PGA PGA setting during high gain portion of line
when dual gain mode is enabled
Default = 97d for Gain = 1
Blue High Gain PGA PGA setting during high gain portion of line
when dual gain mode is enabled
Default = 97d for Gain = 1
[7]
Red Channel Bimodal Not Used
[6:0]
Offset Binary digital Offset for Bimodal
Correction
[7]
Green Channel
Bimodal
Not Used
[6:0]
Offset Binary digital Offset for Bimodal
Correction
[7]
Blue Channel Bimodal Not Used
[6:0]
Offset Binary digital Offset for Bimodal
Correction
[3:0]
Page Register
Used to select desired page of registers being
accessed.
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Table 19. Register Definition, Page 2
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
BITS
[7:3]
[2]
REGISTER TITLE
REGISTER DESCRIPTION
2
0
0
0000 0000
Not Used
DDAC Disable
0 AFE output includes DDAC (digital DAC offset)
correction
1 AFE output does not include DDAC correction
Calibration
Mode
[1:0]
Calibration Mode
00 Black Calibration Only
01 White and Black Calibration - Full/Binary
White Cal
10 White and Black Calibration - Fine Tuning
11 Reserved
2
2
1
2
1
2
0000 0000
0001 0100
[7:0]
[5:4]
Calibration is active for this number of lines
0 Reserved
Calibration # Lines
Black Cal Config
Black Target
1d to 254d sets number of lines
255d sets infinite calibration
DDAC Scaling
00 Linear - 1 LSB adjust
01 Scaling = 1/2
10 Scaling = 1/4
11 Scaling = 1/8
[3:2]
[1:0]
ADAC Scaling
00 Reserved (No scaling)
01 Scaling = 1/2
10 Scaling = 1/4
11 Scaling = 1/8
Number of Black Pixels
Number of pixels averaged by Black Loop
00 4 pixels
01 8 pixels
10 16 pixels
11 32 pixels
2
3
3
0100 0000
[7:0]
Target level for Black calibration Range is 0 to
255 at 11 bit level or 0 to 8160 at 16 bit level
(default = 64 or 2048 at 16 bit level)
114
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Table 19. Register Definition, Page 2 (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
BITS
REGISTER TITLE
REGISTER DESCRIPTION
2
4
4
0100 0011
[6:3]
White Loop Tolerance
White Cal success if |White Peak - White Target|
< White Loop Tolerance 0 to 15 at 10 bit level -
Default = 8
[2:0]
Number of White Pixels
White Cal Config
Number of White Pixels processed in moving
window average to find White Peak in line
between White Pixels Start and White Pixels End
000 4 pixels
001 8 pixels
010 16 pixels
011 32 pixels - Default
White Target
2
5
5
1000 0000
[7:0]
White Target = 768d + [7:0] at 10 bit level
White Target
Range is 768d to 1023d at 10 bit level or 49152
to 65472 at 16 bit level
(Default = 896d or 57344 at 16 bit level)
2
2
2
2
2
2
2
2
2
2
6
6
7
0000 0100
0000 1100
0001 0000
0000 0000
0001 0100
0001 0000
0000 0000
0001 0000
0100 0000
0000 0000
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
AutoCLPIN Start
AutoCLPIN End
Black Loop Start
# of pixels from SH interval End to Start of Black
Pixel Clamping (Default = 4d)
7
# of pixels from SH interval End to End of Black
Pixel Clamping (Default = 12d)
8
8
# of pixels from SH interval End to Start of Black
Loop Pixels (Default = 16d)
9
9
Active/White Pixels
Start - MSB
# of Pixels between SH Interval End and first
Valid Data Pixel (Default = 64d)
10
11
12
13
14
15
A
B
C
D
E
F
Active/White Pixels
Start - LSB
Active/White Pixels
End - MSB
# of Pixels between SH Interval End and last
Valid Data Pixel (Default = 4096)
Active/White Pixels
End - LSB
Line Length MSB
# of Pixel Periods between beginning of
consecutive SH Intervals (Default = 4160)
Line Length LSB
# of Pixel Periods between beginning of
consecutive SH Intervals
[7:2]
[1:0]
Not Used
Multiplier factor for Active/White, LSPIX ON/OFF
and
Line Length Multiplier Line Length Pixels Register Settings
00 1x
01 2x
10 4x
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Table 19. Register Definition, Page 2 (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
BITS
[7]
REGISTER TITLE
REGISTER DESCRIPTION
2
16
10
0000 0000
Not Used
CIS - 2 Color Coefficient Select
6:5
Select which color PGA/DAC coefficients are
used in 2 color CIS sequences
00 Red and Green Lamp/Coefficients Used
01 Green and Blue Lamp/Coefficients Used
10 Red and Blue Lamp/Coefficients Used
11 Reserved
4:3
CCD/CIS Mode Select
00 Normal CCD Timing
01 CISa (2, 3, or 4 color sequences)
10 CISb (2 or 3 color sequences)
11 Reserved
Line Mode
[1:0]
# SH Intervals. How many different SH intervals
in a sequence of lines
00 1 SH Interval - Same SH timing every line
01 2 SH Intervals - 2 different SH interval timings
10 3 SH Intervals - 3 different SH interval timings
11 4 SH Intervals - 4 different SH interval timings
SH States are allocated as follows:
1 Interval 1 = 0 to 30
2 Interval 1 = 0 to 14, Interval 2 = 15 to 30
3 Int 1 = 0 to 9, Int 2 = 10 to 19, Int 3 = 20 to 30
4 Int 1 = 0 to 6, Int 2 = 7 to 14, Int 3 = 15 to 22,
Int 4 = 23 to 30
2
17
11
0000 0000
[7:3]
[2:0]
Not Used
SH State Length values are multiplied by this
factor
SH State Length
Multiplier
000 SH Timings x1
001 SH Timings x2
010 SH Timings x4
011 SH Timings x8
100 SH Timings x16
101 to 111 Reserved
116
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Table 19. Register Definition, Page 2 (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
BITS
[7:6]
[5]
REGISTER TITLE
REGISTER DESCRIPTION
2
18
12
0000 0000
Not Used
PHIA On Delay
0 Normal
1 PHIA begins 1 pixel period late
[4]
[3]
PHIA Off Delay
0 Normal
1 PHIA stops 1 pixel period late
PHIB On Delay
0 Normal
1 PHIB begins 1 pixel period late
PHIA/B/C Delays
[2]
[1]
[0]
PHIB Off Delay
0 Normal
1 PHIB stops 1 pixel period late
PHIC On Delay
0 Normal
1 PHIC begins 1 pixel period late
PHIC Off Delay
0 Normal
1 PHIC stops 1 pixel period late
Not Used
2
19
13
0000 0000
[7:4]
[3]
RS On Delay
0 Normal
1 RS begins 1 pixel period late
[2]
[1]
[0]
RS Off Delay
0 Normal
RS/CP Delays
1 RS stops 1 pixel period late
CP On Delay
0 Normal
1 CP begins 1 pixel period late
CP Off Delay
0 Normal
1 CP stops 1 pixel period late
2
2
20 to 23
24
14 to 17
18
Reserved
1111 1000
[7:5]
[4:3]
[2:0]
Master PLL Range Setting for PLL1 and PLL2
when Autorange is off. Set to 111.
PLL1 Charge Pump Current Control
Default = 11
PLL Control 1
PLL1 Filter Bandwidth Control
Default = 000
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Table 19. Register Definition, Page 2 (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
BITS
REGISTER TITLE
REGISTER DESCRIPTION
2
25
19
0001 1000
[7:5]
Reserved
Default = 000
[4:3]
PLL2 Charge Pump Current Control
Default = 11
PLL Control 2
Set to 00 when using SSCG.
[2:0]
[7:6]
PLL2 Filter Bandwidth Control
Default = 000
Set to 111 when using SSCG.
Spread Rate Multiplier
2
26
1A
0000 0000
(Increases modulation frequency in low pixel
frequency applications)
00 1x - Default
01 2x
10 4x (Page 2, Register D,E max = 32,768)
11 Reserved
[5]
SSCG Spread Boost
0 Normal, PLL divide step is 1/28
1 Boost, PLL divide step is 1/56. Narrower and
cleaner spread for 1ch and 2ch modes, but limits
max pixel freq to 25 MHz.
[4]
SSCG Spread Gain
0 Spread widths as specified in [3:2]
1 Spread widths are 2x [3:2] settings
[3:2]
SSCG Spread Width (Fmod = Fcenter+/-
Width/2)
SSCG Control 1
00 5%
01 2.5%
10 1.25%
11 0.625%
[1]
SSCG SH Sync Enable
0 Spread unsynched, once SSCG Enable is set,
SSCG wil begin immediately.
1 Spread synched to SH interval, once SSCG
Enable
is set, the SSCG will begin at the first SH
Interval.
[0]
SSCG Enable
0 Spread Disabled
1 Spread Enabled
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Table 19. Register Definition, Page 2 (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
BITS
REGISTER TITLE
REGISTER DESCRIPTION
2
27
1B
0000 0010
[7]
Load SSCG state machine
(SSCG Enable 0->1 also performs this function)
0 Normal
1 Load state machine (self clearing)
[6]
FIFO Reset at SH_R
0 FIFO is only reset when SSCG started
1 FIFO is reset at SH_R. Only useful in Slave
Mode with Spread LVDS Only set. Ensures that
FIFO counters are centered if SH_R period is
consistenly shorter or longer than Line Length
settings.
[5]
[4]
Spread Waveform Reset at SH_R
0 Spread waveform not reset by SH_R
1 Spread waveform reset by SH_R
SSCG Control 2
Override PLL2 Lock Detector
0 PLL2 Lock Detector Normal
1 Force PLL2 Lock Detect = 1. Set to 1 when
using SSCG.
[3]
Override PLL1 Lock Detector
0 PLL1 Lock Detector Normal
1 Force PLL1 Lock Detect = 1. Useful only if
using a large multiplication factor and a lot of jitter
is present in the source clock.
[2]
Spread MaxRate
0 Spread Normal
1 Force Spreading to highest modulation
frequency instead of tied to Line Length Setting.
[1:0]
PLL Mode Select
11 Spread All System Clocks, No Multiplication
10 PLLs and SSCG Disabled - Default
01 Spread All System Clocks, Multiplication
Enabled
00 Spread Output Clocks Only, Multiplication
Enabled
2
2
28
29
1C
1D
0000 0000
0000 0000
Clock Mult M
Clock Mult N
Multiplying PLL. Fout = Fin x M/N M =
mmmmmmmm + 1 (1 to 256)
Multiplying PLL. Fout = Fin x M/N N = nnnnnnnn
+ 1 (1 to 256)
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Table 19. Register Definition, Page 2 (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
BITS
REGISTER TITLE
REGISTER DESCRIPTION
2
30
1E
0000 0000
[7]
FIFO Reset
0 FIFO normal operating
1 Force reset of FIFO (self clearing)
SSCG Control 3
[6:0]
FIFO and Spread Waveform SH_R Reset Holdoff
Delay reset of FIFO and Spread Waveform from
0 to 127 ADC clock cycles after the internal
synchronized SH_R. To allow this event to occur
during SH Interval after all valid pixels in the
pipeline have been processed.
2
31
1F
[3:0]
Page Register
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Table 20. Register Definition, Page 3
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
BITS
REGISTER TITLE
REGISTER DESCRIPTION
3
3
3
3
3
3
3
3
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
[7:0]
SH State 0
Length
Sets length of this SH interval state
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
SH State 1
Length
Sets length of this SH interval state
Sets length of this SH interval state
Sets length of this SH interval state
Sets length of this SH interval state
Sets length of this SH interval state
Sets length of this SH interval state
Sets length of this SH interval state
SH State 2
Length
SH State 3
Length
SH State 4
Length
SH State 5
Length
SH State 6
Length
SH State 7
Length
3
3
3
3
8
9
8
9
0000 0000
0000 0000
0000 0000
0000 0000
[7:0]
[7:0]
[7:0]
[7:0]
SH State 8
Sets length of this SH interval state
Sets length of this SH interval state
Sets length of this SH interval state
Sets length of this SH interval state
Length
SH State 9
Length
10
11
A
B
SH State 10
Length
SH State 11
Length
3
3
3
3
3
3
3
3
3
3
3
3
3
3
12
13
14
15
16
17
18
19
20
21
22
23
24
25
C
D
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
SH State 12
Length
Sets length of this SH interval state
Sets length of this SH interval state
Sets length of this SH interval state
Sets length of this SH interval state
Sets length of this SH interval state
Sets length of this SH interval state
Sets length of this SH interval state
Sets length of this SH interval state
Sets length of this SH interval state
Sets length of this SH interval state
Sets length of this SH interval state
Sets length of this SH interval state
Sets length of this SH interval state
Sets length of this SH interval state
SH State 13
Length
E
SH State14
Length
F
SH State 15
Length
10
11
12
13
14
15
16
17
18
19
SH State 16
Length
SH State 17
Length
SH State 18
Length
SH State 19
Length
SH State 20
Length
SH State 21
Length
SH State 22
Length
SH State 23
Length
SH State 24
Length
SH State 25
Length
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Table 20. Register Definition, Page 3 (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
BITS
REGISTER TITLE
REGISTER DESCRIPTION
3
3
3
3
3
3
26
27
28
29
30
31
1A
1B
1C
1D
1E
1F
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
[7:0]
SH State 26
Length
Sets length of this SH interval state
[7:0]
[7:0]
[7:0]
[7:0]
[3:0]
SH State 27
Length
Sets length of this SH interval state
Sets length of this SH interval state
Sets length of this SH interval state
Sets length of this SH interval state
SH State 28
Length
SH State 29
Length
SH State 30
Length
Page Register
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Table 21. Register Definitions, Page 4
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
BITS
REGISTER TITLE
REGISTER DESCRIPTION
4
0
0
0000 0000
[7]
SH State 0
PHI, RS, CP
Controls whether these outputs are 1 or 0 during
this
SH interval state
RS 0 = Low, 1 = High 1 0 = Low, 1 = High
CP 0 = Low, 1 = High
[6]
[5]
PHIA2 0 = Low, 1 = High
PHIA1 0 = Low, 1 = High
PHIB2 0 = Low, 1 = High
PHIB1 0 = Low, 1 = High
PHIC2 0 = Low, 1 = High
PHIC1 0 = Low, 1 = High
[4]
[3]
[2]
[1]
[0]
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
1
2
1
2
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
[7:0]
SH State 1
PHI, RS, CP
Controls whether these outputs are 1 or 0 during
this SH interval state
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
SH State 2
PHI, RS, CP
Controls whether these outputs are 1 or 0 during
this SH interval state
3
3
SH State 3
PHI, RS, CP
Controls whether these outputs are 1 or 0 during
this SH interval state
4
4
SH State 4
PHI, RS, CP
Controls whether these outputs are 1 or 0 during
this SH interval state
5
5
SH State 5
PHI, RS, CP
Controls whether these outputs are 1 or 0 during
this SH interval state
6
6
SH State 6
PHI, RS, CP
Controls whether these outputs are 1 or 0 during
this SH interval state
7
7
SH State 7
PHI, RS, CP
Controls whether these outputs are 1 or 0 during
this SH interval state
8
8
SH State 8
PHI, RS, CP
Controls whether these outputs are 1 or 0 during
this SH interval state
9
9
SH State 9
PHI, RS, CP
Controls whether these outputs are 1 or 0 during
this SH interval state
10
11
12
13
14
15
16
17
18
19
A
B
C
D
E
F
SH State 10
PHI, RS, CP
Controls whether these outputs are 1 or 0 during
this SH interval state
SH State 11
PHI, RS, CP
Controls whether these outputs are 1 or 0 during
this SH interval state
SH State 12
PHI, RS, CP
Controls whether these outputs are 1 or 0 during
this SH interval state
SH State 13
PHI, RS, CP
Controls whether these outputs are 1 or 0 during
this SH interval state
SH State 14
PHI, RS, CP
Controls whether these outputs are 1 or 0 during
this SH interval state
SH State 15
PHI, RS, CP
Controls whether these outputs are 1 or 0 during
this SH interval state
10
11
12
13
SH State 16
PHI, RS, CP
Controls whether these outputs are 1 or 0 during
this SH interval state
SH State 17
PHI, RS, CP
Controls whether these outputs are 1 or 0 during
this SH interval state
SH State 18
PHI, RS, CP
Controls whether these outputs are 1 or 0 during
this SH interval state
SH State 19
PHI, RS, CP
Controls whether these outputs are 1 or 0 during
this SH interval state
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Table 21. Register Definitions, Page 4 (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
BITS
REGISTER TITLE
REGISTER DESCRIPTION
4
4
4
4
4
4
4
4
4
4
4
4
20
21
22
23
24
25
26
27
28
29
30
31
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
[7:0]
SH State 20
PHI, RS, CP
Controls whether these outputs are 1 or 0 during
this SH interval state
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[3:0]
SH State 21
PHI, RS, CP
Controls whether these outputs are 1 or 0 during
this SH interval state
SH State 22
PHI, RS, CP
Controls whether these outputs are 1 or 0 during
this SH interval state
SH State 23
PHI, RS, CP
Controls whether these outputs are 1 or 0 during
this SH interval state
SH State 24
PHI, RS, CP
Controls whether these outputs are 1 or 0 during
this SH interval state
SH State 25
PHI, RS, CP
Controls whether these outputs are 1 or 0 during
this SH interval state
SH State 26
PHI, RS, CP
Controls whether these outputs are 1 or 0 during
this SH interval state
SH State 27
PHI, RS, CP
Controls whether these outputs are 1 or 0 during
this SH interval state
SH State 28
PHI, RS, CP
Controls whether these outputs are 1 or 0 during
this SH interval state
SH State 29
PHI, RS, CP
Controls whether these outputs are 1 or 0 during
this SH interval state
SH State 30
PHI, RS, CP
Controls whether these outputs are 1 or 0 during
this SH interval state
Page Register
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Table 22. Register Definitions, Page 5
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
BITS
REGISTER TITLE
REGISTER DESCRIPTION
5
0
0
0000 0000
[7:5]
SH State 0
SH1-SH5
Not Used
Controls whether these outputs are 1 or 0 during
this SH interval state
[4]
[3]
SH5 0 = Low, 1 = High
SH4 0 = Low, 1 = High
SH3 0 = Low, 1 = High
SH2 0 = Low, 1 = High
SH1 0 = Low, 1 = High
[2]
[1]
[0]
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
1
2
1
2
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
[4:0]
SH State 1
SH1-SH5
Controls whether these outputs are 1 or 0 during
this SH interval state
[4:0]
[4:0]
[4:0]
[4:0]
[4:0]
[4:0]
[4:0]
[4:0]
[4:0]
[4:0]
[4:0]
[4:0]
[4:0]
[4:0]
[4:0]
[4:0]
[4:0]
[4:0]
[4:0]
[4:0]
[4:0]
[4:0]
SH State 2
SH1-SH5
Controls whether these outputs are 1 or 0 during
this SH interval state
3
3
SH State 3
SH1-SH5
Controls whether these outputs are 1 or 0 during
this SH interval state
4
4
SH State 4
SH1-SH5
Controls whether these outputs are 1 or 0 during
this SH interval state
5
5
SH State 5
SH1-SH5
Controls whether these outputs are 1 or 0 during
this SH interval state
6
6
SH State 6
SH1-SH5
Controls whether these outputs are 1 or 0 during
this SH interval state
7
7
SH State 7
SH1-SH5
Controls whether these outputs are 1 or 0 during
this SH interval state
8
8
SH State 8
SH1-SH5
Controls whether these outputs are 1 or 0 during
this SH interval state
9
9
SH State 9
SH1-SH5
Controls whether these outputs are 1 or 0 during
this SH interval state
10
11
12
13
14
15
16
17
18
19
20
21
22
23
A
SH State 10
SH1-SH5
Controls whether these outputs are 1 or 0 during
this SH interval state
B
SH State 11
SH1-SH5
Controls whether these outputs are 1 or 0 during
this SH interval state
C
D
E
SH State 12
SH1-SH5
Controls whether these outputs are 1 or 0 during
this SH interval state
SH State 13
SH1-SH5
Controls whether these outputs are 1 or 0 during
this SH interval state
SH State 14
SH1-SH5
Controls whether these outputs are 1 or 0 during
this SH interval state
F
SH State 15
SH1-SH5
Controls whether these outputs are 1 or 0 during
this SH interval state
10
11
12
13
14
15
16
17
SH State 16
SH1-SH5
Controls whether these outputs are 1 or 0 during
this SH interval state
SH State 17
SH1-SH5
Controls whether these outputs are 1 or 0 during
this SH interval state
SH State 18
SH1-SH5
Controls whether these outputs are 1 or 0 during
this SH interval state
SH State 19
SH1-SH5
Controls whether these outputs are 1 or 0 during
this SH interval state
SH State 20
SH1-SH5
Controls whether these outputs are 1 or 0 during
this SH interval state
SH State 21
SH1-SH5
Controls whether these outputs are 1 or 0 during
this SH interval state
SH State 22
SH1-SH5
Controls whether these outputs are 1 or 0 during
this SH interval state
SH State 23
SH1-SH5
Controls whether these outputs are 1 or 0 during
this SH interval state
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Table 22. Register Definitions, Page 5 (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
BITS
REGISTER TITLE
REGISTER DESCRIPTION
5
5
5
5
5
5
5
5
24
25
26
27
28
29
30
31
18
19
1A
1B
1C
1D
1E
1F
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
[4:0]
SH State 24
SH1-SH5
Controls whether these outputs are 1 or 0 during
this SH interval state
[4:0]
[4:0]
[4:0]
[4:0]
[4:0]
[4:0]
[3:0]
SH State 25
SH1-SH5
Controls whether these outputs are 1 or 0 during
this SH interval state
SH State 26
SH1-SH5
Controls whether these outputs are 1 or 0 during
this SH interval state
SH State 27
SH1-SH5
Controls whether these outputs are 1 or 0 during
this SH interval state
SH State 28
SH1-SH5
Controls whether these outputs are 1 or 0 during
this SH interval state
SH State 29
SH1-SH5
Controls whether these outputs are 1 or 0 during
this SH interval state
SH State 30
SH1-SH5
Controls whether these outputs are 1 or 0 during
this SH interval state
Page Register
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Table 23. Register Tables Page 6
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
REGISTER
TITLE
REGISTER
DESCRIPTION
BITS
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
0
0
1
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
[1:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[1:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[1:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[1:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[1:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:5]
PHIA0
PHIA1
PHIA2
PHIA3
PHIA4
PHIA5
PHIB0
PHIB1
PHIB2
PHIB3
PHIB4
PHIB5
PHIC0
PHIC1
PHIC2
PHIC3
PHIC4
PHIC5
RS0
Upper 2 MSb (first shifted out of HSTG)
1
Next 8
2
2
Next 8
3
3
Next 8
4
4
Next 8
5
5
Lower 8 LSb (last shifted out of HSTG)
6
6
Upper 2 MSb (first shifted out of HSTG)
7
7
Next 8
8
8
Next 8
9
9
Next 8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
Next 8
B
Lower 8 LSb (last shifted out of HSTG)
C
Upper 2 MSb (first shifted out of HSTG)
D
Next 8
E
Next 8
F
Next 8
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
Next 8
Lower 8 LSb (last shifted out of HSTG)
Upper 2 MSb (first shifted out of HSTG)
RS1
Next 8
RS2
Next 8
RS3
Next 8
RS4
Next 8
RS5
Lower 8 LSb (last shifted out of HSTG)
CP0
Upper 2 MSb (first shifted out of HSTG)
CP1
Next 8
CP2
Next 8
CP3
Next 8
CP4
Next 8
CP5
Lower 8 LSb (last shifted out of HSTG)
Not Used
Allows high speed generators to operate at 1/2
normal rate. So the full sequence will be clocked
out over 2 pixels instead of 1 pixel
HSPIX Rate
Select
[4]
[3]
PHIA 0 = Normal Rate, 1 = 1/2
Rate PHIB 0 = Normal Rate, 1 = 1/2
Rate PHIC 0 = Normal Rate, 1 = 1/2
Rate RS 0 = Normal Rate, 1 = 1/2
Rate CP 0 = Normal Rate, 1 = 1/2 Rate
[2]
[1]
[0]
6
31
1F
[3:0]
Page Register
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Table 24. Register Tables Page 7
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
REGISTER
TITLE
REGISTER
DESCRIPTION
BITS
SH1
PIXEL ON
MSB
MSB of Pixel count where this signal goes low to
high Range is 0 to 65535
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
0
1
0
1
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
SH1
PIXEL ON
LSB
LSB of Pixel count where this signal goes low to
high
SH1
PIXEL OFF
MSB
MSB of Pixel count where this signal goes high to
low Range is 0 to 65535
2
2
SH1
PIXEL OFF
LSB
LSB of Pixel count where this signal goes high to
low
3
3
SH2
PIXEL ON
MSB
MSB of Pixel count where this signal goes low to
high Range is 0 to 65535
4
4
SH2
PIXEL ON
LSB
LSB of Pixel count where this signal goes low to
high
5
5
SH2
PIXEL OFF
MSB
MSB of Pixel count where this signal goes high to
low Range is 0 to 65535
6
6
SH2
PIXEL OFF
LSB
LSB of Pixel count where this signal goes high to
low
7
7
SH3
PIXEL ON
MSB
MSB of Pixel count where this signal goes low to
high Range is 0 to 65535
8
8
SH3
PIXEL ON
LSB
LSB of Pixel count where this signal goes low to
high
9
9
SH3
PIXEL OFF
MSB
MSB of Pixel count where this signal goes high to
low Range is 0 to 65535
10
11
12
13
14
15
16
17
18
A
B
C
D
E
F
SH3
PIXEL OFF
LSB
LSB of Pixel count where this signal goes high to
low
SH4
PIXEL ON
MSB
MSB of Pixel count where this signal goes low to
high Range is 0 to 65535
SH4
PIXEL ON
LSB
LSB of Pixel count where this signal goes low to
high
SH4
PIXEL OFF
MSB
MSB of Pixel count where this signal goes high to
low Range is 0 to 65535
SH4
PIXEL OFF
LSB
LSB of Pixel count where this signal goes high to
low
SH5
PIXEL ON
MSB
MSB of Pixel count where this signal goes low to
high Range is 0 to 65535
10
11
12
SH5
PIXEL ON
LSB
LSB of Pixel count where this signal goes low to
high
SH5
PIXEL OFF
MSB
MSB of Pixel count where this signal goes high to
low Range is 0 to 65535
128
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Table 24. Register Tables Page 7 (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
REGISTER
TITLE
REGISTER
DESCRIPTION
BITS
SH5
PIXEL OFF
LSB
LSB of Pixel count where this signal goes high to
low
7
7
19
20
13
14
0000 0000
0000 0000
[7:0]
[7:4]
[3]
Not Used
Polarity Override Line 3
0 Signal Not Inverted
1 Signal Inverted
PHIA Polarity
Override
[2]
[1]
Polarity Override Line 2
Polarity Override Line 1
[0]
Polarity Override Line 0
Not Used
7
21
15
0000 0000
[7:4]
[3]
Polarity Override Line 3
0 Signal Not Inverted
1 Signal Inverted
PHIB Polarity
Override
[2]
[1]
Polarity Override Line 2
Polarity Override Line 1
[0]
Polarity Override Line 0
Not Used
7
22
16
0000 0000
[7:4]
[3]
Polarity Override Line 3
0 Signal Not Inverted
1 Signal Inverted
PHIC Polarity
Override
[2]
[1]
Polarity Override Line 2
Polarity Override Line 1
[0]
Polarity Override Line 0
Not Used
7
23
17
0000 0000
[7:4]
[3]
Polarity Override Line 3
0 Signal Not Inverted
1 Signal Inverted
RS Polarity
Override
[2]
[1]
Polarity Override Line 2
Polarity Override Line 1
[0]
Polarity Override Line 0
Not Used
7
24
18
0000 0000
[7:4]
[3]
Polarity Override Line 3
0 Signal Not Inverted
1 Signal Inverted
CP Polarity
Override
[2]
[1]
[0]
Polarity Override Line 2
Polarity Override Line 1
Polarity Override Line 0
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Table 24. Register Tables Page 7 (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
REGISTER
TITLE
REGISTER
DESCRIPTION
BITS
[7:4]
[3]
7
7
7
7
7
25
26
27
28
29
19
1A
1B
1C
1D
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
Not Used
Polarity Override Line 3
0 Signal Not Inverted
1 Signal Inverted
SH1 Polarity
Override
[2]
[1]
Polarity Override Line 2
Polarity Override Line 1
[0]
Polarity Override Line 0
Not Used
[7:4]
[3]
Polarity Override Line 3
0 Signal Not Inverted
1 Signal Inverted
SH2 Polarity
Override
[2]
[1]
Polarity Override Line 2
Polarity Override Line 1
[0]
Polarity Override Line 0
Not Used
[7:4]
[3]
Polarity Override Line 3
0 Signal Not Inverted
1 Signal Inverted
SH3 Polarity
Override
[2]
[1]
Polarity Override Line 2
Polarity Override Line 1
[0]
Polarity Override Line 0
Not Used
[7:4]
[3]
Polarity Override Line 3
0 Signal Not Inverted
1 Signal Inverted
SH4 Polarity
Override
[2]
[1]
Polarity Override Line 2
Polarity Override Line 1
[0]
Polarity Override Line 0
Not Used
[7:4]
[3]
Polarity Override Line 3
0 Signal Not Inverted
1 Signal Inverted
SH5 Polarity
Override
[2]
[1]
[0]
Polarity Override Line 2
Polarity Override Line 1
Polarity Override Line 0
7
7
30
31
1E
1F
Reserved
[3:0]
Page Register
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Table 25. Register Definition, Page 8
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
REGISTER
TITLE
REGISTER
DESCRIPTION
BITS
[7]
8
8
8
0
1
2
0
1
2
0000 0000
0000 0000
0000 0000
Not Used
[6]
PHIA1 Active (0 = Tristate, 1* = Active)
[5]
PHIA1 Source (0* = Timing, 1 = DC logic 1)
PHIA1 Polarity (0* = Not Inverted, 1 = Inverted)
[4]
PHIA1,
PHIA2,
Polarity /
State
[3]
Not Used
[2]
[1]
PHIA2 Active (0 = Tristate, 1* = Active)
PHIA2 Source (0* = Timing, 1 = DC logic 1)
[0]
[7]
PHIA2 Polarity (0* = Not Inverted, 1 = Inverted)
Not Used
[6]
[5]
[4]
PHIB1 Active (0 = Tristate, 1* = Active) PHIB1
Source (0* = Timing, 1 = DC logic 1) PHIB1
Polarity (0* = Not Inverted, 1 = Inverted)
PHIB1,
PHIB2,
Polarity /
State
[3]
Not Used
[2]
[1]
PHIB2 Active (0 = Tristate, 1* = Active)
PHIB2 Source (0* = Timing, 1 = DC logic 1)
[0]
[7]
PHIB2 Polarity (0* = Not Inverted, 1 = Inverted)
Not Used
[6]
[5]
[4]
PHIC1 Active (0 = Tristate, 1* = Active)
PHIC1 Source (0* = Timing, 1 = DC logic 1)
PHIC1 Polarity (0* = Not Inverted, 1 = Inverted)
PHIC1
PHIC2
[3]
Polarity /
State
Not Used
[2]
[1]
[0]
PHIC2 Active (0 = Tristate, 1* = Active)
PHIC2 Source (0* = Timing, 1 = DC logic 1)
PHIC2 Polarity (0* = Not Inverted, 1 = Inverted)
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Table 25. Register Definition, Page 8 (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
REGISTER
TITLE
REGISTER
DESCRIPTION
BITS
[7]
8
3
3
0000 0000
Not Used
RS Active (0 = Tristate, 1* = Active)
[6]
[5]
RS Source (0* = Timing, 1 = DC logic 1)
RS Polarity (0* = Not Inverted, 1 = Inverted)
[4]
RS, CP
Polarity /
State
[3]
Not Used
[2]
[1]
CP Active (0 = Tristate, 1* = Active)
CP Source (0* = Timing, 1 = DC logic 1)
[0]
[7]
CP Polarity (0* = Not Inverted, 1 = Inverted)
Not Used
8
4
4
0000 0000
[6]
[5]
[4]
SH1 Active (0 = Tristate, 1* = Active)
SH1 Source (0* = Timing, 1 = DC logic 1)
SH1 Polarity (0* = Not Inverted, 1 = Inverted)
SH1, SH2
Polarity /
State
[3]
[2]
[1]
Not Used
SH2 Active (0 = Tristate, 1* = Active)
SH2 Source (0* = Timing, 1 = DC logic 1)
[0]
[7]
SH2 Polarity (0* = Not Inverted, 1 = Inverted)
Not Used
8
5
5
0000 0000
[6]
[5]
[4]
SH3 Active (0 = Tristate, 1* = Active)
SH3 Source (0* = Timing, 1 = DC logic 1)
SH3 Polarity (0* = Not Inverted, 1 = Inverted)
SH3, SH4
Polarity /
State
[3]
[2]
[1]
[0]
Not Used
SH4 Active (0 = Tristate, 1* = Active)
SH4 Source (0* = Timing, 1 = DC logic 1)
SH4 Polarity (0* = Not Inverted, 1 = Inverted)
132
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Table 25. Register Definition, Page 8 (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
REGISTER
TITLE
REGISTER
DESCRIPTION
BITS
[7]
8
6
6
0000 0000
Not Used
[6]
SH5 Active (0 = Tristate, 1* = Active)
SH5
Polarity /
State
[5]
SH5 Source (0* = Timing, 1 = DC logic 1)
[4]
SH5 Polarity (0* = Not Inverted, 1 = Inverted)
Not Used
[3:0]
[7:0]
[7]
8
8
7
8
7
8
0000 0000
0010 0000
Reserved
LVDS TXCLK Disable
0 LVDS TXCLK Enabled - Default
1 LVDS TXCLK Disabled
[6]
CMOS CLKOUT Disable
0 CMOS CLKOUT Enabled - Default
1 CMOS CLKOUT Disabled
[5:4]
LVDS Drive Adjust
00 Reduce 100 mV
01 Reduce 50 mV
10 Default
11 Increase 50 mV
[3]
[2]
[1]
[0]
LVDS
LVDS TXCLK Delay
0 TXCLK timing normal
1 TXCLK delayed
Configuration
BOL CB Bit Latency
0 Normal Compensation
1 No latency compensation
LVDS Disable TXOUT0
0 TXOUT0 LVDS Pair Enabled
1 TXOUT0 LVDS Pair Disabled
LVDS Mode Select
0 LM98714
1 Flexible CB Mapping
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Table 25. Register Definition, Page 8 (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
REGISTER
TITLE
REGISTER
DESCRIPTION
BITS
8
9
9
0000 0000
Selects CB Bit Mapping
[7:4]
CB1 Mapping
0000 CBO1 from LM98714 definition
0001 CBO0 from LM98714 definition
0010 CBO1 from LM98714 definition
0011 CBO2 from LM98714 definition
0100 CBO3 from LM98714 definition
0101 CBO4 from LM98714 definition
0110 R - High for a red channel pixel
0111 G - High for a green channel pixel
1000 B - High for a blue channel pixel
1001 Parity - 21 bit if TXOUT0 enabled, 14 bit if
TXOUT0 disabled
1010 Ping - High for pixels processed by the Ping
section of a channel, low for Pong
1011 Line#lsb - Line = 0 to 3 for lines 0 to 3 in
multiline sequences
1100 Line#msb
1101 Black Loop Pixels - High for pixels
processed by the Black Loop
1110 ActiveWhite Loop Pixels - High for pixels
processed by the White Loop
1111 CLP Pixels - High for pixels where the input
CLP switch is closed
CB1/CB0 CB
Mapping
[3:0]
CB0 Mapping
0000 CBO0 from LM98714 definition
0001 CBO0 from LM98714 definition
0010 CBO1 from LM98714 definition
0011 CBO2 from LM98714 definition
0100 CBO3 from LM98714 definition
0101 CBO4 from LM98714 definition
0110 R - High for a red channel pixel
0111 G - High for a green channel pixel
1000 B - High for a blue channel pixel
1001 Parity - 21 bit if TXOUT0 enabled, 14 bit if
TXOUT0 disabled
1010 Ping - High for pixels processed by the Ping
section of a channel, low for Pong
1011 Line#lsb - Line = 0 to 3 for lines 0 to 3 in
multiline sequences
1100 Line#msb
1101 Black Loop Pixels - High for pixels
processed by the Black Loop
1110 ActiveWhite Loop Pixels - High for pixels
processed by the White Loop
1111 CLP Pixels - High for pixels where the input
CLP switch is closed
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Table 25. Register Definition, Page 8 (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
REGISTER
TITLE
REGISTER
DESCRIPTION
BITS
8
10
A
0000 0000
Selects CB Bit Mapping
[7:4]
CB3 Mapping
0000 CBO30 from LM98714 definition
0001 CBO0 from LM98714 definition
0010 CBO1 from LM98714 definition
0011 CBO2 from LM98714 definition
0100 CBO3 from LM98714 definition
0101 CBO4 from LM98714 definition
0110 R - High for a red channel pixel
0111 G - High for a green channel pixel
1000 B - High for a blue channel pixel
1001 Parity - 21 bit if TXOUT0 enabled, 14 bit if
TXOUT0 disabled
1010 Ping - High for pixels processed by the Ping
section of a channel, low for Pong
1011 Line#lsb - Line = 0 to 3 for lines 0 to 3 in
multiline sequences
1100 Line#msb
1101 Black Loop Pixels - High for pixels
processed by the Black Loop
1110 ActiveWhite Loop Pixels - High for pixels
processed by the White Loop
CB3/CB2 CB
Mapping
1111 CLP Pixels - High for pixels where the input
CLP switch is closed
[3:0]
CB2 Mapping
0000 CBO2 from LM98714 definition
0001 CBO0 from LM98714 definition
0010 CBO1 from LM98714 definition
0011 CBO2 from LM98714 definition
0100 CBO3 from LM98714 definition
0101 CBO4 from LM98714 definition
0110 R - High for a red channel pixel
0111 G - High for a green channel pixel
1000 B - High for a blue channel pixel
1001 Parity - 21 bit if TXOUT0 enabled, 14 bit if
TXOUT0 disabled
1010 Ping - High for pixels processed by the Ping
section of a channel, low for Pong
1011 Line#lsb - Line = 0 to 3 for lines 0 to 3 in
multiline sequences
1100 Line#msb
1101 Black Loop Pixels - High for pixels
processed by the Black Loop
1110 ActiveWhite Loop Pixels - High for pixels
processed by the White Loop
1111 CLP Pixels - High for pixels where the input
CLP switch is closed
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Table 25. Register Definition, Page 8 (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
REGISTER
TITLE
REGISTER
DESCRIPTION
BITS
8
11
B
0000 0000
Selects CB Bit Mapping
D2 Mapping
[7:4]
0000 D2 (Normal output for particular bit position)
0001 CBO0 from LM98714 definition
0010 CBO1 from LM98714 definition
0011 CBO2 from LM98714 definition
0100 CBO3 from LM98714 definition
0101 CBO4 from LM98714 definition
0110 R - High for a red channel pixel
0111 G - High for a green channel pixel
1000 B - High for a blue channel pixel
1001 Parity - 21 bit if TXOUT0 enabled, 14 bit if
TXOUT0 disabled
1010 Ping - High for pixels processed by the Ping
section of a channel, low for Pong
1011 Line#lsb - Line = 0 to 3 for lines 0 to 3 in
multiline sequences
1100 Line#msb
1101 Black Loop Pixels - High for pixels
processed by the Black Loop
1110 Active White Loop Pixels - High for pixels
processed by the White Loop
D2/CB4 CB
Mapping
1111 CLP Pixels - High for pixels where the input
CLP switch is closed
[3:0]
CB4 Mapping
0000 CBO4 from LM98714 definition
0001 CBO0 from LM98714 definition
0010 CBO1 from LM98714 definition
0011 CBO2 from LM98714 definition
0100 CBO3 from LM98714 definition
0101 CBO4 from LM98714 definition
0110 R - High for a red channel pixel
0111 G - High for a green channel pixel
1000 B - High for a blue channel pixel
1001 Parity - 21 bit if TXOUT0 enabled, 14 bit if
TXOUT0 disabled
1010 Ping - High for pixels processed by the Ping
section of a channel, low for Pong
1011 Line#lsb - Line = 0 to 3 for lines 0 to 3 in
multiline sequences
1100 Line#msb
1101 Black Loop Pixels - High for pixels
processed by the Black Loop
1110 ActiveWhite Loop Pixels - High for pixels
processed by the White Loop
1111 CLP Pixels - High for pixels where the input
CLP switch is closed
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Table 25. Register Definition, Page 8 (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
REGISTER
TITLE
REGISTER
DESCRIPTION
BITS
8
12
C
0000 0000
Selects CB Bit Mapping
[7:4]
D4 Mapping
0000 D4 (Normal output for particular bit position)
0001 CBO0 from LM98714 definition
0010 CBO1 from LM98714 definition
0011 CBO2 from LM98714 definition
0100 CBO3 from LM98714 definition
0101 CBO4 from LM98714 definition
0110 R - High for a red channel pixel
0111 G - High for a green channel pixel
1000 B - High for a blue channel pixel
1001 Parity - 21 bit if TXOUT0 enabled, 14 bit if
TXOUT0 disabled
1010 Ping - High for pixels processed by the Ping
section of a channel, low for Pong
1011 Line#lsb - Line = 0 to 3 for lines 0 to 3 in
multiline sequences
1100 Line#msb
1101 Black Loop Pixels - High for pixels
processed by the Black Loop
1110 ActiveWhite Loop Pixels - High for pixels
processed by the White Loop
1111 CLP Pixels - High for pixels where the input
CLP switch is closed
D4/D3 CB
Mapping
[3:0]
D3 Mapping
0000 D4 (Normal output for particular bit position)
0001 CBO0 from LM98714 definition
0010 CBO1 from LM98714 definition
0011 CBO2 from LM98714 definition
0100 CBO3 from LM98714 definition
0101 CBO4 from LM98714 definition
0110 R - High for a red channel pixel
0111 G - High for a green channel pixel
1000 B - High for a blue channel pixel
1001 Parity - 21 bit if TXOUT0 enabled, 14 bit if
TXOUT0 disabled
1010 Ping - High for pixels processed by the Ping
section of a channel, low for Pong
1011 Line#lsb - Line = 0 to 3 for lines 0 to 3 in
multiline sequences
1100 Line#msb
1101 Black Loop Pixels - High for pixels
processed by the Black Loop
1110 ActiveWhite Loop Pixels - High for pixels
processed by the White Loop
1111 CLP Pixels - High for pixels where the input
CLP switch is closed
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Table 25. Register Definition, Page 8 (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
REGISTER
TITLE
REGISTER
DESCRIPTION
BITS
[7:4]
[3:0]
8
13
D
0000 0000
Not Used
Selects CB Bit Mapping
D5 Mapping
0000 D5 (Normal output for particular bit position)
0001 CBO0 from LM98714 definition
0010 CBO1 from LM98714 definition
0011 CBO2 from LM98714 definition
0100 CBO3 from LM98714 definition
0101 CBO4 from LM98714 definition
0110 R - High for a red channel pixel
0111 G - High for a green channel pixel
1000 B - High for a blue channel pixel
D5 CB
1001 Parity - 21 bit if TXOUT0 enabled, 14 bit if
TXOUT0 disabled
Mapping
1010 Ping - High for pixels processed by the Ping
section of a channel, low for Pong
1011 Line#lsb - Line = 0 to 3 for lines 0 to 3 in
multiline sequences
1100 Line#msb
1101 Black Loop Pixels - High for pixels
processed by the Black Loop
1110 ActiveWhite Loop Pixels - High for pixels
processed by the White Loop
1111 CLP Pixels - High for pixels where the input
CLP switch is closed
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Table 25. Register Definition, Page 8 (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
REGISTER
TITLE
REGISTER
DESCRIPTION
BITS
Select level of CLK outputs during register
updating (UNLOCK state)
8
14
E
0000 0000
These can be modified during LOCK state to
allow user to set up chip for what happens during
the next UNLOCK state
[7]
[6]
[5]
PHIA1 Unlock State
0 = Low, 1 = High
PHIA2 Unlock State
0 = Low, 1 = High
Unlock State
Output Values
PHIA, PHIB,
PHIB1 Unlock State
0 = Low, 1 = High
[4]
[3]
[2]
[1]
PHIC, RS, CP
PHIB2 Unlock State
0 = Low, 1 = High
PHIC1 Unlock State
0 = Low, 1 = High
PHIC2 Unlock State
0 = Low, 1 = High
RS Unlock State
0 = Low, 1 = High
[0]
CP Unlock State
0 = Low, 1 = High
Not Used
8
15
F
0000 0000
[7:5]
Select level of CLK outputs during register
updating (UNLOCK state)
These can be modified during LOCK state to
allow user to set up chip for what happens during
the next UNLOCK state
[4]
SH1 Unlock State
0 = Low, 1 = High
Unlock State
Output Values
SH1, SH2,
[3]
[2]
[1]
[0]
SH2 Unlock State
0 = Low, 1 = High
SH3, SH4, SH5
SH3 Unlock State
0 = Low, 1 = High
SH4 Unlock State
0 = Low, 1 = High
SH5 Unlock State
0 = Low, 1 = High
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Table 25. Register Definition, Page 8 (continued)
PAGE
(dec)
ADDR
(dec)
ADDR
(hex)
DEFAULT
(binary)
REGISTER
TITLE
REGISTER
DESCRIPTION
BITS
8
8
16 to 17
18
10 to 11
12
0000 0000
0000 0000
Reserved
[7]
Reserved
Inhibit Scrambling Individual LVDS Bits if 1.
Do Not Scramble LVDS[6]
Do Not Scramble LVDS[5]
Do Not Scramble LVDS[4]
Do Not Scramble LVDS[3]
Do Not Scramble LVDS[2]
Do Not Scramble LVDS[1]
Do Not Scramble LVDS[0]
Reserved
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[7]
Scrambler
Inhibit 0
8
19
13
0000 0000
Inhibit Scrambling Individual LVDS Bits if 1.
Do Not Scramble LVDS[13]
Do Not Scramble LVDS[12]
Do Not Scramble LVDS[11]
Do Not Scramble LVDS[10]
Do Not Scramble LVDS[9]
Do Not Scramble LVDS[8]
Do Not Scramble LVDS[7]
Reserved
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[7]
Scrambler
Inhibit 1
8
20
14
0000 0000
Inhibit Scrambling Individual LVDS Bits if 1.
Do Not Scramble LVDS[20]
Do Not Scramble LVDS[19]
Do Not Scramble LVDS[18]
Do Not Scramble LVDS[17]
Do Not Scramble LVDS[16]
Do Not Scramble LVDS[15]
Do Not Scramble LVDS[14]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Scrambler
Inhibit 2
8
8
21 to 30
31
15 to 1E 0000 0000
1F
Reserved
[3:0]
Page Register
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8 Layout
8.1 Layout Example
U1A 74AC04/SO
1
TP1
1
R1 150
R2 4.7
R3 4.7
R4 4.7
2
6
U1B 74AC04/SO
3
TEST POINT
TP2
4
1
U1C 74AC04/SO
5
TEST POINT
U1D 74AC04/SO
9
8
TP3
U1E 74AC04/SO
11
1
R5 10
10
TEST POINT
U1F 74AC04/SO
13
R6 10
12
U2A 74AC04/SO
1
R7 10
R8 4.7
R10 4.7
R11 4.7
2
6
U2B 74AC04/SO
3
U3
DS90CR218A/SO
U7
LM98722
8
9
RXIN0-
4
1
2
3
56
55
54
53
52
51
50
49
48
47
46
45
PHIC2
PHIC1
SH1
SH5
SH4
PHIB2
PHIB1
VC
DGND
PHIA2
PHIA1
CP
U2C 74AC04/SO
5
R9
100
U5
12
13
14
15
16
17
18
19
20
21
22
11
PHI-TG2
GND
PHI-TG3
PHI-2
PHI-1
NC
10
9
8
7
6
5
4
3
2
1
U2D 74AC04/SO
9
VC
PHI-TG1
PHI-1
PHI-2
NC
PHI-2
NC
PHI-SEL
V0D
VOUT1
VOUT2
RXIN0+
RXIN1-
CE
CAL
4
5
6
7
8
9
10
11
10
CE
CAL
RESET
SH_R
SDI
SDO
SCLK
SEN
8
24
26
27
29
30
31
33
34
35
37
39
40
41
43
45
46
47
1
RXOUT0
+12V
RESET#
SH_R
R12
100
RXOUT1
RXOUT2
RXOUT3
RXOUT4
RXOUT5
RXOUT6
RXOUT7
RXOUT8
RXOUT9
RXOUT10
RXOUT11
RXOUT12
RXOUT13
RXOUT14
RXOUT15
RXOUT16
RXOUT17
RXOUT18
RXOUT19
RXOUT20
U2E 74AC04/SO
11
NC
R13 47
R14 47
PHI-1
PHI-CLB
PHI-R
GND
RS
SH3
CLKOUT/SH2
10
SDIO
SCLK
SEN#
11
14
RXIN1+
RXIN2-
U2F 74AC04/SO
13
12
44
43
42
R15
100
VC
VD
VOUT3
VC
VD
DGND
12
13
14
15
16
17
18
19
20
21
VA
VA
AGND
VA
VREFB
VREFT
VA
AGND
VCLP
VA
C1
47uF/25V
C2
15
16
RXIN2+
0.1u
VREFB
VREFT
41
40
39
38
37
36
35
34
D0_TXOUT0-
D1_TXOUT0+
D2_TXOUT1-
D3_TXOUT1+
D4_TXOUT2-
D5_TXOUT2+
D6_TXCLK-
RXCLKIN-
TP4
1
R16
100
VCLP
R27
9.0k 1%
R17
100
C3
R18
100
C4
47uF/25V
R19
100
C5
47uF/25V
17
IBIAS
RXCLKIN+
PDN
47uF/25V
2
D7_TXCLK+
22
23
24
25
26
27
28
22
4
5
AGND
OSr
AGND
OSg
AGND
OSb
CPOFILT2
33
32
INCLK-
INCLK+
Q1
R20 2SC945
Q2
R21 2SC945
Q3
R22 2SC945
C6
C7
C8
tbd
tbd
tbd
12
20
7
13
18
19
21
LVDSVCC
PLLVCC
LVDSGND
LVDSGND
LVDSGND
PLLGND
23
RXCLKOUT
31
30
29
DVB
CPOFILT1
DGND
100
100
100
C10
0.1uF
PLLGND
C20
0.1
R23
2k
R24
2k
R25
2k
INCLK-
INCLK+
TP5 TP6 TP7
R26
100
J1
Pin 12
Pin 15
Pin 18
Pin 21
VA
Pin 44
Pin 52
Install 100 Ohm for LVDS INCLK.
Install solder jumper for CMOS
INCLK
VA
VA
VA
VD
VC
VCLP
VREFB
VREFT
C13
0.1uF
C14
0.1uF
C15
0.1uF
C15
0.1uF
C16
0.1uF
C17
0.1uF
C18
0.1uF
C11
C19
0.1uF
C12
0.1uF
4.7uF
Figure 65. Example Application Circuit
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9 Device and Documentation Support
9.1 Device Support
For additional information, see Texas Instruments' E2E community resources: http://e2e.ti.com.
9.2 Trademarks
All trademarks are the property of their respective owners.
9.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
9.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LM98722CCMT/NOPB
LM98722CCMTX/NOPB
ACTIVE
ACTIVE
TSSOP
TSSOP
DGG
DGG
56
56
34
RoHS & Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
0 to 70
0 to 70
LM98722CCMT
LM98722CCMT
1000 RoHS & Green
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM98722CCMTX/NOPB TSSOP
DGG
56
1000
330.0
24.4
8.6
14.5
1.8
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP DGG 56
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
LM98722CCMTX/NOPB
1000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
DGG TSSOP
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LM98722CCMT/NOPB
56
34
495
10
2540
5.79
Pack Materials-Page 3
PACKAGE OUTLINE
DGG0056A
TSSOP - 1.2 mm max height
S
C
A
L
E
1
.
2
0
0
SMALL OUTLINE PACKAGE
C
8.3
7.9
SEATING PLANE
TYP
PIN 1 ID
AREA
0.1 C
A
54X 0.5
56
1
14.1
13.9
NOTE 3
2X
13.5
28
B
29
0.27
0.17
6.2
6.0
56X
1.2 MAX
0.08
C A
B
(0.15) TYP
0.25
GAGE PLANE
0 - 8
SEE DETAIL A
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4222167/A 07/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
DGG0056A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
56X (1.5)
SYMM
1
56
56X (0.3)
54X (0.5)
(R0.05)
TYP
SYMM
28
29
(7.5)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
METAL
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222167/A 07/2015
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DGG0056A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
56X (1.5)
SYMM
1
56
56X (0.3)
54X (0.5)
(R0.05) TYP
SYMM
28
29
(7.5)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4222167/A 07/2015
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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