LMG1025-Q1 [TI]
适用于窄脉冲应用、具有 5V UVLO 的汽车类 7A/5A 单通道低侧栅极驱动器;
| 型号： | LMG1025-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于窄脉冲应用、具有 5V UVLO 的汽车类 7A/5A 单通道低侧栅极驱动器 栅极驱动 脉冲 驱动器 |
| 文件： | 总25页 (文件大小：1390K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMG1025-Q1
SNOSD74B –MAY 2019–REVISED JANUARY 2020
LMG1025-Q1 Automotive Low Side GaN and MOSFET Driver
For High Frequency and Narrow Pulse Applications
1 Features
3 Description
The LMG1025-Q1 is a single channel low-side
1
•
•
•
•
•
•
AEC-Q100 grade 1 qualified
enhancement-mode GaN FET and logic-level
MOSFET driver for high switching frequency
automotive applications. Narrow pulse width
capability, fast switching specification, and small
pulse distortion combine to significantly enhance
LiDAR, ToF, and Power Converter performance.
1.25-ns output pulse width enables more powerful,
eye-safe diode pulses. This, combined with 300-ns
distortion, leads to longer-range, precise LiDAR/ToF
systems. 2.9-ns propagation delay significantly
improves the control loop response time and thus
overall performance of the power converters. Split
output allows the drive strength and timing to be
independently adjusted through external resistors
between OUTH, OUTL, and the FET gate.
1.25-ns typical minimum input pulse width
2.6-ns typical rising propagation delay
2.9-ns typical falling propagation delay
300-ps typical pulse distortion
Independent 7-A pull-up and 5-A pull-down
current
•
•
•
•
•
•
650-ps typical rise time (220-pF load)
850-ps typical fall time (220-pF load)
2-mm x 2-mm QFN package
Inverting and non-inverting inputs
UVLO and over-temperature protection
Single 5-V supply voltage
The driver features undervoltage lockout (UVLO) and
over-temperature protection (OTP) to ensure the
device is not damaged in overload or fault conditions.
LMG1025-Q1 is available in a compact, leadless,
AEC-Q100 automotive qualified package to meet the
size and gate loop inductance requirements of high
switching frequency automotive applications.
2 Applications
•
•
•
•
Automotive LIDAR
Driver Monitoring
Vehicle Occupant Detection Sensor
DC/DC Converter
Device Information(1)
BODY SIZE (NOM)
PART NUMBER
PACKAGE
(mm)
LMG1025-Q1
WSON(6)
2-mm x 2-mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical (Simplified) System Diagram
+5 V
Vbus
LMG1025-Q1
R1
OUTH
VDD
IN+
R2
OUTL
PWM
GaN
INœ
EN
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMG1025-Q1
SNOSD74B –MAY 2019–REVISED JANUARY 2020
www.ti.com
Table of Contents
7.3 Feature Description................................................... 7
7.4 Device Functional Modes.......................................... 8
Application and Implementation .......................... 9
8.1 Application Information.............................................. 9
8.2 Typical Application ................................................... 9
Power Supply Recommendations...................... 15
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 5
6.7 Typical Characteristics.............................................. 6
Detailed Description .............................................. 7
7.1 Overview ................................................................... 7
7.2 Functional Block Diagram ......................................... 7
8
9
10 Layout................................................................... 16
10.1 Layout Guidelines ................................................. 16
10.2 Layout Example .................................................... 16
11 Device and Documentation Support ................. 17
11.1 Receiving Notification of Documentation Updates 17
11.2 Support Resources ............................................... 17
11.3 Trademarks........................................................... 17
11.4 Electrostatic Discharge Caution............................ 17
11.5 Glossary................................................................ 17
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
Changes from Revision A (August 2019) to Revision B
Page
•
Changed marketing status from Advance Information to Production Data ............................................................................ 1
2
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SNOSD74B –MAY 2019–REVISED JANUARY 2020
5 Pin Configuration and Functions
DEE
6-Pin WSON
Top View
Pin Functions
PIN
I/O(1)
DESCRIPTION
NAME
GND
IN+
NO.
2
G
I
Power supply and source return. Connect with a direct path to the transistor’s source.
Positive logic-level input.
1
IN–
6
I
Negative logic-level input.
Pull-down gate drive output. Connect through an optional resistor to the target transistor’s
gate.
OUTL
5
O
OUTH
VDD
4
3
O
P
Pull-up gate drive output. Connect through a resistor to the target transistor’s gate.
Input voltage supply. Decouple through a compact capacitor to GND.
Internally connected to GND through substrate. Connect this pad to large copper area,
generally a ground plane.
Thermal Pad
-
-
(1) I=Input, O=Output, P=Power, G=Ground
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6 Specifications
6.1 Absolute Maximum Ratings
All voltages are with respect to GND pin.(1)
MIN
0
MAX
5.75
UNIT
V
VDD
VIN
Supply voltage
IN+, IN- pin voltage
OUTH, OUTL pin voltage
Storage Temperature
Operating Temperature
-0.3
-0.3
-55
-40
VDD + 0.3
5.75
V
VOUT
TSTG
TJ
V
150
°C
°C
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per AEC Q100-002(1)
Charged device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stessing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.75
0
NOM
MAX
5.25
VDD
5.25
125
UNIT
V
VDD
VINx
VOUTx
TJ
Supply voltage
5
IN+ or IN- input voltage
OUTH, OUTL pin voltage
Operating Temperature
V
0
V
-40
°C
6.4 Thermal Information
LMG1025-Q1
DEE (WSON)
6 PINS
66.7
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
87.3
30.8
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.2
YJB
30.7
RθJC(bot)
6.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SNOSD74B –MAY 2019–REVISED JANUARY 2020
6.5 Electrical Characteristics
VDD = 5V, good feed-through bypass capacitor from VDD to GND pin, over operating free-air temperature range (unless
otherwise noted)
PARAMETER
DC Characteristics
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IVDD, Q
VDD Quiescent Current
VDD Operating Current
Under-voltage Lockout
IN+ = IN- = 0 V
75
µA
fsw = 30 MHz, no load, 2Ω as ROUTH and
ROUTL
40
51
mA
IVDD, op
fsw = 30 MHz, 100-pF load, 2Ω as
ROUTH and ROUTL
mA
VDD, UVLO
VDD rising
4.0
4.35
V
ΔVDD, UVLO UVLO Hysteresis
85
170
20
mV
Over temperature shutdown, turn-off
threshold
TOTP
°C
°C
ΔTOTP
Over temperature hysteresis
Input DC Characteristics
VIH
IN+, IN- high threshold
1.7
1.1
2.6
1.8
1
V
V
VIL
IN+, IN- low threshold
VHYST
RIN+
RIN-
CIN+
CIN-
IN+, IN- hysteresis
0.38
100
100
V
Positive input pull-down resistance
Negative input pull-up resistance
Positive input pin capacitance
Negative input pin capacitance
To GND
to VDD
150
150
250
250
kΩ
kΩ
pF
pF
To GND
To GND
1.45
1.45
Output DC Characteristics
VOL
OUTL voltage
IOUTL = 100 mA, IN+= IN- = 0 V
45
52
mV
mV
IOUTH = 100 mA, IN+= 5 V, IN- = 0 V,
VDD = 5 V
VDD-VOH
OUTH voltage
VOUTH = 0 V, IN+= 5 V, IN- = 0 V, VDD
5 V
=
IOH
IOL
Peak source current
Peak sink current
7
5
A
A
VOUTL = 5 V, IN+= IN- = 0 V, VDD = 5 V
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IN- = GND, IN+ = VDD , VDD rising above
4.4 V to OUTH rising
tstart
Startup Time, VDD rising above UVLO
40
78
µs
IN- = GND, IN+ = VDD , VDD falling
below 3.9 V to OUTH falling
tshut-off
ULVO falling
0.7
2.5
3.5
µs
tpd, r
tpd, f
Δtpd
trise
tfall
Propagation delay, turn on
Propagation delay, turn off
IN- = 0 V, IN+ to OUTH, 100-pF load
IN- = 0 V, IN+ to OUTL, 100-pF load
1.5
1.8
0
2.6
2.9
4.1
4.4
ns
ns
ps
ps
ps
Pulse positive distrortion, (tpd, f - tpd, r
Output rise time
)
300
650
850
610
0Ω series 220 pF load(1)
0Ω series 220 pF load(1)
Output fall time
Minimum input pulse width that changes
output state
tmin
0Ω series 220 pF load(1)
1.25
ns
(1) Rise and fall time calcuated as time from 20% of the gate voltage to 80% of the gate voltage of the GaN FET.
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6.7 Typical Characteristics
VDD = 5 V
51
50
49
48
47
100
90
80
70
60
50
40
30
20
10
0
T=-40°C
T=0°C
T=25°C
T=85°C
T=125°C
0
5
10 15 20 25 30 35 40 45 50 55 60
Frequency (MHz)
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
Figu
Figu
Figure 1. IVDD,op with 2 Ω in series with 100 pF load
Figure 2. IVDD,op with 2 Ω in series with 100 pF load
3.4
48
46
44
42
40
TDR
TDF
3.2
3
2.8
2.6
2.4
2.2
-40
-20
0
20
40 60
Temperature (°C)
80
100 120 140
Figu
-40
-20
0
20
40 60
Temperature(°C)
80
100 120 140
PDel
Figure 3. Quiescent current
Figure 4. Propagation Delay with 1.8nC load
900
870
840
810
780
750
720
690
660
630
RISE
FALL
600
-40
-20
0
20
40 60
Temperature(°C)
80
100 120 140
Rise
Figure 5. Rise And Fall Time with 1.8nC load
6
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7 Detailed Description
7.1 Overview
LMG1025-Q1 is a high-performance low-side 5-V gate driver for GaN and logic-level MOSFETs. While it is
designed to function well in high-speed applications, such as wireless power transmission and LiDAR/ToF, it can
be used in any application where a low-side gate driver is required. The LMG1025-Q1 is optimized to provide the
lowest propagation delay through the driver to the power transistor. LMG1025-Q1 is in a small 2mm×2mm QFN
package with wettable flanks, in order to minimize its parasitic inductance. This low inductance design is
necessary to achieve high current, low ringing performance in very high frequency operation when driving power
FETs. The same holds true for when designing with LMG1025-Q1. QFN package with wettable flanks is also
needed to improve system robustness in many automotive applications.
7.2 Functional Block Diagram
1
6
5
2
VDD
OUTH
OUTL
GND
UVLO
OTP
IN+
3
VDD
INœ
4
7.3 Feature Description
7.3.1 Input Stage
The input stage features two Schmitt-triggers at the pins IN+ and IN– to reduce sensitivity to noise on the inputs.
IN+ signal and the inverted IN– signal are both sent to an AND gate. IN+ is connected with a pull-down resistor
while IN– is connected with a pull-up resistor to prevent unintended turn-on. The output of the driver will be high
when input voltage goes above input thresholds and output goes low when input voltage is below input threshold
mentioned in the electrical characteristics table. Both IN+ and IN– are single ended inputs, and these two pins
cannot be used as a differential input pair. Parasitic elements become extremely important in high frequency
designs and extreme care should be taken while laying out the printed circuit board to minimize these parasitic
elements. The performance of the LMG1025-Q1 and the performance of the overall system gets affected by the
layout and components being selected.
7.3.2 Output Stage
LMG1025-Q1 provides 7-A source, 5-A sink (asymmetrical drive) peak-drive current capability, and features a
split output configuration. The OUTH and OUTL outputs of the LMG1025-Q1 allow the user to use independent
resistors connecting to the gate. The two resistors allow the user to independently adjust the turn-on and turn-off
drive strengths to control slew rate and EMI, and to control ringing on the gate signal. For GaN FETs, controlling
ringing is important to reduce stress on the GaN FET and driver. The output stage OUTL is also pulled down in
undervoltage condition, which prevents the unintended charge accumulation of device Ciss, and thus preventing
false turn-on. This ringing heavily depends on the layout as switching frequency increases and as rise and fall
time gets shorter. The distance between the gate driver and power device need to be as minimum as possible.
Gate loop should be as minimum as possible. If ringing is un-avoidable then the gate resistor should be selected
in such a way that the ringing is minimized. Bypass capacitor type, value, and position also significantly affects
this ringing.
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Feature Description (continued)
7.3.3 Bias Supply and Under Voltage Lockout
LMG1025-Q1 features nominal 5 V and maximum 5.25 V of supply voltage, and its absolute maximum supply
voltage is 5.75 V. In the design, it is recommended to limit the variability of the power supply to be within 5%
(0.25 V), and the overshoot voltage during switching transient not to exceed the absolute maximum voltage.
Refer to Section VDD and Overshoot for more on the detailed design guide. LMG1025-Q1 also features internal
undervoltage lockout (UVLO) to protect the driver and circuit in case of fault conditions. The UVLO point is setup
between 4.0 V and 4.35 V with a hysteresis of 85mV. This UVLO level is specifically designed to guarantee that
GaN power devices can be switched at a low RDS(ON) region. During UVLO condition, the OUTL pin is pulled
down to ground.
7.3.4 Overtemperature Protection (OTP)
LMG1025-Q1 features overtemperature protection (OTP) function by having a rising edge trigger point at around
170°C of junction temperature. With a hysteresis of 20°C, the device can restart to operate when junction
temperature is below 150°C.
7.4 Device Functional Modes
The device will operate in following mode when not in UVLO state.
Table 1. Truth Table
IN-
L
IN+
L
OUTH
Open
H
OUTL
L
Open
L
L
H
H
H
L
Open
Open
H
L
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
To operate GaN FET or MOSFET at very high switching frequencies and to reduce associated switching losses,
a powerful gate driver is employed between the PWM output of controller and the gate of the GaN transistor.
Also, gate drivers are indispensable when the outputs of the PWM controller do not meet the voltage or current
levels needed to directly drive the gates of the switching devices. With the advent of digital power, this situation
is often encountered because the PWM signal from the digital controller is often a 3.3-V logic signal, which
cannot effectively turn on a power switch. A level-shift circuit is needed to boost the 3.3-V signal to the gate-drive
voltage (such as 5 V) in order to fully turn on the power device and minimize conduction losses.
Gate drivers effectively provide the buffer-drive functions. Gate drivers also address other needs such as
minimizing the effect of high-frequency switching noise (by placing the high-current driver IC physically close to
the power switch), reducing power dissipation and thermal stress in controllers by moving gate charge power
losses from the controller into the driver.
The LMG1025-Q1 is a high frequency low-side gate driver for enhancement mode GaN FETs and Si FETs in a
single ended configuration. The split-gate outputs with strong source and sink capability provides flexibility to
adjust the turn-on and turn-off strength independently. As a low side driver, LMG1025-Q1 can be used in a
variety of applications, including different power converters, LiDAR, time-of-flight (ToF) laser drivers, class-E
wireless chargers, synchronous rectifiers, and augmented reality devices. LMG1025-Q1 can also be used as a
high frequency low current laser diode driver, or as a signal buffer with very fast rise/fall time.
8.2 Typical Application
The LMG1025-Q1 is designed to be used with a single low-side, ground-referenced GaN or logic-level FET, as
shown in Figure 6. Independent gate drive resistors, R1 and R2, are used to independently control the turnon
and turnoff drive strengths, respectively. For fast and strong turnoff, R2 can be shorted and OUTL directly
connected to the transistor’s gate. For symmetric drive strengths, it is acceptable to short OUTH and OUTL and
use a single gate-drive resistor. The care should be taken that the ringing on the gate of the power device or
ringing on any of the gate driver pin does not exceed the recommended rating. Resistors play an important role
in damping these ringing. The layout and type of gate resistor with respect to gate driver and power device is
also very important.
It is strongly recommended to use at least a 2-Ω resistor at each OUTH and OUTL to avoid voltage overstress
due to inductive ringing. Ringing has to be ensured to be below VDD+0.3 V.
For applications requiring smaller resistance, please contact the factory for guidance.
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Typical Application (continued)
+5 V
Vbus
LMG1025
R1
OUTH
VDD
IN+
R2
OUTL
PWM
GaN
INœ
EN
GND
Figure 6. Typical Implementation of a Circuit
8.2.1 Design Requirements
When designing a multi-MHz (or nano-second pulse) application that incorporates the LMG1025-Q1 gate driver
and GaN power FETs, some design considerations must be evaluated first to make the most appropriate
selection. Among these considerations are layout optimization, circuit voltages, passive components, operating
frequency, and controller selection.
8.2.2 Detailed Design Procedure
8.2.2.1 Handling Ground Bounce
For the best switching performance and gate loop with lowest parasitics, it is recommended to connect the
ground return pin of LMG1025-Q1 as close as possible to the source of the low-side FET in a low inductance
manner. However, doing so can cause the ground of LMG1025-Q1 to bounce relative to the system or controller
ground and lead to erroneous switching logic on the input so as mis-turn on/off on the output.
First of all, LMG1025-Q1 has input hysteresis built into the input buffers to help counteract this effect. The
maximum di/dt allowed to prevent the input voltage transient from exceeding the input hysteresis is given by
Equation 1
dis VHYST
=
dt
LRS
where
•
•
•
LRS is the inductance of the sense resistor,
VHYST is the hysteresis of the input pin,
and dis/dt is the maximum allowed current slew rate.
(1)
For an assumed shunt resistor parasitic inductance of 0.5 nH and a minimum hysteresis of 0.5 V, the maximum
slew rate is 1 A/ns. Many applications would exhibit higher current slew rates, up to the 10 A/ns range, which
would make this approach impractical. The stability of this approach can be improved by using the IN– input for
the PWM signal and locally tying IN+ to VDD. By using the inverting input, the transient voltage applied to the
input pin reinforces the PWM signal in a positive feedback loop. While this approach would reduce the probability
of false pulses or oscillation, the transient spikes due to high di/dt may overly stress the inputs to the LMG1025-
Q1. A current-limiting, 100 Ω resistor can be placed right before the IN– input to limit excessive current spikes in
the device.
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Typical Application (continued)
Secondly, for moderate ground-bounce cases, a simple R-C filter can be built with a simple resistor in series with
the inputs. By utilizing the input capacitance of LMG1025-Q1, the resistor could be close to its input pin. The
addition of a small capacitor on the input as supplement can also be helpful. A small time constant of the R-C
filter may be enough to filter out high frequency noise. This solution is acceptable for moderate cases in
applications where extra delay is acceptable and the pulse width is not extremely short such as in 1ns range.
For more extreme cases, or where no delay is tolerable while pulse width is extremely short, using a
commonmode choke provides the best results.
One example application where ground-bounce is particularly challenging is when using a current sense resistor.
In Figure 7 LMG1025-Q1 ground is connected to the source of GaN FET, while the controller ground is
connected to the other side of the current sense resistor as shown in Figure 7. Due to the fast switching and very
fast current slew rates, the high ground potential bounce induced by inductance of the sense resistor can disrupt
the operation of the circuit or even damage the part. To prevent this, a common-mode choke can be used for IN+
and IN–, respectively. Resistors can also added to the signal output line before LMG1025-Q1 depending on the
input signal pulse width to provide additional RC filtering. Figure 9 presents the schematic using approach A with
the preferred filtering method. Approach B as shown in Figure 8 places the current sense resistor within the gate
drive loop path. In this case, the LMG1025-Q1 GND pin is connected to the signal ground, and with good ground
plane connection, the ground bounce issue can be less severe than approach A. However, the inductance of the
current sense resistor adds common-source inductance to the gate drive loop. The voltage generated across this
parasitic inductance will subtract from the gate-drive voltage of the FET, slowing down the turnon and turnoff di/dt
of the FET, or even cause mis-turn on and off. Additional gate resistance will have to be added to ensure the
loop is stable and ring-free. The slower rise may negate the advantage of the fast switching of the GaN FET and
may cause additional losses in the circuit. Therefore, this approach is not recommended.
(a)
(b)
R1
R2
R1
R2
OUTH
OUTL
GND
OUTH
OUTL
GND
GaN
RS
GaN
RS
LMG1025
LMG1025
Figure 7. Source Resistor Current Sense A
Configuration
Figure 8. Source Resistor Current Sense B
Configuration
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Typical Application (continued)
5V
LMG1025
R1
R2
VDD
OUTH
RC filter
GaN
IN+
IN-
OUTL
GND
RS
CM choke
Controller
Figure 9. Filtering For Ground Bounce Noise Handling When Using LMG1025-Q1
8.2.2.2 Creating Nanosecond Pulse
LMG1025-Q1 can be used to drive pulses of nano seconds duration on to a capacitive load. LMG1025-Q1 can
be driven with a equivalently short pulse on one input pin. However, this takes a sufficiently strong digital driver
and careful consideration of the routing parasitics from digital output to input of LMG1025-Q1. Two inputs and
included AND gate in LMG1025-Q1 provide an alternate method to create a short pulse at the LMG1025-Q1
output. Starting with both IN+ and IN– at low, taking IN+ high will cause the output to go high. Now if IN– is taken
high as well, output will be pulled low. So a digital signal and its delayed version can be applied to IN+ and IN–
respectively to create a pulse at the output with width corresponding to the delay between the signals, as shown
in Figure 10. The delay can be digitally controlled in the nanosecond range. This method alleviates the
requirements for driving the input of LMG1025-Q1. If a separate delayed version of the digital signal is not
available, an RC delay followed by a buffer can be used to derive the second signal. Optionally, if LMG1025-Q1
must be driven with a single short duration pulse, that pulse can itself be generated using another LMG1025-Q1
by the above method to meet drive requirements.
12
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SNOSD74B –MAY 2019–REVISED JANUARY 2020
Typical Application (continued)
IN+
IN-
OUT
Figure 10. Timing Diagram To Create Short Pulses
8.2.3 VDD and Overshoot
Fast switching with high current is prone to ringing with parasitic inductances, including those on PCB traces.
Overshoot associated with such ringing transients need to be evaluated and controlled as a part of the PCB
design process to limit device stress. The parameters affecting stress are how high the overshoot is above the
absolute maximum specification and the ratio of overshoot duration to the switching time period. Recommended
design practice is to limit the overshoots to the absolute maximum pin voltages. This is accomplished with carful
PCB layout to minimize parasitic inductances, choice of components with low ESL and addition of series
resistance to limit rise times. For large overshoots, limiting the variability of the power supply may be required.
For example, 0.5V of overshoot will be permissible with a maximum recommended supply of 5.25 V (5%
variability); however, for larger overshoots, a supply with lower variability will be preferred.
8.2.4 Operating at Higher Frequency
With fast rise/fall time, and capability of achieving nano-second pulse width, depending on the capacitive load
condition, the operating frequency of LMG1025-Q1 can be increased in a burst manner. In conditions which
requires very high frequency pulsing, a pulse train with certain period of pause between each burst can be
adopted to avoid overheat of the device. This will help maintain the RMS output current similar as lower
frequency operation but boost the transient frequency to very high. In addition, higher decoupling capacitance will
be needed to supply high frequency charging of the capacitive load.
8.2.5 Application Curves
LMG1025-Q1 EVM is used to take application waveforms. This EVM has LDO, input buffer, GaN FET, and load
resistor. It shows the switching performance of the LMG1025-Q1 when equivalent laser diode current is
switched. Figure 11 and Figure 12 show VDD turn-on and turn-off delay in an application-like set-up. System
designer need to make sure that these delays are acceptable in their designs. LIDAR design needs to pulse the
laser diode for very short duration. Figure 13 shows how LMG1025-Q1 can not only handle nano-second pulse at
its input but also can produce a nano-second pulse at the output while driving a reasonably sized GaN FET that
has 3.2nC of typical total gate charge. Figure 13 also shows very small, e.g. less than 3 ns, rising and falling
propagation delay of LMG1025-Q1. Figure 14 shows drive strength of LMG1025-Q1. It shows how LMG1025-Q1
can achieve sub-nano second rise and fall time, which is very important for LIDAR applicatoins.
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Typical Application (continued)
Figure 11. Startup Time
Figure 12. Shutdown Time
2.6ns
2.4ns
1.2ns
Vg
620ps
640ns
IN+
Vg
Figure 13. Input pulse width and propagation delays
Figure 14. Rise and fall time
14
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SNOSD74B –MAY 2019–REVISED JANUARY 2020
9 Power Supply Recommendations
A low-ESR/ESL ceramic capacitor must be connected close to the IC, between VDD and GND pins to support
the high peak current being drawn from VDD during turnon of the FETs. It is most desirable to place the VDD
decoupling capacitor on the same side of the PC board as the driver. The inductance of via holes can impose
excessive ringing on the IC pins.
TI recommends the use of a three-terminal capacitor connecting in shunt-through manner to achieve the lowest
ESL and best transient performance. This capacitor can be placed as close as possible to the IC, while another
capacitor in larger capacitance can be placed closely to the three-terminal cap to supply enough charge but with
slightly lower bandwidth. As a general practice, the combination of a 0.1 µF of 0402 or feed-through capacitor
(closest to LMG1025-Q1) and a 1 µF 0603 capacitor is recommended.
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10 Layout
10.1 Layout Guidelines
The layout of the LMG1025-Q1 is critical to its performance and functionality. The LMG1025-Q1 is available in a
2x2 DFN, which allows a low inductance connection to a FET. Figure 15shows the recommended layout of the
LMG1025-Q1 with a ball-grid GaN FET.
A four-layer or higher layer count board is required to reduce the parasitic inductances of the layout to achieve
suitable performance. To minimize inductance and board space, resistors and capacitors in the 0201 package
should be used here. The gate drive power loss must be calculated to ensure an 0201 resistor will be able to
handle the power level.
10.1.1 Gate Drive Loop Inductance and Ground Connection
A compact, low-inductance gate-drive loop is essential to achieving fast switching frequencies with the
LMG1025-Q1. The LMG1025-Q1 should be placed as close to the GaN FET as possible, with gate drive
resistors immediately connecting OUTH and OUTL to the FET gate. Large traces need to be used to minimize
resistance and parasitic inductance.
To minimize gate drive loop inductance, the source return should be on layer 2 of the PCB, immediately under
the component (top) layer. Vias immediately adjacent to both the FET source and the LMG1025-Q1 GND pin
connect to this plane with minimal impedance. Finally, care must be taken to connect the GND plane to the
source power plane only at the FET to minimize common-source inductance and to reduce coupling to the
ground plane.
10.1.2 Bypass Capacitor
The VDD power terminal of the LMG1025-Q1 must by bypassed to ground immediately adjacent to the IC. The
placement and value of the bypass capacitor is very critical because of the fast gate drive of the IC, . The bypass
capacitor must be located on the top layer, as close as possible to the IC, and connected to both VDD and GND
using large power planes. This bypass capacitor has to be at least a 0.1 µF, up to 1 µF, with temperature
coeffient X7R or better. Recommended body types are LICC, IDC, Feed-though, and LGA. Finally, an additional
1μF capacitor should be placed as close to the IC as practical.
10.2 Layout Example
C_VDD
R_OUTL
R_OUTH
GaN
FET
Pin 6
Pad
Pin 1
Ground on layer 2, 3, & 4
Figure 15. Typical LMG1025-Q1 Layout With Ball-Grid GaN FET
16
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SNOSD74B –MAY 2019–REVISED JANUARY 2020
11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMG1025QDEERQ1
LMG1025QDEETQ1
ACTIVE
ACTIVE
WSON
WSON
DEE
DEE
6
6
3000 RoHS & Green
250 RoHS & Green
SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
LMG
LMG
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMG1025QDEERQ1
LMG1025QDEETQ1
WSON
WSON
DEE
DEE
6
6
3000
250
180.0
180.0
8.4
8.4
2.2
2.2
2.2
2.2
1.2
1.2
4.0
4.0
8.0
8.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMG1025QDEERQ1
LMG1025QDEETQ1
WSON
WSON
DEE
DEE
6
6
3000
250
213.0
213.0
191.0
191.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DEE0006A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
0.1 MIN
(0.05)
A
-
A
4
0
.
0
0
0
SECTION A-A
TYPICAL
0.8 MAX
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
0.9 0.1
EXPOSED
THERMAL PAD
3
4
6
2X
A
A
7
1.3
1.6 0.1
1
4X 0.65
0.45
0.35
6X
PIN 1 ID
(OPTIONAL)
0.35
0.25
6X
0.1
C A B
C
0.05
4219364/A 01/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DEE0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.5)
6X (0.4)
(0.9)
1
6
(1.6)
SYMM
7
(1.1)
4X (0.65)
4
3
SYMM
(1.9)
(R0.05) TYP
(
0.2) TYP
VIA
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:25X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219364/A 01/2019
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
4. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DEE0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
6X (0.5)
METAL
1
6
6X (0.4)
(0.45)
SYMM
7
4X (0.65)
(0.7)
4
3
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD #7:
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4219364/A 01/2019
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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