LMH0307SQE [TI]
IC,LINE DRIVER,2 DRIVER,LLCC,16PIN,PLASTIC;
| 型号： | LMH0307SQE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC,LINE DRIVER,2 DRIVER,LLCC,16PIN,PLASTIC PC 驱动 接口集成电路 驱动器 |
| 文件： | 总23页 (文件大小：832K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMH0307
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SNLS286I –APRIL 2008–REVISED APRIL 2013
3 Gbps HD/SD SDI Dual Output Cable Driver With Cable Detect
Check for Samples: LMH0307
1
FEATURES
DESCRIPTION
The LMH0307 3 Gbps HD/SD SDI Dual Output Cable
Driver with Cable Detect is designed for use in
SMPTE 424M, SMPTE 292M, SMPTE 344M, and
SMPTE 259M serial digital video applications. The
LMH0307 implements two complementary output
drivers and drives 75Ω transmission lines (Belden
1694A, Belden 8281, or equivalent) at data rates up
to 2.97 Gbps.
2
•
SMPTE 424M, SMPTE 292M, SMPTE 344M, and
SMPTE 259M Compliant
•
•
•
•
•
•
Data Rates to 2.97 Gbps
Supports DVB-ASI at 270 Mbps
Cable Detect on Output
Loss of Signal Detect at Input
Output Driver Power Down Control
The LMH0307 includes intelligent sensing capabilities
to improve system diagnostics. The cable detect
feature senses near-end termination to determine if a
cable is correctly attached to the output BNC. Input
loss of signal (LOS) detects the presence of a valid
signal at the input of the cable driver. These sensing
features may be used to alert the user of a system
fault and activate a deep power save mode, reducing
the cable driver's power consumption to 4 mW. These
features are accessible via an SMBus interface.
Typical Power Consumption: 230 mW in SD
Mode and 275 mW in HD Mode
•
Power Save Mode Typical Power
Consumption: 4 mW
•
•
•
•
•
•
Single 3.3V Supply Operation
Differential Input
Dual Complementary 75Ω Outputs
Selectable Slew Rate
The LMH0307 provides two selectable slew rates for
SMPTE 259M and SMPTE 424M / 292M compliance.
The output amplitude is adjustable ±10% in 5 mV
steps via the SMBus.
Industrial Temperature Range: −40°C to +85°C
16-Pin WQFN or 25-Ball CS-BGA package
APPLICATIONS
The LMH0307 is powered from a single 3.3V supply.
Power consumption is typically 230 mW in SD mode
and 275 mW in HD mode. The LMH0307 is available
in two space-saving packages: a 4 x 4 mm 16-pin
WQFN and even more space-efficient 3 x 3 mm 25-
ball CS-BGA package.
•
SMPTE 424M, SMPTE 292M, SMPTE 344M, and
SMPTE 259M Serial Digital Interfaces
•
•
Digital Video Routers and Switches
Distribution Amplifiers
Typical Application
SDI In
SD/HD
SDI
SDI Out
LMH0356
3G/HD/SD
LMH0307
3G/HD/SD
SDI Reclocker
SDI Dual Cable Driver
SDA SCL
ENABLE
Clock or
Second
FAULT
Data Output
SMBus
Data
SMBus
Clock
Microcontroller
or
FPGA
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2013, Texas Instruments Incorporated
LMH0307
SNLS286I –APRIL 2008–REVISED APRIL 2013
www.ti.com
Connection Diagram
16
15
14
13
SDO0
SDO0
SD/HD
SDI
SDI
1
2
3
4
12
11
10
9
LMH0307SQ
(top view)
V
EE
V
CC
R
REF
5
6
7
8
The exposed die attach pad is a negative electrical terminal for this device. It should be connected to the negative
power supply voltage.
Figure 1. 16-Pin WQFN
Package Number RUM
1
2
3
4
5
SDI
A1
RSTO
A2
SDO1
A3
SDO1
A4
FAULT
A5
A
B
C
D
E
V
EE
V
EE
SDI
B1
NC
B3
SDO0
B5
B2
B4
V
EE
V
EE
V
EE
V
EE
SDO0
C5
C1
C2
C3
C4
V
NC
D3
SD/HD
D5
R
CC
RSTI
D2
REF
D1
D4
R
ENABLE
E2
SDA
E3
SCL
E4
NC
E5
REF
E1
LMH0307GR
(top view)
Figure 2. 25-Ball CS-BGA
Package Number NYA
2
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SNLS286I –APRIL 2008–REVISED APRIL 2013
PIN DESCRIPTIONS
WQFN Pin
CS-BGA Ball
Name
Description
1
2
4
A1
B1
SDI
Serial data true input.
SDI
Serial data complement input.
D1, E1
RREF
Bias resistor. Connect a 750Ω resistor to VCC (also connect D1 to E1 on CS-BGA
version).
5
D2
RSTI
Reset input. RSTI has an internal pullup.
H = Normal operation.
L = Device reset. The device operates with default register settings. Forcing RSTI low
also forces RSTO low.
6
7
E2
E3
ENABLE
SDA
Output driver enable. ENABLE has an internal pullup.
H = Normal operation.
L = Output driver powered off.
SMBus bidirectional data pin. When functioning as an output, it is open drain. This pin
requires an external pullup.
8
E4
D5
SCL
SMBus clock input. SCL is input only. This pin requires an external pullup.
10
SD/HD
Output slew rate control. SD/HD has an internal pulldown.
H = Output rise/fall time complies with SMPTE 259M.
L = Output rise/fall time complies with SMPTE 424M / 292M.
11
12
13
C5
B5
A5
SDO0
SDO0
FAULT
Serial data output 0 complement output.
Serial data output 0 true output.
Fault open drain output flag. Requires external pullup resistor and may be wire ORed
with multiple cable drivers.
H = Normal operation.
L = Loss of signal or termination fault for any output.
14
15
16
A4
A3
A2
SDO1
SDO1
RSTO
Serial data output 1 true output.
Serial data output 1 complement output.
Reset output. RSTO is automatically set to 1 when register 0 is written. It can be reset
back to zero by forcing RSTI to zero to reset the device. Used to daisy chain multiple
cable drivers on the same SMBus.
9
D4
VCC
VEE
Positive power supply (+3.3V).
Negative power supply (ground).
DAP, 3
B2, B4, C1,
C2, C3, C4
—
B3, D3, E5
NC
No connect.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)
Supply Voltage
−0.5V to 3.6V
−0.3V to VCC+0.3V
28 mA
Input Voltage (all inputs)
Output Current
Storage Temperature Range
Junction Temperature
−65°C to +150°C
+125°C
Lead Temperature (Soldering 4 Sec)
Package Thermal Resistance
+260°C
θJA 16-pin WQFN
θJC 16-pin WQFN
θJA 25-ball CS-BGA
HBM
+43°C/W
+7°C/W
+67.6°C/W
8 kV
ESD Rating
MM
400V
CDM
2 kV
(1) "Absolute Maximum Ratings" are those parameter values beyond which the life and operation of the device cannot be ensured. The
stating herein of these maximums shall not be construed to imply that the device can or should be operated at or beyond these values.
The table of Electrical Characteristics specifies acceptable device operating conditions.
Recommended Operating Conditions
Supply Voltage (VCC – VEE
)
3.3V ±5%
Operating Free Air Temperature (TA)
−40°C to +85°C
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SNLS286I –APRIL 2008–REVISED APRIL 2013
DC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified(1)(2)
.
Symbol Parameter
Conditions
Reference
Min
Typ
Max
Units
V
VCMIN
Input Common Mode Voltage
SDI, SDI
1.6 +
VSDI/2
VCC –
VSDI/2
VSDI
Input Voltage Swing
Differential
100
2200
mVP−P
V
VCMOUT
Output Common Mode Voltage
SDO, SDO
VCC –
VSDO
VSDO
Output Voltage Swing
Single-ended, 75Ω load,
RREF = 750Ω 1%
720
2.0
800
880
mVP-P
VIH
VIL
ICC
Input Voltage High Level
Input Voltage Low Level
Supply Current
SD/HD,
ENABLE
V
V
0.8
SD/HD = 0,
SDO/SDO enabled
84
100
mA
SD/HD = 1,
SDO/SDO enabled
70
77
mA
mA
SDO/SDO disabled
1.3
2.5
SMBus DC Specifications
VSIL
VSIH
Data, Clock Input Low Voltage
0.8
V
V
Data, Clock Input High Voltage
2.1
4
VSDD
Current through pullup resistor or
current source
ISPULLUP
VOL = 0.4V
mA
VSDD
Nominal Bus Voltage
3.0
−200
−10
3.6
200
10
V
(3)
ISLEAKB
ISLEAKP
CSI
Input Leakage per bus segment
Input Leakage per pin
µA
µA
pF
(3)(4)
Capacitance for SDA and SCL
10
(1) Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated
referenced to VEE = 0 Volts.
(2) Typical values are stated for VCC = +3.3V and TA = +25°C.
(3) Recommended value — Parameter not tested.
(4) Recommended maximum capacitive load per bus segment is 400 pF.
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AC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified(1)
.
Symbol
DRSDI
tjit
Parameter
Conditions
Reference
SDI, SDI
Min
Typ
Max
Units
Mbps
psP-P
psP-P
psP-P
ps
Input Data Rate
Additive Jitter
2970
2.97 Gbps
SDO, SDO
20
18
15
90
1.485 Gbps
270 Mbps
tr,tf
Output Rise Time, Fall Time
Mismatch in Rise/Fall Time
Duty Cycle Distortion
SD/HD = 0, 20% – 80%,
SD/HD = 1, 20% – 80%
SD/HD = 0
130
800
30
50
27
30
100
10
8
400
ps
ps
SD/HD = 1
ps
SD/HD = 0, 2.97 Gbps(2)
SD/HD = 0, 1.485 Gbps(2)
SD/HD = 1(2)
SD/HD = 0(2)
SD/HD = 1(2)
ps
ps
ps
tOS
Output Overshoot
%
%
tSK
SDO1 to SDO0 Skew
Output Return Loss
SD/HD = 0(2)
SD/HD = 1(2)
5 MHz - 1.5 GHz(3)
1.5 GHz - 3.0 GHz(3)
8
ps
54
ps
RLSDO
15
10
dB
dB
SMBus AC Specifications
fSMB Bus Operating Frequency
tBUF
10
100
kHz
µs
Bus free time between Stop
and Start Condition
4.7
tHD:STA
Hold time after (repeated) Start At ISPULLUP = MAX
Condition. After this period, the
4.0
4.7
µs
µs
first clock is generated.
tSU:STA
Repeated Start Condition setup
time
tSU:STO
tHD:DAT
tSU:DAT
tLOW
tHIGH
tF
Stop Condition setup time
Data hold time
4.0
300
250
4.7
4.0
µs
ns
ns
µs
µs
ns
ns
Data setup time
Clock low period
Clock high period
Clock/Data Fall Time
Clock/Data Rise Time
50
300
tR
1000
tPOR
Time in which device must be
operational after power on
500
ms
(1) Typical values are stated for VCC = +3.3V and TA = +25°C.
(2) Specification is ensured by characterization.
(3) Output return loss is dependent on board design. The LMH0307 meets this specification on the SD307 evaluation board.
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SNLS286I –APRIL 2008–REVISED APRIL 2013
TIMING DIAGRAM
t
LOW
t
R
t
HIGH
SCL
t
t
t
t
SU:STA
HD:STA
F
HD:DAT
t
t
SU:STO
BUF
t
SU:DAT
SDA
ST
SP
SP
ST
Figure 3. SMBus Timing Parameters
DEVICE OPERATION
INPUT INTERFACING
The LMH0307 accepts either differential or single-ended input. For single-ended operation, the unused input
must be properly terminated.
OUTPUT INTERFACING
The LMH0307 uses current mode outputs. Single-ended output levels are 800 mVP-P into 75Ω AC-coupled
coaxial cable with an RREF resistor of 750Ω. The RREF resistor is connected between the RREF pin and VCC. The
only resistor value that should be used for RREF is 750Ω.
The RREF resistor should be placed as close as possible to the RREF pin. In addition, the copper in the plane
layers below the RREF network should be removed to minimize parasitic capacitance.
OUTPUT SLEW RATE CONTROL
The LMH0307 output rise and fall times are selectable for either SMPTE 259M or SMPTE 424M / 292M
compliance via the SD/HD pin. For slower rise and fall times, or SMPTE 259M compliance, SD/HD is set high.
For faster rise and fall times, or SMPTE 424M and SMPTE 292M compliance, SD/HD is set low. SD/HD may
also be controlled using the SMBus, provided the SD/HD pin is held low. SD/HD has an internal pulldown.
OUTPUT ENABLE
The SDO0/SDO0 and SDO1/SDO1output drivers can be enabled or disabled with the ENABLE pin. When set
low, both output drivers are powered off and the LMH0307 enters a deep power save mode. ENABLE has an
internal pullup.
INPUT LOSS OF SIGNAL DETECTION (LOS)
The LMH0307 detects when the input signal does not have a video-like pattern. Self oscillation and low levels of
noise are rejected. This loss of signal detect allows a very sensitive input stage that is robust against coupled
noise without any degradation of jitter performance.
Via the SMBus, the loss of signal detect can either add an input offset or mute the outputs. An offset is added by
default. Additionally, the loss of signal detect can be linked to the ENABLE functionality so that when the LOS
goes low, ENABLE will also go low.
OUTPUT CABLE DETECTION
The LMH0307 detects when an output is locally terminated. When a video signal (or AC test signal) is present on
SDI, the device senses the SDO and SDO amplitudes. If the output is not properly terminated (via a terminated
cable or local termination), the amplitude will be higher than expected, and the Termination Fault signal is
asserted. The Termination Fault signal is de-asserted when the proper termination is applied. This feature allows
the system designer the flexibility to react to cable attachment and removal. Note that a long length of cable will
look like a proper termination at the device output.
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The cable driver must be enabled for the termination detection to operate. If the Termination Fault will be used to
power down the LMH0307, then periodic polling (enabling) is recommended to monitor the output termination.
For example, when a Fault condition is triggered, ENABLE can be driven low to power down the device. The
LMH0307 should be re-enabled periodically to check the status of the output termination. The LMH0307 needs to
be powered on for roughly 4 ms for Termination Fault detection to work.
SMBUS INTERFACE
The System Management Bus (SMBus) is a two-wire interface designed for the communication between various
system component chips. By accessing the control functions of the circuit via the SMBus, pin count is kept to a
minimum while allowing a maximum amount of versatility. The LMH0307 has several internal configuration
registers which may be accessed via the SMBus.
The 7-bit default address for the LMH0307 is 17h. The LSB is set to 0b for a WRITE and 1b for a READ, so the
8-bit default address for a WRITE is 2Eh and the 8-bit default address for a READ is 2Fh. The SMBus address
may be dynamically changed.
In applications where there might be several LMH0307s, the SDA, SCL, and FAULT pins can be shared. The
SCL, SDA, and FAULT pins are open drain and require external pullup resistors. Multiple LMH0307s may have
the FAULT pin wire ORed. This signal becomes active when either loss of signal is detected or any termination
faults are detected. The registers may be read in order to determine the cause. Additionally, each signal can be
masked from the FAULT pin.
TRANSFER OF DATA VIA THE SMBus
During normal operation the data on SDA must be stable during the time when SCL is High.
There are three unique states for the SMBus:
START: A High-to-Low transition on SDA while SCL is High indicates a message START condition.
STOP: A Low-to-High transition on SDA while SCL is High indicates a message STOP condition.
IDLE: If SCL and SDA are both High for a time exceeding tBUF from the last detected STOP condition or if they
are High for a total exceeding the maximum specification for tHIGH then the bus will transfer to the IDLE state.
SMBus TRANSACTIONS
The device supports WRITE and READ transactions. See Table 1 for register address, type (Read/Write, Read
Only), default value and function information.
WRITING A REGISTER
To write a register, the following protocol is used (see SMBus 2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drives the 8-bit data byte.
6. The Device drives an ACK bit (“0”).
7. The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may
now occur.
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READING A REGISTER
To read a register, the following protocol is used (see SMBus 2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drives a START condition.
6. The Host drives the 7-bit SMBus Address, and a “1” indicating a READ.
7. The Device drives an ACK bit “0”.
8. The Device drives the 8-bit data value (register contents).
9. The Host drives a NACK bit “1”indicating end of the READ transfer.
10. The Host drives a STOP condition.
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APPLICATION INFORMATION
Figure 4 shows the application circuit for the LMH0307.
V
CC
6.8 nH
0.1 mF
75W
75W
Coaxial Cable
Coaxial Cable
4.7 mF
4.7 mF
75W
75W
75W
75W
6.8 nH
V
V
CC
CC
10 kW
FAULT
RSTO
0.1 mF
75W
75W
6.8 nH
49.9W
49.9W
Coaxial Cable
4.7 mF
4.7 mF
75W
75W
12
1
SDO0
SDI
SDI
Differential
Input
Coaxial Cable
75W
11
10
9
2
3
4
SDO0
LMH0307
0.1 mF
75W
SD/HD
V
R
EE
6.8 nH
V
CC
REF
V
CC
750W
RSTI
V
CC
ENABLE
SDA
SCL
0.1 mF
V
CC
10 kW
10 kW
SD/HD
Figure 4. Application Circuit
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COMMUNICATING WITH MULTIPLE LMH0307 CABLE DRIVERS VIA THE SMBus
A common application for the LMH0307 will utilize multiple cable driver devices. Even though the LMH0307
devices all have the same default SMBus device ID (address), it is still possible for them share the SMBus
signals as shown in Figure 5. A third signal is required from the host to the first device. This signal acts as a
“Enable / Reset” signal. Additional LMH0307s are controlled from the upstream device. In this control scheme,
multiple LMH0307s may be controlled via the two-wire SMBus and the use of one GPO (General Purpose
Output) signal. Other SMBus devices may also be connected to the two wires, assuming they have their own
unique SMBus addresses.
3.3V
LMH0307
#1
LMH0307
#2
LMH0307
#N
Host
(e.g. FPGA)
RSTI
RSTO
RSTI
RSTO
RSTI
RSTO
GPO
SCL
SDA
Figure 5. SMBus Configuration for Multiple LMH0307 Cable Drivers
The RSTI pin of the first device is controlled by the system with a GPO pin from the host. The first LMH0307
RSTO pin is then daisy chained to the next device's RSTI pin. That device’s RSTO pin is connected to the next
device and so on.
The procedure at initialization is to:
1. Hold the host GPO pin Low in RESET, to the first device. RSTO output default is also Low which holds the
next device in RESET in the chain.
2. Raise the host GPO signal to LMH0307 #1 RSTI input pin.
3. Write to Address 8’h2E (7’h17) Register 0 with the new address value (e.g. 8’h2C (7’h16).
4. Upon writing Register 0 in LMH0307 #1, its RSTO signal will switch High. Its new address is 8’h2C (7’h16),
and the next LMH0307 in the chain will now respond to the default address of 8’h2E (7’h17).
5. The process is repeated until all LMH0307 devices have a unique address loaded.
6. Direct SMBus writes and reads may now take place between the host and any addressed device.
The 7-bit address field allows for 128 unique addresses. The above procedure allows for the reprogramming of
the LMH0307 devices such that multiple devices may share the two-wire SMBus. Make sure all devices on the
bus have unique device IDs.
If power is toggled to the system, the SMBus address routine needs to be repeated.
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Table 1. SMBus Registers
Address
R/W
Name
Bits
Field
Default
Description
00h
R/W
ID
7:1
DEVID
0010111
Device ID. Writing this register will force the
RSTO pin high. Further accesses to the
device must use this 7-bit address.
0
7:5
4
RSVD
RSVD
TF1N
0
000
0
Reserved as 0. Always write 0 to this bit.
Reserved.
01h
R
STATUS
Termination Fault for SDI1.
0: No Termination Fault Detected.
1: Termination Fault Detected.
3
2
1
0
7
TF1P
TF0N
TF0P
LOS
SD
0
0
0
0
0
Termination Fault for SDI1.
0: No Termination Fault Detected.
1: Termination Fault Detected.
Termination Fault for SDI0.
0: No Termination Fault Detected.
1: Termination Fault Detected.
Termination Fault for SDI0.
0: No Termination Fault Detected.
1: Termination Fault Detected.
Loss Of Signal (LOS) detect at input.
0: No Signal Detected.
1: Signal Detected.
02h
R/W
MASK
SD Rate select bit. If the SD/HD pin is set
to VCC, it overrides this bit. With the SD/HD
pin set to ground, this bit selects the output
edge rate as follows:
0: HD edge rate.
1: SD edge rate.
6
5
PD1
PD0
0
0
Power Down for SDO1 output stage. If the
ENABLE pin is set to ground, it overrides
this bit. With the ENABLE pin set to VCC
PD1 functions as follows:
0: SDO1 active.
,
1: SDO1 powered down.
Power Down for SDO0 output stage. If the
ENABLE pin is set to ground, it overrides
this bit. With the ENABLE pin set to VCC
PD0 functions as follows:
0: SDO0 active.
,
1: SDO0 powered down.
4
3
2
1
0
MTF1N
MTF1P
MTF0N
MTF0P
MLOS
0
0
0
0
0
Mask TF1N from affecting FAULT pin.
0: TF1N=1 will cause FAULT to be 0.
1: TF1N=1 will not affect FAULT; the
condition is masked off.
Mask TF1P from affecting FAULT pin.
0: TF1P=1 will cause FAULT to be 0.
1: TF1P=1 will not affect FAULT; the
condition is masked off.
Mask TF0N from affecting FAULT pin.
0: TF0N=1 will cause FAULT to be 0.
1: TF0N=1 will not affect FAULT; the
condition is masked off.
Mask TF0P from affecting FAULT pin.
0: TF0P=1 will cause FAULT to be 0.
1: TF0P=1 will not affect FAULT; the
condition is masked off.
Mask LOS from affecting FAULT pin.
0: LOS=0 will cause FAULT to be 0.
1: LOS=0 will not affect FAULT; the
condition is masked off.
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Table 1. SMBus Registers (continued)
Address
R/W
Name
Bits
Field
Default
Description
03h
R/W
DIRECTION
7
HDTF0ThreshLSB
1
Least Significant Bit for HDTF0Thresh
detection threshold. Combines with
HDTF0Thresh bits in register 04h.
6
SDTF0ThreshLSB
1
Least Significant Bit for SDTF0Thresh
detection threshold. Combines with
SDTF0Thresh bits in register 05h.
5
4
RSVD
0
0
Reserved as 0. Always write 0 to this bit.
DTF1N
Direction of TF1N that affects FAULT pin
(when not masked).
0: TF1N=1 will cause FAULT to be 0 (when
the condition is not masked off).
1: TF1N=0 will cause FAULT to be 0 (when
the condition is not masked off).
3
2
1
0
DTF1P
DTF0N
DTF0P
DLOS
0
0
0
0
Direction of TF1P that affects FAULT pin
(when not masked).
0: TF1P=1 will cause FAULT to be 0 (when
the condition is not masked off).
1: TF1P=0 will cause FAULT to be 0 (when
the condition is not masked off).
Direction of TF0N that affects FAULT pin
(when not masked).
0: TF0N=1 will cause FAULT to be 0 (when
the condition is not masked off).
1: TF0N=0 will cause FAULT to be 0 (when
the condition is not masked off).
Direction of TF0P that affects FAULT pin
(when not masked).
0: TF0P=1 will cause FAULT to be 0 (when
the condition is not masked off).
1: TF0P=0 will cause FAULT to be 0 (when
the condition is not masked off).
Direction of LOS that affects FAULT pin
(when not masked).
0: LOS=0 will cause FAULT to be 0 (when
the condition is not masked off).
1: LOS=1 will cause FAULT to be 0 (when
the condition is not masked off).
04h
R/W
OUTPUT0
7:5
4:0
HDTF0Thresh
AMP0
100
Sets the Termination Fault threshold for
SDO0, when SD is set to HD rates (0).
Combines with HDTF0ThreshLSB in
register 03h (default for combined value is
1001).
10000
SDO0 output amplitude in roughly 5 mV
steps.
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Table 1. SMBus Registers (continued)
Address
R/W
Name
Bits
7
Field
Default
Description
05h
R/W
OUTPUT0CTRL
RSVD
FLOSOF
0
0
Reserved as 0. Always write 0 to this bit.
6
Force LOS to always OFF in regard to its
effect on the output signal. This forces the
device into either the mute or “add offset”
state. The LOS bit in register 01h still
reflects the correct state of LOS.
0: LOS operates normally, muting or adding
offset as specified by the MUTE bit.
1: Muting or adding offset is always in place
as specified by the MUTE bit.
5
4
FLOSON
0
0
Force LOS to always ON in regard to its
effect on the output signal. This prevents
the device from muting or adding offset.
The LOS bit in register 01h still reflects the
correct state of LOS.
0: LOS operates normally, muting or adding
offset as specified in the MUTE bit.
1: Muting or adding offset never occurs.
LOSEN
Configures LOS to be combined with the
ENABLE functionality.
0: Only the PD bits and ENABLE pin affect
the power down state of the output drivers.
1: If the ENABLE pin is set to ground, it
powers down the output drivers regardless
of the state of LOS or the PD bits. With the
ENABLE pin set to VCC, LOS=0 will power
down the output drivers, and LOS=1 will
leave the power down state dependent on
the PD bits.
3
MUTE
0
Selects whether the device will MUTE when
loss of signal is detected or add an offset to
prevent self oscillation. When an input
signal is detected (LOS=1), the device will
operate normally.
0: Loss of signal will force a small offset to
prevent self oscillation.
1: Loss of signal will force the channel to
MUTE.
2:0
7:5
SDTF0Thresh
HDTF1Thresh
010
100
Sets the Termination Fault threshold for
SDO0, when SD is set to SD rates (1).
Combines with SDTF0ThreshLSB in
register 03h (default for combined value is
0101).
06h
07h
R/W
R/W
OUTPUT1
Sets the Termination Fault threshold for
SDO1, when SD is set to HD rates (0).
Combines with HDTF1ThreshLSB in
register 07h (default for combined value is
1001).
4:0
7
AMP1
10000
1
SDO1 output amplitude in roughly 5 mV
steps.
OUTPUT1CTRL
HDTF1ThreshLSB
Least Significant Bit for HDTF1Thresh
detection threshold. Combines with
HDTF1Thresh bits in register 06h.
6
SDTF1ThreshLSB
1
Least Significant Bit for SDTF1Thresh
detection threshold. Combines with
SDTF1Thresh bits in register 07h.
5:3
2:0
RSVD
011
010
Reserved as 011. Always write 011 to these
bits.
SDTF1Thresh
Sets the Termination Fault threshold for
SDO1, when SD is set to SD rates (1).
Combines with SDTF1ThreshLSB in bit 6
(default for combined value is 0101).
14
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SNLS286I –APRIL 2008–REVISED APRIL 2013
Table 1. SMBus Registers (continued)
Address
R/W
Name
Bits
Field
Default
Description
08h
R/W
TEST
7:5
CMPCMD
000
Compare command. Determines whether
the peak value or the current value of the
Termination Fault counters is read in
registers 0Ah-0Dh.
000: Resets compare value to 00; registers
0Ah-0Dh all show current counter values.
Sets detection to look for MAX peak values.
001: Capture counter 0. Register 0Ah
shows peak value.
010: Capture counter 1. Register 0Bh
shows peak value.
011: Capture counter 2. Register 0Ch
shows peak value.
100: Capture counter 3. Register 0Dh
shows peak value.
101: Resets compare value to 1Fh. Sets
detection to look for MIN peak values.
110, 111: Reserved.
4:0
RSVD
00000
Reserved as 00000. Always write 00000 to
these bits.
09h
R
REV
7:5
4:3
2:0
RSVD
000
10
Reserved.
DIEREV
PARTID
Die Revision.
010
Part Identifier. Note that single output
devices (LMH0303) have the LSB=1. Dual
output devices (LMH0307) have the LSB=0.
0Ah
0Bh
0Ch
0Dh
R
R
R
R
TF0PCOUNT
TF0NCOUNT
TF1PCOUNT
TF1NCOUNT
7:5
4:0
RSVD
000
Reserved.
TF0PCOUNT
00000
This is either the current value of TF0P
Counter, or the peak value of the counter,
depending on CMPCMD in register 08h.
7:5
4:0
RSVD
000
Reserved.
TF0NCOUNT
00000
This is either the current value of TF0N
Counter, or the peak value of the counter,
depending on CMPCMD in register 08h.
7:5
4:0
RSVD
000
Reserved.
TF1PCOUNT
00000
This is either the current value of TF1P
Counter, or the peak value of the counter,
depending on CMPCMD in register 08h.
7:5
4:0
RSVD
000
Reserved.
TF1NCOUNT
00000
This is either the current value of TF1N
Counter, or the peak value of the counter,
depending on CMPCMD in register 08h.
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REVISION HISTORY
Changes from Revision H (April 2013) to Revision I
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 15
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PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2013
PACKAGING INFORMATION
Orderable Device
LMH0307GR/NOPB
LMH0307GRE/NOPB
LMH0307GRX/NOPB
LMH0307SQ/NOPB
LMH0307SQE/NOPB
LMH0307SQX/NOPB
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
csBGA
csBGA
csBGA
WQFN
WQFN
WQFN
NYA
25
25
25
16
16
16
1000
Green (RoHS CU SNAGCU Level-1-260C-UNLIM
& no Sb/Br)
307G
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NYA
NYA
RUM
RUM
RUM
250
3500
1000
250
Green (RoHS CU SNAGCU Level-1-260C-UNLIM
& no Sb/Br)
307G
307G
L0307
L0307
L0307
Green (RoHS CU SNAGCU Level-1-260C-UNLIM
& no Sb/Br)
Green (RoHS
& no Sb/Br)
CU SN
CU SN
CU SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Green (RoHS
& no Sb/Br)
4500
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH0307GR/NOPB
LMH0307GRE/NOPB
LMH0307GRX/NOPB
LMH0307SQ/NOPB
LMH0307SQE/NOPB
LMH0307SQX/NOPB
csBGA
csBGA
csBGA
WQFN
WQFN
WQFN
NYA
NYA
NYA
RUM
RUM
RUM
25
25
25
16
16
16
1000
250
178.0
178.0
330.0
178.0
178.0
330.0
12.4
12.4
12.4
12.4
12.4
12.4
3.3
3.3
3.3
4.3
4.3
4.3
3.3
3.3
3.3
4.3
4.3
4.3
1.6
1.6
1.6
1.3
1.3
1.3
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
3500
1000
250
4500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMH0307GR/NOPB
LMH0307GRE/NOPB
LMH0307GRX/NOPB
LMH0307SQ/NOPB
LMH0307SQE/NOPB
LMH0307SQX/NOPB
csBGA
csBGA
csBGA
WQFN
WQFN
WQFN
NYA
NYA
NYA
RUM
RUM
RUM
25
25
25
16
16
16
1000
250
210.0
210.0
367.0
213.0
213.0
367.0
185.0
185.0
367.0
191.0
191.0
367.0
35.0
35.0
35.0
55.0
55.0
35.0
3500
1000
250
4500
Pack Materials-Page 2
MECHANICAL DATA
NYA0025A
GRA25A (Rev A)
www.ti.com
MECHANICAL DATA
RUM0016A
SQB16A (Rev A)
www.ti.com
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