LMH2190 [TI]
具有 I2C 接口的四通道 27MHz 时钟树驱动器;
| 型号： | LMH2190 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 I2C 接口的四通道 27MHz 时钟树驱动器 时钟 驱动 驱动器 |
| 文件： | 总31页 (文件大小：944K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMH2190
www.ti.com
SNAS473H –JUNE 2009–REVISED MAY 2013
LMH2190 Quad Channel 27 MHz Clock Tree Driver with I2C Interface
Check for Samples: LMH2190
1
FEATURES
DESCRIPTION
The LMH2190 is a quad channel configurable clock
tree driver which supplies a digital system clock to
peripherals in mobile handsets or other applications.
It provides a solution to clocking issues such as
limited drive capability for fanout or longer traces,
protection of the master clock from varying loads and
frequency pulling effects, isolation buffering from
noisy modules, and crosstalk isolation. It has very low
phase noise which enables it to drive sensitive
modules such as Wireless LAN and Bluetooth.
2
•
•
•
•
•
•
•
•
•
•
1 Input Clock, 4 Output Clocks
Supports both Square or Sine Wave Input
1.8V Square Wave Clock Outputs
Skewed Clock Outputs
Independent Clock Request
High Isolation of Supply Noise to Clock Input
High Output to Output Isolation
Output Drive up to 50 pF
The LMH2190 can be clocked up to 27 MHz, and has
an independent clock request pin for each clock
output which allows the peripheral to control the
clock. It features an integrated LDO which provides
an ultra low noise voltage supply with 10 mA external
load current which can be used to supply the TCXO
or other clock source.
The I2C serial interface can be used to override the
default configuration of the device to optimize the
LMH2190 for the application. Some of these
programmable features include setting the polarity of
both the clock and the clock request inputs. In
addition, the clock outputs have programmable output
drive current to optimize for the connected load. EMI
switching noise can be controlled by configuring
output drive and skew settings.
EMI Controlled Output Edges and EMI Filtering
Integrated 1.8V Low-Dropout Regulator
–
Low Output Noise Voltage
–
10 mA load Current
•
•
•
I2C Configurable up to 400 kHz (Fast Mode)
Ultra Low Standby Current
VBAT Range = 2.5V to 5.5V
APPLICATIONS
•
•
•
Mobile Handsets
PDAs
Portable Equipment
The LMH2190 quad clock distributor is offered in a
tiny 1.61mm x 1.61mm 16 bump DSBGA package. Its
small size and low supply current make it ideal for
portable applications.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2013, Texas Instruments Incorporated
LMH2190
SNAS473H –JUNE 2009–REVISED MAY 2013
www.ti.com
Typical Application
V
BAT
C
BAT
V
BAT
1 mF
A1
V
OUT B1
1.8V LDO, 10 mA
C
OUT
2.2 mF
A3 CLK1
A4 CLK2
D4 CLK3
PERIPHERAL
C
IN
PERIPHERAL
PERIPHERAL
PERIPHERAL
470 pF
SCLK_IN
CLOCK
TREE
DRIVER
C1
C2
V
DD
C
CLK
10 nF
CLOCK
SCLK_REQ
EN
GND
CLK4
D3
CONTROL
LOGIC
R
1,2
5.1 kW
B3
CLK_REQ1
CLK_REQ2
CLK_REQ3
CLK_REQ4
B4
C4
C3
ENABLE
SCL
A2
D2
D1
CLOCK
REQUEST
CPU/
BASE
BAND
2
I C
SDA
LMH2190
B2
V
SS
2
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SNAS473H –JUNE 2009–REVISED MAY 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)(2)
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
VBAT - VSS
-0.3V to 6V
-0.3V to (VOUT + 0.3V)
+/- 65 mA
LVCMOS port IO voltage
Current on CLKx pins
(3)
ESD Tolerance
Human Body Model
Machine Model
2000V
200V
Storage Temperature Range
−65°C to 150°C
150°C
(4)
Junction Temperature
Maximum Lead Temperature
(Soldering,10 sec)
230°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but performance is not specified. For specifications and the test conditions, see the
Electrical Characteristics Tables.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human body model, applicable std. MIL-STD-883, Method 3015.7. Machine model, applicable std. JESD22–A115–A (ESD MM std of
JEDEC). Field-Induced Charge-Device Model, applicable std. JESD22–C101–C. (ESD FICDM std. of JEDEC)
(4) The maximum power dissipation is a function of TJ(MAX) , θJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly onto a PC board.
(1)
OPERATING RATINGS
Supply Voltage (VBAT - VSS
)
2.5V to 5.5V
0 to 2V
VENABLE
Input Clock, SCLK_IN
DC Mode
32 kHz to 27 MHz
13 MHz to 27 MHz
45% to 55%
AC Mode
Duty Cycle
Temperature Range
-40°C to +85°C
113.6°C/W
(2)
Package Thermal Resistance θJA
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but performance is not specified. For specifications and the test conditions, see the
Electrical Characteristics Tables.
(2) The maximum power dissipation is a function of TJ(MAX) , θJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly onto a PC board.
Copyright © 2009–2013, Texas Instruments Incorporated
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(1)(2)
3.5 V DC AND AC ELECTRICAL CHARACTERISTICS
Unless otherwise specified, all limits are specified at TA = 25°C, VBAT = 3.5V, fSCLK_IN = 26 MHz, COUT = 2.2 µF, VDD_IO = 1.8V
(See Figure 6 ) (3), IOUT = 1 mA, Registers are in default setting. Boldface limits apply at the temperature extremes.
(4)
(5)
(4)
Symbol
Parameter
Condition
Min
Typ
Max
Units
(6)
Supply Current
IDD
Active Supply Current
Clock outputs toggling at 26 MHz
without external capacitors on
3
mA
CLK1/2/3/4, LDO is ON, IOUT = 0 mA
Shutdown Supply Current
In Shutdown. No clocks toggling. LDO
is OFF
0.1
1
1
μA
μA
In Shutdown. Input CLK toggling, no
Clock outputs toggling. LDO is OFF
0.1
36
50
IDDQ
Quiescent Supply Current
No Clock outputs toggling. LDO is ON,
IOUT = 0 mA
60
80
No Clock outputs toggling, LDO is ON,
IOUT = 10 mA
IDDEN
Current to Enable pin
I2C port is operational
I2C port is idle
300
0.1
μA
CPD
Power Dissipation Capacitance
per CLK output,
Defined with respect to VOUT = 1.8V
15.7
6.5
17.5
pF
(7)
Clock Outputs (CLK1/2/3/4)
tpLH
Propagation Delay SCLK_IN to
50% to 50%
10
ns
ns
(7)
CLK1 - Low to High, Figure 1
tpHL
Propagation Delay SCLK_IN to
50% to 50%
7.5
6
11
8.5
7.3
(7)
CLK1 - High to Low, Figure 1
tSKEW
Skew Between Outputs (Either
CLK1 to CLK2, 50% to 50%
3
1
(7)
Edge), Figure 1,
ns
CLK2 to CLK3 and CLK3 to CLK4,
50% to 50%
3.5
(7)(8)
tRISE
Rise Time, Figure 3,
CL = 10 pF to 50 pF, 20% to 80%
CL = 10 pF to 50 pF, 80% to 20%
CL = 10 pF to 50 pF
3
6
5
ns
%
(7)(8)
tFALL
Fall Time, Figure 3
2.5
CLK_DC
Output Clock Duty Cycle,
42
50
58
(7)
Figure 3,
JitterRMS
Additive RMS period Jitter
BW = 100 Hz to 1 MHz
CLK1
CLK2
CLK3
CLK4
100
240
330
400
fs
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
(2) CBAT, COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
(3) VDD_IO is equal to VOUT when the LDO is enabled and it is equal to VENABLE when it is disabled.
(4) Limits are 100% production tested at 25°C. Limits over temperature range are specified through correlations using statistical quality
control (SQC) method.
(5) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped
production material.
(6) IDD current depends on switching frequency and load.
(7) This parameter is specified by design and/or characterization and is not tested in production.
(8) Appropriate output load register must be set.
4
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SNAS473H –JUNE 2009–REVISED MAY 2013
3.5 V DC AND AC ELECTRICAL CHARACTERISTICS (1)(2) (continued)
Unless otherwise specified, all limits are specified at TA = 25°C, VBAT = 3.5V, fSCLK_IN = 26 MHz, COUT = 2.2 µF, VDD_IO = 1.8V
(See Figure 6 ) (3), IOUT = 1 mA, Registers are in default setting. Boldface limits apply at the temperature extremes.
(4)
(5)
(4)
Symbol
Parameter
Condition
Min
Typ
-130
Max
Units
Phase
Noise
CLK1 Additive Phase Noise with
all Outputs toggling
f = 100 Hz
f = 1 kHz
-144
-152
-158
-165
-128
-139
-146
-151
-153
-127
-138
-144
-148
-150
-125
-135
-142
-147
-148
f = 10 kHz
f = 100 kHz
f = 1 MHz
f = 100 Hz
f = 1 kHz
CLK2 Additive Phase Noise with
all Outputs toggling
f = 10 kHz
f = 100 kHz
f = 1 MHz
f = 100 Hz
f = 1 kHz
dBc/Hz
CLK3 Additive Phase Noise with
all Outputs toggling
f = 10 kHz
f = 100 kHz
f = 1 MHz
f = 100 Hz
f = 1 kHz
CLK4 Additive Phase Noise with
all Outputs toggling
f = 10 kHz
f = 100 kHz
f = 1 MHz
VOH
VOL
CLK1/2/3/4 Output Voltage High
Level
CLK1/2/3/4 = -2 mA
1.6
V
CLK1/2/3/4 Output Voltage Low
Level
CLK1/2/3/4 = 2 mA
0.2
ROFF
Output Impedance when disabled LDO enabled
LDO disabled
grounded
diode to ground
System Clock Input (SCLK_IN)
VIH SCLK_IN Input Voltage High Level DC Mode
0.65 x
VOUT
2.0
1.8
V
V
AC Mode
1.2
VIL
SCLK_IN Input Voltage Low Level DC Mode
0.35 x
VOUT
0
AC Mode
0
0.6
0.1
IIH
SCLK_IN Input Current High Level SCLK_IN = 1.8V, Clock path disabled
SCLK_IN Input Current Low Level SCLK_IN = VSS, Clock path disabled
0
0
µA
µA
pF
V
IIL
-0.1
(9)
CIN
VBIAS
RIN
Input Capacitance
7.5
0.805
30
10
DC Bias Voltage
Input Resistance
AC Mode
AC Mode, Clock path enabled.
21
kΩ
(9) This parameter is specified by design and/or characterization and is not tested in production.
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3.5 V DC AND AC ELECTRICAL CHARACTERISTICS (1)(2) (continued)
Unless otherwise specified, all limits are specified at TA = 25°C, VBAT = 3.5V, fSCLK_IN = 26 MHz, COUT = 2.2 µF, VDD_IO = 1.8V
(See Figure 6 ) (3), IOUT = 1 mA, Registers are in default setting. Boldface limits apply at the temperature extremes.
(4)
(5)
(4)
Symbol
Parameter
Condition
Min
Typ
Max
Units
Clock Request Output (SCLK_REQ)
tpLH
tpHL
VOH
Propagation Delay, Push-Pull and 50% to 50%
Open Source, Figure 2,
21
15
32
21
(10)
ns
Propagation Delay, Push-Pull and 50% to 50%
(10)
Open Drain, Figure 2,
SCLK_REQ Output Voltage High
Level
SCLK_REQ = -500 µA, Push-Pull
Output
1.52
1.52
V
V
SCLK_REQ = -500 µA, Open Source
Output
VOL
SCLK_REQ Output Voltage Low
Level
SCLK_REQ = 500 µA, Push-Pull Output
0.2
0.2
SCLK_REQ = 500 µA, Open Drain
Output
Clock Request Inputs (CLK_REQ1/2/3/4)
tSET
Setup Time from CLK_REQx to
SCLK_IN, to enable CLKx,
Figure 4,
16
ns
(10)
VIH
VIL
IIH
CLK_REQ1/2/3/4 Input Voltage
High Level
0.8 x
VDD_IO
V
V
CLK_REQ1/2/3/4 Input Voltage
Low Level
0.2 x
VDD_IO
CLK_REQ1/2/3/4 Input Current
High Level
200 kΩ internal pull down resistor.
CLK_REQ1/2/3/4 = 1.8V
8.3
12.7
0.1
µA
µA
Without internal / external pull down
resistor. CLK_REQ1/2/3/4 = 1.8V
0
0
IIL
CLK_REQ1/2/3/4 Input Current
Low Level
VIL = VSS
-0.1
(11)
SCL and SDA Inputs, VENABLE = 1.8V
VIH
VIL
IIH
SCL and SDA Input Voltage High
Level
0.8 x
VENABLE
V
V
SCL and SDA Input Voltage Low
Level
0.2 x
VENABLE
SCL and SDA Input Current High SCL/SDA = VENABLE
Level
0
0.1
µA
IIL
SCL and SDA Input Current Low
Level
100 kΩ internal Pull-up resistor,
SCL/SDA = VSS
-28
-18
µA
V
VOL
SDA Output Voltage Low Level
SDA = 3 mA
0.2
ENABLE Input
VIH
VIL
IIH
ENABLE Input Voltage High Level
ENABLE Input Voltage Low Level
1.65
-0.1
2
V
V
0.5
0.1
ENABLE Input Current High Level ENABLE = VOUT
ENABLE Input Current Low Level ENABLE = VSS
µA
µA
IIL
(10) This parameter is specified by design and/or characterization and is not tested in production.
(11) I2C interface uses IO cells specified at 1.8V typical supply (1.6V Min - 2.0V Max).
6
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3.5 V DC AND AC ELECTRICAL CHARACTERISTICS (1)(2) (continued)
Unless otherwise specified, all limits are specified at TA = 25°C, VBAT = 3.5V, fSCLK_IN = 26 MHz, COUT = 2.2 µF, VDD_IO = 1.8V
(See Figure 6 ) (3), IOUT = 1 mA, Registers are in default setting. Boldface limits apply at the temperature extremes.
(4)
(5)
(4)
Symbol
LDO
Parameter
Condition
Min
Typ
Max
Units
VOUT
ILOAD
VDO
Output Voltage
IOUT = 1 mA
1.78
1.805
1.82
10
V
(12)
Load Current
Dropout Voltage
VOUT > 1.74V
0
mA
mV
mA
(13)
VOUT = 1.7V, IOUT = 10 mA
100
300
93
90
78
62
54
50
42
35
150
ISC
Short Circuit Current Limit
PSRR
Power Supply Rejection Ratio
VBAT ripple = 200 mVPP
IOUT = 10 mA
,
f = 100 Hz
f = 217.5 Hz
f = 1 kHz
f = 10 kHz
f = 50 kHz
f = 100 kHz
f = 1 MHz
dB
f = 3.25 MHz
EN
Output Noise Voltage
Thermal Shutdown
BW = 10Hz to 100 kHz, VBAT = 4.2V,
COUT = 2.2 µF, All Outputs are Off
10
µVRMS
°C
TSHTDWN
Temperature
Hysteresis
160
20
(14)
ΔVOUT
Line Transient
VBAT = (VOUT (NOM) + 1.0V) to (VOUT
(NOM) + 1.6V) in 30 µs
-1
mV
VBAT = (VOUT (NOM) + 1.6V) to (VOUT
(NOM) + 1.0V) in 30 µs
1
(14)
Load Transient
IOUT = 0 mA to 10 mA in 10 µs
IOUT = 10 mA to 0 mA in 10 µs
-70
mV
30
(14)
Overshoot on Startup
100
mV
Ω
ROUT
TON
DC Output Resistance
5
(14)
Turn on Time
to 95% of VOUT (NOM)
185
270
µs
(12) The device maintains stable, regulated output voltage without a load.
(13) Dropout voltage is the voltage difference between the supply voltage and the output voltage at which the output voltage drops to 100
mV below its nominal value.
(14) This parameter is specified by design and/or characterization and is not tested in production.
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TIMING WAVEFORMS
50%
50%
SCLK_IN
CLK1
tp
LH
tp
HL
50%
50%
Skew
Skew
50%
50%
CLK2
Figure 1. Clock Output Timing Waveforms
50%
50%
CLK_REQx
tp
LH
tp
HL
50%
50%
SCLK_REQ
Figure 2. Clock Request Timing Waveforms
CLK_DC
80%
20%
80%
20%
50%
CLKx
t
t
RISE
FALL
Figure 3. Rise / Fall Time and Duty Cycle Waveform for Clock Outputs
50%
CLK_REQx
t
SET
50%
SCLK_IN
Figure 4. Setup Time from SCLK_IN to CLK_REQ
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Connection Diagram
CLK_
REQ2
CLK_
REQ3
4
3
2
1
CLK2
CLK1
CLK3
CLK4
SCL
CLK_
REQ1
CLK_
REQ4
SCLK_
REQ
Enable
V
SS
SCLK_IN
SDA
V
V
Out
BAT
A
B
C
D
Figure 5. 16-Bump DSBGA
See YFQ0016 Package
PIN DESCRIPTIONS(1)
Pin
C1
C2
A3
Pin Name
SCLK_IN
SCLK_RQ
CLK1
Port/Direction
Host
Type
DESCRIPTION
I
Source Clock Input
Host
O
Source Clock Request
Clock Output 1
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Peripheral
Host
O
B3
CLK_REQ1
CLK2
I
Clock Request Input 1
Clock Output 2
A4
O
B4
CLK_REQ2
CLK3
I
Clock Request Input2
Clock Output 3
D4
C4
D3
C3
A2
O
CLK_REQ3
CLK4
I
Clock Request Input 3
Clock Output 4
O
CLK_REQ4
ENABLE
SCL
I
I
Clock Request Input 4
Enable Device, Active High
I2C Clock Input, 100 kΩ Pull-up to ENABLE
I2C Data I/O, 100 kΩ Pull-up to ENABLE
Power Supply
D2
D1
A1
Host
I
SDA
Host/Bidrectional
Battery/Input
LDO/Output
Ground
I/O
VBAT
Power
Power
Ground
B1
VOUT
Power Supply to Clock Source and Clock Outputs
Ground Pin
B2
VSS
(1) I = Input, O = Output, I/O = Input / Output
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V
OUT
A1
B1
V
OUT
V
1.8V LDO
BAT
1
0
V
DD_IO
A3
A4
D4
D3
CLK1
CLK2
CLK3
CLK4
SD LOGIC
CLOCK
TREE
DRIVER
C1
SCLK_IN
V
BAT
A2
ENABLE
CONTROL
LOGIC
2
D2
I C
SCL
VDD_IO
D1
SDA
B3
CLK_REQ1
CLK_REQ2
CLK_REQ3
CLK_REQ4
B4
C4
C3
CLOCK
REQUEST
C2
SCLK_REQ
LMH2190
B2
V
SS
Figure 6. LMH2190 Block Diagram
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TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise specified, TA = 25°C, VBAT = 3.5V, fSCLK_IN = 26 MHz, COUT = 2.2 µF, VDD_IO = 1.8V (See Figure 19),
Registers are in default configuration.
Supply Current
vs.
Supply Current
vs.
Supply Voltage
Input Clock Frequency
7.45
6
- All Clocks Toggling
- 22.5 pF Capacitive Load per CLK
- No external Capacitor on CLK1/2/3/4
- SCLK_IN = 0 to 1.8V Square Wave
- DC Mode
7.40
5
7.35
7.30
4
7.25
7.20
3
2
7.15
1
0
7.10
7.05
2.5
3.0
3.5
4.0
(V)
4.5
5.0
5.5
0
10
20
30
40
V
BAT
FREQUENCY (MHz)
Figure 7.
Figure 8.
Supply Current
vs.
Capacitive Load
LDO Output Voltage
vs.
Supply Voltage
15
1.80
- Appropriate Drive Strength Setting
- SCLK_IN = 0 to 1.8V Square Wave
- DC Mode
12
1.78
9
1.76
6
1.74
3
1.72
I
= 10 mA
5.0
OUT
0
1.70
2.5
3.0
3.5
4.0
(V)
4.5
5.5
0
10
20
30
40
50
CAPACITIVE LOAD (pF)
V
BAT
Figure 9.
Figure 10.
LDO Output Voltage
vs.
LDO Output Current
LDO Output Voltage
vs.
Time
1.82
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.80
1.78
1.76
1.74
C
OUT
= 2.2 mF
1.72
0
2
4
6
8
10
I
(mA)
OUT
TIME (50 ms/DIV)
Figure 11.
Figure 12.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, TA = 25°C, VBAT = 3.5V, fSCLK_IN = 26 MHz, COUT = 2.2 µF, VDD_IO = 1.8V (See Figure 19),
Registers are in default configuration.
Additive Phase Noise
vs.
Frequency Offset
CLK1 Response, CL = 10 pF
-100
-110
-120
-130
-140
-150
-160
-170
-180
SCLK_IN
CLK3
CLK4
CLK1
DRIVE STRENGTH = 10 - 15 pF
100
1k
10k
100k
1M
FREQUENCY OFFSET (Hz)
TIME (5 ns/DIV)
Figure 13.
Figure 14.
CLK1 Response, CL = 22pF
CLK1 Response, CL = 33 pF
SCLK_IN
SCLK_IN
CLK1
CLK1
DRIVE STRENGTH = 15 - 22.5 pF
DRIVE STRENGTH = 22.5 - 33.5 pF
TIME (5 ns/DIV)
TIME (5 ns/DIV)
Figure 15.
Figure 16.
Power Supply Rejection Ratio
vs.
Frequency
CLK1 Response, CL = 50 pF
100
80
60
40
20
0
SCLK_IN
CLK1
I
V
V
= 10 mA
: No capacitors
: 2.2 #F and 100 nF
OUT
OUT
BAT
DRIVE STRENGTH = 33.5 - 50 pF
100
1k
10k
100k
1M
TIME (5 ns/DIV)
FREQUENCY (Hz)
Figure 17.
Figure 18.
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APPLICATION INFORMATION
The LMH2190 is a quad channel configurable clock distribution device which supplies a digital system clock to
peripherals in mobile handsets or other applications. Examples of peripherals are Bluetooth, Wireless LAN,
and/or Digital Video Broadcast-H (DVB-H).
The LMH2190 provides a solution to clocking issues such as limited drive capability, frequency pulling and
crosstalk. The drive capability of a TCXO can be insufficient when traces are long and/ or multiple peripherals
are connected to one TCXO. The LMH2190’s clock outputs can be configured independently to drive capacitive
loads up to 50 pF per channel. The buffer function of the LMH2190 prevents frequency pulling of the TCXO.
Frequency pulling can occur when the TCXO observes varying loads. A peripheral device that shuts down can
cause this load variation for instance. Crosstalk between peripheral devices is minimal since each peripheral has
its own LMH2190 digital clock output. Also isolation from peripheral to TCXO is specified by use of the LMH2190.
Adding a component in the clock path inherently means adding noise. The LMH2190 though has excellent phase
noise specifications in order to minimize degradation of the clock quality. A typical LMH2190 application is
depicted in Figure 19.
The LMH2190 clock tree driver can be divided into 4 blocks:
•
Clock tree driver
The clock tree driver provides a clean clock to a maximum of 4 separately connected peripheral devices.
Clock request logic
–
•
–
Independent clock request inputs allow the peripheral to control when the particular clock should be
enabled. Further, the clock request inputs control the source clock request (SCLK_REQ) and enabling of
the LDO.
•
•
Low Dropout regulator (LDO)
–
The LDO provides a low noise, high PSRR supply voltage that enables low phase noise on the clock
outputs, and low quiescent current for portable applications. It can also be used to provide a low noise
supply to the TCXO eliminating the need for a separate LDO.
I2C Control logic
–
An I2C control port enables re-configuration of settings of many features of the device in order to optimize
the device performance based on the application. For these settings see Table 2, Table 3, Table 4,
Table 5, and Table 6 in I2C Registers.
All the blocks can be switched into a low power-consumption mode to save energy. This functionality is
controlled via the ENABLE pin.
The following sections provide an explanation on PHASE NOISE and a detailed description of each block.
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V
BAT
C
BAT
V
BAT
1 mF
A1
V
OUT B1
1.8V LDO, 10 mA
C
OUT
2.2 mF
A3 CLK1
A4 CLK2
D4 CLK3
PERIPHERAL
C
IN
PERIPHERAL
PERIPHERAL
PERIPHERAL
470 pF
SCLK_IN
CLOCK
TREE
DRIVER
C1
C2
V
DD
C
CLK
10 nF
CLOCK
SCLK_REQ
EN
GND
CLK4
D3
CONTROL
LOGIC
R
1,2
5.1 kW
B3
CLK_REQ1
CLK_REQ2
CLK_REQ3
CLK_REQ4
B4
C4
C3
ENABLE
SCL
A2
D2
D1
CLOCK
REQUEST
CPU/
BASE
BAND
2
I C
SDA
LMH2190
B2
V
SS
Figure 19. Typical LMH2190 Setup
PHASE NOISE
An important specification for oscillators and clock buffers is phase noise. It determines the timing and thus
accuracy of various peripheral devices in a cell phone such as Bluetooth, WLAN and DVB-H.
Phase noise is expressed in the frequency domain and is usually specified at a number of offset frequencies
from the carrier frequency. The phase noise of the oscillator and the LMH2190 together determine the phase
noise of the clock that is distributed to the peripheral devices. Therefore an additive phase noise is specified for
the LMH2190 rather than its total output phase noise since that depends on the TCXO connected to the
LMH2190.
Knowing the TCXO phase noise and the additive phase noise of the LMH2190, the total phase noise to the
peripheral can be calculated:
PN_TCXO
10
10
add.PN_LMH2190
10
+ 10
PN = 10 LOG
Where, PN is the total phase noise at the output of the LMH2190, PN_TCXO is the TCXO’s phase noise and
add.PN_LMH2190 is the additive phase noise of the LMH2190, all in dBc/Hz.
CLOCK TREE DRIVER
The clock tree driver consists of one input that drives 4 outputs (Figure 20). It is supplied by the highly accurate
1.8V LDO. In default configuration the outputs are switched on when the clock request inputs are high. The input
as well as the output can be configured in several ways though I2C programming.
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Clock Tree Driver Input
The source clock input (SCLK_IN) is the input for the clock tree driver. It can be configured to DC or AC coupled
mode. In shutdown mode, the input stage is completely switched off to prevent unnecessary power consumption
when the source clock is still present.
In the DC coupled mode, the clock input may range from 32 kHz to 27 MHz. DC coupling mode requires that the
input is a square wave.
In AC mode an external capacitor needs to be connected in series with the clock source and the SCLK_IN pin to
block external DC. Internally, a DC bias network centers it at about VOUT/2. This enables the use of a sine wave
clock source with a amplitude between 0.8 VPP and 1.8 VPP. The bias voltage is enabled only when the clock
request output is activated in order to eliminate the DC power. In the AC coupled mode, the clock input may
range from 13 MHz up to 27 MHz. It is assumed to be a sine wave. Signals with sharp edges, such as square
wave signals, should be prevented as the DC control loop will not be able to maintain its internal DC level.
Clock Tree Driver Outputs
The LMH2190's clock tree driver outputs have many modes of operation to reduce power consumption and
minimize EMI. The output drive strength of the LMH2190 can be selected in 4 steps based on the load
capacitance it needs to drive. The configuration can be done via the I2C interface.
There are two dedicated methods for reducing EMI that can be selected through the I2C interface. As shown in
Figure 21 and Figure 22 the first method (default) skews all of the clock edges individually, so that the EMI
generated by the switching is spread out over time. The second method inverts two of the outputs and also
skews one pair from the other.
CLK1 ENABLE
CLK1
CLK1 LOAD
REG01-Bit0:1
CLK INPUT TYPE
REG00-Bit4
CLK2 ENABLE
CLK3 ENABLE
CLK4 ENABLE
CLK2
CLK3
CLK4
DC
AC
CLK2 LOAD
REG02-Bit0:1
1
0
SKEW
SETTING
SCLK_IN
CLK3 LOAD
REG03-Bit0:1
CLK TREE
REG00-Bit0
CLK4 LOAD
REG04-Bit0:1
Figure 20. Clock Tree Driver
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SCLK_IN
CLK1
SCLK_IN
CLK1
CLK2
CLK2
CLK3
CLK3
CLK4
CLK4
Figure 21. Clock Outputs Timing: With Skew only
CLOCK REQUEST LOGIC
Figure 22. Clock Outputs Timing: With Skew and
Inversion
The clock request logic enables an independent control of the clock tree driver outputs (CLK1 to CLK4) as well
as an overall source clock request (SCLK_REQ) and LDO enabling. Since the clock request logic always needs
to be active, it is supplied by either the output of the LDO (VOUT) or by the external ENABLE. Further details
about the selection between VOUT and ENABLE can be found in the LOW DROPOUT REGULATOR section later
in the datasheet.
Clock Request Inputs
A clock request input is provided for each clock output (Figure 23). This allows the peripheral device to control
the LMH2190 when it wants to receive a clock. In case the peripheral device does not have clock request
functionality, the CLKx_REQ can be wired to a logic high level to enable the clock output (in default register
setting). Alternatively, it can be controlled through I2C. The CLKx_REQ input can be configured to be active high
or active low. When the LDO is off, the clock request logic still need to be powered such that it can turn on the
LDO. This is why the ENABLE input is used to power the Clock Request Logic in case the LDO is off. Although
the CLK_REQ logic is supplied with 1.8V LDO voltage (or ENABLE), the CLKx_REQ input can tolerate voltages
up to VBAT
.
To prevent glitches on CLK outputs, enabling of the outputs is done synchronously. A latch is used to ensure that
the CLK outputs will be enabled on the falling edge of the source clock input (SCLK_IN).
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CLK_REQx INPUT POLARITY
REG0x-Bit2
CLK_REQx_FORCE ON
REG0x-Bit3
CLKx ENABLE
CLK_REQx
CLK_REQx INPUT VALUE
REG05-Bitx
0
1
CLK_REQx_FORCE OFF
REG0x-Bit4
200 kÖ
CLK_REQx PULL DOWN RESISTOR
REG0x-Bit5
Figure 23. Clock Request Input
System Clock Request Output
In the typical mode of operation, the clock request output will be enabled if one of the 4 CLK_REQ inputs is high
(Figure 24). However, this can be overridden via the I2C interface which has a register bit that forces the output
to be enabled, independent of the CLK_REQ input. The polarity of the output can be controlled via I2C
(CLK_REQ Output Polarity) along with whether the output is configured as push/pull, open drain or open source.
For the open drain case, there needs to be an external resistor that pulls the SCLK_REQ to a high level. This
high level may be greater than the LDO voltage of 1.8V, but not more than the supply voltage (VBAT) of the
LMH2190.
CLK_REQ OUTPUT TYPE
REG00-Bit1
CLK_REQ OUTPUT POLARITY
REG00-Bit2
V
DD_IO
CLKx_ENABLE
0
1
SCLK_REQ
CLK_REQ OUTPUT MODE
REG00-Bit3
SCLK_REQ OUTPUT VALUE
REG05-Bit5
Figure 24. System Clock Request Output
The System Clock Request Output pin can be used to enable or disable an external TCXO to save power
consumption. See Figure 25. The LDO powers the TCXO, while the SCLK_REQ enables or disables the TCXO.
If the TXCO doesn't have an enable pin, power savings can be realized by switching off the LMH2190's LDO and
therewith the TCXO.
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V
OUT
LMH2190
V
DD
EN
SCLK_REQ
TCXO
CLK_OUT
SCLK_IN
GND
Figure 25. TCXO Powered from LMH2190's LDO
Note that the LMH2190 initializes to its default settings when VBAT is powered-up. As a consequence, the
LMH2190 is in it's default state until it is configured through I2C. Because of this configuration the CLK1/2/3/4
outputs may transmit the clock to a peripheral upon startup when it is not requested by the peripheral and before
the device is initialized through the I2C port. This may happen for instance when the default settings of the device
for SCLK_REQ and CLK_REQ1/2/3/4 polarities do not correspond to what is expected by the TCXO and the
peripheral. Care must be taken to prevent any unwanted behavior in the peripheral device until the I2C port
correctly configures the device. The setting of the registers is maintained as long as the VBAT voltage is present.
LOW DROPOUT REGULATOR
The linear and low dropout regulator (LDO) is used to regulate the input voltage, VBAT, to generate an accurate
1.8V supply voltage. This allows the LMH2190 to suppress VBAT voltage ripples. A voltage ripple would distort
clock edges causing phase noise on the distributed clock signal.
In default mode the LDO is powered-up when one or more Clock Request inputs are high. Therefore the Clock
Request Logic needs to be powered continuously such that it can wake-up the LMH2190 and its LDO. The
VDD_IO voltage that takes care of supplying the Clock Request Logic can therefore be driven by either the LDO
output voltage or the ENABLE signal. Normally the VDD_IO signal is connected to the LDO output, unless the LDO
is in a low power shutdown mode. In that case the ENABLE signal will drive VDD_IO (Figure 26). As soon as there
is a clock request, the built in LDO will power up and takes over the sourcing of VDD_IO from the ENABLE signal.
LDO
V
BAT
V
OUT
V
OUT
V
BAT
LDO_EN
1
0
LDO MODE
REG00-Bit5:6
V
DD_IO
OFF
SD LOGIC
00
01
10
11
CLKx ENABLE
ENABLE
ON
TSD
REG05-Bit0
THERMAL
SHUTDOWN
Figure 26. Linear Regulator Block Diagram
The LDO contains thermal overheating detection. If it does overheat, the LMH2190 (except the register logic) will
shutdown and sets a status bit in the I2C status register.
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The LDO can be configured to be always ON for the case when it needs to supply power to the TCXO even
when the LMH2190 is not requesting any clocks to be distributed.
It is possible to use an external 1.8V supply connected to VOUT and shut off the internal LDO, although it is highly
recommended to use the internally generated 1.8V. If an external supply is used, care should be taken during
startup as the default configuration is for the internal LDO to be enabled. In this case, there could be contention
between the two supplies which could cause excessive current flow.
I2C CONTROL LOGIC
The LMH2190 can be controlled by a I2C host device. The I2C address of the LMH2190 is 38h. It can configure
the registers inside the LMH2190 to change the default configuration. The I2C communication is based on a
READ/WRITE structure, following the I2C transmission protocol. According to the I2C specification one set of pull-
up resistors needs to be present on the I2C bus.
Some of the features are for instance setting the polarity of the clock request inputs and outputs and setting the
drive strength of the clock outputs. It also allows direct control of the clock request signals and the LDO via the
I2C. The I2C interface is powered by the ENABLE, while the control logic and registers are powered by the VBAT
.
I2C Data Validity
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the state
of the data line should only change when SCL is LOW (Figure 27).
SCL
SDA
data
change
allowed
data
change
allowed
data
change
allowed
data
valid
data
valid
Figure 27. I2C Signals: Data Validity
I2C Start and Stop Condition
START and STOP bits classify the beginning and the end of the I2C session. START condition is defined as SDA
signal transitioning from HIGH to LOW while SCL line is HIGH (Figure 28). STOP condition is defined as the
SDA transitioning from LOW to HIGH while SCL is HIGH. The I2C master always generates START and STOP
bits. The I2C bus is considered to be busy after START condition and free after STOP condition. During data
transmission, I2C master can generate repeated START conditions. First START and repeated START
conditions are equivalent, function-wise.
SDA
SCL
S
P
STOP condition
START condition
Figure 28. I2C Start and Stop Conditions
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Transferring Data
Every frame on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated
by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver
must pull down the SDA line during the 9th clock pulse, signifying an acknowledge. A receiver which has been
addressed must generate an acknowledge after each byte has been received.
After the START condition, the I2C master sends a chip address (Figure 29). This address is seven bits long
followed by an eight bit which is a data direction bit (R/W). For the eighth bit, a “0” indicates a WRITE and a “1”
indicates a READ. The second byte selects the register to which the data will be written. The third byte contains
data to write to the selected register.
MSB
LSB
ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 R/W
Bit7
bit6
2
bit5
bit4
bit3
bit2
bit1
bit0
I C SLAVE address (chip address)
Figure 29. I2C Chip Address
Register changes take effect at the SCL rising edge during the last ACK from slave. An example of a WRITE
cycle is given in Figure 30. When a READ function is to be accomplished, a WRITE function must precede the
READ function, as shown in the Read Cycle waveform (Figure 31).
ack from slave
ack from slave
ack from slave
ack
start MSB Chip Address LSB
w
MSB Register 0x02h LSB ack MSB
Data
LSB ack stop
SCL
SDA
slave address =
start
w
ack register address = 0x02h ack
register 0x02h data
ack
stop
38 or 0111000
h
2
Figure 30. Example I2C Write Cycle
ack from slave
repeated start
ack from slave data from slave ack from master
ack from slave
start
w
ack
ack rs
r
MSB Chip Address LSB
ack
ack stop
LSB
MSB Chip Address LSB
MSB Register 0x00h LSB
MSB
Data
SCL
SDA
slave address =
38 or 0111000
slave address =
38 or 0111000
2
start
w
ack
ack rs
r ack register 0x05h data ack stop
register address = 0x05h
h
2
h
Figure 31. Example I2C Read Cycle
I2C Timing
The timing of the SDA and SCL signals is depicted in Figure 32 and the parameters are given in Table 1.
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SDA
SCL
10
8
7
6
1
7
8
2
5
1
4
9
3
Figure 32. I2C Timing Diagram
Table 1. I2C Timing
Limit
Units
Max
Symbol
Parameter
Min
fSCL
1
Clock Frequency
400
kHz
µs
Hold Time (repeated) START Condition
Clock Low Time
0.6
1.3
2
ns
3
Clock High Time
600
600
ns
4
Setup Time for a Repeated START Condition
ns
5
Data Hold Time (Output direction, delay generated by
LMH2190)
300
0
900
900
µs
ns
5
Data Hold Time (Input direction, delay generated by the
Master)
6
7
Data Setup Time
100
20+0.1 Cb
10+0.1 Cb
600
ns
ns
ns
ns
µs
pF
Rise Time of SDA and SCL
300
300
8
Fall Time of SDA and SCL
9
Set-up Time for STOP condition
Bus Free Time between a STOP and a START Condition
Capacitive Load for Each Bus Line
10
Cb
1.3
10
200
I2C Registers
Table 2. Configuration Register(1)
Field
Bits
Description
Output Mode
[0]
Sets the timing relationship of the clock
outputs (Figure 21 and Figure 22).
0 - All 4 outputs are skewed from each
other
1 - Two pair of outputs where one output of
the pair is the inversion of the other and the
second pair is skewed from the first pair.
Clock Request Output Type
[1]
Sets whether the output is push-pull or open
drain.
0 - Push-Pull Output
1 - Open Drain/Source Output (Open drain
with Active low output, Open source with
Active high output).
Clock Request Output Polarity
Clock Request Output Mode
[2]
[3]
Sets whether the clock request output is
active low or active high.
0 - Active low output
1 - Active high output
Sets how the clock request output operates.
0 - Use clock request inputs
1 - Force the clock request output to be
asserted.
(1) Address = 00H, type = R/W, reset value = 44H, 0100_0100, Bold face settings are the default configuration.
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Table 2. Configuration Register(1) (continued)
Field
Bits
Description
Clock Input Type
[4]
Sets whether the input is AC or DC coupled.
0 - AC coupled
1 - DC coupled
LDO Mode
Reserved
[6-5]
Sets the regulator mode of operation.
00 - OFF
01 - Reserved
10 - Track Clock Requests
11 - Force ON
[7]
Table 3. CLK1 Output Register(1)
Field
Bits
Description
CLK1 Load
[1-0]
Sets the drive strength of the clock output
based on the capacitive load.
00 - 10pF to 15pF
01 - 15pF to 22.5pF
10 - 22.5pF to 33.5pF
11 - 33.5pF to 50pF
CLK_REQ1 Input Polarity
[2]
[3]
Sets whether a logic low or high enables the
clock output.
0 - Logic low enables the clock output.
1 - Logic high enables the clock output.
CLK_REQ1 Force ON Control
Selects whether to use a clock request or
I2C logic to enable the output.
0 - Use the clock request pin to control
the output.
1 - Force the clock output to be enabled
(Force ON).
CLK_REQ1 Force OFF Control
CLK_REQ1 Pull down Resistor
[4]
[5]
Selects whether to use a clock request or
I2C logic to disable the output.
0 - Use the clock request pin to control
the output.
1 - Force the clock output to be disabled
(Force OFF). ”Force OFF" overrides ”Force
ON".
Selects whether an internal 200 kΩ pull
down resistor on the clock request input to
GND is present.
0 - No internal pull down resistor is
present.
1 - Internal 200 kΩ pull-down resistor is
present.
Reserved
Reserved
[6]
[7]
(1) Address = 01H, type = R/W, reset value = 06H, 0000_0110, Bold face settings are the default configuration.
Table 4. CLK2 Output Register(1)
Field
Bits
Description
CLK2 Load
[1-0]
Sets the drive strength of the clock output
based on the capacitive load.
00 - 10pF to 15pF
01 - 15pF to 22.5pF
10 - 22.5pF to 33.5pF
11 - 33.5pF to 50pF
CLK_REQ2 Input Polarity
[2]
Sets whether a logic low or high enables the
clock output.
0 - Logic low enables the clock output.
1 - Logic high enables the clock output.
(1) Address = 02H, type = R/W, reset value = 06H, 0000_0110, Bold face settings are the default configuration.
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Table 4. CLK2 Output Register(1) (continued)
Field
Bits
Description
CLK_REQ2 Force ON Control
[3]
Selects whether to use a clock request or
I2C logic to enable the output.
0 - Use the clock request pin to control
the output.
1 - Force the clock output to be enabled
(Force ON).
CLK_REQ2 Force OFF Control
CLK_REQ2 Pull down Resistor
[4]
[5]
Selects whether to use a clock request or
I2C logic to disable the output.
0 - Use the clock request pin to control
the output.
1 - Force the clock output to be disabled
(Force OFF). ”Force OFF" overrides ”Force
ON".
Selects whether an internal 200 kΩ pull
down resistor on the clock request input to
GND is present.
0 - No internal pull down resistor is
present.
1 - Internal 200 kΩ pull-down resistor is
present.
Reserved
Reserved
[6]
[7]
Table 5. CLK3 Output Register(1)
Field
Bits
Description
CLK3 Load
[1-0]
Sets the drive strength of the clock output
based on the capacitive load.
00 - 10pF to 15pF
01 - 15pF to 22.5pF
10 - 22.5pF to 33.5pF
11 - 33.5pF to 50pF
CLK_REQ3 Input Polarity
[2]
[3]
Sets whether a logic low or high enables the
clock output.
0 - Logic low enables the clock output.
1 - Logic high enables the clock output.
CLK_REQ3 Force ON Control
Selects whether to use a clock request or
I2C logic to enable the output.
0 - Use the clock request pin to control
the output.
1 - Force the clock output to be enabled
(Force ON).
CLK_REQ3 Force OFF Control
CLK_REQ3 Pull down Resistor
[4]
[5]
Selects whether to use a clock request or
I2C logic to disable the output.
0 - Use the clock request pin to control
the output.
1 - Force the clock output to be disabled
(Force OFF). ”Force OFF" overrides ”Force
ON".
Selects whether an internal 200 kΩ pull
down resistor on the clock request input to
GND is present.
0 - No internal pull down resistor is
present.
1 - Internal 200 kΩ pull-down resistor is
present.
Reserved
Reserved
[6]
[7]
(1) Address = 03H, type = R/W, reset value = 06H, 0000_0110, Bold face settings are the default configuration.
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Table 6. CLK4 Output Register(1)
Field
Bits
Description
CLK4 Load
[1-0]
Sets the drive strength of the clock output
based on the capacitive load.
00 - 10pF to 15pF
01 - 15pF to 22.5pF
10 - 22.5pF to 33.5pF
11 - 33.5pF to 50pF
CLK_REQ4 Input Polarity
[2]
[3]
Sets whether a logic low or high enables the
clock output.
0 - Logic low enables the clock output.
1 - Logic high enables the clock output.
CLK_REQ4 Force ON Control
Selects whether to use a clock request or
I2C logic to enable the output.
0 - Use the clock request pin to control
the output.
1 - Force the clock output to be enabled
(Force ON).
CLK_REQ4 Force OFF Control
CLK_REQ4 Pull down Resistor
[4]
[5]
Selects whether to use a clock request or
I2C logic to disable the output.
0 - Use the clock request pin to control
the output.
1 - Force the clock output to be disabled
(Force OFF). ”Force OFF" overrides ”Force
ON".
Selects whether an internal 200 kΩ pull
down resistor on the clock request input to
GND is present.
0 - No internal pull down resistor is
present.
1 - Internal 200 kΩ pull-down resistor is
present.
Reserved
Reserved
[6]
[7]
(1) Address = 04H, type = R/W, reset value = 06H, 0000_0110, Bold face settings are the default configuration.
Table 7. Status Register(1)
Field
Bits
Description
Thermal Shutdown (TSD)
[0]
Indicates if a thermal shutdown event has occurred.
0 - Thermal shutdown has not occurred.
1 - Thermal shutdown has occurred
CLK_REQ1 Input Value
CLK_REQ2 Input Value
CLK_REQ3 Input Value
CLK_REQ4 Input Value
SCLK_REQ Output Value
[1]
[2]
[3]
[4]
[5]
[6]
Captures the state of the generated clock request
input value.
0 - Generated clock request is low.
1 - Generated clock request is high.
Captures the state of the generated clock request
input value.
0 - Generated clock request is low.
1 - Generated clock request is high.
Captures the state of the generated clock request
input value.
0 - Generated clock request is low.
1 - Generated clock request is high.
Captures the state of the generated clock request
input value.
0 - Generated clock request is low.
1 - Generated clock request is high.
Captures the state of the system clock request output
value.
0 - System clock request is low.
1 - System clock request is high.
Reserved
(1) Address = 05H, type = R
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Table 7. Status Register(1) (continued)
Field
Bits
Description
Reserved
[7]
LAYOUT RECOMMENDATIONS
As with any other device, careful attention must be paid to the board layout. If the board isn't properly designed,
the performance of the device can be less than might be expected. Especially the input clock trace (SCLK_IN)
and output traces (CLK1/2/3/4) should be as short as possible to reduce the capacitive load observed by the
clock outputs. Also proper decoupling close to the device is necessary. Beside a capacitor in the µF range (See
Table 8), a capacitor of 100 nF on VBAT and VOUT is recommended close to device. The equivalent series
resistance (ESR) of the capacitors should be sufficiently low. A standard capacitor is usually adequate. Advised
values are given in Table 8. An evaluation board is available to ease evaluation and demonstrate a proper board
layout.
Table 8. Recommended Component Values
Symbol
Parameter
Min
0.47
1
Typ
1
Max
Units
(1)
CBAT
Capacitor on VBAT
µF
(1)
COUT
Capacitor on VOUT
2.2
ESR
Equivalent Series Resistance
Input AC Coupling Capacitor
5
500
mΩ
CSCLK_IN
330
470
10000
pF
(1) CBAT, COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCC's) used in setting electrical characteristics.
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REVISION HISTORY
Changes from Revision G (April 2013) to Revision H
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 25
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH2190TM-38/NOPB
ACTIVE
DSBGA
YFQ
16
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-20 to 85
AA
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Nov-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH2190TM-38/NOPB DSBGA
YFQ
16
250
178.0
8.4
1.7
1.7
0.76
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Nov-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
DSBGA YFQ 16
SPQ
Length (mm) Width (mm) Height (mm)
208.0 191.0 35.0
LMH2190TM-38/NOPB
250
Pack Materials-Page 2
MECHANICAL DATA
YFQ0016x
D
0.600±0.075
E
TMD16XXX (Rev A)
D: Max = 1.64 mm, Min = 1.58 mm
E: Max = 1.64 mm, Min = 1.58 mm
4215081/A
12/12
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
NOTES:
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