LMH2191TME/NOPB [TI]
双通道 52MHz 时钟树驱动器 | YFX | 8 | -40 to 85;
| 型号： | LMH2191TME/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 双通道 52MHz 时钟树驱动器 | YFX | 8 | -40 to 85 时钟 驱动 逻辑集成电路 驱动器 |
| 文件： | 总23页 (文件大小：1029K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMH2191
www.ti.com
SNAS485D –JULY 2010–REVISED MAY 2013
LMH2191 Dual Channel 52 MHz Clock Tree Driver
Check for Samples: LMH2191
1
FEATURES
DESCRIPTION
The LMH2191 is a dual-channel clock tree driver that
supplies a digital system clock to peripherals in
mobile handsets or other applications. It provides a
solution to clocking issues such as limited drive
capability for fanout or longer traces. It also provides
protection of the master clock from varying loads and
frequency pulling effects, isolation from noisy
modules, and crosstalk isolation. It has very low
phase noise which enables it to drive sensitive
modules such as Wireless LAN and Bluetooth.
2
•
•
•
•
•
•
•
One Input Clock, Two Output Clocks
1.8V Square Wave Clock Outputs
Inverted Clock Outputs
Independent Clock Requests
High Isolation of Supply Noise to Clock Input
High Output-to-Output Isolation
Integrated 1.8V Low-Dropout Regulator
–
–
Low Output-Noise Voltage
10 mA Load Current
The LMH2191 can be clocked up to 52 MHz and has
an independent clock request pin for each clock
output which allows the peripheral to control the
clock. It features an integrated LDO which provides
an ultra low-noise voltage supply with 10 mA external
load current which can be used to supply the TCXO
or other clock source. The LMH2191 dual clock
distributor is offered in a tiny 1.61 mm x 1.063 mm 8-
bump DSBGA package. Its small size and low supply
current make it ideal for portable applications.
•
•
•
•
EMI Filtering
Ultra Low Standby Current
VBAT Range = 2.5V to 5.5V
8-Bump DSBGA Package
APPLICATIONS
•
•
Mobile Handsets
Portable Equipment
Typical Application
V
BAT
V
BAT
C
BAT
1 µF
A1
LMH2191
V
B1
C1
OUT
1.8V LDO
C
OUT
V
DD
A2 CLK1
D2 CLK2
2.2 µF
Peripheral
Peripheral
Clock
Tree
SCLK_IN
C
Clock
Source
CLK
10 nF
Driver
C
SERIES
B2 CLK_REQ1
C2 CLK_REQ2
Clock
Request
D1
V
SS
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2013, Texas Instruments Incorporated
LMH2191
SNAS485D –JULY 2010–REVISED MAY 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS(1)(2)
VBAT - VSS
-0.3V to 6V
Supply Voltage
LVCMOS port IO voltage
Human Body Model
Machine Model
Charge Device Model
LDO
-0.3V to (VOUT + 0.3V)
2000V
200V
ESD Tolerance(3)
1000V
infinite
infinite
Output Short Circuit Duration(4)
Clock Output
For Soldering Information see http://www.ti.com/lit/SNOA549
Storage Temperature Range
−65°C to 150°C
Junction Temperature(5)
150°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not specified. For specifications and the test conditions, see
the Electrical Characteristics Tables.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human body model, applicable std. MIL-STD-883, Method 3015.7. Machine model, applicable std. JESD22–A115–A (ESD MM std of
JEDEC). Field-Induced Charge-Device Model, applicable std. JESD22–C101–C. (ESD FICDM std. of JEDEC)
(4) Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature
of 1500C.
(5) The maximum power dissipation is a function of TJ(MAX) , θJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly onto a PC board.
OPERATING RATINGS(1)
Supply Voltage (VBAT - VSS
Input Clock, SCLK_IN
Temperature Range
)
2.5V to 5.5V
10 MHz to 52 MHz
Frequency
Duty Cycle
45% to 55%
-40°C to +85°C
(2)
Package Thermal Resistance θJA
Board specification: 4LCELLPHONE
153 °C/W
Package YFX
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not specified. For specifications and the test conditions, see
the Electrical Characteristics Tables.
(2) The maximum power dissipation is a function of TJ(MAX) , θJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly onto a PC board.
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SNAS485D –JULY 2010–REVISED MAY 2013
3.5 V ELECTRICAL CHARACTERISTICS(1)
Unless otherwise specified, all limits are specified at TJ = 25°C, VBAT = 3.5V, CBAT = 1µF, COUT = 2.2 µF(2), fSCLK_IN = 26 MHz,
IOUT = 1mA, Boldface limits apply at the temperature extremes.
Symbol
Parameter
Condition
Min(3)
Typ(4)
Max(3)
Units
Supply Current(5)(6)
IDD
Supply Current
Active Mode SCLK_IN = 19.2 MHz;
both clock outputs toggling; CLOAD
CLK1/2 = 0pF; IOUT = 0mA
1.65
1.7
1.4
3.7
1.9
5
mA
mA
mA
mA
Active Mode SCLK_IN = 19.2 MHz;
both clock outputs toggling; CLOAD for
CLK1/2 = 33.5pF; IOUT = 0mA
4.45
4.50
Active Mode SCLK_IN = 26 MHz, both
clock outputs toggling, CLOAD for
CLK1/2 = 0pF, IOUT=0mA
2.15
2.25
Active Mode SCLK_IN = 26 MHz, both
clock outputs toggling, CLOAD for
CLK1/2 = 33.5 pF, IOUT=0mA
5.80
5.95
In shutdown. Input clock not active.
CLK_REQ1/2=Low
0.1
0.1
20
1
1
µA
uA
pF
In shutdown. Input clock toggling.
CLK_REQ1/2=Low
CPD
Power Dissipation Capacitance
per CLK output
CLOAD for CLK1,2 = 0pF, Defined with
respect to VOUT = 1.8V
23.0
24.0
Clock Outputs (CLK1/2) Figure 1, Figure 2
tPD_LH
tPD_HL
tSKEW
tRISE
Propagation Delay - Low to High
50% to 50%;
CLOAD = 33 pF; measured on CLK1
6.1
6.1
1.5
3.7
3.5
10.5
10.5
3.1
Propagation Delay - High to Low
50% to 50%;
CLOAD = 33 pF; measured on CLK1
ns
ns
Skew Between Outputs (Either
Edge)
Rise Time(7)
CLK1 to CLK2. 50% to 50%
For CL between 33.5 pF - 50 pF, 20% to
80%; typical value based on 40 pF load
2.1
5.9
tFALL
Fall Time(7)
For CL between 33.5 pF - 50 pF, 20% to
80%; typical value based on 40pF load
2
5
CLK_DC
JitterRMS
Output Clock Duty Cycle
Additive RMS period Jitter
For CL between 33.5 pF - 50 pF
42
50
95
58
%
fs
fSCLK-IN= 26 MHz, BW = CLK1
100 Hz to 1MHz
CLK2
110
(1) Electrical Table values apply only for factory testing (ATE) conditions at the temperature indicated. Factory testing conditions result in
very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables
under conditions of internal self-heating where TJ > TA.
(2) CBAT, COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
(3) Limits are 100% production tested at 25°C. Limits over temperature range are specified through correlations using statistical quality
control (SQC) method.
(4) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped
production material.
(5) Supply current depends on switching frequency and load.
(6) Positive current is current flowing into the device.
(7) This parameter is specified by design and/or characterization and is not tested in production.
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3.5 V ELECTRICAL CHARACTERISTICS(1) (continued)
Unless otherwise specified, all limits are specified at TJ = 25°C, VBAT = 3.5V, CBAT = 1µF, COUT = 2.2 µF(2), fSCLK_IN = 26 MHz,
IOUT = 1mA, Boldface limits apply at the temperature extremes.
Symbol
Parameter
Condition
Min(3)
Typ(4)
-128
-144
-150
-160
-163
-127
-146
-153
-161
-163
-127
-142
-148
-160
-162
-129
-144
-151
-163
-164
Max(3)
Units
CLK1
Phase
Noise
Additive Phase Noise
All outputs enabled at 26 f = 100 Hz
MHz
f = 1 kHz
f = 10 kHz
f = 100 kHz
f = 1 MHz
All outputs enabled at
19.2 MHz
f = 100 Hz
f = 1 kHz
f = 10 kHz
f = 100 kHz
f = 1 MHz
dBc/Hz
CLK2
Phase
Noise
Additive Phase Noise
All outputs enabled at 26 f = 100 Hz
MHz
f = 1 kHz
f = 10 kHz
f = 100 kHz
f = 1 MHz
All outputs enabled at
19.2 MHz
f = 100 Hz
f = 1 kHz
f = 10 kHz
f = 100 kHz
f = 1 MHz
VOH
CLK1/2 Output Voltage High Level IOH = -2mA (equivalent output load
1.6
800Ω)
V
VOL
CLK1/2 Output Voltage Low Level IOL = 2mA
0.2
ROFF
Ouput Impedance when disabled
with other output enabled (LDO
enabled)
grounded
Both outputs disabled (LDO disabled)
diode to ground
System Clock Input (SCLK_IN)
VI-pp
SCLK_IN peak- to- peak input
For duty cycle variation < 1%
SCLK_IN = 1.8V, CLK_REQ1/2=Low
SCLK_IN = 0V, CLK_REQ1/2=Low
CLK_REQ1/2=High
0.6
1
0
1.8
0.1
V
level(7)
IIH
Current into SCLK_IN pin (Input
HIGH)
µA
IIL
Current into SCLK_IN pin (Input
LOW)
Input Capacitance(8)
Input Resistance(8)
–0.1
0
CIN
RIN
7.5
14
13
20
pF
CLK_REQ1/2=High
see Application Note: Input Impedance
kΩ
Switching Characteristics: System Clock Input
fSCLK_IN
System Clock
10
26
50
52
MHz
%
CLK_DC
Input Clock Duty Cycle
45
55
(8) This parameter is specified by design and/or characterization and is not tested in production.
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SNAS485D –JULY 2010–REVISED MAY 2013
3.5 V ELECTRICAL CHARACTERISTICS(1) (continued)
Unless otherwise specified, all limits are specified at TJ = 25°C, VBAT = 3.5V, CBAT = 1µF, COUT = 2.2 µF(2), fSCLK_IN = 26 MHz,
IOUT = 1mA, Boldface limits apply at the temperature extremes.
Symbol
Parameter
Condition
Min(3)
Typ(4)
Max(3)
Units
ns
Clock Request Inputs (CLK_REQ1/2)
tSET
Setup Time from CLK_REQx to
SCLK_IN, to enable CLKx
(Figure 3)
12
6.2
VIH
CLK_REQ1/2 logic HIGH input
level. (clock output = ON)(9)
VBAT = 2.5V
VBAT = 3.5V
VBAT = 5.5V
VBAT = 2.5V
VBAT = 3.5V
VBAT = 5.5V
1.4
1.4
1.4
V
VIL
CLK_REQ1/2 logic LOW input
level. (clock output = OFF)
0.4
0.4
0.4
V
IIH
Current into CLK_REQ pin
Current into CLK_REQ pin
VIH = 1.8V, 200 kΩ pull down resistor
(Input HIGH)
8.5
0
14
µA
µA
IIL
VIL = VSS, (Input LOW)
-0.2
LDO
VOUT
ILOAD
VDO
ISC
Output Voltage
Load Current(10)
Dropout Voltage(11)
Short Circuit Current Limit
Power Supply Rejection Ratio
IOUT = 1mA
1.73
1.8
1.88
V
VOUT > 1.7V
0
10
mA
mV
mA
IOUT = 10 mA Vout=1.7V
125
300
92
PSRR
VBAT ripple = 200 mVPP
IOUT = 10 mA
,
f = 100 Hz
f = 217.5 Hz
f = 1 kHz
90
78
f = 10 kHz
f = 100 kHz
f = 1 MHz
60
dB
50
50
f = 3.25 MHz
42
EN
Output Noise Voltage(12)
BW = 10 Hz to 100 kHz,
CLK_REQ1/2=High, Input clock not
active
18
µVRMS
TSHTDWN
Thermal Shutdown
Line Transient
Temperature
Hysteresis
160
20
°C
ΔVOUT
VBAT = 2.8V to 3.4V in 30 µs, IOUT
1mA
=
-1
mV
mV
VBAT = 3.4V to 2.8V in 30 µs, IOUT
1mA
=
1
Load Transient
IOUT = 0mA to 10 mA in 10 µs
IOUT = 10 mA to 0mA in 10 µs
-15
10
20
Overshoot on Startup
DC Output Resistance
Turn on Time
mV
ROUT
TON
5
Ω
From rising edge of CLK_REQ1 to 95%
of VOUT(NOM)
260
350
200
µs
(9) Clock Request Inputs can tolerate logic high input levels up to VBAT
.
(10) The device maintains stable, regulated output voltage without a load.
(11) Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its
nominal value.
(12) The noise figure is the noise of the LDO only; harmonics of the output clocks are excluded.
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TIMING DIAGRAMS
DC 50%
80%
80%
50%
50%
20%
20%
CLKx
tFALL
tRISE
Figure 1. Rise / Fall time and Duty Cycle Waveform for Clock Outputs
50%
50%
SCLK_IN
CLK1
tpd
LH
tpd
HL
50%
50%
Skew
50%
Skew
50%
CLK2
Figure 2. Clock Output Timing Waveforms
50%
50%
CLK_REQ2
SET
CLK_REQ1
t
t
SET
50%
SCLK_IN
50%
Figure 3. Clock Request Timing Waveforms
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SNAS485D –JULY 2010–REVISED MAY 2013
Connection Diagram
Top View
CLK_
REQ1
CLK_
REQ2
2
1
CLK1
CLK2
V
V
SCLK_IN
C
V
SS
BAT
A
Out
B
D
Figure 4. 8-Bump DSBGA
See YFX0008 Package
PIN DESCRIPTIONS
Port /
Direction
Pin
Pin Name
Type(1)
Description
C1
A2
B2
D2
C2
A1
SCLK_IN
CLK1
Host
Input
Output
Input
Source Clock Input
Clock Output 1
Peripheral
CLK_REQ1 Peripheral
CLK2 Peripheral
CLK_REQ2 Peripheral
Clock Request Input 1 Clock1 = ON at high level
Clock Output 2
Output
Input
Clock Request Input 2 Clock2 = ON at high level
Power Supply
VBAT
Vout
VSS
Battery /
Input
Power
B1
D1
LDO /
Output
Power
Power Supply to Clock Source and clock outputs
Ground Pin
Ground
Ground
(1) I = Input, O = Output, I/O = Input / Output
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TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise specified, TA = 25°C, VBAT = 3.5V, fSCLK_IN = 26 MHz, COUT = 2.2 µF
Supply Current
vs.
Supply Voltage
Supply Current
vs.
Input Clock Frequency
6.0
5.8
5.6
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
12.0
11.0
10.0
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
S
C
= 26 MHz
= 33 pF
CLK-IN
LOAD
50pF
25°C
-40°C
85°C
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0
10
20
30
40
50
SUPPLY VOLTAGE (V)
CLOCK FREQUENCY (MHz)
Figure 5.
Figure 6.
Supply Current
vs.
Capacitive Load
LDO output Voltage
vs.
Supply Voltage
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
1.82
1.81
1.80
1.79
1.78
26 MHz/CLK1+2
-40°C
4.5
20 30
85°C
4.0
0
10
40
50
2.5
3.0
3.5
5.0
5.5
CAPACITIVE LOAD (pF)
SUPPLY VOLTAGE (V)
Figure 7.
Figure 8.
LDO output Voltage
vs.
LDO output current
LDO output voltage ON timing
1.85
1.80
1.75
1.70
1.65
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
CLK REQ
LDO OUTPUT
-40°C
0
2
4
6
8
10
-100
0
100
200
300
400
LOAD CURRENT (mA)
TIME (ms)
Figure 9.
Figure 10.
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SNAS485D –JULY 2010–REVISED MAY 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, TA = 25°C, VBAT = 3.5V, fSCLK_IN = 26 MHz, COUT = 2.2 µF
Additive Phase Noise
vs.
Frequency Offset
LDO output voltage OFF timing
-110
-120
-130
-140
-150
-160
-170
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
LDO 1 mA
CLK2_26 MHz
CLK1 - 26 MHz
LDO 10 mA
CLK1 - 19 MHz
CLK2_19 MHz
CLK REQ
0
100
1k
10k
100k
1M
-2k
2k
4k
6k
8k
10k
TIME (ms)
FREQUENCY OFFSET (Hz)
Figure 11.
Figure 12.
Power Supply Rejection Ratio
vs.
CLK1 Pulse Response 10-50pF @ 19MHz
Frequency
1.8
100
90
80
70
60
50
40
1.3
C
C
C
C
= 10 pF
= 22 pF
= 33 pF
= 50 pF
L
L
L
L
0.9
0.4
0.0
C
V
: 2.2 mF
OUT
CLK1 OUTPUT @ 19 MHz
-40 -30 -20 -10
TIME (ns)
: No Capacitors
BAT
-0.5
-60
-50
0
100
1k
10k
100k
1M
10M
POWER SUPPLY REJECTION RATIO
Figure 13.
Figure 14.
CLK1 Pulse Response 10-50pF @ 26MHz
CLK1 Pulse Response 10-50pF @ 52MHz
1.8
1.8
1.3
1.3
C
L
C
L
C
L
C
L
= 10 pF
= 22 pF
= 33 pF
= 50 pF
C
L
C
L
C
L
C
L
= 10 pF
= 22 pF
= 33 pF
= 50 pF
0.9
0.4
0.9
0.4
0.0
0.0
CLK1 OUTPUT @ 26 MHz
10 20 30 40
TIME (ns)
CLK1 OUTPUT @ 52 MHz
25 35
-0.5
-10
-0.5
15
0
50
TIME (ns)
Figure 15.
Figure 16.
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APPLICATION INFORMATION
The LMH2191 is a complete 52 MHz clocking conditioner and clock tree driver. The LMH2191 is used to supply
a common clock to mobile phone peripherals such as Bluetooth, Wireless LAN, and/or Digital Video Broadcast-H
(DVB-H). The high isolation between the clock outputs ensures that the peripherals don't disrupt each other. Its
excellent phase noise characteristics prevent the clock quality from deteriorating. A typical LMH2191 setup is
depicted in Figure 17.
V
BAT
V
BAT
C
BAT
1 µF
A1
LMH2191
V
B1
C1
OUT
1.8V LDO
C
OUT
V
DD
A2 CLK1
2.2 µF
Peripheral
Peripheral
Clock
Tree
SCLK_IN
C
Clock
Source
CLK
10 nF
Driver
C
SERIES
D2 CLK2
B2 CLK_REQ1
C2 CLK_REQ2
Clock
Request
D1
V
SS
Figure 17. LMH2191 Typical Application Schematic
The internal structure of the LMH2191 is depicted in the block diagram of Figure 18.
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SNAS485D –JULY 2010–REVISED MAY 2013
V
BAT
A1
LMH2191
V
OUT
B1
1.8V LDO
On/Off
V
OUT
Clock Tree Driver
A2
CLK1
SCLK_IN C1
CLK2
D2
C
SERIES
V
BAT
CLK_REQ1
CLK_REQ2
B2
C2
Clock Request Logic
D1
V
SS
Figure 18. Block Diagram
The LMH2191 clock distribution circuit is comprised of 3 blocks:
•
•
•
Clock tree driver
Clock request logic
Low Dropout Regulator (LDO)
The clock tree driver provides a clean clock to 2 separately connected peripheral devices. Independent clock
request inputs allow the peripheral to control when the particular clock should be enabled. Furthermore, both
clock request inputs control the LDO output voltage, e.g., when both request inputs are low (no CLK1 and no
CLK2 output required), the LDO voltage is disabled. The LDO provides a low-noise, high-PSRR supply voltage
that enables low phase noise on the clock outputs, and low quiescent current for portable applications. It can
also be used to supply the TCXO. The following sections provide a detailed description of each block.
CLOCK TREE DRIVER
The clock tree driver consists of one input that drives 2 outputs. It is supplied by a high-precision voltage
regulator of 1.8V, the LDO. The Clock outputs are enabled when the appropriate Clock Request inputs are logic
high.
Clock Tree Driver Input
The source clock input (SCLK_IN) is the input for the clock tree driver. This input has an internally connected
coupling capacitor (CSERIES) with a value of 33pF. In shutdown mode (when both CLK_REQ inputs are low), the
input stage is completely switched off to prevent unnecessary power consumption when the source clock is still
present.
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Due to the internal coupling capacitor, the clock signal is DC biased, since the coupling capacitor prevents the
internal biasing of the input circuitry to be affected by the external DC voltage. Because of the coupling capacitor,
the minimum clock frequency is 10 MHz. It is assumed that the input signal is a sine wave or a typical TCXO
waveform (the signal from a TCXO has slow edges), enabling the control loop to adjust to a duty cycle of 50% if
the input signal differs slightly from 50% duty cycle. The duty cycle is an important timing parameter for the
peripheral equipment. The circuit that adjust the duty cycle is shown in Figure 19.
SCLK_IN
C
SERIES
Figure 19. Clock Duty Cycle Regulation
Duty Cycle 50%
Shifted DC level
DC level 50% duty cycle
Duty Cycle 50%
Figure 20. Duty Cycle adjust levels
|n order to achieve a duty cycle of 50%, the edges of the incoming clock signal (SCLK_IN) are used to move the
switching point to the level that is needed to create the 50% duty cycle. The simplified input circuit consists of an
inverter and a feedback resistor. Together with the input series capacitor of about 30 pF, the circuit creates a DC
level depending on the duty cycle of the incoming clock signal. When the duty cycle is exactly 50%, the DC level
is in the middle of the upper and lower pulse level. When the duty cycle differs from 50%, the DC level shifts
slightly to maintain the duty cycle level at 50%. (See Duty Cycle adjust levels of Figure 20.) As explained above,
the slow edges of the SCLK_IN signal are important to make the control loop work.
Input Impedance
The input impedance can be split up into two parts: the DC input resistance and the AC input impedance. Due to
the used series capacitor in the input signal path the DC resistance is infinite. The AC input impedance is formed
by the circuit drawn in Figure 19. This circuit consists of an inverter and a feedback resistor. A signal fed to the
input pin is connected to the inverter input which has a high input impedance and is in parallel to the feedback
resistor of 30 kΩ. The other pin of the feedback resistor is connected to the output of the inverter which means
that the input current is higher than it would be if it were connected to a decoupled supply connection. For this
reason the AC input resistance can be much lower than the connected feedback resistor of 30 kΩ. The input
resistance is dependant on the amplitude of the input signal. When an input amplitude of 1.8V is used (the same
amplitude as the output of the inverter), the input impedance is theoretical half the value of the feedback resistor.
When the amplitude of the input signal lowers, the input resistance becomes lower too. With an input signal of
1VPP, the input impedance will be about 10 kΩ.
Clock Tree Driver Outputs
The LMH2191's clock tree driver outputs have a drive strength that make each output capable of driving a
capacitive load up to 50 pF, together with a minimum of EMI. Further reduction of EMI is achieved by the
inversion of the CLK2 output. (See Figure 21.) Both the drive strength and the capacitive load make the edges of
the output pulse relative slow which is favorable for EMI reduction.
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SNAS485D –JULY 2010–REVISED MAY 2013
SCLK_IN
CLK 1
CLK 2
Figure 21. Clock Outputs
CLOCK REQUEST LOGIC
A clock request input is provided for each clock output. This allows the peripheral device to control when it wants
to receive a clock. In case the application does not have clock request functionality, the CLKx_REQ can be hard
wired to a logic high level to enable the clock output continuously. The clock request inputs have logic levels
compatible with 1.8V logic, but can tolerate logic high levels up to VBAT
.
CLK_REQ x
D
Q
CLK signal
CLKx
Inverter only
added for CLK2
Figure 22. Enabling the output
The clock request logic enables an independent control of the clock tree driver outputs, CLK1 and CLK2, as well
as an LDO disable when both request inputs are low.
The on and off switching of the clock output drivers is done synchronously with the clock input in order to prevent
glitches at the clock output. For this the clock request signal is connected to the D input of a latch. The Q output
of this latch enables the clock output driver (see Figure 22). For the CLK1 output the CLK input signal is
connected via an inverter to the clock input of the latch. In this way the latch enables and disables the CLK1
output buffer on the falling edge of the clock signal. For the CLK2 output an extra inverter is inserted prior to the
latch circuit, and the CLK2 output buffer is enabled and disabled on the rising edge of the clock input signal
(equal to the falling edge of the CLK2 output signal).
LOW DROPOUT REGULATOR
The linear and Low-Dropout regulator (LDO) is used to regulate the input voltage, VBAT, thus generating a well-
defined ultra low noise 1.8V supply voltage. This allows the LMH2191 to suppress VBAT supply voltage ripple and
noise for the TCXO and the internal Clock Path. Voltage ripple and noise would distort clock edges causing extra
phase noise on the distributed clock signal.
The LDO is powered up whenever a Clock Request is active; it supports overheating detection and will switch off
in case overheating occurs. The recommended sequence for powering up the LDO is to raise a clock request to
a high level with the supply already powered up. Thus the LDO stays in shutdown mode with sub µA current
consumption until an output clock is actually needed. The LDO will power up within the turn-on time of about 200
µs (as specified in the data sheet tables). Alternatively, the clock request input can be hard wired to VBAT which
powers up the LDO simultaneously with VBAT. A drawback is that the LDO and clock path (and if connected, the
TCXO) will always draw current when VBAT is powered up. Also, in this setup, care should be taken with supplies
with an excessive long startup time of more than about 25 ms. Under this condition the LDO could exhibit
excessive long turn-on delay (order of seconds.)
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LAYOUT RECOMMENDATIONS
As with any other device, careful attention must be paid to the board layout. If the board isn't properly designed,
the performance of the device can be less than desired. Care should be taken that the SCLK_IN input trace and
the output traces of CLK1 and CLK2 are as short as possible to reduce extra capacitive load observed by the
clock outputs. Also proper de-coupling close to the device is necessary. Table 1 depicts the advised component
values. TI suggests to use the evaluation board, available from the Texas Instruments web site www.ti.com, as a
guide for layout and as an aid in device testing and characterization.
Table 1. Recommended Component Values
Symbol
Parameter
Min
0.47
1
Typ
1
Max
Units
µF
(1)
CBAT
Capacitor on VBAT
Capacitor on VOUT
Equivalent Series Resistance
(1)
COUT
2.2
ESR
5
500
mΩ
(1) CBAT, COUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCC's) used in setting electrical characteristics.
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SNAS485D –JULY 2010–REVISED MAY 2013
REVISION HISTORY
Changes from Revision C (April 2013) to Revision D
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 14
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH2191TME/NOPB
LMH2191TMX/NOPB
ACTIVE
ACTIVE
DSBGA
DSBGA
YFX
YFX
8
8
250
RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
5
5
3000 RoHS & Green
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Oct-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH2191TME/NOPB
LMH2191TMX/NOPB
DSBGA
DSBGA
YFX
YFX
8
8
250
178.0
178.0
8.4
8.4
1.24
1.24
1.7
1.7
0.76
0.76
4.0
4.0
8.0
8.0
Q1
Q1
3000
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Oct-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMH2191TME/NOPB
LMH2191TMX/NOPB
DSBGA
DSBGA
YFX
YFX
8
8
250
208.0
208.0
191.0
191.0
35.0
35.0
3000
Pack Materials-Page 2
PACKAGE OUTLINE
YFX0008
DSBGA - 0.675 mm max height
SCALE 10.000
DIE SIZE BALL GRID ARRAY
B
E
A
BALL A1
CORNER
D
0.675
0.525
C
SEATING PLANE
0.05 C
0.205
0.165
SYMM
D
C
B
SYMM
1.2
TYP
D: Max = 1.64 mm, Min = 1.58 mm
E: Max = 1.093 mm, Min =1.033 mm
0.4 TYP
A
0.28
8X
1
2
0.25
0.4 TYP
0.015
C A B
4215093/B 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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EXAMPLE BOARD LAYOUT
YFX0008
DSBGA - 0.675 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
8X ( 0.225)
1
2
A
(0.4) TYP
B
C
SYMM
D
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 50X
0.05 MIN
0.05 MAX
METAL UNDER
SOLDER MASK
(
0.225)
METAL
(
0.225)
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4215093/B 04/2022
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
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EXAMPLE STENCIL DESIGN
YFX0008
DSBGA - 0.675 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
8X ( 0.25)
1
2
A
(0.4) TYP
B
C
SYMM
METAL
TYP
D
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE: 50X
4215093/B 04/2022
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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