LMH32401IRGTR [TI]
可编程增益、差分输出高速跨阻放大器 | RGT | 16 | -40 to 125;
| 型号： | LMH32401IRGTR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 可编程增益、差分输出高速跨阻放大器 | RGT | 16 | -40 to 125 放大器 |
| 文件： | 总41页 (文件大小：2432K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMH32401
ZHCSKC6D –OCTOBER 2019 –REVISED JANUARY 2023
LMH32401 450MHz 可编程增益、差分输出跨阻放大器
1 特性
3 说明
• 集成的可编程增益：2kΩ或20kΩ
• 性能：增益= 2kΩ、CPD = 1pF：
LMH32401 器件是一款增益可编程的单端输入转差分
输出跨阻放大器，适用于光检测和测距（激光雷达）应
用和激光测距系统。可以为 LMH32401 器件配置 2kΩ
或20kΩ增益。LMH32401 器件具有1.5VPP 的输出摆
幅，可驱动100Ω负载。
– 带宽：450 MHz
– 输入参考噪声：250nARMS
– 上升，下降时间：0.8ns
• 性能：增益= 20kΩ、CPD = 1pF：
LMH32401 器件集成了一个100mA 钳位电路，可以为
放大器提供保护并允许器件迅速从过载输入状况中恢
复。LMH32401 器件还具有一个集成式环境光消除电
路，可取代光电二极管与放大器之间的交流耦合，从而
节省布板空间并降低系统成本。当需要直流耦合时，可
以禁用环境光消除电路。
– 带宽：275 MHz
– 输入参考噪声：49nARMS
– 上升，下降时间：1.3ns
• 集成式环境光消除
• 集成式100mA 保护钳位
• 集成式输出多路复用器
• 宽输出摆幅：1.5 V VPP
• 静态电流：30mA
当不使用放大器时，可以使用 EN 引脚将 LMH32401
器件置于低功耗模式，以节省电力。将放大器置于低功
耗模式会使其输出引脚进入高阻抗状态。此功能允许多
个 LMH32401 放大器多路复用到单个 ADC 中，EN 控
制引脚将用作多路复用器选择功能。
• 封装：16 引脚VQFN 和裸片
• 温度范围：–40 至125° C
2 应用
封装信息(1)
• 机械扫描激光雷达
• 固态扫描激光雷达
• 激光测距仪
• 光学ToF 位置传感器
• 无人机视觉
• 工业机器人激光雷达
• 移动机器人激光雷达
• 扫地机器人激光雷达
封装尺寸（标称值）
器件型号
LMH32401
封装
VQFN (16)
3.00mm × 3.00mm
器件信息(1)
芯片尺寸（标称值）
器件型号
LMH32401
封装
裸片
1.025mm × 1.060mm
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
3
GAIN
EN
VDD1
VDD2
1 kΩ
0
-3
-6
-9
100-mA
Clamp
10 kΩ
Differential Output ADC
Driver
IN
TIA
10 Ω
OUTÞ
VOCM
OUT+
Ambient Light
Cancellation
Þ VBIAS
IDC EN
VOD
+
2x
œ
-12
Gain = 2 kW
Gain = 20 kW
Output Offset
10 Ω
-15
10M
100M
Frequency [Hz]
1G
GND
简化版方框图
闭环跨阻带宽
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS965
LMH32401
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ZHCSKC6D –OCTOBER 2019 –REVISED JANUARY 2023
Table of Contents
7.3 Feature Description...................................................22
7.4 Device Functional Modes..........................................24
8 Application and Implementation..................................25
8.1 Application Information............................................. 25
8.2 Typical Application ................................................... 26
9 Power Supply Recommendations................................29
10 Layout...........................................................................29
10.1 Layout Guidelines................................................... 29
10.2 Layout Example...................................................... 30
11 Device and Documentation Support..........................31
11.1 Device Support........................................................31
11.2 Documentation Support.......................................... 31
11.3 接收文档更新通知................................................... 31
11.4 支持资源..................................................................31
11.5 Trademarks............................................................. 31
11.6 静电放电警告...........................................................31
11.7 术语表..................................................................... 31
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics: Gain = 2 kΩ....................... 7
6.6 Electrical Characteristics: Gain = 20 kΩ..................... 8
6.7 Electrical Characteristics: Both Gains.........................9
6.8 Electrical Characteristics: Logic Threshold and
Switching Characteristics............................................ 11
6.9 Typical Characteristics..............................................12
7 Detailed Description......................................................21
7.1 Overview...................................................................21
7.2 Functional Block Diagram.........................................21
Information.................................................................... 32
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision C (August 2022) to Revision D (January 2023)
Page
• Updated the backside potential information for bare die package information in the Pin Configuration and
Functions section ...............................................................................................................................................3
Changes from Revision B (February 2022) to Revision C (August 2022)
Page
• 将裸片的状态从预发布更改为正在供货.............................................................................................................1
• Updated the bare die package information in the Pin Configuration and Functions section.............................. 3
Changes from Revision A (September 2020) to Revision B (February 2022)
Page
• 更新了整个文档的表、图和交叉参考的编号格式................................................................................................ 1
• 向特性部分和器件信息表添加了裸片预发布封装............................................................................................. 1
• Added the bare die preview package to the Pin Configuration and Functions section.......................................3
Changes from Revision * (October 2019) to Revision A (June 2020)
Page
• 将状态从“预告信息”更改为“量产数据”....................................................................................................... 1
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ZHCSKC6D –OCTOBER 2019 –REVISED JANUARY 2023
5 Pin Configuration and Functions
GAIN
16
NC
15
VDD2
14
NC
13
12
11
10
9
VOCM
OUTÞ
OUT+
VOD
GND
VDD1
IN
1
2
3
4
Thermal Pad
NC
5
6
8
7
IDC_EN
EN
NC
GND
Not to scale
图5-1. RGT Package, 16-Pin VQFN with Exposed Thermal Pad (Top View)
表5-1. Pin Functions
PIN
TYPE(2)
DESCRIPTION
NAME
EN
NO.
6
I
I
I
Device enable pin. EN = logic low = normal operation (default)(1); EN = logic high = power off mode.
Gain setting. GAIN = low = 2 kΩ(default)(1); GAIN = high = 20 kΩ.
Amplifier ground.
GAIN
GND
16
1, 7
Ambient light cancellation (ALC) loop enable. IDC_EN = logic low = enable DC current cancellation
(default)(1); IDC_EN = logc high = disable DC current cancellation.
IDC_EN
5
3
I
IN
I
Transimpedance amplifier input.
No connection.
NC
4, 8, 13, 15
11
—
Inverting amplifier output. When light is incident on the photodiode the output pin transitions in a
negative direction from the no light condition (APD anode connected to negative bias).
O
OUT–
Noninverting amplifier output. When light is incident on the photodiode the output pin transitions in a
positive direction from the no light condition (APD anode connected to negative bias).
OUT+
VDD1
VDD2
10
2
O
I
Positive power supply for the transimpedance amplifier stage.
Positive power supply for the differential amplifier stage. Tie VDD1 and VDD2 to the same power
supply with independent power-supply bypassing.
14
I
VOCM
12
9
I
I
Differential amplifier common-mode output setting.
VOD
Differential amplifier differential output offset setting.
Thermal pad
Connect the thermal pad to GND or the most negative power supply of the device under test (DUT).
—
(1) TI recommends driving a digital pin with a low-impedance source rather than leaving the pin floating because fast-moving transients
can couple into the pin and inadvertently change the logic level.
(2) I = input, O = output
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BOND PAD
ZHCSKC6D –OCTOBER 2019 –REVISED JANUARY 2023
DIE THICKNESS
BACKSIDE FINISH
BACKSIDE POTENTIAL
METALLIZATION
Silicon with backgrind
Wafer backside is not electrically isolated and should be held at
the same potential as the most negative power supply
connected to the die (GND)
AlCu
381 μm
40
LMH
32401
17
16
15
14
13
1
PAD#1
12
2
11
10
9
3
4
5
6
7
8
0
40
0
1025
图5-2. Bare Die Package
表5-2. Bond Pad Coordinates of Bare Die Version in Microns
PAD NUMBER
PAD NAME
GND
VDD1
IN
X-MIN
Y-MIN
711.4
543
X-MAX
Y-MAX
786.4
618
1
15
90
2
15
90
3
15
362
90
437
4
NC
15
201
90
276
5
IDC_EN
EN
124.675
286.675
547.7
713.675
855
15
199.675
361.675
622.7
788.675
930
90
6
15
90
7
GND
NC
15
90
8
15
90
9
VOD
OUT+
NC
169.075
307.6
452.5
597.325
736.05
890
244.075
382.6
527.5
672.325
811.05
965
10
11
12
13
14
15
16
17
855
930
855
930
OUT-
VOCM
NC
855
930
855
930
713.65
547.675
286.675
124.675
788.65
622.675
361.675
199.675
VDD2
NC
890
965
890
965
GAIN
890
965
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
3.65
VDD
VDD
25
UNIT
V
(2)
VDD1, VDD2
Total supply voltage, VDD
Voltage at output pins
0
V
Voltage at logic pins
V
–0.25
IIN
Continuous current into IN
Continuous output current
Junction temperature
mA
mA
°C
°C
°C
IOUT
TJ
35
150
125
150
TA
Operating free-air temperature
Storage temperature
–40
–65
Tstg
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) VDD1 and VDD2 should always be tied to the same supply and have separate power-supply bypass capacitors.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±1000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3
NOM
MAX
3.45
125
UNIT
V
VDD
TA
Total supply voltage
3.3
Operating free-air temperature
°C
–40
6.4 Thermal Information
LMH32401(2)
THERMAL METRIC(1)
RGT (VQFN)
12 PINS
56.3
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
67
31.3
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
3.7
ΨJT
31.2
ΨJB
RθJC(bot)
15.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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(2) Thermal information is applicable to packaged parts only.
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6.5 Electrical Characteristics: Gain = 2 kΩ
VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD (1) = 1 pF, EN = 0 V, GAIN = 0 V, IDC_EN = 3.3 V, RL = 100 Ω, and TA = 25℃
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
SSBW
LSBW
tR, tF
Small-signal bandwidth
Large-signal bandwidth
Rise and fall time
VOUT = 100 mVPP
450
450
0.8
MHz
MHz
ns
VOUT = 1 VPP
VOUT = 100 mVPP, pulse width = 10 ns
VOUT = 1 VPP, pulse width = 10 ns
IIN = 10 mA, pulse width = 10 ns
f = 500 MHz
Slew rate(2)
1100
4
V/µs
ns
Overload pulse extention (3)
iN
Integrated input current noise
250
nARMS
DC PERFORMANCE
Z21
Small-signal transimpedance gain(4)
Differential output offset voltage
(VOUT– –VOUT+
Differential output offset voltage drift
1.75
2
3.5
2.25
12
kΩ
mV
VOD
–12
)
±5.5
µV/°C
ΔVOD/ΔTA
INPUT PERFORMANCE
RIN
Input Resistance
60
100
2.47
1.1
120
Ω
VIN
Default input bias voltage
Input pin floating
Input pin floating
2.42
2.52
V
Default input bias voltage drift
mV/°C
µA
ΔVIN/ΔTA
Z21 < 3-dB degradation from
IIN = 50 µA
IIN
DC input current range
600
705
(1) Input capacitance of photodiode.
(2) Average of rising and falling slew rate.
(3) Pulse width extension measured at 50% of pulse height of a square wave.
(4) Gain measured at the amplifier output pins when driving a 100-Ωresistive load. At higher resistor loads the gain increases.
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6.6 Electrical Characteristics: Gain = 20 kΩ
VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD (1) = 1 pF, EN = 0 V, GAIN = 3.3 V, IDC_EN = 3.3 V, RL = 100 Ω, and TA = 25℃
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AC PERFORMANCE
SSBW
LSBW
tR, tF
Small-signal bandwidth
Large-signal bandwidth
Rise and fall time
VOUT = 100 mVPP
275
275
1.3
700
4
MHz
MHz
ns
VOUT = 1 VPP
VOUT = 100 mVPP, pulse width = 10 ns
VOUT = 1 VPP, pulse width = 10 ns
IIN = 10 mA, pulse width = 10 ns
f = 250 MHz
Slew rate(2)
V/µs
ns
Overload pulse extension (4)
iN
Integrated input current noise
49
nARMS
DC PERFORMANCE
Z21
Small-signal transimpedance gain(3)
Differential output offset voltage
(VOUT– –VOUT+
Differential output offset voltage
17
20
5
22.5
20
kΩ
mV
VOD
–20
)
±17.5
µV/°C
ΔVOD/ΔTA
INPUT PERFORMANCE
RIN
Input Resistance
270
350
2.47
1.1
410
Ω
VIN
Default input bias voltage
Input pin floating
Input pin floating
2.42
2.52
V
Default input bias voltage drift
mV/°C
µA
ΔVIN/ΔTA
Z21 < 3-dB degradation from
IIN = 5 µA
IIN
DC input current range
60
72
(1) Input capacitance of photodiode.
(2) Average of rising and falling slew rate.
(3) Gain measured at the amplifier output pins when driving a 100-Ωresistive load. At higher resistor loads the gain increases.
(4) Pulse width extension measured at 50% of pulse height of a square wave.
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6.7 Electrical Characteristics: Both Gains
VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD (1) = 1 pF, EN = 0 V, GAIN = 0 V / 3.3 V, IDC_EN = 3.3 V, RL = 100 Ω, and TA =
25℃(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT PERFORMANCE
Single-sided output voltage swing (high)
VOH
VOL
TA = 25°C
Single-sided output voltage swing (low)(2) TA = 25°C
2.87
2.9
0.36
26.6
V
V
(2)
0.39
32
TA = 25°C, IIN = 500 µA, gain = 2 kΩ,
RL = 25 Ω
24
TA = –40°C, IIN = 500 µA, gain = 2 kΩ,
RL = 25 Ω
IOUT
Linear output drive (sink and source)
27.1
25.1
mA
TA = 125°C, IIN = 500 µA, gain = 2 kΩ,
RL = 25 Ω
ISC
Output short-circuit current (differential) (3)
70
21
mA
Ω
ZOUT
ZOUT
DC output impedance (amplifier enabled) Differential impedance
DC output impedance in shutdown Differential impedance
18
24
2.8
3.3
kΩ
OUTPUT COMMON-MODE CONTROL (VOCM) PERFORMANCE
SSBW
LSBW
Small-signal bandwidth
Large-signal bandwidth
VOCM = 100 mVPP at VOCM pin
VOCM = 1 VPP at VOCM pin
285
85
MHz
MHz
f = 10 MHz, 1-nF capacitor to GND on VOCM
pin
eN
Output common-mode noise
17.8
nV/√Hz
IN floating, VOCM = 1.1 V (driven)
1
0.5%
±1%
17
V/V
Gain, (ΔVOCM/ΔVOCM)
AV
TA = 25°C, VOCM = 0.7 V to 2.3 V
2%
20
–2%
0
Gain error
TA = –40°C to 125°C, VOCM = 0.7 V to 2.3 V
Input impedance
kΩ
VOCMOS VOCM pin default offset from 1.1 V
VOCM floating, (VOCM measured - 1.1 V)
10
mV
ΔVOCM
ΔIIN
/
VOCM error vs Input current
µV/µA
V
Gain = 20 kΩ, VOCM driven to 1.1 V
–15
1.1
Output common-mode voltage,
(VOUT+ + VOUT-)/2
VOCM
TA = 25°C, VOCM pin floating
1.05
1.15
Output common-mode voltage drift,
(ΔVOCM/ΔTA)
75
µV/°C
V
TA = –40°C to 125°C, VOCM pin floating
TA = 25°C, VOCM pin driven to 1.1 V
Output common-mode voltage,
(VOUT+ + VOUT-)/2
VOCM
1.05
1.1
1.15
Output common-mode voltage drift,
(ΔVOCM/ΔTA)
TA = –40°C to 125°C,
VOCM pin driven to 1.1 V
µV/°C
–14
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VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD (1) = 1 pF, EN = 0 V, GAIN = 0 V / 3.3 V, IDC_EN = 3.3 V, RL = 100 Ω, and TA =
25℃(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT DIFFERENTIAL OFFSET (VOD) PERFORMANCE
SSBW
LSBW
Small-signal bandwidth
Large-signal bandwidth
Differential output offset,
VOD = 100 mVPP at VOD pin
45
14
MHz
MHz
VOD = 1 VPP
VOS_D
IN floating, VOD = 0.5 V
490
490
510
0.03
510
530
530
mV
mV/℃
mV
VOUT = (VOUT– –VOUT+
)
Differential output offset drift, ΔVOS_D
ΔTA
/
/
IN floating, VOD = 0.5 V
Differential output offset,
VOS_D
IN floating, VOD floating
VOUT = (VOUT– –VOUT+
)
Differential output offset drift, ΔVOS_D
ΔTA
IN floating, VOD floating
0.04
1.01
mV/℃
V/V
Gain, (ΔVOUT/ΔVOD), where
IN floating, VOCM = 1.1 V (driven)
VOUT = (VOUT– –VOUT+
)
AV
5%
TA = 25℃, VOD = 0 V to 1.2 V
–5%
–1%
±1.5%
2.5
Gain error
TA = –40℃to 125℃, VOD = 0 V to 1.2 V
Input impedance
kΩ
AMBIENT LIGHT CANCELLATION PERFORMANCE (IDC_EN = 0 V) (4)
18
2.5
35
IIN = 0 µA →100 µA, GAIN = 2 kΩ
IIN = 0 µA →10 µA, GAIN = 20 kΩ
IIN = 100 µA →0 µA, GAIN= 2 kΩ
IIN = 10 µA →0 µA, GAIN = 20 kΩ
Settling time (within VOD limit)
µs
13
Differential output offset (VOUT– –VOUT+
shift from IDC = 10 µA < ±10 mV
)
Ambient light current cancellation range
2
3
mA
POWER SUPPLY
TA = 25°C
24
30
32
27
33.5
TA = 125°C
TA = –40°C
IQ
Quiescent current, total
mA
dB
Positive power-supply rejection ratio,
VDD1 = VDD2
PSRR+
54
66
SHUTDOWN
TA = 25°C
TA = –40°C
TA = 125°C
TA = 25°C
2.4
3.3
2.75
5.2
4.2
IQ
Disabled quiescent current (EN = VDD
)
mA
µA
Enable pin input bias current
(1) Input capacitance of photodiode.
75
120
(2) Output levels achieved by adjusting VOCM, VOD, and input current.
(3) Device cannot withstand continuous short-circuit between the differential outputs.
(4) Enabling the ambient light cancellation loop adds noise to the system.
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6.8 Electrical Characteristics: Logic Threshold and Switching Characteristics
VDD = 3.3 V, VOCM = Open, VOD = 0 V, CPD (1) = 1 pF, EN = 0 V, GAIN = 0 V / 3.3 V, IDC_EN = 3.3 V, RL = 100 Ω, and TA =
25℃. (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC THRESHOLD PERFORMANCE
High gain enable, threshold voltage
Low gain enable, threshold voltage
EN control, disable threshold voltage
EN control, enable threshold voltage
Amplifier in high gain above this voltage
Amplifier in low gain below this voltage
Amplifier disabled above this voltage
Amplifier enabled below this voltage
1.8
1
2
2
V
V
V
V
0.8
0.8
1.8
1
Ambient light cancellation loop disabled
above this voltage
IDC_EN control, disable threshold voltage
1.8
1
2
V
V
Ambient light cancellation loop enabled
below this voltage
IDC_EN control, enable threshold voltage
0.8
GAIN CONTROL TRANSIENT PERFORMANCE
High gain to low gain transition-time,
(1% settling)
Ambient loop disabled, fIN = 25 MHz,
VOUT = 1 VPP (Initial condition), IDC = 0 µA
90
ns
ns
Low gain to high gain transition-time,
(1% settling)
Ambient loop disabled, fIN = 25 MHz,
VOUT = 1 VPP (Final condition), IDC = 0 µA
750
Ambient loop enabled, fIN = 25 MHz,
VOUT = 1 VPP (Initial condition), IDC = 100
µA
High gain to low gain transition-time,
(1% settling)
4
4
µs
µs
Low gain to high gain transition-time,
(1% settling)
Ambient loop enabled, fIN = 25 MHz,
VOUT = 1 VPP (Final condition), IDC = 100 µA
EN CONTROL TRANSIENT PERFORMANCE
Ambient loop disabled, fIN = 25 MHz, VOUT
= 1 VPP, IDC = 0 µA, GAIN = 2 kΩ
Enable transition-time (1% settling)
125
3
ns
ns
ns
ns
µs
ns
µs
ns
Ambient loop disabled, fIN = 25 MHz, VOUT
= 1 VPP, IDC = 0 µA, GAIN = 2 kΩ
Disable transition-time (1% settling)
Enable transition-time (1% settling)
Disable transition-time (1% settling)
Enable transition-time (1% settling)
Disable transition-time (1% settling)
Enable transition-time (1% settling)
Disable transition-time (1% settling)
(1) Input capacitance of photodiode.
Ambient loop disabled, fIN = 25 MHz, VOUT
= 1 VPP, IDC = 0 µA, GAIN = 20 kΩ
850
3
Ambient loop disabled, fIN = 25 MHz, VOUT
= 1 VPP, IDC = 0 µA, GAIN = 20 kΩ
Ambient loop enabled, fIN = 25 MHz, VOUT
1 VPP, IDC = 100 µA, GAIN = 2 kΩ
=
=
=
=
10
3.5
4
Ambient loop enabled, fIN = 25 MHz, VOUT
1 VPP, IDC = 100 µA, GAIN = 20 kΩ
Ambient loop enabled, fIN = 25 MHz, VOUT
1 VPP, IDC = 100 µA, GAIN = 20 kΩ
Ambient loop enabled, fIN = 25 MHz, VOUT
1 VPP, IDC = 100 µA, GAIN = 2 kΩ
3
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6.9 Typical Characteristics
At VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω(differential
load between OUT+ and OUT–), and TA = 25°C (unless otherwise noted).
69
66
63
60
57
54
51
89
86
83
80
77
74
71
CIN = PCB only
CIN = 0.5 pF
CIN = 1 pF
CIN = 2 pF
CIN = 4.7 pF
CIN = 10 pF
CIN = PCB only
CIN = 0.5 pF
CIN = 1 pF
CIN = 2 pF
CIN = 4.7 pF
CIN = 10 pF
10M
100M
Frequency [Hz]
1G
1G
1G
10M
100M
Frequency [Hz]
1G
1G
1G
Gain = 2 kΩ, VOUT = 100 mVPP
Gain = 20 kΩ, VOUT = 100 mVPP
图6-1. Small Signal Response vs Input Capacitance
图6-2. Small Signal Response vs Input Capacitance
69
89
66
63
60
86
83
80
CIN = PCB only
57
CIN = PCB only
77
CIN = 0.5 pF
CIN = 1 pF
CIN = 2 pF
CIN = 4.7 pF
CIN = 10 pF
CIN = 0.5 pF
CIN = 1 pF
CIN = 2 pF
CIN = 4.7 pF
CIN = 10 pF
54
74
51
10M
71
10M
100M
Frequency [Hz]
100M
Frequency [Hz]
Gain = 2 kΩ, VOUT = 1 VPP
Gain = 20 kΩ, VOUT = 1 VPP
图6-3. Large Signal Response vs Input Capacitance
图6-4. Large Signal Response vs Input Capacitance
69
89
66
63
60
57
86
83
80
77
54
74
CIN = 0.5 pF, CLOAD = open
CIN = 0.5 pF, CLOAD = 2.7 pF
51
CIN = 0.5 pF, CLOAD = open
CIN = 0.5 pF, CLOAD = 2.7pF
71
10M
100M
Frequency [Hz]
10M
100M
Frequency [Hz]
Gain = 2 kΩ, VOUT = 100 mVPP
Gain = 20 kΩ, VOUT = 100 mVPP
图6-5. Small Signal Response vs Load Capacitance
图6-6. Small Signal Response vs Load Capacitance
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6.9 Typical Characteristics (continued)
At VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω(differential
load between OUT+ and OUT–), and TA = 25°C (unless otherwise noted).
69
66
63
60
57
54
51
89
86
83
80
77
74
71
TA = -40èC
TA = 25èC
TA = 85èC
TA = 125èC
TA = -40èC
TA = 25èC
TA = 85èC
TA = 125èC
10M
100M
Frequency [Hz]
1G
10M
100M
Frequency [Hz]
1G
Gain = 2 kΩ, CIN = PCB
Gain = 20 kΩ, CIN = PCB
图6-7. Small Signal Response vs Ambient Temperature
图6-8. Small Signal Response vs Ambient Temperature
3
10k
Amplifier Enabled
Amplifier Disabled
0
-3
-6
-9
1k
100
10
ALC Disabled
ALC Enabled, Gain = 2 kW
ALC Enabled, Gain = 20 kW
-12
-15
10k
100k
1M
Frequency [Hz]
10M
1M
10M
100M
Frequency (Hz)
1G
IDC_IN = 100 µA
Gain = 2 kΩ
图6-9. Low-side Frequency Response vs Ambient Light
图6-10. Closed-loop Output Impedance vs Frequency
Cancellation
20
10
CPD = 0.5 pF
CPD = 1 pF
CPD = 2 pF
CPD = 3 pF
CPD = 0.5 pF
CPD = 1 pF
CPD = 2 pF
CPD = 3 pF
10
5
10k
1
10k
100k
1M 10M
Frequency (Hz)
100M
1G
100k
1M 10M
Frequency (Hz)
100M
1G
Gain = 2 kΩ
Gain = 20 kΩ
图6-11. Input Noise Density vs Input Capacitance
图6-12. Input Noise Density vs Input Capacitance
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6.9 Typical Characteristics (continued)
At VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω(differential
load between OUT+ and OUT–), and TA = 25°C (unless otherwise noted).
20
10
5
5
CLOAD = open
CLOAD = 2.7 pF
CLOAD = open
CLOAD = 2.7 pF
1
10k
10k
100k
1M 10M
Frequency (Hz)
100M
1G
100k
1M 10M
Frequency (Hz)
100M
1G
Gain = 2 kΩ
Gain = 20 kΩ
图6-13. Input Noise Density vs Load Capacitance
100
图6-14. Input Noise Density vs Load Capacitance
50
IDC = 0 mA
IDC = 0 mA
IDC = 10 mA
IDC = 100 mA
IDC = 1 mA
IDC = 10 mA
IDC = 100 mA
IDC = 1 mA
10
10
5
1
10k
10k
100k
1M 10M
Frequency (Hz)
100M
1G
100k
1M 10M
Frequency (Hz)
100M
1G
Gain = 2 kΩ
Gain = 20 kΩ
图6-15. Input Noise Density vs Ambient Light DC Current
图6-16. Input Noise Density vs Ambient Light DC Current
10
200
TA = 125èC
TA = 25èC
TA = -40èC
Differential Noise
Single-Ended Noise
100
1
0.5
10k
10
10k
100k
1M 10M
Frequency (Hz)
100M
1G
100k
1M 10M
Frequency (Hz)
100M
1G
Gain = 20 kΩ
Gain = 20 kΩ
图6-17. Input Noise Density vs Ambient Temperature
图6-18. Output Noise Density vs Output Configuration
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6.9 Typical Characteristics (continued)
At VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω(differential
load between OUT+ and OUT–), and TA = 25°C (unless otherwise noted).
1.75
1.5
1.75
1.5
0.1 VPP
1 VPP
1.5 VPP
0.1 VPP
1 VPP
1.5 VPP
1.25
1
1.25
1
0.75
0.5
0.75
0.5
0.25
0
0.25
0
-0.25
-0.25
Time (5 ns/div)
Time (5 ns/div)
Gain = 2 kΩ
Gain = 20 kΩ
图6-19. Pulse Response vs Output Swing
图6-20. Pulse Response vs Output Swing
1.5
1.25
1
1.5
1.25
1
IIN = 500 mA
IIN = 1 mA
IIN = 50 mA
IIN = 1 mA
0.75
0.5
0.75
0.5
0.25
0
0.25
0
-0.25
-0.25
Time (5 ns/div)
Time (5 ns/div)
Gain = 20 kΩ
Gain = 2 kΩ
图6-22. Overloaded Pulse Response
图6-21. Overloaded Pulse Response
3.5
3
3.5
3
EN
Differential Output
EN
Differential Output
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
-0.5
-1
-0.5
-1
Time (25 ns/div)
Time (25 ns/div)
Gain = 2 kΩ
Gain = 20 kΩ
图6-23. Turn-On Time
图6-24. Turn-On Time
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6.9 Typical Characteristics (continued)
At VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω(differential
load between OUT+ and OUT–), and TA = 25°C (unless otherwise noted).
3.5
3
3.5
3
2.5
2
2.5
2
EN
Differential Output
EN
Differential Output
1.5
1
1.5
1
0.5
0
0.5
0
-0.5
-0.5
Time (1 ns/div)
Time (1 ns/div)
Gain = 2 kΩ, VOD = 0.5 V
图6-25. Turn-Off Time
Gain = 20 kΩ, VOD = 0.5 V
图6-26. Turn-Off Time
0.15
0.125
0.1
0
-0.02
-0.04
-0.06
-0.08
-0.1
0.075
0.05
0.025
0
-0.12
-0.14
-0.16
-0.025
Time (5 ms/div)
Time (5 ms/div)
Gain = 2 kΩ, IDC_IN = 0 µA →100 µA 1
Gain = 2 kΩ, IDC_IN = 100 µA →0 µA1
图6-27. Ambient Loop Cancellation Settling Time
图6-28. Ambient Loop Cancellation Settling Time
1.6
1.4
1.2
1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
0.8
0.6
0.4
0.2
0
-0.2
Time (1 ms/div)
Time (2 ms/div)
Gain = 20 kΩ, IDC_IN = 0 µA →100 µA1
Gain = 20 kΩ, IDC_IN = 100 µA →0 µA1
图6-29. Ambient Loop Cancellation Settling Time
图6-30. Ambient Loop Cancellation Settling Time
1
Current due to ambient light transitions at t = 0 in.
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6.9 Typical Characteristics (continued)
At VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω(differential
load between OUT+ and OUT–), and TA = 25°C (unless otherwise noted).
5
50
125 èC
-40 èC
25 èC
1
10
5
125 èC
-40 èC
25 èC
0.5
-1000 -750 -500 -250
0
250
500
750 1000
-100 -80 -60 -40 -20
0
20
40
60
80 100
Input Current (mA)
Input Current (mA)
Gain = 2 kΩ, positive current is sinking current into the
Gain = 20 kΩ, positive current is sinking current into the
photodiode's cathode
photodiode's cathode
图6-31. Transimpedance Gain vs Input Current
图6-32. Transimpedance Gain vs Input Current
2040
2020
2000
1980
1960
1940
21000
Unit 1
Unit 2
Unit 3
Unit 1
Unit 2
Unit 3
20500
20000
19500
19000
18500
18000
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Temperature (èC)
Gain = 20 kΩ
Gain = 2 kΩ
图6-34. Transimpedance Gain vs Ambient Temperature
图6-33. Transimpedance Gain vs Ambient Temperature
2.5
2.25
2
2.6
2.55
2.5
1.75
1.5
1.25
1
0.75
0.5
0.25
0
2.45
Unit 1
Unit 2
Unit 3
2.4
-40
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Supply Voltage (V)
3
3.3
-20
0
20
40
60
80
100 120 140
Temperature (èC)
.
Gain = 20 kΩ
图6-35. Input Bias Voltage vs Supply Voltage
图6-36. Input Bias Voltage vs Ambient Temperature
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6.9 Typical Characteristics (continued)
At VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω(differential
load between OUT+ and OUT–), and TA = 25°C (unless otherwise noted).
34
32
30
28
26
35
30
25
20
15
10
5
Unit 1
Unit 2
Unit 3
125 èC
-40 èC
25 èC
0
-40
-20
0
20
40
60
80
100 120 140
0
0.5
1
1.5
Supply Voltage (V)
2
2.5
3
3.5
Temperature (èC)
.
.
图6-37. Quiescent Current vs Ambient Temperature
图6-38. Quiescent Current vs Supply Voltage
1.8
1.2
1.1
1
1.7
1.6
1.5
0.9
0.8
0.7
0.6
0.5
0.4
Vout- (V)
Vout+ (V)
Vout- (V)
Vout+ (V)
1.4
1.3
1.2
1.1
1
0
10
20
30
40
50
60
70
80
90 100
0
10
20
30
40
50
60
70
80
90 100
Input Current (mA)
Input Current (mA)
VOD = 0.75 V, VOCM = 1.4 V
图6-39. High-side Swing vs Input Current
VOD = 0.75 V, VOCM = 0.8 V
图6-40. Low-side Swing vs Input Current
1.5
1.2
0.9
0.6
0.3
0
550
540
530
520
510
500
490
480
470
460
450
125 èC
-40 èC
25 èC
0
0.3
0.6
Differential Output Offset Set (V)
0.9
1.2
1.5
1.8
2
0.5
1
1.5
2
Input Current (mA)
2.5
3
3.5
.
.
图6-41. Differential Output Offset Gain
图6-42. Ambient Light Cancellation Range vs Ambient
Temperature
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6.9 Typical Characteristics (continued)
At VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω(differential
load between OUT+ and OUT–), and TA = 25°C (unless otherwise noted).
35
30
25
20
15
10
5
3500
3000
2500
2000
1500
1000
500
125 èC
-40 èC
25 èC
0
0
25
26
27
28
29
30
31
32
33
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7
Enable Voltage (EN) (V)
3
3.3
Quiescent Current (mA)
Logic switching demonstrated using EN pin. IDC_EN and gain
pins behave similarly.
.
图6-44. Quiescent Current Distribution
图6-43. Logic Threshold vs Ambient Temperature
2500
3500
3000
2500
2000
1500
1000
500
2000
1500
1000
500
0
0
17500
1750
1850
1950
2050
2150
2250
18500
19500
20500
Gain (W)
21500
22500
Gain (W)
.
Gain = 20 kΩ
图6-46. Transimpedance Gain (High) Distribution
图6-45. Transimpedance Gain (Low) Distribution
4500
3000
4000
3500
3000
2500
2000
1500
1000
500
2500
2000
1500
1000
500
0
0
1
1.05
1.1
1.15
1.2
1.25
450 460 470 480 490 500 510 520 530 540 550
Output Common Mode Voltage (V)
Differential Output Voltage(mV)
.
.
图6-47. Output Common-Mode Voltage (VOCM) Distribution
图6-48. Differential Output Offset Voltage (VOD) Distribution
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6.9 Typical Characteristics (continued)
At VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω(differential
load between OUT+ and OUT–), and TA = 25°C (unless otherwise noted).
2000
1500
1000
500
0
3000
2500
2000
1500
1000
500
0
17.5
18.25
19
19.75
20.5
21.25
22
2.8 2.9
3
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9
4
Differential Output Impedance (W)
Differential Output Impedance (kW)
Amplifier Enabled
Amplifier Disabled
图6-49. Differential Output Impedance (ZOUT) Distribution
图6-50. Differential Output Impedance (ZOUT) Distribution
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7 Detailed Description
7.1 Overview
The LMH32401 device is a single-channel, differential output, high-speed transimpedance amplifier (TIA) that
features several integrated functions geared towards light detection and ranging (LIDAR) and pulsed time-of-
flight (ToF) systems. The LMH32401 device is designed to work with photodiode (PD) configurations that can
source or sink the current. When the photodiode sinks the photocurrent (anode is biased to a negative voltage
and cathode is tied to the amplifier input) the fast recovery clamp activates when the amplifier input is
overloaded. When the photodiode sources the photocurrent (cathode is biased to a positive voltage and anode
is tied to the amplifier input) a soft clamp activates when the amplifier input is overloaded. When the soft clamp
activates, the amplifier takes longer to recover. The recovery time depends on the level of input overload. The
LMH32401 device is offered in a space-saving 3-mm × 3-mm, 16-pin VQFN package and is rated over a
temperature range from –40°C to +125°C.
7.2 Functional Block Diagram
GAIN
VDD1
VDD2
EN
100 mA
Clamp
1 k
IDC + ISIG
10 k
Differential Output ADC Driver
IN
ISIG
R
2.4 × R
10
OUT
TIA
IDC
+
Ambient Light
Cancellation
VBIAS
–
OUT+
VOCM
IDC EN
R
2.4 × R
10
VDD
VREF
VDD
Voltage to Current
17 k
3 k
50.4 k
25 k
VOD
GND
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7.3 Feature Description
7.3.1 Switched Gain Transimpedance Amplifier
The LMH32401 device features a programmable gain transimpedance amplifier (TIA) stage followed by a fixed-
gain, single-ended input to differential output amplifier stage. The closed-loop bandwidth and noise of a TIA are
affected by the transimpedance gain and photodiode capacitance. For a given value of photodiode capacitance,
the LMH32401 device has higher bandwidth in its low-gain configuration compared to the high-gain
configuration. Increasing the gain of the TIA stage by a factor of X increases the output signal by a factor X, but
the noise contribution from the resistor only increases by √X. The input-referred noise density of the low-gain
configuration is therefore higher than the input-referred noise density of the high-gain configuration.
The gain of the TIA stage is controlled by the GAIN pin. Setting this pin low places the TIA in its low-gain
configuration, whereas setting the pin high places the TIA in a high-gain configuration. The LMH32401 device
defaults to its low-gain configuration when the GAIN pin is left floating.
7.3.2 Clamping and Input Protection
The LMH32401 device is designed to work with photodiode (PD) configurations that can source or sink current;
however, the LMH32401 is optimized for a sinking current configuration. It is assumed that the LMH32401 device
is being used with a PD that is configured with its cathode tied to the amplifier input and the anode tied to a
negative supply voltage, unless stated otherwise.
The LMH32401 features two internal clamps, a fast recovery clamp and a soft clamp. The fast recovery clamp is
the active clamp when the photodiode is sinking a photocurrent. The soft clamp is the active clamp when the
photodiode is sourcing a photocurrent. Stray reflections from nearby objects with high reflectivity can produce
large output current pulses from the PD. The linear input range of the LMH32401 device is approximately 65 µA
in the high-gain configuration and 650 µA in the low-gain configuration (PD sinking the photocurrent).
Input currents in excess of the linear current range cause the internal nodes of the amplifier to saturate, which
increases the amplifier recovery time. The end result is a broadening of the output pulse leading to blind zones
in the system response. To protect against this condition, the LMH32401 features an integrated clamp that
absorbs and diverts the excess current to the positive supply (VDD1) when the amplifier detects its nodes
entering a saturated condition. The integrated clamp minimizes the pulse extension to less than a few ns for
input pulses up to 100 mA. The power-supply pins (VDD1 and VDD2) must each have their own bypass
capacitors to prevent large input pulses from affecting the differential output stage. When the amplifier is in low-
power mode, the clamp circuitry is still active, thereby protecting the TIA input.
7.3.3 ESD Protection
All LMH32401 pins have an internal electrostatic discharge (ESD) protection diode to the positive and negative
supply rails to protect the amplifier from ESD events.
7.3.4 Differential Output Stage
The differential output stage of the LMH32401 device performs the following two functions, which are common
across all differential amplifiers:
1. Converts the single-ended output from the TIA stage to a differential output.
2. Performs a common-mode output shift to match the specified ADC input common-mode voltage.
The differential output stage has two 10-Ω series resistors on its output to isolate the amplifier output stage
transistors from the package bond-wire inductance and printed circuit board (PCB) capacitance. The net gain of
the LMH32401 device (TIA + output stage) is 2 kΩ (low gain) and 20 kΩ (high gain) when driving an external
100-Ω resistor. When the external load resistor is increased above 100 Ω, the effective gain from the IN pin to
the differential output pin increases. Conversely, when the external load resistor is decreased to less than 100
Ω, the effective gain from the IN pin to the differential output pin decreases as a result of the larger voltage drop
across the two internal 10-Ω resistors. When there is no load resistor between the OUT+ and OUT– pins, the
effective gain of the LMH32401 is 2.4 kΩand 24 kΩin the low-gain and high-gain configurations, respectively.
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The output common-mode voltage of the LMH32401 device can be set externally through the VOCM pin. A
resistor divider internal to the amplifier, between VDD2 and ground sets the default voltage to 1.1 V. The internal
resistors generate common-mode noise that is typically rejected by the CMRR of the subsequent ADC stage. To
maximize the amplifier signal-to-noise ratio (SNR), place an external noise bypass capacitor to ground on the
VOCM pin. In single-ended signal chains, such as ToF systems that use time-to-digital converters (TDCs), only a
single output of the LMH32401 device is needed. In such situations, terminate the unused differential output in
the same manner as the used output to maintain balance and symmetry. The signal swing of the single-ended
output is half the available differential output swing. Additionally, the common-mode noise of the output stage,
which is typically rejected by the differential input ADC, is now added to the total noise, further degrading SNR.
The output stage of the LMH32401 device has an additional VOD input that sets the differential output between
OUT– and OUT+. 图 7-1 shows how each output pin of the LMH32401 device is at the voltage set by the
VOCM pin (default = 1.1 V) when the photodiode output current is zero and the VOD input is set to 0 V. When
the VOD pin is driven to a voltage of X volts, the two output pins are separated by X volts when the photodiode
current is zero. The average voltage is still equal to VOCM. For example, 图 7-2 shows if VOCM is set to 1.1 V
and VOD is set to 0.4 V, then OUT–= 1.1 V + 0.2 V = 1.3 V and OUT+ = 1.1 V –0.2 V = 0.9 V.
The VOD pin is functional only when the LMH32401 device is used with a PD that sinks the photocurrent. Set
VOD = 0 V when the LMH32401 device is interfaced with a PD that sources the photocurrent. The VOD output
offset feature is included in the LMH32401 device because the output current of a photodiode is unipolar.
Depending on the reverse bias configuration, the photodiode can either sink or source current, but cannot do
both at the same time. With the anode connected to a negative bias and the cathode connected to the TIA stage
input, the photodiode can only sink current, which implies that the TIA stage output swings in a positive direction
above its default input bias voltage (2.47 V). Subsequently, OUT– only swings below VOCM and OUT+ only
swings above VOCM. 图 7-1 shows how the LMH32401 device only uses half of its output swing range (VOUT
OUT+ – VOUT–) when VOD = 0 V, because one output never swings below VOCM and the other output never
goes above VOCM. The signal dynamic range in this case is 0.4 VPP –0 V = 0.4 VPP
=
V
.
图 7-2 shows how the VOD pin voltage allows OUT– to be level-shifted above VOCM and OUT+ to be level-
shifted below VOCM to maximize the output swing capabilities of the amplifier. The signal dynamic range in this
case is 0.4 VPP –(–0.4 VPP) = 0.8 VPP
.
VOUT = 0.4 VPP
APD Excited
VOUT = 0.4 VPP
APD Excited
VOUTÞ
VOUT+
VOUTÞ
VOUT+
1.3 V
1.3 V
VOD = 0 V
VOCM = 1.1 V
VOD = 0.4 V
VOCM = 1.1 V
0.9 V
0.9 V
VOUT = 0 VPP
No output from APD
VOUT = Þ0.4 VPP
No output from APD
图7-1. Individual Single-Ended Outputs With VOD
图7-2. Individual Single-Ended Outputs With VOD
= 0 V
= 0.4 V
When the LMH32401 device drives a 100-Ω load, the voltage set at the VOD pin is equal to the differential
output offset (VOUT = VOUT+ – VOUT–) when the input signal current is zero. Use 方程式 1 to calculate the
differential output offset under other load conditions.
RL
VOD = 1.2 ì VOD ì
R ì 20 W
L
(1)
Where:
• VOD = Voltage applied at pin 9
• VOD = (VOUT– –VOUT+
)
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• RL = External load resistance
7.4 Device Functional Modes
7.4.1 Ambient Light Cancellation (ALC) Mode
The LMH32401 device has an integrated DC cancellation loop that cancels and voltage offsets from incidental
ambient light. The ALC mode only works when the PD is sinking the photocurrent. The DC cancellation loop is
enabled by setting IDC_EN low. Incident ambient light on a photodiode produces a DC current resulting in an
offset voltage at the output of the LMH32401's TIA stage. The Functional Block Diagram shows how the ALC
loop senses the low-frequency DC offset at the output of the TIA stage and compares it against an internal
reference voltage (VREF). The ALC loop then outputs an opposing DC current (IDC) to compensate for the
differential offset voltage at its input. The loop has a high-pass cutoff frequency of 100 kHz. The ambient light
cancellation loop is disabled when the amplifier is placed in power-down mode.
The shot noise current introduced by the DC cancellation loop increases the overall amplifier noise; so, if the
ambient light level is negligible, then disable the loop to improve SNR. The cancellation loop helps save PCB
space and system costs by eliminating the need for external AC coupling passive components. Additionally, the
extra trace inductance and PCB capacitance introduced by using external AC coupling components degrades
the LMH32401 device dynamic performance.
7.4.2 Power-Down Mode (Multiplexer Mode)
The LMH32401 device can be placed in low-power mode by setting EN high, which helps in saving system
power. Enabling low-power mode puts the outputs of the internal amplifiers in the LMH32401 device, including
the differential outputs, in a high-impedance state. 图 7-3 shows how this device feature can further save board
space and cost by eliminating the need for a discrete high-speed multiplexer, if a system consists of several
photodiode and amplifier channels multiplexed to a single ADC channel. The disabled channel outputs are not
an ideal open circuit so as the number of multiplexed channels increases the disabled channels begin to load the
enabled channel. Multiplexing more than four channels in parallel degrades the performance of the enabled
channel. When the amplifier is in its low-power mode, the clamp circuitry is still active thereby protecting the TIA
input. The ambient light cancellation loop is disabled when the amplifier is placed in power-down mode. When
the LMH32401 device is brought out of power-down operation the ambient light cancellation loop requires
several time constants to settle. 图6-9 shows the low-frequency loop response which in turn determines the time
constant needed for the loop to settle.
1 kΩ
DISABLED AMPLIFIER
100mA
Clamp
10 kΩ
10 Ω
RISO
TIA
OUTÞ
Ambient Light
Cancellation
Þ VBIAS
+
œ
OUT+
Output Offset
10 Ω
RISO
RADC_IN
EN = 3.3 V
ADC12QJ1600
CFILT
VOCM
RADC_IN
1 kΩ
ENABLED AMPLIFIER
100mA
Clamp
10 kΩ
10 Ω
RISO
TIA
OUTÞ
Ambient Light
Cancellation
Þ VBIAS
+
œ
OUT+
Output Offset
10 Ω
RISO
EN = 0 V
图7-3. Configuring Two LMH32401 Devices in Multiplexer Mode to Drive a Single ADC
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8 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
8.1 Application Information
The differential outputs of the LMH32401 device can directly drive a high-speed differential input ADC. 图 8-1
shows the LMH32401 differential outputs directly driving the ADC12QJ1600. The effective signal gain between
the TIA input and the ADC input is 2 kΩ or 20 kΩ when driving an ADC with a 100-Ω differential input
impedance (RADC_IN = 50 Ω). 方程式 2 gives the effective signal gain between the TIA input and the ADC input
when driving an ADC with any other value of differential input impedance (RADC_IN ≠50 Ω).
GAIN
VDD1
VDD2
1 kΩ
100mA
Clamp
10 kΩ
Differential Output
ADC Driver
IN
OUTÞ
TIA
10 Ω
RADC_IN
Ambient Light
Cancellation
Þ VBIAS
IDC EN
VOD
+
VOCM
RADC_IN
ADC12QJ1600
œ
Output Offset
10 Ω
OUT+
GND
EN
图8-1. LMH32401 to ADC Interface
2ì RADC_IN
A V = 2 kW or 20 kW ì 1.2 ì
(
)
2ì R
+ 20 W
ADC_IN
(2)
Where:
• AV = Differential gain from the TIA input to the ADC input
• RADC_IN = Input resistance of the ADC
图 8-2 shows a matching resistor network between the LMH32401 output and the ADC12QJ1600 input. The
matching network is needed to prevent signal reflections when the signal path between the LMH32401 and ADC
is very long. 方程式3 gives the effective gain from the TIA input to the ADC input when using a matching resistor
network.
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GAIN
VDD1
VDD2
1 kΩ
100mA
Clamp
10 kΩ
Differential Output
ADC Driver
IN
10 Ω
RISO
TIA
OUTÞ
RADC_IN
Ambient Light
Cancellation
Þ VBIAS
IDC EN
VOD
+
ADC12QJ1600
VOCM
RADC_IN
œ
OUT+
Output Offset
10 Ω
RISO
GND
EN
图8-2. LMH32401 to ADC Interface with a Matching Resistor Network
2ì RADC_IN
A V = 2 kW or 20 kW ì 1.2 ì
(
)
2ì RADC_IN +2 ì RISO + 20 W
(3)
Where:
• AV = Gain from the TIA input to the ADC input
• RADC_IN = Differential input resistance of the ADC
• RISO = Series resistance between the TIA and ADC
方程式 4 gives the voltage to be applied at the VOD pin (pin 9) if a certain differential offset voltage (VOD) is
needed at the ADC input for the circuit in 图8-2.
2 ì R
+ 2 ì RISO + 20 W
(
ì
)
1
ADC _IN
≈
’
VOD = VOD
ì
∆
«
÷
◊
1.2
2 ì R
ADC _IN
(4)
Where:
• VOD = Voltage applied at pin 9
• VOD = Desired differential offset voltage at the ADC input
• RADC_IN = Differential input resistance of the ADC
• RISO = Series resistance between the TIA and ADC
8.2 Typical Application
This section demonstrates the performance of the LMH32401 device when the input current flows into the IN pin.
图 8-3 shows the circuit used to test the LMH32401 device with a voltage source. This configuration
demonstrates the use case when the photodiode's anode is tied to the amplifier input and its cathode is tied to a
positive voltage greater than 2.47 V.
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GAIN
VDD1
VDD2
100mA
Clamp
1 kΩ
10 kΩ
2kꢀ
Differential Output ADC Driver
IN
50ꢀ measurement
instrument
ISIG
R
2.4 × R
10 ꢀ
OUTÞ
TIA
25 ꢀ
1 …F
1 …F
IDC
+
+
2.47 V
œ
CLOAD
Ambient Light
Cancellation
œ
25 ꢀ
IDC EN
GND
R
2.4 × R
10 ꢀ
VDD
OUT+
VREF
VDD
Voltage to Current
17 kΩ
3 kΩ
50.4 kΩ
VOD
VOCM
25 kΩ
GND
EN
图8-3. LMH32401 Test Circuit
8.2.1 Design Requirements
The objective is to design a low-noise, wideband differential output transimpedance amplifier. The design
requirements are as follows:
• Amplifier supply voltage: 3.3 V
• Transimpedance gain: 2 kΩand 20 kΩ
• Input capacitance: CPCB ≅ 1 pF
• Target bandwidth: > 250 MHz
• Differential output offset (VOD): 0 V
• Ambient light cancellation (IDC_EN): 3.3 V (disabled)
8.2.2 Detailed Design Procedure
图8-3 shows the LMH32401 device test circuit used to measure its bandwidth and transient pulse response. The
voltage source is DC biased close to the input bias voltage of the LMH32401 device (approximately 2.47 V). The
internal design of the LMH32401 device is optimized to only source current out of the input pin (pin 3), and all
the data shown previously is with the current flowing out of the pin. When the voltage input from the source
exceeds 2.47 V, the LMH32401 device input will sink the current. Set VOD = 0 V when the input has to sink the
current from the photodiode, or in this case the voltage source. Set the DC bias so that sum of the input AC and
DC component is always greater than the input voltage (2.47 V) when testing the LMH32401 device with a
network analyzer or sinusoidal source.
图 8-4 and 图 8-5 shows the bandwidth of the LMH32401 device when its input is sinking the current. The input
current range of the LMH32401 device is reduced when it is sinking the current. This effect is seen by the
decrease in bandwidth as the output swing increases and is more pronounced in a gain configuration of 20 kΩ.
Compare 图 8-4 with 图 6-1 and 图 6-3 to see the effect of current direction and input range in a 2 kΩ gain
configuration. In a similar way, compare 图 8-5 with 图 6-2 and 图 6-4 to see the effect of current direction and
input range in a gain of 20 kΩ.
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图 8-6 and 图8-7 show the pulsed output response of the LMH32401 device when the input current is increased
past the amplifier linear input range. When the input is sinking current, a soft clamp will aid in fast recovery;
however, the pulse will stretch slightly as the input current overrange increases. Compare 图 8-6 with 图 6-21 to
see the pulse extension effect in a gain of 2 kΩ. Compare 图 8-7 with 图 6-22 to see the pulse extension effect
in a gain of 20 kΩ. Knowledge of the pulse extension can be used to determine the approximate input current
even under overrange situations that can occur due to the presence of retro-reflectors in the environment. As
shown in 图 7-1, each half of the differential output pulse will only swing above or below the VOCM voltage and
the resulting maximum differential output swing is 0.75 VPP since VOD is set to 0 V. Consequently only half of
the total ADC range is utilized in this photodiode configuration.
8.2.3 Application Curves
69
66
63
60
57
54
51
89
86
83
80
77
74
71
VOUT = 0.1 VPP
VOUT = 0.5 VPP
VOUT = 1 VPP
VOUT = 0.1 VPP
VOUT = 0.5 VPP
VOUT = 1 VPP
10M
100M
Frequency [Hz]
1G
10M
100M
Frequency [Hz]
1G
图8-4. Bandwidth vs Output Swing
(Gain = 2 kΩ)
图8-5. Bandwidth vs Output Swing
(Gain = 20 kΩ)
1
1
IIN = 500 mA
IIN = 1 mA
IIN = 2.5 mA
IIN = 50 mA
IIN = 100 mA
IIN = 500 mA
IIN = 1 mA
0.75
0.5
0.75
0.5
0.25
0
0.25
0
-0.25
-0.25
Time (5 ns/div)
Time (5 ns/div)
图8-6. Pulse Response vs Input Current
(Gain = 2 kΩ)
图8-7. Pulse Response vs Input Current
(Gain = 20 kΩ)
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9 Power Supply Recommendations
The LMH32401 device operates on 3.3-V supplies. The VDD1 and VDD2 pins must always be driven from the
same supply source and individually bypassed. A low power-supply source impedance must be maintained
across frequency. So use multiple bypass capacitors in parallel. Place the bypass capacitors as close to the
supply pins as possible. Place the smallest capacitor on the same side of the PCB as the LMH32401 device.
Placing the larger valued bypass capacitors on the same side of the PCB is preferable as well. However, if there
are space constraints, then the capacitors can be moved to the opposite side of the PCB using multiple vias to
reduce the series inductance resulting from the vias. The LMH32401 device can operate on bipolar supplies by
connecting pins 1 and 7 to the negative supply. The thermal pad must always be connected to the most negative
supply. The digital pin threshold voltages must be appropriately level shifted as they are connected to voltages at
pins 1 and 7.
10 Layout
10.1 Layout Guidelines
Achieving optimum performance with a high-frequency amplifier such as the LMH32401 device requires careful
attention to board layout parasitics and external component types. Recommendations that optimize performance
include the following:
• Minimize parasitic capacitance from the signal I/O pins to ac ground. Parasitic capacitance on the
output pins can cause instability whereas parasitic capacitance on the input pin reduces the amplifier
bandwidth. To reduce unwanted capacitance, cut out the power and ground traces under the signal input and
output pins. Otherwise, ground and power planes must be unbroken elsewhere on the board.
• Minimize the distance from the power-supply pins to high-frequency bypass capacitors. Use high-
quality, 100-pF to 0.1-µF, C0G and NPO-type decoupling capacitors with voltage ratings at least three times
greater than the amplifiers maximum power supplies. Place the smallest value capacitors on the same side
as the DUT. If space constraints force the larger value bypass capacitors to be placed on the opposite side of
the PCB, then use multiple vias on the supply and ground side of the capacitors. This configuration makes
sure that there is a low-impedance path to the amplifiers power-supply pins across the amplifiers gain
bandwidth specification. Avoid narrow power and ground traces to minimize inductance between the pins and
the decoupling capacitors. Larger (2.2-µF to 6.8-µF) decoupling capacitors that are effective at lower
frequency must be used on the supply pins. Place these decoupling capacitors further from the device. Share
the decoupling capacitors among several devices in the same area of the printed circuit board (PCB).
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10.2 Layout Example
GND
Place bypass capacitors close to VDD
and GND pins on the same side as
DUT. Use multiple vias to connect to
power and GND planes
16
GAIN
15
NC
14
VDD2
13
NC
Optional capacitor to reduce
VOCM noise from internal
resistors
GND
1
12
VOCM
GND
VDD1
11
OUTÞ
2
Remove GND and Power
plane near output pins to
minimize parasitic PCB
capacitance. Resistors to
further isolate parasitics
Remove GND and Power plane
between IN and APD to minimize
parasitic capacitance
Thermal Pad
IN
3
10
OUT+
Optional capacitor to reduce
VOD noise from internal
resistors
9
VOD
NC
4
Þ VBIAS
GND
5
6
8
7
Optional isolation resistor to dampen
resonance due to bond wire
inductances and component
capacitances
IDC_EN
EN
NC
GND
图10-1. Layout Recommendation
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
• Texas Instruments, LMH32401 Transimpedance Amplifier Evaluation Module.
• Texas Instruments, Optical Front-End System Reference Design design guide.
• Texas Instruments, LIDAR-Pulsed Time-of-Flight Reference Design Using High-Speed Data Converters
design guide.
• Texas Instruments, LIDAR Pulsed Time of Flight Reference Design design guide.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, LMH32401IRGT Evaluation Module user's guide.
• Texas Instruments, Transimpedance Considerations for High-Speed Amplifiers application report.
• Texas Instruments, What You Need To Know About Transimpedance Amplifiers –Part 1 blog.
• Texas Instruments, An Introduction to Automotive LIDAR.
• Texas Instruments, Maximizing the Dynamic Range of Analog Front Ends Having a Transimpedance
Amplifier.
• Texas Instruments, Time of Flight and LIDAR –Optical Front End Design.
• Texas Instruments, What You Need To Know About Transimpedance Amplifiers –Part 2 blog.
• Texas Instruments, Training Video: How to Design Transimpedance Amplifier Circuits.
• Texas Instruments, Training Video: High-Speed Transimpedance Amplifier Design Flow.
• Texas Instruments, Training Video: How to Convert a TINA-TI Model into a Generic SPICE Model.
11.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
11.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: LMH32401
PACKAGE OPTION ADDENDUM
www.ti.com
13-Jan-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH32401IRGTR
LMH32401IRGTT
LMH32401YR
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
RGT
RGT
Y
16
16
0
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 125
-40 to 125
-40 to 125
L32401
L32401
Samples
Samples
Samples
NIPDAU
Call TI
DIESALE
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
13-Jan-2023
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH32401IRGTR
LMH32401IRGTT
VQFN
VQFN
RGT
RGT
16
16
3000
250
330.0
180.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMH32401IRGTR
LMH32401IRGTT
VQFN
VQFN
RGT
RGT
16
16
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RGT0016C
VQFN - 1 mm max height
S
C
A
L
E
3
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
SIDE WALL
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
1.0
0.8
C
SEATING PLANE
0.08
0.05
0.00
1.68 0.07
(DIM A) TYP
5
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X
SYMM
1.5
1
12
0.30
16X
0.18
13
16
0.1
C A B
PIN 1 ID
(OPTIONAL)
SYMM
0.05
0.5
0.3
16X
4222419/D 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGT0016C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.68)
SYMM
13
16
16X (0.6)
1
12
16X (0.24)
SYMM
(2.8)
(0.58)
TYP
12X (0.5)
9
4
(
0.2) TYP
VIA
5
(0.58) TYP
8
(R0.05)
ALL PAD CORNERS
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222419/D 04/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGT0016C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.55)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
8
SYMM
(2.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4222419/D 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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