LMH6574MAX/NOPB [TI]
具有 4:1 高速多路复用器的 500MHz 高速运算放大器 | D | 14 | -40 to 85;
| 型号： | LMH6574MAX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 4:1 高速多路复用器的 500MHz 高速运算放大器 | D | 14 | -40 to 85 放大器 光电二极管 运算放大器 复用器 |
| 文件： | 总30页 (文件大小：1057K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
LMH6574
ZHCSIM9E –NOVEMBER 2004–REVISED AUGUST 2018
LMH6574 4:1 高速视频多路复用器
1 特性
3 说明
1
•
•
•
•
•
•
•
•
•
•
500MHz、500mV −3dB 带宽、AV = 2
LMH6574 是一款经过优化的高性能模拟多路复用器，
适用于专业级视频应用和其他高保真度、高带宽模拟
应用。输出放大器可根据两个地址位的状态选择四个输
入信号中的任何一个。LMH6574 可在 2VPP 输出信号
电平提供 400MHz 带宽。LMH6574 具有 150MHz 的
0.1dB 带宽和 2200V/μs 的压摆率，这对多媒体和高清
电视 (HDTV) 应用 非常有利。
400MHz、2VPP −3dB 带宽、AV = 2
8ns 通道开关时间
70dB 通道到通道隔离（在 10MHz 条件下）
0.02% 差动增益，0.05° 差动相位
0.1dB 增益平坦度：150MHz
2200V/μs 压摆率
宽电源电压范围：6V (±3V) 至 12V (±6V)
5MHz 时为 −68dB HD2
LMH6574 针对 NTSC 和 PAL 视频信号的差动增益误
差和差动相位误差分别为 0.02% 和 0.05°，支持复合
视频 应用 ，同时可驱动后部端接的单个 75Ω 负载。
该器件可提供 80mA 线性输出电流来驱动多个视频负
载 应用。
5MHz 时为 −84dB HD3
2 应用
•
•
•
•
•
•
视频路由器
LMH6574 支持通过外部反馈和增益设置电阻器来设置
增益，以实现最大灵活性。
多输入视频监控器
仪表/测试设备
接收器中频分集开关
多通道模数转换驱动器
画中画视频开关
LMH6574 可提供 14 引脚 SOIC 封装。
器件信息(1)
器件型号
LMH6574
封装
SOIC (14)
封装尺寸（标称值）
8.65mm × 3.91mm
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品
附录。
频率响应与增益间的关系
频率响应与 VOUT 间的关系
1
1
0
0
-1
A
= 1, R = 1.5 kW
F
V
-1
-2
-3
-4
V
= 0.5 V
PP
OUT
A
V
= 2, R = 575W
F
-2
-3
-4
V
= 1 V
PP
OUT
A
= 6, R = 300W
V
F
-5
-6
-7
-8
-9
V
= 2 V
PP
OUT
A
V
= 10, R = 180W
-5
-6
-7
-8
-9
F
V
= 4 V
OUT
PP
V
= ±5V
S
V
= 2 V
PP
V
= ±5V
OUT
S
A
V
= 2V/V
10
100
FREQUENCY (MHz)
1000
10
100
1000
FREQUENCY (MHz)
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNCS103
LMH6574
ZHCSIM9E –NOVEMBER 2004–REVISED AUGUST 2018
www.ti.com.cn
目录
7.3 Device Functional Modes........................................ 16
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
Power Supply Recommendations...................... 21
9.1 Power Dissipation ................................................... 21
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics ±5 V ................................. 5
6.6 Electrical Characteristics ±3.3 V .............................. 7
6.7 Typical Characteristics.............................................. 8
Detailed Description ............................................ 13
7.1 Functional Block Diagram ....................................... 13
7.2 Feature Description................................................. 13
8
9
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
11 器件和文档支持 ..................................................... 22
11.1 文档支持................................................................ 22
11.2 接收文档更新通知 ................................................. 22
11.3 社区资源................................................................ 22
11.4 商标....................................................................... 22
11.5 静电放电警告......................................................... 22
11.6 术语表 ................................................................... 22
12 机械、封装和可订购信息....................................... 22
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision D (December 2014) to Revision E
Page
•
•
•
Changed IBN parameter maximum specifications from ±5 µA to ±5.2 µA and from ±5.6 µA to ±5.8 µA .............................. 5
Changed PSRR parameter minimum specifications from 47 dB to 43 dB and from 45 dB to 41 dB .................................... 5
Changed Supply Current Disabled parameter maximum specifications from 5.8 mA to 6.2 mA and from 5.9 mA to
6.3 mA .................................................................................................................................................................................... 6
•
•
Changed IiL parameter minimum specifications from –2.9 µA to –3.3 µA and from –8.5 µA to –9 µA ................................. 6
Added Feature Description and Device Functional Modes sections.................................................................................... 13
Changes from Revision C (November 2012) to Revision D
Page
•
添加、更新或修订了以下部分：引脚配置和功能、规格、应用和实施、电源建议、布局、器件和文档支持 以及机械、
封装和可订购信息................................................................................................................................................................... 1
Revised text in Application and Implementation section, formerly titled "Application Notes"............................................... 17
Revised text in Multiplexer Expansion section. Added Figure 31, Figure 32, and Figure 33 .............................................. 17
•
•
2
Copyright © 2004–2018, Texas Instruments Incorporated
LMH6574
www.ti.com.cn
ZHCSIM9E –NOVEMBER 2004–REVISED AUGUST 2018
5 Pin Configuration and Functions
14-Pin SOIC
Package D
(Top View)
IN0
GND
IN1
1
2
3
4
5
6
7
14
13
12
11
10
9
V+
+
-
OUT
FB
GND
IN2
SD
EN
A1
A0
V-
IN3
8
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
IN0
GND
IN1
GND
IN2
V-
1
I
Input Channel 0
Ground
2
––
3
I
––
I
Input Channel 1
Ground
4
5
Input Channel 2
V- Supply
6
I
7
IN3
A0
I
Input Channel 3
Select Pin A0
Select Pin A1
Enable
8
I
9
A1
I
10
11
12
13
14
EN
I
SD
I
Shutdown
FB
I
Feedback
OUT
V+
O
I
Output
V+ Supply
Truth Table
A1
1
A0
1
EN
SD
0
OUT
CH 3
0
1
0
0
0
CH2
0
1
0
0
CH1
0
0
0
0
CH 0
X
X
X
X
1
0
Disable
Shutdown
X
1
Copyright © 2004–2018, Texas Instruments Incorporated
3
LMH6574
ZHCSIM9E –NOVEMBER 2004–REVISED AUGUST 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings(1)(2)
MIN
MAX
13.2
130
UNIT
V
Supply Voltage (V+ − V−)
(3)
IOUT
mA
Signal & Logic Input Pin Voltage
Signal & Logic Input Pin Current
Maximum Junction Temperature
Storage Temperature
±(VS+0.6)
±20
V
mA
°C
°C
+150
−65
+150
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics ±5 V tables
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) The maximum output current (IOUT) is determined by the device power dissipation limitations (The junction temperature cannot be
allowed to exceed 150°C). See the Power Dissipation for more details. A short circuit condition should be limited to 5 seconds or less.
6.2 ESD Ratings
VALUE
±2000
±200
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(2)
Machine model (MM)
V(ESD)
Electrostatic discharge(1)
V
(1) Human Body model, 1.5 kΩ in series with 100 pF. Machine model, 0 Ω In series with 200 pF.
(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 2000-V HBM is possible with the necessary precautions. Pins listed as ±200 V may actually have higher performance.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
−40
6
NOM
MAX
85
UNIT
°C
Operating Temperature
Supply Voltage
12
V
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical
Characteristics ±5 V tables
6.4 Thermal Information
D
THERMAL METRIC(1)
UNIT
14 PINS
130
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
RθJC(top)
40
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2004–2018, Texas Instruments Incorporated
LMH6574
www.ti.com.cn
ZHCSIM9E –NOVEMBER 2004–REVISED AUGUST 2018
6.5 Electrical Characteristics ±5 V
VS = ±5 V, RL = 100 Ω, AV = 2 V/V, RF = 575 Ω, TJ = 25 °C, unless otherwise specified.
PARAMETER
TEST CONDITIONS(1)
MIN
TYP
MAX
UNIT
FREQUENCY DOMAIN PERFORMANCE
SSBW
LSBW
−3 dB Bandwidth
VOUT = 0.5 VPP
VOUT = 2 VPP
500
400
MHz
MHz
MHz
–3 dB Bandwidth
.1 dBBW 0. 1 dB Bandwidth
VOUT = 0.25 VPP
150
DG
DP
Differential Gain
RL = 150 Ω, f = 4.43 MHz
RL = 150 Ω, f = 4.43 MHz
0.02%
0.05
Differential Phase
deg
dB
Channel to Channel
Crosstalk
XTLK
All Hostile, 5 MHz
−85
TIME DOMAIN RESPONSE
Channel to Channel
TRS
Logic Transition to 90% Output
8
ns
ns
Switching Time
Enable and Disable
Times
Logic Transition to 90% or 10% Output
4-V Step
10
TRL
TSS
OS
Rise and Fall Time
2.4
17
ns
ns
Settling Time to 0.05% 2-V Step
Overshoot
Slew Rate
2-V Step
4-V Step
5%
SR
2200
V/μs
DISTORTION
HD2
HD3
2nd Harmonic Distortion 2 VPP , 5 MHz
3rd Harmonic Distortion 2 VPP , 5 MHz
3rd Order
−68
−84
dBc
dBc
IMD
Intermodulation
Products
10 MHz, Two Tones 2 VPP at Output
−80
dBc
EQUIVALENT INPUT NOISE
VN
Voltage
Current
>1 MHz, Input Referred
>1 MHz, Input Referred
5
5
nV√Hz
pA/√Hz
ICN
STATIC, DC PERFORMANCE
±0.005% ±0.032%
±0.035%
Channel to Channel
CHGM
DC, Difference in Gain
Between Channels
Gain Difference
-40°C ≤ TJ ≤ 85°C
-40°C ≤ TJ ≤ 85°C
1
±20
±25
VIO
Input Offset Voltage(2)
Offset Voltage Drift
VIN = 0 V
mV
µV/°C
µA
DVIO
IBN
30
−3
±5.2
±5.8
Input Bias Current(2)(3) VIN = 0 V
Bias Current Drift
-40°C ≤ TJ ≤ 85°C
DIBN
11
nA/°C
−7
±10
±13
Inverting Input Bias
Current
Pin 12, Feedback Point,
VIN = 0 V
-40°C ≤ TJ ≤ 85°C
-40°C ≤ TJ ≤ 85°C
43
41
54
Power Supply Rejection
Ratio(2)
PSRR
DC, Input Referred
dB
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensure of parametric performance is indicated in the electrical tables under
conditions of internal self heating where TJ > TA. See Application and Implementation for information on temperature de-rating of this
device. Min/Max ratings are based on product testing, characterization and simulation. Individual parameters are tested as noted.
(2) Parameters guaranteed by electrical testing at 25°C.
(3) Positive Value is current into device.
Copyright © 2004–2018, Texas Instruments Incorporated
5
LMH6574
ZHCSIM9E –NOVEMBER 2004–REVISED AUGUST 2018
www.ti.com.cn
Electrical Characteristics ±5 V (continued)
VS = ±5 V, RL = 100 Ω, AV = 2 V/V, RF = 575 Ω, TJ = 25 °C, unless otherwise specified.
PARAMETER
TEST CONDITIONS(1)
MIN
TYP
MAX
UNIT
13
16
18
ICC
Supply Current(2)
No Load
mA
-40°C ≤ TJ ≤ 85°C
4.7
1.8
6.2
6.3
2.5
2.6
Supply Current
Disabled(2)
ENABLE > 2 V
SHUTDOWN > 2 V
mA
mA
-40°C ≤ TJ ≤ 85°C
-40°C ≤ TJ ≤ 85°C
Supply Current
Shutdown
VIH
VIL
Logic High Threshold(2) Select & Enable Pins (SD & EN)
Logic Low Threshold(2) Select & Enable Pins (SD & EN)
2.0
V
V
0.8
−3.3
−1
Logic Pin Input Current Logic Input = 0 V Select &
IiL
µA
µA
Low(3)
Enable Pins (SD & EN)
-40°C ≤ TJ ≤ 85°C
-40°C ≤ TJ ≤ 85°C
–9
47
68
Logic Pin Input Current Logic Input = 2.0 V, Select
High(3)
& Enable Pins (SD & EN)
IiH
72.5
MISCELLANEOUS PERFORMANCE
RIN+
CIN
Input Resistance
Input Capacitance
Output Resistance
Output Resistance
Output Capacitance
5
0.8
kΩ
pF
Ω
ROUT
ROUT
COUT
Output Active, (EN and SD < 0.8 V)
Output Disabled, (EN or SD > 2 V)
Output Disabled, (EN or SD > 2 V)
0.04
3000
3.1
Ω
pF
±3.54
±3.53
±3.18
±3.17
±2.5
+60
±3.7
VO
No Load
V
-40°C ≤ TJ ≤ 85°C
Output Voltage Range
Input Voltage Range
±3.5
±2.6
VOL
RL = 100 Ω
V
V
-40°C ≤ TJ ≤ 85°C
CMIR
-70
Linear Output
Current(2)(3)
IO
VIN = 0 V
±80
mA
mA
-40°C ≤ TJ ≤ 85°C
-40°C ≤ TJ ≤ 85°C
+50
−60
ISC
Short Circuit Current(4) VIN = ±2 V, Output Shorted to Ground
±230
(4) The maximum output current (IOUT) is determined by the device power dissipation limitations (The junction temperature cannot be
allowed to exceed 150°C). See the Power Dissipation for more details. A short circuit condition should be limited to 5 seconds or less.
6
Copyright © 2004–2018, Texas Instruments Incorporated
LMH6574
www.ti.com.cn
ZHCSIM9E –NOVEMBER 2004–REVISED AUGUST 2018
6.6 Electrical Characteristics ±3.3 V
VS = ±3.3 V, RL = 100 Ω, AV = 2 V/V, RF = 575 Ω; unless otherwise specified.
PARAMETER
TEST CONDITIONS(1)
MIN
TYP
MAX
UNIT
FREQUENCY DOMAIN PERFORMANCE
SSBW
LSBW
−3 dB Bandwidth
−3 dB Bandwidth
VOUT = 0.5 VPP
475
375
100
0.4
MHz
MHz
MHz
dB
VOUT = 2.0 VPP
0.1 dBBW 0.1 dB Bandwidth
VOUT = 0.5 VPP
GFP
Peaking
DC to 200 MHz
All Hostile, f = 5 MHz
XTLK
Channel to Channel Crosstalk
−85
dBc
TIME DOMAIN RESPONSE
TRL
TSS
OS
Rise and Fall Time
Settling Time to 0.05%
Overshoot
2-V Step
2-V Step
2-V Step
2-V Step
2
20
ns
ns
5%
SR
Slew Rate
1400
V/μs
DISTORTION
HD2
HD3
2nd Harmonic Distortion
3rd Harmonic Distortion
2 VPP, 10 MHz
2 VPP, 10 MHz
−67
−87
dBc
dBc
STATIC, DC PERFORMANCE
VIO
IBN
Input Offset Voltage
Input Bias Current(2)
Power Supply Rejection Ratio
Supply Current
VIN = 0 V
-5
-3
mV
μA
dB
mA
V
VIN = 0 V
PSRR
ICC
VIH
DC, Input Referred
No Load
49
12
Logic High Threshold
Logic Low Threshold
Select & Enable Pins (SD & EN)
Select & Enable Pins (SD & EN)
1.3
VIL
0.4
V
MISCELLANEOUS PERFORMANCE
RIN+
CIN
Input Resistance
Input Capacitance
Output Resistance
5
0.8
kΩ
pF
Ω
ROUT
VO
0.06
±2
No Load
V
Output Voltage Range
VOL
CMIR
IO
RL = 100 Ω
±1.8
±1.2
±60
±150
V
Input Voltage Range
Linear Output Current
Short Circuit Current
V
VIN = 0 V
mA
mA
ISC
VIN = ±1 V, Output Shorted to Ground
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensure of parametric performance is indicated in the electrical tables under
conditions of internal self heating where TJ > TA. See Application and Implementation for information on temperature de-rating of this
device. Min/Max ratings are based on product testing, characterization and simulation. Individual parameters are tested as noted.
(2) Positive Value is current into device.
Copyright © 2004–2018, Texas Instruments Incorporated
7
LMH6574
ZHCSIM9E –NOVEMBER 2004–REVISED AUGUST 2018
www.ti.com.cn
6.7 Typical Characteristics
VS = ±5 V, RL = 100 Ω, AV = 2, RF = RG = 575 Ω, unless otherwise specified.
1
0
1
0
-1
-1
A
= 1, R = 1.5 kW
F
V
V
= 0.5 V
PP
OUT
V
-2
-3
-4
-2
-3
-4
A
V
= 2, R = 575W
F
= 1 V
PP
OUT
A
= 6, R = 300W
F
V
V
= 2 V
PP
OUT
-5
-6
-7
-8
-9
-5
-6
-7
-8
-9
A
= 10, R = 180W
F
V
V
= 4 V
OUT
PP
V
= ±5V
V = ±5V
S
S
A
V
= 2V/V
V
= 2 V
OUT PP
10
100
10
100
FREQUENCY (MHz)
1000
1000
FREQUENCY (MHz)
Figure 1. Frequency Response vs VOUT
Figure 2. Frequency Response vs Gain
90
2
C
= 8.6 pF, R
= 63W
V = ±5V
S
L
OUT
80
70
60
50
40
30
20
LOAD = 1 kW || C
L
0
C
C
= 18 pF, R
= 56 pF, R
= 48W
= 24W
L
L
L
OUT
-2
OUT
-4
-6
C
= 100 pF, R = 19W
OUT
V
= 1 V
PP
OUT
C
|| 1 kW
L
S
V
-8
V
A
= ±5V
= 2 (V/V)
10
0
-10
1
10
100
1000
1
10
100
1000
CAPACTIVE LOAD (pF)
FREQUENCY (MHz)
Figure 4. Suggested ROUT vs Capacitive Load
Figure 3. Frequency Response vs Capacitive Load
1600
2.5
2
1400
1200
1000
800
600
400
200
0
1.5
1
0.5
0
-0.5
-1
-1.5
V
= ±5V
S
-2
-2.5
5
7
1
2
3
4
6
8
9
10
8
12
14 16 18 20
0
2
4
6
10
GAIN (V/V)
TIME (ns)
Figure 5. Suggested Value of RF vs Gain
Figure 6. Pulse Response 4VPP
8
Copyright © 2004–2018, Texas Instruments Incorporated
LMH6574
www.ti.com.cn
ZHCSIM9E –NOVEMBER 2004–REVISED AUGUST 2018
Typical Characteristics (continued)
VS = ±5 V, RL = 100 Ω, AV = 2, RF = RG = 575 Ω, unless otherwise specified.
1.5
1.5
V
S
= ±5V
V = ±3.3V
S
1
0.5
0
1
0.5
0
-0.5
-1
-0.5
-1
-1.5
-1.5
0
5
10
15
20
25
30
0
5
10
15
20
25
30
TIME (ns)
TIME (ns)
Figure 7. Pulse Response 2VPP
Figure 8. Pulse Response 2VPP
10000
1000
10000
1000
DISABLED
DISABLED
V
V
A
= ±5V
= 0V
S
100
10
V
V
A
= ±5V
= 0V
100
10
S
IN
V
IN
V
= 2V/V
= 1V/V
1
ENABLED
1
ENABLED
0.1
0.1
0.01
0.1
1
10
100
1000
0.01
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 9. Closed Loop Output Impedance
Figure 10. Closed Loop Output Impedance
0.75
60
PSRR +
CHANNEL 1
0.5
50
0.25
0
40
PSRR -
CHANNEL 0
-0.25
-0.5
30
20
10
0
3
2
1
0
ADDRESS LINE 0
0.1
1
10
100
1000
0
10 20 30 40 50 60 70 80
TIME (ns)
FREQUENCY (MHz)
Figure 11. PSRR vs Frequency
Figure 12. Channel Switching
Copyright © 2004–2018, Texas Instruments Incorporated
9
LMH6574
ZHCSIM9E –NOVEMBER 2004–REVISED AUGUST 2018
www.ti.com.cn
Typical Characteristics (continued)
VS = ±5 V, RL = 100 Ω, AV = 2, RF = RG = 575 Ω, unless otherwise specified.
0.5
0.5
0.25
0
V
A
= 0V
= 2
IN
0.25
V
V
OUT
0
-0.25
-0.5
V
OUT
-0.25
-0.5
-0.75
3
2
1
0
6
4
2
0
SHUTDOWN
SHUTDOWN
0
10 20 30 40 50 60 70 80
TIME (ns)
0
20 40 60 80 100 120 140 160
TIME (ns)
Figure 13. SHUTDOWN Switching
Figure 14. Shutdown Glitch
0.5
0.5
0.25
0
V
A
= 0V
= 2
IN
0.25
0
V
V
OUT
V
OUT
-0.25
-0.5
-0.25
-0.5
3
2
1
0
6
4
2
0
ENABLE
ENABLE
0
10 20 30 40 50 60 70 80
TIME (ns)
0
20 40 60 80 100 120 140 160
TIME (ns)
Figure 15. ENABLE Switching
Figure 16. Disable Glitch
-40
-50
-40
-50
V
= 2 V
PP
V
= 2 V
OUT
OUT
PP
CH3
-60
-70
-80
-60
-70
-80
CH2
HD3 ALL CHANNELS
CH0
CH1
-90
-90
-100
-100
10
FREQUENCY (MHz)
100
10
FREQUENCY (MHz)
100
1
1
Figure 17. HD2 vs Frequency
Figure 18. HD3 vs Frequency
10
Copyright © 2004–2018, Texas Instruments Incorporated
LMH6574
www.ti.com.cn
ZHCSIM9E –NOVEMBER 2004–REVISED AUGUST 2018
Typical Characteristics (continued)
VS = ±5 V, RL = 100 Ω, AV = 2, RF = RG = 575 Ω, unless otherwise specified.
-60
-60
CH3
CH2
f = 5 MHz
-65
-70
-75
-80
-85
-90
-95
-100
-65
-70
-75
-80
-85
-90
-95
-100
V
=
2 V
PP
OUT
CH3
CH1
CH1
CH0
f = 5 MHz
CH2
CH0
V
=
2 V
OUT
PP
11
11
5
0
0
6
7
9
10
12
5
6
7
9
10
12
8
8
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 19. HD2 vs VS
Figure 20. HD3 vs VS
-40
-50
-30
-40
-50
-60
-70
-80
-90
f = 5 MHz
f = 5 MHz
CH3
CH2
-60
-70
-80
CH0
CH1
-90
-100
-100
6
7
6
7
1
2
4
5
8
0
1
2
4
5
8
3
3
OUTPUT VOLTAGE (V
PP
)
OUTPUT VOLTAGE (V
)
PP
Figure 21. HD2 vs VOUT
Figure 22. HD3 vs VOUT
4
-2.4
-2.6
-2.8
3.8
3.6
3.4
3.2
3
-3
-3.2
-3.4
-3.6
-3.8
-4
2.8
20
40
60
80
100
-100
-80
-60
-40
-20
0
OUTPUT CURRENT (mA)
OUTPUT CURRENT (mA)
Positive Value is current into device
Positive Value is current into device
Figure 23. Minimum VOUT vs IOUT
Figure 24. Maximum VOUT vs IOUT
Copyright © 2004–2018, Texas Instruments Incorporated
11
LMH6574
ZHCSIM9E –NOVEMBER 2004–REVISED AUGUST 2018
www.ti.com.cn
Typical Characteristics (continued)
VS = ±5 V, RL = 100 Ω, AV = 2, RF = RG = 575 Ω, unless otherwise specified.
-30
-30
-40
UNSELECTED INPUT TO
SELECTED INPUT TO OUTPUT
-40
OUTPUT, V = ±5V
V = 2 V
IN PP
S
-50
-60
-50
-60
DISABLE
-70
-70
-80
-80
SHUTDOWN
-90
-90
-100
-100
-110
-110
10
FREQUENCY (MHz)
100
0.01
0.1
1
1000
0.01
0.1
1
10
100
FREQUENCY (MHz)
Figure 25. Crosstalk vs Frequency
Figure 26. Off Isolation
12
Copyright © 2004–2018, Texas Instruments Incorporated
LMH6574
www.ti.com.cn
ZHCSIM9E –NOVEMBER 2004–REVISED AUGUST 2018
7 Detailed Description
7.1 Functional Block Diagram
+
V
A0
14
R
T
8
9
IN 0
1
A1
R
IN0
R
T
IN 1
IN 2
IN 3
V
OUT
3
5
+
-
13
12
R
IN1
R
IN2
R
IN3
R
OUT
R
F
R
G
SD
11
10
R
T
7
EN
2, 4
6
R
T
-
V
7.2 Feature Description
7.2.1 Video Performance
The LMH6574 has been designed to provide excellent performance with production quality video signals in a
wide variety of formats such as HDTV and High Resolution VGA. Best performance will be obtained with back-
terminated loads. The back termination reduces reflections from the transmission line and effectively masks
transmission line and other parasitic capacitances from the amplifier output stage. The Functional Block Diagram
shows a typical configuration for driving a 75Ω cable. The output buffer is configured for a gain of 2, so using
back terminated loads will give a net gain of 1.
7.2.2 Feedback Resistor Selection
1600
1400
1200
1000
800
600
400
200
0
1
2
3
4
5
6
7
8
9
10
GAIN (V/V)
Figure 27. Suggested RF vs Gain
Copyright © 2004–2018, Texas Instruments Incorporated
13
LMH6574
ZHCSIM9E –NOVEMBER 2004–REVISED AUGUST 2018
www.ti.com.cn
Feature Description (continued)
The LMH6574 has a current feedback output buffer with gain determined by external feedback (RF) and gain set
(RG) resistors. With current feedback amplifiers, the closed loop frequency response is a function of RF. For a
gain of 2 V/V, the recommended value of RF is 575Ω. For other gains see Figure 27. Generally, lowering RF from
the recommended value will peak the frequency response and extend the bandwidth while increasing the value
of RF will cause the frequency response to roll off faster. Reducing the value of RF too far below the
recommended value will cause overshoot, ringing and, eventually, oscillation.
Since all applications are slightly different it is worth some experimentation to find the optimal RF for a given
circuit. For more information see Current Feedback Loop Gain Analysis and Performance Enhancement,
Application Note OA-13 (SNOA366), which describes the relationship between RF and closed-loop frequency
response for current feedback operational amplifiers. The impedance looking into pin 12 is approximately 20Ω.
This allows for good bandwidth at gains up to 10 V/V. When used with gains over 10 V/V, the LMH6574 will
exhibit a “gain bandwidth product” similar to a typical voltage feedback amplifier. For gains of over 10 V/V
consider selecting a high performance video amplifier like the LMH6720 (SNOSA39) to provide additional gain.
7.2.3 Other Applications
The LMH6574 could support a multi antenna receiver with up to four separate antennas. Monitoring the signal
strength of all 4 antennas and connecting the strongest signal to the final IF stage would provide effective spacial
diversity.
For direction finding, the LMH6574 could be used to provide high speed sampling of four separate antennas to a
single DSP which would use the information to calculate the direction of the received signal.
14
Copyright © 2004–2018, Texas Instruments Incorporated
LMH6574
www.ti.com.cn
ZHCSIM9E –NOVEMBER 2004–REVISED AUGUST 2018
Feature Description (continued)
7.2.4 Driving Capacitive Loads
Capacitive output loading applications will benefit from the use of a series output resistor ROUT. Figure 28 shows
the use of a series output resistor, ROUT, to stabilize the amplifier output under capacitive loading. Capacitive
loads of 5 to 120 pF are the most critical, causing ringing, frequency response peaking and possible oscillation.
Figure 29 provides a recommended value for selecting a series output resistor for mitigating capacitive loads.
The values suggested in the charts are selected for 0.5 dB or less of peaking in the frequency response. This
gives a good compromise between settling time and bandwidth. For applications where maximum frequency
response is needed and some peaking is tolerable, the value of ROUT can be reduced slightly from the
recommended values.
R
OUT
V
OUT
45W
C
R
L
L
LMH6574
10 pF
1 kW
Figure 28. Decoupling Capacitive Loads
90
80
70
60
50
40
30
20
2
V
= ±5V
C
= 8.6 pF, R
= 63W
S
L
OUT
LOAD = 1 kW || C
L
0
C
C
= 18 pF, R
= 56 pF, R
= 48W
= 24W
L
L
L
OUT
-2
OUT
-4
-6
C
= 100 pF, R = 19W
OUT
V
= 1 V
PP
OUT
C
|| 1 kW
L
S
V
-8
V
A
= ±5V
= 2 (V/V)
10
0
-10
1
10
100
1000
1
10
100
1000
CAPACTIVE LOAD (pF)
FREQUENCY (MHz)
Figure 29. Suggested ROUT vs Capacitive Load
Figure 30. Frequency Response vs Capacitive Load
7.2.5 ESD Protection
The LMH6574 is protected against electrostatic discharge (ESD) on all pins. The LMH6574 will survive 2000-V
Human Body model and 200-V Machine model events. Under normal operation the ESD diodes have no effect
on circuit performance. There are occasions, however, when the ESD diodes will be evident. If the LMH6574 is
driven by a large signal while the device is powered down the ESD diodes will conduct . The current that flows
through the ESD diodes will either exit the chip through the supply pins or will flow through the device, hence it is
possible to power up a chip with a large signal applied to the input pins. Using the shutdown mode is one way to
conserve power and still prevent unexpected operation.
Copyright © 2004–2018, Texas Instruments Incorporated
15
LMH6574
ZHCSIM9E –NOVEMBER 2004–REVISED AUGUST 2018
www.ti.com.cn
7.3 Device Functional Modes
7.3.1 SD vs EN
The LMH6574 has both shutdown and disable capability. The shutdown feature affects the entire chip, whereas
the disable function only affects the output buffer. When in shutdown mode, minimal power is consumed. The
shutdown function is very fast, but causes a very brief spike of about 400 mV to appear on the output. When in
shutdown mode the LMH6574 consumes only 1.8 mA of supply current. For maximum input to output isolation
use the shutdown function.
The EN pin only disables the output buffer which results in a substantially reduced output glitch of only 50 mV.
While disabled the chip consumes 4.7 mA, considerably more than when shutdown. This is because the input
buffers are still active. For minimal output glitch use the EN pin. Also, care should be taken to ensure that, while
in the disabled state, the voltage differential between the active input buffer (the one selected by pins A0 and A1)
and the output pin stays less than 2V. As the voltage differential increases, input to output isolation decreases.
Normally this is not an issue. See Multiplexer Expansion for further details.
To reduce the output glitch when using the SD pin, switch the EN pin at least 10 ns before switching the SD pin.
This can be accomplished by using an RC delay circuit between the two pins if only one control signal is
available.
Logic inputs "SD" and "EN" will revert to the "High", while "A0" and "A1" will revert to the "Low" state when left
floating.
16
Copyright © 2004–2018, Texas Instruments Incorporated
LMH6574
www.ti.com.cn
ZHCSIM9E –NOVEMBER 2004–REVISED AUGUST 2018
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMH6574 is a high-speed 4:1 analog multiplexer, optimized for very high speed and low distortion. With
selectable gain and excellent AC performance, the LMH6574 is ideally suited for switching high resolution,
presentation grade video signals. The LMH6574 has no internal ground reference. Single or split supply
configurations are both possible. The LMH6574 features very high speed channel switching and disable times.
When disabled the LMH6574 output is high impedance making MUX expansion possible by combining multiple
devices. See Multiplexer Expansion.
8.1.1 Multiplexer Expansion
It is possible to use multiple LMH6574 devices to expand the number of inputs that can be selected for output.
Figure 31 shows an 8:1 MUX using two LMH6574 devices.
Figure 31. 8:1 MUX Using Two LMH6574 Devices
Copyright © 2004–2018, Texas Instruments Incorporated
17
LMH6574
ZHCSIM9E –NOVEMBER 2004–REVISED AUGUST 2018
www.ti.com.cn
Application Information (continued)
In such an application, the output settling may be longer than the LMH6574 switching specifications (~20ns),
while switching between two separate LMH6574 devices. The switching time limiting factor occurs when one
LMH6574 is turned off and another one is turned on, using the SD (shutdown) pin. The output settling time
consists of the time needed for the first LMH6574 to enter high impedance state plus the time required for the
second LMH6574 output to dissipate the left-over output charge of the first device (limited by the output current
capability of the second device) and the time needed to settle to the final voltage value.
While Figure 31 MUX expansion benefits from more isolation, originating from the parasitic loading of the un-
selected channels on the selected channel, afforded by individual ROUT on each multiplexer output, this
configuration does not produce the fastest transition between individual LMH6574 devices. For the fastest
transition, the configuration of Figure 32 can be used where the LMH6574 output pins are all shorted together.
Figure 32. Alternate 8:1 MUX Expansion Schematic (for Faster SD Switching)
18
Copyright © 2004–2018, Texas Instruments Incorporated
LMH6574
www.ti.com.cn
ZHCSIM9E –NOVEMBER 2004–REVISED AUGUST 2018
Application Information (continued)
Figure 33 shows typical transition waveforms and shows that SD pin switching settles in less than 145 ns.
4.5
4
1.5
145 ns
1
3.5
3
0.5
SD_MUX1
2.5
2
SD_MUX2
OUT
0
1.5
1
-0.5
Settled final value
0.5
0
-1
-0.5
-1.5
-1E-07
-5E-08
0
5E-08
0.0000001
1.5E-07
0.0000002
2.5E-07
Time (50 ns/div)
Figure 33. SD Pin Switching Waveform and Output Settling
If it is important in the end application to make sure that no two inputs are presented to the output at the same
time, an optional delay block can be added, to drive the SHUTDOWN pin of each device. Figure 34 shows one
possible approach to this delay circuit. The delay circuit shown will delay SHUTDOWN's H to L transitions (R1
and C1 decay) but will not delay its L to H transition. R2 should be kept small compared to R1 in order to not
reduce the SHUTDOWN voltage and to produce little or no delay to SHUTDOWN.
D
1
R
2
TO SD
C
R
1
1
Figure 34. Delay Circuit Implementation
Copyright © 2004–2018, Texas Instruments Incorporated
19
LMH6574
ZHCSIM9E –NOVEMBER 2004–REVISED AUGUST 2018
www.ti.com.cn
Application Information (continued)
With the SHUTDOWN pin putting the output stage into a high impedance state, several LMH6574’s can be tied
together to form a larger input MUX. However, there is a loading effect on the active output caused by the
unselected devices. The circuit in Figure 35 shows how to compensate for this effect. For the 16:1 MUX function
shown in Figure 35, the gain error would be about −0.8 dB, or about 9%. In the circuit in Figure 35, resistor ratios
have been adjusted to compensate for this gain error. By adjusting the gain of each multiplexer circuit the error
can be reduced to the tolerance of the resistors used (1% in this example).
Figure 35. Multiplexer Gain Compensation
NOTE
Disabling of the LMH6574 using the EN pin is not recommended for use when doing
multiplexer expansion. While disabled, If the voltage between the selected input and the
chip output exceeds approximately 2V the device will begin to enter a soft breakdown
state. This will show up as reduced input to output isolation. The signal on the non-
inverting input of the output driver amplifier will leak through to the inverting input, and
then to the output through the feedback resistor. The worst case is a gain of 1
configuration where the non inverting input follows the active input buffer and (through the
feedback resistor) the inverting input follows the voltage driving the output stage. The
solution for this is to use shutdown mode for multiplexer expansion.
20
Copyright © 2004–2018, Texas Instruments Incorporated
LMH6574
www.ti.com.cn
ZHCSIM9E –NOVEMBER 2004–REVISED AUGUST 2018
9 Power Supply Recommendations
9.1 Power Dissipation
The LMH6574 is optimized for maximum speed and performance in the small form factor of the standard SOIC
package. To ensure maximum output drive and highest performance, thermal shutdown is not provided.
Therefore, it is of utmost importance to make sure that the TJMAX is never exceeded due to the overall power
dissipation.
Follow these steps to determine the Maximum power dissipation for the LMH6574:
1. Calculate the quiescent (no-load) power.
PAMP = ICC* (VS)
where
•
VS = V+ - V−
(1)
2. Calculate the RMS power dissipated in the output stage:
PD (rms) = rms ((VS - VOUT) * IOUT
)
where
•
•
•
VOUT is the voltage across the external load
IOUT is the current through the external load
VS is the total supply voltage
(2)
3. Calculate the total RMS power: PT = PAMP + PD.
The maximum power that the LMH6574 package can dissipate at a given temperature can be derived with the
following equation:
PMAX = (150° – TAMB)/RθJA
where
•
•
TAMB = Ambient temperature (°C)
θJA = Thermal resistance, from junction to ambient, for a given package (°C/W)
R
(3)
For the SOIC package RθJA is 130 °C/W.
10 Layout
10.1 Layout Guidelines
Whenever questions about layout arise, use the evaluation board LMH730276 as a guide. To reduce parasitic
capacitances, ground and power planes should be removed near the input and output pins. For long signal paths
controlled impedance lines should be used, along with impedance matching elements at both ends. Bypass
capacitors should be placed as close to the device as possible. Bypass capacitors from each rail to ground are
applied in pairs. The larger electrolytic bypass capacitors can be located farther from the device, the smaller
ceramic capacitors should be placed as close to the device as possible. In the Functional Block Diagram, the
capacitor between V+ and V− is optional, but is recommended for best second harmonic distortion. Another way
to enhance performance is to use pairs of 0.01 μF and 0.1 μF ceramic capacitors for each supply bypass.
版权 © 2004–2018, Texas Instruments Incorporated
21
LMH6574
ZHCSIM9E –NOVEMBER 2004–REVISED AUGUST 2018
www.ti.com.cn
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档
更多信息，请参见以下文档：
•
•
•
《OA-13 电流反馈环路增益分析和性能增强》 应用手册
《IC 封装热指标》 应用报告
《LMH730276 4:1 多路复用器评估板》
11.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.6 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。
22
版权 © 2004–2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH6574MA
NRND
SOIC
SOIC
SOIC
D
D
D
14
14
14
55
Non-RoHS
& Green
Call TI
Level-1-235C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
LMH65
74MA
LMH6574MA/NOPB
LMH6574MAX/NOPB
ACTIVE
ACTIVE
55
RoHS & Green
SN
SN
LMH65
74MA
2500 RoHS & Green
LMH65
74MA
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Sep-2021
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH6574MAX/NOPB
SOIC
D
14
2500
330.0
16.4
6.5
9.35
2.3
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC 14
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
LMH6574MAX/NOPB
D
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Jul-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMH6574MA
LMH6574MA
D
D
D
D
SOIC
SOIC
SOIC
SOIC
14
14
14
14
55
55
55
55
495
495
495
495
8
8
8
8
4064
4064
4064
4064
3.05
3.05
3.05
3.05
LMH6574MA/NOPB
LMH6574MA/NOPB
Pack Materials-Page 3
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
相关型号：
©2020 ICPDF网 联系我们和版权申明