LMH6611MKX [TI]
Single Supply 345 MHz Rail-to-Rail Output Amplifiers; 单电源345 MHz轨到轨输出放大器
| 型号： | LMH6611MKX |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Single Supply 345 MHz Rail-to-Rail Output Amplifiers |
| 文件： | 总32页 (文件大小：1363K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMH6611,LMH6612
LMH6611/LMH6612 Single Supply 345 MHz Rail-to-Rail Output Amplifiers
Literature Number: SNOSB00H
January 26, 2010
LMH6611/LMH6612
Single Supply 345 MHz Rail-to-Rail Output Amplifiers
General Description
Features
The LMH6611 (single, with shutdown) and LMH6612 (dual)
are 345 MHz rail-to-rail output amplifiers consuming just 3.2
mA of quiescent current per channel and designed to deliver
high performance in power conscious single supply systems.
The LMH6611 and LMH6612 have precision trimmed input
offset voltages with low noise and low distortion performance
as required for high accuracy video, test and measurement,
and communication applications. The LMH6611 and
LMH6612 are members of the PowerWise family and have an
exceptional power-to-performance ratio.
VS = 5V, RL = 1 kΩ, TA = 25°C and AV = +1, unless otherwise
specified.
Operating voltage range
Supply current per channel
Small signal bandwidth
Open loop gain
Input offset voltage (limit at 25°C)
Slew rate
2.7V to 11V
3.2 mA
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■
■
■
■
■
■
■
■
■
■
■
■
■
■
345 MHz
103 dB
±0.750 mV
460 V/µs
45 MHz
0.1 dB bandwidth
Settling time to 0.1%
Settling time to 0.01%
SFDR (f = 100 kHz, AV = 2, VOUT = 2 VPP
Low voltage noise
Output current
CMVR
67 ns
100 ns
With a trimmed input offset voltage of 0.022 mV and a high
open loop gain of 103 dB the LMH6611 and LMH6612 meet
the requirements of DC sensitive high speed applications
such as low pass filtering in baseband I and Q radio channels.
These specifications combined with a 0.01% settling time of
)
102 dBc
10 nV/√Hz
±100 mA
−0.2V to 3.8V
100 ns, a low noise of 10 nV/
and better than 102 dBc
SFDR at 100 kHz make these amplifiers particularly suited to
driving 10, 12 and 14-bit high speed ADCs. The 45 MHz 0.1
dB bandwidth (AV = 2) driving 2 VPP into 150Ω allows the am-
plifiers to be used as output drivers in 1080i and 720p HDTV
applications.
Rail-to-Rail output
−40°C to +125°C temperature range
Applications
ADC driver
■
■
■
■
■
■
■
■
The input common mode range extends from 200 mV below
the negative supply rail up to 1.2V from the positive rail. On a
single 5V supply with a ground terminated 150Ω load the out-
put swings to within 49 mV of the ground, while a mid-rail
terminated 1 kΩ load will swing to 77 mV of either rail.
The amplifiers will operate on a 2.7V to 11V single supply or
±1.35V to ±5.5V split supply. The LMH6611 single is available
in 6-Pin TSOT23 and has an independent active low disable
pin which reduces the supply current to 120 µA. The
LMH6612 is available in 8-Pin SOIC. Both the LMH6611 and
LMH6612 are available in −40°C to +125°C extended indus-
trial temperature grade.
DAC buffer
Active filters
High speed sensor amplifier
Current sense amplifier
1080i and 720p analog video amplifier
STB, TV video amplifier
Video switching and muxing
Typical Application
30033629
WEBENCH® is a registered trademark of National Semiconductor Corporation.
© 2010 National Semiconductor Corporation
300336
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Supply Voltage (VS = V+ – V−)
12V
150°C max
Absolute Maximum Ratings (Note 1)
Junction Temperature (Note 3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Operating Ratings (Note 1)
Supply Voltage (VS = V+ – V−)
2.7V to 11V
ESD Tolerance (Note 2)
Ambient Temperature Range (Note 3)
−40°C to +125°C
Human Body Model
Package Thermal Resistance (θJA
6-Pin TSOT23
8-Pin SOIC
)
For input pins only
For all other pins
Machine Model
2000V
2000V
200V
231°C/W
160°C/W
Charge Device Model
1000V
+3V Electrical Characteristics
Unless otherwise specified, all limits are guaranteed for TJ = +25°C, V+ = 3V, V− = 0V, VS = V+ – V−, DISABLE = 3V, VCM = VO
=
V+/2, AV = +1, RF = 0Ω, when AV ≠ +1 then RF = 560Ω, RL = 1 kΩ. Boldface limits apply at temperature extremes. (Note 4)
Symbol
Parameter
Condition
Min
Typ
Max
Units
(Note 8) (Note 7) (Note 8)
Frequency Domain Response
SSBW
GBW
–3 dB Bandwidth Small Signal
305
115
AV = 1, RL = 1 kΩ, VOUT = 0.2 VPP
MHz
MHz
AV = 2, −1, RL = 1 kΩ, VOUT = 0.2 VPP
Gain Bandwidth
(LMH6611)
115
135
AV = 10, RF = 2 kΩ, RG = 221Ω, RL = 1 kΩ,
VOUT = 0.2 VPP
Gain Bandwidth
(LMH6612)
130
AV = 10, RF = 2 kΩ, RG = 221Ω, RL = 1 kΩ,
VOUT = 0.2 VPP
LSBW
Peak
−3 dB Bandwidth Large Signal
90
85
1.0
33
65
AV = 1, RL = 1 kΩ, VOUT = 1.5 VPP
AV = −1, RL = 150Ω, VOUT = 2 VPP
AV = 1
MHz
dB
Peaking
0.1
dBBW
0.1 dB Bandwidth
AV = 1, VOUT = 0.5 VPP, RL = 1 kΩ
AV = 2, VOUT = 0.5 VPP, RL = 1 kΩ
RF = RG = 560Ω
MHz
47
AV = 2, VOUT = 1.5 VPP, RL = 150Ω,
RF = RG = 510Ω
DG
DP
Differential Gain
AV = 2, 4.43 MHz, 0.6V < VOUT < 2V,
RL = 150Ω to V+/2
0.03
0.06
%
Differential Phase
AV = 2, 4.43 MHz, 0.6V < VOUT < 2V,
RL = 150Ω to V+/2
deg
Time Domain Response
tr/tf
Rise & Fall Time
Slew Rate
1.5V Step, AV = 1
2V Step, AV = 1
2V Step, AV = −1
2V Step, AV = −1
2.8
330
74
ns
SR
V/μs
ts_0.1
ts_0.01
0.1% Settling Time
0.01% Settling Time
ns
116
Noise and Distortion Performance
SFDR
Spurious Free Dynamic Range
fC = 100 kHz, AV = −1, VOUT= 2 VPP
fC = 1 MHz, AV = −1, VOUT = 2 VPP
fC = 5 MHz, AV = −1, VOUT = 2 VPP
f = 100 kHz
109
97
dBc
80
en
in
Input Voltage Noise
Input Current Noise
10
nV/
pA/
dB
f = 100 kHz
2
CT
Crosstalk
f = 5 MHz, VIN = 2 VPP
71
(LMH6612)
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2
Symbol
Parameter
Condition
Min
Typ
Max
Units
(Note 8) (Note 7) (Note 8)
Input, DC Performance
VOS
Input Offset Voltage
(LMH6611)
VCM = 0.5V
VCM = 0.5V
0.022
±0.600
±1.0
mV
Input Offset Voltage
(LMH6612)
−0.015
±0.750
±1.3
TCVOS
IB
Input Offset Voltage Average Drift (Note 5)
0.1
μV/°C
μA
Input Bias Current
VCM = 0.5V
−5.9
−10.1
−11.1
IO
Input Offset Current
0.01
±0.5
±0.7
μA
CIN
Input Capacitance
Input Resistance
2.5
6
pF
RIN
MΩ
CMVR
CMRR
AOL
Input Voltage Range
−0.2
79
1.8
V
DC, CMRR ≥ 76 dB
Common Mode Rejection Ratio VCM Stepped from −0.1V to 1.7V
98
101
85
dB
Open Loop Gain
89
RL = 1 kΩ, VOUT = 2.7V to 0.3V
RL = 150Ω, VOUT = 2.5V to 0.5V
dB
78
Output DC Characteristics
RL = 1 kΩ to V+/2
RL = 150Ω to V+/2
RL = 1 kΩ to V+/2
RL = 150Ω to V+/2
RL = 150Ω to V−
RL = 1 kΩ to V+/2
RL = 150Ω to V+/2
RL = 1 kΩ to V+/2
RL = 150Ω to V+/2
RL = 150Ω to V−
VO
Output Swing High (LMH6611)
(Voltage from V+ Supply Rail)
59
133
59
72
76
169
182
Output Swing Low (LMH6611)
(Voltage from V− Supply Rail)
74
80
133
42
171
188
52
56
mV
Output Swing High (LMH6612)
(Voltage from V+ Supply Rail)
58
68
73
131
61
157
172
Output Swing Low (LMH6612)
(Voltage from V− Supply Rail)
71
79
139
43
168
187
51
56
IOUT
RO
Linear Output Current
Output Resistance
VOUT = V+/2 (Note 6)
±70
mA
f = 1 MHz
0.07
Ω
Enable Pin Operation
Enable High Voltage Threshold Enabled (Note 9)
2.0
V
µA
V
Enable Pin High Current
VDISABLE = 3V
Disabled (Note 9)
VDISABLE = 0V
0.001
Enable Low Voltage Threshold
Enable Pin Low Current
Turn-On Time
1.0
0.8
18
50
µA
ns
ns
ton
toff
Turn-Off Time
3
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Symbol
Parameter
Condition
Min
Typ
Max
Units
(Note 8) (Note 7) (Note 8)
Power Supply Performance
PSRR
IS
Power Supply Rejection Ratio
DC, VCM = 0.5V, VS = 2.7V to 11V
81
96
dB
mA
μA
Supply Current (LMH6611)
3.0
3.4
3.8
RL = ∞
Supply Current (LMH6612)
(per channel)
2.95
101
3.45
3.9
RL = ∞
ISD
Disable Shutdown Current
(LMH6611)
DISABLE = 0V
132
+5V Electrical Characteristics
Unless otherwise specified, all limits are guaranteed for TJ = +25°C, V+ = 5V, V− = 0V, VS = V+ – V−, DISABLE = 5V, VCM = VO
=
V+/2, AV = +1, RF = 0Ω, when AV ≠ +1 then RF = 560Ω, RL = 1 kΩ. Boldface limits apply at temperature extremes.
Symbol
Parameter
Condition
Min
Typ
Max
Units
(Note 8) (Note 7) (Note 8)
Frequency Domain Response
SSBW
GBW
–3 dB Bandwidth Small Signal
345
112
AV = 1, RL = 1 kΩ, VOUT = 0.2 VPP
MHz
MHz
AV = 2, −1, RL = 1 kΩ, VOUT = 0.2 VPP
Gain Bandwidth
(LMH6611)
115
135
AV = 10, RF = 2 kΩ, RG = 221Ω, RL = 1 kΩ,
VOUT = 0.2 VPP
Gain Bandwidth
(LMH6612)
130
AV = 10, RF = 2 kΩ, RG = 221Ω, RL = 1 kΩ,
VOUT = 0.2 VPP
LSBW
Peak
−3 dB Bandwidth Large Signal
77
85
0.3
45
68
AV = 1, RL = 1 kΩ, VOUT = 2 VPP
AV = 2, RL = 150Ω, VOUT = 2 VPP
AV = 1
MHz
dB
Peaking
0.1
dBBW
0.1 dB Bandwidth
AV = 1, VOUT = 0.5 VPP, RL = 1 kΩ
AV = 2, VOUT = 0.5 VPP, RL = 1 kΩ
RF = RG = 680Ω
MHz
45
AV = 2, VOUT = 2 VPP, RL = 150Ω,
RF = RG = 665Ω
DG
DP
Differential Gain
AV = 2, 4.43 MHz, 0.6V < VOUT < 2V,
RL = 150Ω to V+/2
0.05
0.06
%
Differential Phase
AV = 2, 4.43 MHz, 0.6V < VOUT < 2V,
RL = 150Ω to V+/2
deg
Time Domain Response
tr/tf
Rise & Fall Time
Slew Rate
2V Step, AV = 1
2V Step, AV = 1
2V Step, AV = −1
2V Step, AV = −1
3.6
460
67
ns
SR
V/μs
ts_0.1
ts_0.01
0.1% Settling Time
0.01% Settling Time
ns
100
Distortion and Noise Performance
SFDR
Spurious Free Dynamic Range fC = 100 kHz, AV = 2, VOUT = 2 VPP
fC = 1 MHz, AV = 2, VOUT = 2 VPP
102
96
dBc
fC = 5 MHz, AV = 2, VO = 2 VPP
82
en
in
Input Voltage Noise
Input Current Noise
f = 100 kHz
10
nV/
pA/
dB
f = 100 kHz
2
CT
Crosstalk
f = 5 MHz, VIN = 2 VPP
71
(LMH6612)
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4
Symbol
Parameter
Condition
Min
Typ
Max
Units
(Note 8) (Note 7) (Note 8)
Input, DC Performance
VOS
Input Offset Voltage
(LMH6611)
VCM = 0.5V
VCM = 0.5V
(Note 5)
0.013
0.022
0.1
±0.600
±1.0
mV
µV/°C
μA
Input Offset Voltage
(LMH6612)
±0.750
±1.3
TCVOS
Input Offset Voltage Average
Drift
IB
Input Bias Current
VCM = 0.5V
−6.3
0.01
−10.1
−11.1
IO
Input Offset Current
±0.5
±0.7
μA
CIN
Input Capacitance
Input Resistance
2.5
6
pF
RIN
MΩ
CMVR
CMRR
AOL
Input Voltage Range
−0.2
81
3.8
V
DC, CMRR ≥ 78 dB
Common Mode Rejection Ratio VCM Stepped from −0.1V to 3.7V
98
103
86
dB
Open Loop Gain
92
RL = 1 kΩ, VOUT = 4.6V to 0.4V
RL = 150Ω, VOUT = 4.4V to 0.6V
dB
80
Output DC Characteristics
RL = 1 kΩ to V+/2
RL =150Ω to V+/2
RL = 1 kΩ to V+/2
RL =150Ω to V+/2
RL = 150Ω to V−
RL = 1 kΩ to V+/2
RL =150Ω to V+/2
RL = 1 kΩ to V+/2
RL =150Ω to V+/2
RL = 150Ω to V−
VO
Output Swing High (LMH6611)
(Voltage from V+ Supply Rail)
76
195
74
90
93
239
256
Output Swing Low (LMH6611)
(Voltage from V− Supply Rail)
92
98
193
48
243
265
60
64
mV
Output Swing High (LMH6612)
(Voltage from V+ Supply Rail)
75
86
91
195
77
223
241
Output Swing Low (LMH6612)
(Voltage from V− Supply Rail)
88
98
202
49
234
261
58
64
IOUT
RO
Linear Output Current
Output Resistance
VOUT = V+/2 (Note 6)
±100
0.07
mA
f = 1 MHz
Ω
Enable Pin Operation
Enable High Voltage Threshold Enabled (Note 9)
Enable Pin High Current VDISABLE = 5V
Enable Low Voltage Threshold Disabled (Note 9)
3.0
V
µA
V
1.2
2.0
Enable Pin Low Current
Turn-On Time
VDISABLE = 0V
2.8
20
60
µA
ns
ns
ton
toff
Turn-Off Time
5
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Symbol
Parameter
Condition
Min
Typ
Max
Units
(Note 8) (Note 7) (Note 8)
Power Supply Performance
PSRR
IS
Power Supply Rejection Ratio
DC, VCM = 0.5V, VS = 2.7V to 11V
81
96
dB
mA
μA
Supply Current (LMH6611)
3.2
3.6
4.0
RL = ∞
Supply Current (LMH6612)
(per channel)
3.2
3.7
4.25
RL = ∞
ISD
Disable Shutdown Current
(LMH6611)
DISABLE = 0V
120
162
±5V Electrical Characteristics
Unless otherwise specified, all limits are guaranteed for TJ = +25°C, V+ = 5V, V− = −5V, VS = V+ – V−, DISABLE = 5V, VCM = VO
=
0V, AV = +1, RF = 0Ω, when AV ≠ +1 then RF = 560Ω, RL = 1 kΩ. Boldface limits apply at temperature extremes.
Symbol
Parameter
Condition
Min
Typ
Max
Units
(Note 8) (Note 7) (Note 8)
Frequency Domain Response
SSBW
GBW
–3 dB Bandwidth Small Signal
365
110
AV = 1, RL = 1 kΩ, VOUT = 0.2 VPP
MHz
MHz
AV = 2, −1, RL = 1 kΩ, VOUT = 0.2 VPP
Gain Bandwidth
(LMH6611)
115
135
AV = 10, RF = 2 kΩ, RG = 221Ω, RL = 1 kΩ,
VOUT = 0.2 VPP
Gain Bandwidth
(LMH6612)
130
AV = 10, RF = 2 kΩ, RG = 221Ω, RL = 1 kΩ,
VOUT = 0.2 VPP
LSBW
Peak
−3 dB Bandwidth Large Signal
85
87
AV = 1, RL = 1 kΩ, VOUT = 2 VPP
AV = 2, RL = 150Ω, VOUT = 2 VPP
AV = 1
MHz
dB
Peaking
0.01
92
0.1
dBBW
0.1 dB Bandwidth
AV = 1, VOUT = 0.5 VPP, RL = 1 kΩ
65
AV = 2, VOUT = 0.5 VPP, RL = 1 kΩ
RF = RG = 750Ω
MHz
45
AV = 2, VOUT = 2 VPP, RL = 150Ω,
RF = RG = 680Ω
DG
DP
Differential Gain
AV = 2, 4.43 MHz, 0.6V < VOUT < 2V,
RL = 150Ω to V+/2
0.05
0.05
%
Differential Phase
AV = 2, 4.43 MHz, 0.6V < VOUT < 2V,
RL = 150Ω to V+/2
deg
Time Domain Response
tr/tf
Rise & Fall Time
Slew Rate
2V Step, AV = 1
2V Step, AV = 1
2V Step, AV = −1
2V Step, AV = −1
3.5
460
60
ns
SR
V/μs
ts_0.1
ts_0.01
0.1% Settling Time
0.01% Settling Time
ns
100
Noise and Distortion Performance
SFDR
Spurious Free Dynamic Range fC = 100 kHz, AV = 2, VOUT = 2 VPP
fC = 1 MHz, AV = 2, VOUT = 2 VPP
102
100
81
dBc
fC = 5 MHz, AV = 2, VOUT = 2 VPP
en
in
Input Voltage Noise
Input Current Noise
f = 100 kHz
10
nV/
pA/
dB
f = 100 kHz
2
CT
Crosstalk
f = 5 MHz, VIN = 2 VPP
71
(LMH6612)
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6
Symbol
Parameter
Condition
Min
Typ
Max
Units
(Note 8) (Note 7) (Note 8)
Input DC Performance
VOS
Input Offset Voltage
(LMH6611)
VCM = −4.5V
VCM = −4.5V
(Note 5)
0.074
0.095
0.4
±0.600
±1.1
mV
µV/°C
μA
Input Offset Voltage
(LMH6612)
±0.750
±1.4
TCVOS
Input Offset Voltage Average
Drift
IB
Input Bias Current
VCM = −4.5V
−6.5
0.01
−10.1
−11.1
IO
Input Offset Current
±0.5
±0.7
μA
CIN
Input Capacitance
Input Resistance
2.5
6
pF
RIN
MΩ
CMVR
CMRR
AOL
Input Voltage Range
−5.2
81
3.8
V
DC, CMRR ≥ 81 dB
Common Mode Rejection Ratio VCM Stepped from −5.1V to 3.7V
98
103
87
dB
Open Loop Gain
96
RL = 1 kΩ, VOUT = +4.6V to −4.6V
RL = 150Ω, VOUT = +4.3V to −4.3V
dB
80
Output DC Characteristics
VO
Output Swing High (LMH6611)
(Voltage from V+ Supply Rail)
107
339
103
332
54
125
130
RL = 1 kΩ to GND
RL = 150Ω to GND
RL = 1 kΩ to GND
RL = 150Ω to GND
RL = 150Ω to V−
402
433
Output Swing Low (LMH6611)
(Voltage from V− Supply Rail)
123
132
404
445
70
74
mV
Output Swing High (LMH6612)
(Voltage from V+ Supply Rail)
107
340
108
348
56
118
125
RL = 1 kΩ to GND
RL = 150Ω to GND
RL = 1 kΩ to GND
RL = 150Ω to GND
RL = 150Ω to V−
375
407
Output Swing Low (LMH6612)
(Voltage from V− Supply Rail)
120
135
389
434
66
74
IOUT
RO
Linear Output Current
Output Resistance
VOUT = GND (Note 6)
±120
0.07
mA
f = 1 MHz
Ω
Enable Pin Operation
Enable High Voltage Threshold Enabled (Note 9)
Enable Pin High Current VDISABLE = +5V
Enable Low Voltage Threshold Disabled (Note 9)
0.5
V
µA
V
17.0
−0.5
Enable Pin Low Current
Turn-On Time
VDISABLE = −5V
18.6
19
µA
ns
ns
ton
toff
Turn-Off Time
60
7
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Symbol
Parameter
Condition
Min
Typ
Max
Units
(Note 8) (Note 7) (Note 8)
Power Supply Performance
PSRR
IS
Power Supply Rejection Ratio
DC, VCM = −4.5V, VS = 2.7V to 11V
81
96
dB
mA
μA
Supply Current (LMH6611)
3.3
3.8
4.4
RL = ∞
Supply Current (LMH6612)
(per channel)
3.45
160
4.05
4.85
RL = ∞
ISD
Disable Shutdown Current
(LMH6611)
DISABLE = −5V
212
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics.
Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC)
Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
Note 3: The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX)) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
Note 4: Boldface limits apply to temperature range of −40°C to 125°C
Note 5: Voltage average drift is determined by dividing the change in VOS by temperature change.
Note 6: Do not short circuit the output. Continuous source or sink currents larger than the IOUT typical are not recommended as they may damage the part.
Note 7: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will
also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material.
Note 8: Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlations using the Statistical Quality
Control (SQC) method.
Note 9: This parameter is guaranteed by design and/or characterization and is not tested in production.
Connection Diagrams
6-Pin TSOT23
8-Pin SOIC
30033601
Top View
30033678
Top View
Ordering Information
Package
Part Number
LMH6611MK
LMH6611MKE
LMH6611MKX
LMH6612MA
LMH6612MAX
Package Marking
Transport Media
NSC Drawing
1k Units Tape and Reel
250 Units Tape and Reel
3k Units Tape and Reel
95 Rail/Units
6-Pin TSOT23
AX4A
MK06A
M08A
8-Pin SOIC
LMH6612MA
2.5k Units Tape and Reel
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8
Typical Performance Characteristics At TJ = 25°C, AV = +1 (RF = 0Ω), otherwise RF = 560Ω for
AV ≠ +1, unless otherwise specified.
Closed Loop Frequency Response for
Various Supplies
Closed Loop Frequency Response for
Various Supplies
30033624
30033625
Closed Loop Frequency Response for
Various Supplies
Closed Loop Frequency Response for
Various Supplies (Gain = +2)
30033604
30033605
Closed Loop Gain vs. Frequency for
Various Temperatures
Closed Loop Gain vs. Frequency for
Various Temperatures
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Closed Loop Gain vs. Frequency for
Various Gains
Large Signal Frequency Response
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30033623
Large Signal Frequency Response
±0.1 dB Gain Flatness for Various Supplies
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30033631
±0.1 dB Gain Flatness for Various Supplies
±0.1 dB Gain Flatness for Various Supplies
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±0.1 dB Gain Flatness for Various Supplies
±0.1 dB Gain Flatness for Various Supplies (Gain = +2)
30033675
30033607
Small Signal Frequency Response with
Various Capacitive Load
Small Signal Frequency Response with
Capacitive Load and Various RISO
30033608
30033609
HD2 and HD3 vs. Frequency and Supply Voltage
HD2 and HD3 vs. Frequency and Load
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HD2 and HD3 vs. Common Mode Voltage
HD2 and HD3 vs. Common Mode Voltage
30033677
30033681
HD2 vs. Frequency and Gain
HD3 vs. Frequency and Gain
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30033652
Open Loop Gain and Phase
HD2 vs. Output Swing
30033682
30033676
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HD3 vs. Output Swing
HD2 vs. Output Swing
HD3 vs. Output Swing
HD2 vs. Output Swing
30033683
30033693
HD3 vs. Output Swing
30033694
30033684
Settling Time vs. Input Step Amplitude
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Settling Time vs. Input Step Amplitude
Input Noise vs. Frequency
30033687
30033674
VOS vs. VOUT
VOS vs. VOUT
30033661
30033668
VOS vs. VCM
VOS vs. VS
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VOS vs. IOUT
VOS Distribution
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IB vs. VS
IS vs. VS
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30033659
VOUT vs. VS
VOUT vs. VS
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VOUT vs. VS
Closed Loop Output Impedance vs. Frequency AV = +1
30033696
30033671
Circuit for Positive (+) PSRR Measurement
+PSRR vs. Frequency
30033688
30033633
Circuit for Negative (−) PSRR Measurement
−PSRR vs. Frequency
30033689
30033634
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CMRR vs. Frequency
Small Signal Step Response
Small Signal Step Response
Crosstalk vs. Frequency
Small Signal Step Response
Small Signal Step Response
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30033697
30033610
30033611
30033612
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Small Signal Step Response
Small Signal Step Response
Small Signal Step Response
Small Signal Step Response
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30033616
Small Signal Step Response
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30033618
Large Signal Step Response
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Large Signal Step Response
Overload Recovery Response
30033620
30033621
IS vs. VDISABLE
30033656
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Application Information
The LMH6611 and LMH6612 are based on National
Semiconductor’s proprietary VIP10 dielectrically isolated
bipolar process. This device family architecture features the
following:
•
•
•
•
Complimentary bipolar devices with exceptionally high ft
(∼8 GHz) even under low supply voltage (2.7V) and low
bias current.
Common emitter push-push output stage. This
architecture allows the output to reach within millivolts of
either supply rail.
Consistent performance with little variation from any
supply voltage (2.7V - 11V) for the most important
specifications (e.g. BW, SR, IOUT.)
Significant power saving compared to competitive devices
on the market with similar performance.
30033639
With 3V supplies and a common mode input voltage range
that extends beyond either supply rail, the LMH6611 is well
suited to many low voltage/low power applications. Even with
3V supplies, the −3 dB BW (at AV = +1) is typically 305 MHz.
FIGURE 2. Input Equivalent Circuit During Shutdown
When the LMH6611 is shutdown, there may be current flow
through the internal diodes shown, caused by input potential,
if present. This current may flow through the external feed-
back resistor and result in an apparent output signal. In most
shutdown applications the presence of this output is incon-
sequential. However, if the output is “forced” by another de-
vice, the other device will need to conduct the current
described in order to maintain the output potential.
The LMH6611 and LMH6612 are designed to avoid output
phase reversal. With input overdrive, the output is kept near
the supply rail (or as close to it as mandated by the closed
loop gain setting and the input voltage). Figure 1 shows the
input and output voltage when the input voltage significantly
exceeds the supply voltages.
To keep the output at or near ground during shutdown when
there is no other device to hold the output low, a switch using
a transistor can be used to shunt the output to ground.
SELECTION OF RF AND EFFECT ON STABILITY AND
PEAKING
The peaking of the LMH6611 depends on the value of the
RF. From the graph shown in Figure 3, as the RF value in-
creases, the peaking increases.
For AV = 2, at RF = 1 kΩ, the −3 dB bandwidth is 113 MHz
and peaking is about 0.6 dB whereas at RF = 665Ω, the −3
dB bandwidth is about 110 MHz and peaking is 0 dB. RF and
the input capacitance form a pole in the amplifier’s response.
If the time constant is too big, it will cause peaking and ringing.
Except for AV = 1 when RF should be 0Ω, across all other gain
settings it is recommended that RF remain between 500Ω and
1 kΩ to ensure optimum performance.
30033622
FIGURE 1. Input and Output Shown with CMVR Exceeded
If the input voltage range is exceeded by more than a diode
drop beyond either rail, the internal ESD protection diodes will
start to conduct. The current flow in these ESD diodes should
be externally limited.
SHUTDOWN CAPABILITY AND TURN ON/OFF
BEHAVIOR
The LMH6611 can be shutdown by connecting the
DISABLE pin to a voltage 0.5V below the supply midpoint
which will reduce the supply current to typically 120 µA. The
DISABLE pin is “active low” and can be connected through a
resistor to V+ or left floating for normal operation. Shutdown
is guaranteed when the DISABLE pin is 0.5V below the supply
midpoint at any operating supply voltage and temperature.
Typical turn on time is 20 ns and the turn off time is 60 ns.
In the shutdown mode, essentially all internal device biasing
is turned off in order to minimize supply current flow and the
output goes into high impedance mode. During shutdown, the
input stage has an equivalent circuit as shown in Figure 2.
30033692
FIGURE 3. Closed Loop Gain vs. Frequency and RF = RG
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20
quired to drive the input of the ADC. To minimize the droop in
the input voltage, external shunt capacitance (CL) should be
about ten times larger than the internal input capacitance of
the ADC and external series resistance (RL) should be large
enough to maintain the phase delay at the output of the op
amp and hence maintain the stability (See Figure 4) . Most
applications benefit from the inclusion of a series isolation re-
sistor connected between the op amp output and ADC input.
This series resistor helps to limit the output current of the op
amp. The value chosen for this series resistor is very impor-
tant, as a higher value will increase the load impedance seen
by the op amp and improve the total harmonic distortion
(THD) performance of the op amp; however, the ADC prefers
a low impedance source driving it. Thus, the optimum value
for this series resistor must be found so that it will offer the
best performance in terms of THD, SNR and SFDR of the
combined op amp and ADC.
RF = RG
665
f −3 dB (MHz)
Peaking (dB)
110
113
0
1000
0.6
MINIMIZING NOISE
With a low input voltage noise of 10 nV/
rent noise of 2 pA
and an input cur-
the LMH6611 and LMH6612 are suit-
able for high accuracy applications. Still being able to reduce
the frequency band of operation of the various noise sources
(i.e. op amp noise voltage, resistor thermal noise, input noise
current) can further improve the noise performance of a sys-
tem. In a non-inverting amplifier configuration inserting a
capacitor, CG, in series with the gain setting resistor, RG, will
reduce the gain of the circuit below frequency,
f =
1/2πRGCG. This can be set to reduce the contribution of noise
from the 1/f region. Alternatively applying a feedback capac-
itor, CF, in parallel with the feedback resistor, RF, will introduce
a pole into your system at f = 1/2πRFCF and create a low pass
filter. This filter can be set to reduce high frequency noise and
harmonics. Finally remember to keep resistor values as small
as possible for a given application in order to reduce resistor
thermal noise.
Important Specifications of Op Amp and ADC
When interfacing an ADC with an op amp it is imperative to
understand the specifications that are important to get the
expected performance results. Modern ADC AC specifica-
tions such as THD, SNR, settling time and SFDR are critical
for filtering, test and measurement, video and reconstruction
applications. The high performance op amp’s settling time,
THD, and noise performance must be better than that of the
ADC it is driving to maintain the proper system accuracy with
minimal or no error.
POWER SUPPLY BYPASS
Since the LMH6611 and LMH6612 are wide bandwidth am-
plifiers, proper power supply bypassing is critical for optimum
performance. Improper power supply bypassing can result in
large overshoot, ringing or oscillation. 0.1 μF capacitors
should be connected from the supply pins, V+ and V−, to
ground, as close to the device as is practical. Additionally, a
10 μF electrolytic capacitor should be connected from both
supply pins to ground reasonably close to the device. Finally,
near the device a 0.1 μF ceramic capacitor between the sup-
plies will provide the best harmonic distortion performance.
Some system applications require low THD, low SFDR and
wide dynamic range (SNR), whereas some system applica-
tions require high SNR and they may sacrifice THD and SFDR
to focus on the noise performance.
Noise is a very important specification for both the op amp
and the ADC. There are three main sources of noise that
contribute to the overall performance of the ADC: Quantiza-
tion noise, noise generated by the ADC itself (particularly at
higher frequencies) and the noise generated by the applica-
tion circuit. The impedance of the input source affects the
noise performance of the op amp. Theoretically, an ADC’s
signal to noise ratio (SNR) can be found from the equation:
INTERFACING HIGH PERFORMANCE OP AMPS WITH
ADCs
These amplifiers are designed for ease of use in a wide range
of applications requiring high speed, low supply current, low
noise, and the ability to drive complex ADC and video loads.
SNR (in dB) = 6.02*N+1.72
The source that drives the modern high resolution analog-to-
digital converters (ADCs) sees a high frequency AC load and
a DC load of a few hundred ohms or more. Thus, a high per-
formance op amp with high input impedance of a few mega
ohms and low output impedance would be an ideal choice as
an input ADC driver. The LMH6611/LMH6612 have the low
output impedance of 0.07Ω at f = 1 MHz. The ADC driver acts
as a buffer and a low pass filter to reduce the overall system
noise. To utilize the full dynamic range of the ADC, the ADC
input has to be driven to full scale input voltage.
where N is the resolution of the ADC. For example, according
to this equation a 12-bit ADC has an SNR of 74 dB. However,
the practical SNR number would be about 72 dB. In order to
achieve better SNR, the ADC driver noise should be as small
as possible. The LMH6611/LMH6612 have the low voltage
noise of only 10 nV/
.
The combined settling time of the op amp and the ADC must
be within 1 LSB. The 0.01% settling time of the LMH6611/
LMH6612 is 100 ns.
As signals travel through the traces of a printed circuit board
(PCB) and long cables, system noise accumulates in the sig-
nals and a differential ADC rejects any signals noise that
appears as a common mode voltage. There are a couple of
advantages to using differential signals rather than single-
ended signals. First, differential signals double the dynamic
range of the ADC and second, they offer better harmonic dis-
tortion performance. There are several ways to produce dif-
ferential signals from a dual op amp configuration. One
method is to utilize the single-ended to differential conversion
technique and the other is the differential to differential con-
version technique. The first method requires a single input
source and the second method requires differential input
source.
The ADC driver’s THD should be inherently lower than that of
the ADC. The LMH6611/LMH6612 have an SFDR of 96 dBc
at 2 VPP output and 1 MHz input frequency.
Signal to Noise and Distortion (SINAD) is a parameter which
is the combination of the SNR and THD specifications. SINAD
is defined as the RMS value of the output signal to the RMS
value of all of the other spectral components below half the
clock frequency, including harmonics but excluding DC. It can
be calculated from SNR and THD according to the equation:
A real world input source can have non-ideal impedance thus
the buffer amplifier, with very low output impedance, is re-
21
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Because SINAD compares all undesired frequency compo-
nents with the input frequency, it is an overall measure of an
ADC’s dynamic performance. The following sections will dis-
cuss the three different ADC driver architectures in detail.
uration is preferred over the non-inverting configuration, as it
offers more linear output response. Table 1 shows the per-
formance data of the LMH6611 combined with the AD-
C121S101. The ADC driver’s cutoff frequency of 500 kHz is
found from the equation:
SINGLE TO SINGLE ADC DRIVER
This architecture has a single-ended input source connected
to the input of the op amp and the single-ended output of the
op amp is then fed to the single-ended input of the ADC. The
low noise of only 10 nV/
and a wide bandwidth of 345 MHz
make the LMH6611 an excellent choice for driving the 12-bit
ADC121S101 500 KSPS to 1 MSPS ADC, which has a suc-
cessive approximation architecture with internal sample and
hold circuits. Figure 2 shows the schematic of the LMH6611
in a 2nd order multiple-feedback with gain of −1 (inverting)
configuration, driving an ADC121S101. The inverting config-
The op amp’s gain is set by the equation:
30033629
FIGURE 4. Single to Single ADC Driver
TABLE 1. Performance of the LMH6611 Combined with the ADC121S101
Amplifier
Output/ADC Input
SINAD
(dB)
SNR
(dB)
71.6
THD
(dB)
SFDR
(dBc)
77.6
ENOB
Notes
4
70.2
−75.7
11.4
ADC121S101 @ f = 200 kHz
When the op amp and the ADC are using the same supply, it
is important that both devices are well bypassed. A 0.1 µF
ceramic capacitor and a 10 µF tantalum capacitor should be
located as close as possible to each supply pin. A sample
layout is shown in Figure 5. The 0.1 µF capacitors (C13 and
C6) and the 10 µF capacitors (C11 and C5) are located very
close to the supply pins of the LMH6611 and the AD-
C121S101.
•
•
Place ADC and amplifier as close together as possible.
Put the supply bypassing capacitors as close as possible
to the device (<1”).
Utilize surface mount instead of through-hole components
and ground and power planes.
Keep the traces short where possible.
•
•
•
Use terminated transmission lines for long traces.
The following are recommendations for the design of PCB
layout in order to obtain the optimum high frequency perfor-
mance:
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30033640
FIGURE 5. LMH6611 and ADC121S101 Layout
SINGLE-ENDED TO DIFFERENTIAL ADC DRIVER
up at the non-inverting inputs of both op amps U1 and U2.
This configuration produces differential ±2.5 VPP output sig-
nals, when the single-ended input signal of 0 to VREF is AC
coupled into the non-inverting terminal of the op amp and
each non-inverting terminal of the op amp is biased at the mid-
scale of 2.5V. The two output RC anti-aliasing filters are used
between both the outputs of U1 and U2 and the input of the
ADC121S625 to minimize the effect of undesired high fre-
quency noise coming from the input source. Each RC filter
has the cutoff frequency of approximately 22 MHz.
The single-ended to differential ADC driver in Figure 3 utilizes
an LMH6612 dual op amp to buffer a single-ended source to
drive an ADC with differential inputs. One of the op amps is
configured as a unity gain buffer that drives the inverting
(IN−) input of the op amp U2 and non-inverting (IN+) input of
the ADC121S625. U2 inverts the input signal and drives the
inverting input of the ADC121S625. The ADC driver is con-
figured for a gain of +2 to reduce the noise without sacrificing
THD performance. The common mode voltage of 2.5V is set
30033680
FIGURE 6. Single-Ended to Differential ADC Driver
23
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The performance of the LMH6612 with the ADC121S625 is
shown in Table 2.
TABLE 2. Performance of the LMH6612 Combined with the ADC121S625
Amplifier
Output/ADC Input
SINAD
(dB)
SNR
(dB)
69
THD
(dB)
SFDR
(dBc)
75.1
ENOB
Notes
2.5
68.8
−81.5
11.2
ADC121S625 @ f = 20 kHz
DIFFERENTIAL TO DIFFERENTIAL ADC DRIVER
single ADC drivers. Each output from these drivers goes to a
separate input of the differential ADC. Here, each single to
single ADC driver uses the same components and is config-
ured for a gain of -1 (inverting).
The LMH6612 dual op amp can be configured as a differential
to differential ADC driver to buffer a differential source to a
differential input ADC as shown in Figure 7. The differential
to differential ADC driver can be formed using two single to
30033642
FIGURE 7. Differential to Differential ADC Driver
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24
The following table summarizes the performance of the
LMH6612 combined with the ADC121S625 at two different
frequencies. In order to utilize the full dynamic range of the
ADC, the maximum input of 2.5 VPP is applied to the ADC
input. Figure 8 shows the FFT plot of the LMH6612 and AD-
C121S625 combination tested at f = 20 kHz input frequency.
TABLE 3. Performance of the LMH6612 Combined with the ADC121S625
Amplifier
Output/ADC Input
SINAD
(dB)
SNR
(dB)
72.3
72.2
THD
(dB)
SFDR
(dBc)
92.1
ENOB
Notes
2.5
2.5
72.2
−87.7
−87.8
11.7
11.7
ADC121S625 @ f = 20 kHz
ADC121S625 @ f = 200 kHz
72.2
90.8
30033673
FIGURE 8. The FFT Plot of Differential to Differential ADC Driver
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DC LEVEL SHIFTING
Often a signal must be both amplified and level shifted while
using a single supply for the op amp. The circuit in Figure 9
can do both of these tasks. The procedure for specifying the
resistor values is as follows.
1. Determine the input voltage.
2. Calculate the input voltage midpoint, VINMID = VINMIN
(VINMAX – VINMIN)/2.
+
3. Determine the output voltage needed.
4. Calculate the output voltage midpoint, VOUTMID
VOUTMIN + (VOUTMAX – VOUTMIN)/2.
=
5. Calculate the gain needed, gain = (VOUTMAX – VOUTMIN)/
(VINMAX – VINMIN
)
6. Calculate the amount the voltage needs to be shifted
30033648
from input to output, ΔVOUT = VOUTMID – gain x VINMID
.
7. Set the supply voltage to be used.
FIGURE 9. DC Level Shifting
8. Calculate the noise gain, noise gain = gain + ΔVOUT/VS.
9. Set RF.
The following example is for a VIN of 0V to 1V with a VOUT of
2V to 4V.
10. Calculate R1, R1 = RF/gain.
11. Calculate R2, R2 = RF/(noise gain-gain).
12. Calculate RG, RG= RF/(noise gain – 1).
1. VIN = 0V to 1V
2. VINMID = 0V + (1V – 0V)/2 = 0.5V
3. VOUT = 2V to 4V
Check that both the VIN and VOUT are within the voltage
ranges of the LMH6611.
4. VOUTMID = 2V + (4V – 2V)/2 = 3V
5. Gain = (4V – 2V)/(1V – 0V) = 2
6.
ΔVOUT = 3V – 2 x 0.5V = 2
7. For the example the supply voltage will be +5V.
8. Noise gain = 2 + 2/5V = 2.4
9. RF = 2 kΩ
10. R1 = 2 kΩ/2 = 1 kΩ
11. R2 = 2 kΩ/(2.4-2) = 5 kΩ
12. RG = 2 kΩ/(2.4 – 1) = 1.43 kΩ
4th ORDER MULTIPLE FEEDBACK LOW-PASS FILTER
of +1 and a −3 dB point of 1 MHz. Values can be determined
by using the WEBENCH® Active Filter Designer found at
www.amplifiers.national.com.
Figure 10 shows the LMH6612 used as the amplifier in a mul-
tiple feedback low pass filter. This filter is set up to have a gain
30033628
FIGURE 10. 4th Order Multiple Feedback Low-Pass Filter
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CURRENT SENSE AMPLIFIER AND OPTIMIZING
ACCURACY IN PRECESION APPLICATIONS
current by using larger values of gain (RF). The total capaci-
tance (CT) on the inverting terminal of the op amp includes
the photodiode capacitance (CPD) and the input capacitance
of the op amp (CIN). This total capacitance (CT) plays an im-
portant role in the stability of the circuit. The noise gain of this
circuit determines the stability and is defined by:
With it’s rail-to-rail output capability, low VOS, and low IB the
LMH6611 is an ideal choice for a current sense amplifier ap-
plication. Figure 11 shows the schematic of the LMH6611 set
up in a low-side sense configuration which provides a con-
version gain of 2V/A. Voltage error due to VOS can be calcu-
lated to be VOS x (1 + RF/RG) or 0.6 mV x 21 = 12.6 mV.
Voltage error due to IO is IO x RF or 0.5 µA x 1 kΩ = 0.5 mV.
Hence worst case total voltage error is 12.6 mV + 0.5 mV or
13.1 mV which translates into a current error of 13.1 mV/(2 V/
A) = 6.55 mA.
(1)
(2)
This circuit employs DC source resistance matching at the
two input terminals in order to minimize the output DC error
caused by input bias current. Another technique to reduce
output offset in a non-inverting amplifier configuration is to in-
troduce a DC offset current into the inverting input of the
amplifier. To ensure minimal impact on frequency response
be sure to inject the DC offset current through large resistors.
Conversely if optimizing an inverting amplifier configuration
simply apply offset adjustment to the non-inverting input.
30033665
30033641
FIGURE 13. Bode Plot of Noise Gain Intersecting with Op
Amp Open Loop Gain
FIGURE 11. Current Sense Amplifier
TRANSIMPEDANCE AMPLIFIER
Figure 13 shows the bode plot of the noise gain intersecting
the op amp open loop gain. With larger values of gain, CT and
RF create a zero in the transfer function. At higher frequencies
the circuit can become unstable due to excess phase shift
around the loop.
By definition, a photodiode produces either a current or volt-
age output from exposure to a light source. A Tran-
simpedance Amplifier (TIA) is utilized to convert this low-level
current to a usable voltage signal. The TIA often will need to
be compensated to insure proper operation.
A pole at fP in the noise gain function is created by placing a
feedback capacitor (CF) across RF. The noise gain slope is
flattened by choosing an appropriate value of CF for optimum
performance.
Theoretical expressions for calculating the optimum value of
CF and the expected −3 dB bandwidth are:
(3)
(4)
Equation 4 indicates that the −3 dB bandwidth of the TIA is
inversely proportional to the feedback resistor. Therefore, if
the bandwidth is important then the best approach would be
to have a moderate transimpedance gain stage followed by a
broadband voltage gain stage.
30033662
FIGURE 12. Photodiode Modeled with Capacitance
Elements
Table 4 shows the measurement results of the LMH6611 with
different photodiodes having various capacitances (CPD) and
a feedback resistance (RF) of 1 kΩ.
Figure 12 shows the LMH6611 modeled with photodiode and
the internal op amp capacitances. The LMH6611 allows cir-
cuit operation of a low intensity light due to its low input bias
27
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TABLE 4. TIA (Figure 1) Compensation and Performance Results
CPD
(pF)
22
CT
(pF)
24
CF CAL
(pF)
CF USED
(pF)
5.6
8
f −3 dB CAL
(MHz)
29.3
f −3 dB MEAS
(MHz)
27.1
Peaking
(dB)
0.5
5.42
47
49
7.75
20.5
21
0.5
100
222
330
102
224
332
11.15
20.39
20.2
12
14.2
15.2
0.5
18
9.6
10.7
0.5
22
7.9
9
0.8
Note:
GBWP = 130 MHz
CT = CPD + CIN
CIN = 2 pF
VS = ±2.5V
Figure 14 shows the frequency response for the various pho-
todiodes in Table 4.
noise voltage, feedback resistor thermal noise, input noise
current, photodiode noise current) do not all operate over the
same frequency band. Therefore, when the noise at the out-
put is calculated, this should be taken into account. The op
amp noise voltage will be gained up in the region between the
noise gain’s zero and pole (fZ and fP in Figure 13). The higher
the values of RF and CT, the sooner the noise gain peaking
starts and therefore its contribution to the total output noise
will be larger. It is advantageous to minimize CIN by proper
choice of op amp or by applying a reverse bias across the
diode but this will be at the expense of excess dark current
and noise.
EVALUATION BOARD
National Semiconductor provides the following evaluation
board as a guide for high frequency layout and as an aid in
device testing and characterization. Many of the datasheet
plots were measured with this board:
Device
Package
Board Part #
LMH6611MK
TSOT23
LMH730216
30033635
This evaluation board can be shipped when a device sample
request is placed with National Semiconductor.
FIGURE 14. Frequency Response for Various Photodiode
and Feedback Capacitors
When analyzing the noise at the output of the TIA, it is im-
portant to note that the various noise sources (i.e. op amp
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28
Physical Dimensions inches (millimeters) unless otherwise noted
6-Pin TSOT23
NS Package Number MK06A
8-Pin SOIC
NS Package Number M08A
29
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