LMK00308SQX/NOPB [TI]

具有 8 个可配置输出的 3.1GHz 差动时钟缓冲器/电平转换器 | RTA | 40 | -40 to 85;


型号：	LMK00308SQX/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	具有 8 个可配置输出的 3.1GHz 差动时钟缓冲器/电平转换器 \| RTA \| 40 \| -40 to 85 时钟驱动逻辑集成电路时钟驱动器转换器电平转换器
文件：	总25页 (文件大小：1459K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

March 14, 2012

LMK00308

3-GHz 8-Output Differential Clock Buffer/Level Translator

Servers, Workstations, and Computing

■

1.0 General Description

The LMK00308 is a 3-GHz, 8-output differential fanout buffer

3.0 Features

intended for high-frequency, low-jitter clock/data distribution

3:1 Input Multiplexer

■

and level translation. The input clock can be selected from

two universal inputs or one crystal input. The selected input

clock is distributed to two banks of 4 differential outputs and

one LVCMOS output. Both differential output banks can be

independently configured as LVPECL, LVDS, or HCSL

drivers, or disabled. The LVCMOS output has a synchronous

enable input for runt-pulse-free operation when enabled or

disabled. The LMK00308 operates from a 3.3 V core supply

and 3 independent 3.3 V/2.5 V output supplies..

Two universal inputs operate up to 3.1 GHz and accept

LVPECL, LVDS, CML, SSTL, HSTL, HCSL (AC-

coupled), or single-ended clocks

—

One crystal input accepts a 10 to 40 MHz crystal or

single-ended clock

—

Two Banks with 4 Differential Outputs each

■

LVPECL, LVDS, HCSL, or Hi-Z (selectable per bank)

—

LVPECL Additive Jitter with LMK03806 clock source

The LMK00308 provides high performance, versatility, and

power efficiency, making it ideal for replacing fixed-output

buffer devices while increasing timing margin in the system.

20 fs RMS at 156.25 MHz (10 kHz – 1 MHz)

51 fs RMS at 156.25 MHz (12 kHz – 20 MHz)

■

High PSRR: -65 / -76 dBc (LVPECL/LVDS) at 156.25 MHz

LVCMOS output with synchronous enable input

Pin-controlled configuration

■

2.0 Target Applications

Clock Distribution and Level Translation for high-speed

■

V_CCCore Supply: 3.3 V ± 5%

ADCs, DACs, Serial Interfaces (Multi-Gigabit Ethernet,

XAUI, Fibre Channel, PCIe, SATA/SAS, SONET/SDH,

CPRI), and high-frequency backplanes

3 Independent V_CCOOutput Supplies: 3.3 V/2.5 V ± 5%

Industrial temperature range: -40°C to +85°C

Package: 40-pin LLP (6.0 x 6.0 x 0.8 mm)

Remote Radio Units (RRU) and Baseband Units (BBU)

■

Switches and Routers

4.0 Functional Block Diagram

30177601

301776 SNAS576A

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5.0 Connection Diagram

40-Pin LLP Package

30177602

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6.0 Pin Descriptions

Pin #

DAP

1, 2

Pin Name(s)

DAP

Type

GND

Description

Die Attach Pad. Connect to the PCB ground plane for heat dissipation.

Differential clock output A0. Output type set by CLKoutA_TYPE pins.

Power supply for Bank A Output buffers. V_CCOAcan operate from 3.3 V or

CLKoutA0, CLKoutA0*

V_CCOA

3, 6

PWR 2.5 V. The V_CCOApins are internally tied together. Bypass with a 0.1 uF

low-ESR capacitor placed very close to each Vcco pin. (Note 1)

4, 5

7, 8

CLKoutA1, CLKoutA1*

CLKoutA2, CLKoutA2*

CLKoutA3, CLKoutA3*

Differential clock output A1. Output type set by CLKoutA_TYPE pins.

Differential clock output A2. Output type set by CLKoutA_TYPE pins.

Differential clock output A3. Output type set by CLKoutA_TYPE pins.

9, 10

CLKoutA_TYPE0,

CLKoutA_TYPE1

11, 39

Bank A output buffer type selection pins (Note 2)

Power supply for Core and Input buffer blocks. The Vcc supply operates

12, 35

Vcc

PWR from 3.3 V. Bypass with a 0.1 uF low-ESR capacitor placed very close to

each Vcc pin.

Input for crystal. Can also be driven by a XO, TCXO, or other external

single-ended clock.

OSCin

Output for crystal. Leave OSCout floating if OSCin is driven by a single-

ended clock.

OSCout

15, 18

16, 17

CLKin_SEL0, CLKin_SEL1

CLKin0, CLKin0*

Clock input selection pins (Note 2)

Universal clock input 0 (differential/single-ended)

CLKoutB_TYPE0,

CLKoutB_TYPE1

19, 32

Bank B output buffer type selection pins (Note 2)

20, 31, 40

21, 22

GND

Ground

CLKoutB3*, CLKoutB3

CLKoutB2*, CLKoutB2

Differential clock output B3. Output type set by CLKoutB_TYPE pins.

Differential clock output B2. Output type set by CLKoutB_TYPE pins.

Power supply for Bank B Output buffers. V_CCOBcan operate from 3.3 V or

23, 24

V_CCOB

25, 28

PWR 2.5 V. The V_CCOBpins are internally tied together. Bypass with a 0.1 uF

low-ESR capacitor placed very close to each Vcco pin. (Note 1)

26, 27

29, 30

33, 34

CLKoutB1*, CLKoutB1

CLKoutB0*, CLKoutB0

CLKin1*, CLKin1

REFout

Differential clock output B1. Output type set by CLKoutB_TYPE pins.

Differential clock output B0. Output type set by CLKoutB_TYPE pins.

Universal clock input 1 (differential/single-ended)

LVCMOS reference output. Enable output by pulling REFout_EN pin high.

Power supply for REFout Output buffer. V_CCOCcan operate from 3.3 V or

2.5 V. Bypass with a 0.1 uF low-ESR capacitor placed very close to each

Vcco pin. (Note 1)

V_CCOC

PWR

REFout enable input. Enable signal is internally synchronized to selected

clock input. (Note 2)

REFout_EN

Note 1: The output supply voltages/pins (V_CCOA, V_CCOB, and V_CCOC) will be referred to generally as V_CCOwhen no distinction is needed, or when the output supply

can be inferred by the output bank/type.

Note 2: CMOS control input with internal pull-down resistor.

Note 3: Any unused output pins should be left floating with minimum copper length (Note 5), or properly terminated if connected to a transmission line, or disabled/

Hi-Z if possible. See Section 7.3 Clock Outputs for output configuration or Section 14.3 Termination and Use of Clock Drivers output interface and termination

techniques.

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7.3 Clock Outputs

7.0 Functional Description

The differential output buffer type for Bank A and Bank B out-

puts can be separately configured using the CLKoutA_TYPE

[1:0] and CLKoutB_TYPE[1:0] inputs, respectively, as shown

in Table 3. For applications where all differential outputs are

not needed, any unused output pin should be left floating with

a minimum copper length (Note 5) to minimize capacitance

and potential coupling and reduce power consumption. If an

entire output bank will not be used, it is recommended to dis-

able/Hi-Z the bank to reduce power. Refer to Section 14.3

Termination and Use of Clock Drivers for more information on

output interface and termination techniques.

The LMK00308 is an 8-output differential clock fanout buffer

with low additive jitter that can operate up to 3.1 GHz. It fea-

tures a 3:1 input multiplexer with an optional crystal oscillator

input, two banks of 4 differential outputs with multi-mode

buffers (LVPECL, LVDS, HCSL, or Hi-Z), one LVCMOS out-

put, and 3 independent output buffer supplies. The input

selection and output buffer modes are controlled via pin strap-

ping. The device is offered in a 40-pin LLP package and

leverages much of the high-speed, low-noise circuit design

employed in the LMK04800 family of clock conditioners.

Note 5: For best soldering practices, the minimum trace length for any

unused output pin should extend to include the pin solder mask. This way

during reflow, the solder has the same copper area as connected pins. This

allows for good, uniform fillet solder joints helping to keep the IC level during

reflow.

7.1 V_CCand V_CCOPower Supplies

The LMK00308 has a 3.3 V core power supply (V_CC) and 3

independent 3.3 V/2.5 V output power supplies (V_CCOA

V_CCOB, V_CCOC). Output supply operation at 2.5 V enables low-

er power consumption and output-level compatibility with 2.5

V receiver devices. The output levels for LVPECL (V_OH, V_OL

TABLE 3. Differential Output Buffer Type Selection

)

and LVCMOS (V_OH) are referenced to the respective Vcco

supply, while the output levels for LVDS and HCSL are rela-

tively constant over the specified Vcco range. Refer to Sec-

tion 14.4 Power Supply and Thermal Considerations for

additional supply related considerations, such as power dis-

sipation, power supply bypassing, and power supply ripple

rejection (PSRR).

CLKoutX_

TYPE1

CLKoutX_

TYPE0

CLKoutX Buffer Type

(Bank A or B)

LVPECL

LVDS

HCSL

Disabled (Hi-Z)

Note 4: Care should be taken to ensure the Vcco voltages do not exceed

the Vcc voltage to prevent turning-on the internal ESD protection circuitry.

7.3.1 Reference Output

The reference output (REFout) provides a LVCMOS copy of

the selected input clock. The LVCMOS output high level is

referenced to the Vcco voltage. REFout can be enabled or

disabled using the enable input pin, REFout_EN, as shown in

Table 4.

7.2 Clock Inputs

The input clock can be selected from CLKin0/CLKin0*,

CLKin1/CLKin1*, or OSCin. Clock input selection is controlled

using the CLKin_SEL[1:0] inputs as shown in Table 1. Refer

to Section 14.1 Driving the Clock Inputs for clock input re-

quirements. When CLKin0 or CLKin1 is selected, the crystal

circuit is powered down. When OSCin is selected, the crystal

oscillator circuit will start-up and its clock will be distributed to

all outputs. Refer to Section 14.2 Crystal Interface for more

information. Alternatively, OSCin may be be driven by a sin-

gle-ended clock (up to 250 MHz) instead of a crystal.

TABLE 4. Reference Output Enable

REFout_EN

REFout State

Disabled (Hi-Z)

Enabled

The REFout_EN input is internally synchronized with the se-

lected input clock by the SYNC block. This synchronizing

function prevents glitches and runt pulses from occurring on

the REFout clock when enabled or disabled. REFout will be

enabled within 3 cycles (t_EN) of the input clock after

REFout_EN is toggled high. REFout will be disabled within 3

cycles (t_DIS) of the input clock after REFout_EN is toggled low.

TABLE 1. Input Selection

CLKin_SEL1

CLKin_SEL0

Selected Input

CLKin0, CLKin0*

CLKin1, CLKin1*

OSCin

When REFout is disabled, the use of a resistive loading can

be used to set the output to a predetermined level. For ex-

ample, if REFout is configured with a 1 kΩ load to ground,

then the output will be pulled to low when disabled.

Table 2 shows the output logic state vs. input state when ei-

ther CLKin0/CLKin0* or CLKin1/CLKin1* is selected. When

OSCin is selected, the output state will be an inverted copy of

the OSCin input state.

TABLE 2. CLKin Input vs. Output States

State of

Selected CLKin

Enabled Outputs

CLKinX and CLKinX*

inputs floating

Logic low

CLKinX and CLKinX*

inputs shorted together

CLKin logic low

CLKin logic high

Logic low

Logic high

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8.0 Absolute Maximum Ratings (Note 6, Note 7)

If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for

availability and specifications.

Parameter

Symbol

V_CC, V_CCO

V_IN

Ratings

-0.3 to 3.6

-0.3 to (V_CC+ 0.3)

-65 to +150

+260

Units

Supply Voltages

Input Voltage

T_STG

Storage Temperature Range

Lead Temperature (solder 4 s)

Junction Temperature

°C

T_L

T_J

+150

9.0 Recommended Operating Conditions

Parameter

Ambient Temperature Range

Junction Temperature

Symbol

T_A

Min

Typ

Max

Units

-40

°C

T_J

125

3.45

V_CC

Core Supply Voltage Range

3.15

3.3

Output Supply Voltage Range (Note 8,

Note 9)

3.3 – 5%

2.5 – 5%

3.3

2.5

3.3 + 5%

2.5 + 5%

V_CCO

Note 6: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see Section 11.0 Electrical

Characteristics. The guaranteed specifications apply only to the test conditions listed.

Note 7: This device is a high-performance integrated circuit with an ESD rating up to 2 kV Human Body Model, up to 150 V Machine Model, and up to 750 V

Charged Device Model and is ESD sensitive. Handling and assembly of this device should only be done at ESD-free workstations.

Note 8: The output supply voltages/pins (V_CCOA, V_CCOB, and V_CCOC) will be referred to generally as V_CCOwhen no distinction is needed, or when the output supply

can be inferred by the output bank/type.

Note 9: Vcco should be less than or equal to Vcc (Vcco ≤ Vcc).

10.0 Package Thermal Resistance

Package

θ_JA

θ_{JC (DAP)}

40-Lead LLP (Note 10)

31.4 °C/W

7.2 °C/W

Note 10: Specification assumes 9 thermal vias connect the die attach pad (DAP) to the embedded copper plane on the 4-layer JEDEC board. These vias play a

key role in improving the thermal performance of the LLP. It is recommended that the maximum number of vias be used in the board layout.

11.0 Electrical Characteristics Unless otherwise specified: Vcc = 3.3 V ± 5%, Vcco = 3.3 V ± 5%, 2.5 V ±

5%, -40 °C ≤ T_A≤ 85 °C, CLKin driven differentially, input slew rate ≥ 3 V/ns. Typical values represent most likely parametric

norms at Vcc = 3.3 V, Vcco = 3.3 V, T_A= 25 °C, and at the Recommended Operation Conditions at the time of product

characterization and are not guaranteed. (Note 8, Note 11)

Symbol

Parameter

Conditions

Current Consumption

CLKinX selected

Min

Typ

Max

Units

8.5

10.5

13.5

Core Supply Current, All Outputs

Disabled

I_{CC_CORE}

I_{CC_PECL}

I_{CC_LVDS}

I_{CC_HCSL}

I_{CC_CMOS}

OSCin selected

Additive Core Supply Current,

Per LVPECL Bank Enabled

3.5

26.5

30.5

38.5

5.5

Additive Core Supply Current,

Per LVDS Bank Enabled

Additive Core Supply Current,

Per HCSL Bank Enabled

Additive Core Supply Current,

LVCMOS Output Enabled

Includes Output Bank Bias and Load

Currents, R_T= 50 Ω to Vcco - 2V

on all outputs in bank

Additive Output Supply Current,

Per LVPECL Bank Enabled

I_{CCO_PECL}

132

160

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Symbol

Parameter

Conditions

Min

Typ

Max

Units

Additive Output Supply Current,

Per LVDS Bank Enabled

I_{CCO_LVDS}

34.5

Includes Output Bank Bias and Load

Currents, R_T= 50 Ω

on all outputs in bank

Vcco =

Additive Output Supply Current,

Per HCSL Bank Enabled

I_{CCO_HCSL}

3.3 V ± 5%

200 MHz,

C_L= 5 pF

Additive Output Supply Current,

LVCMOS Output Enabled

I_{CCO_CMOS}

Vcco =

2.5 V ± 5%

Power Supply Ripple Rejection (PSRR)

Ripple-Induced

Phase Spur Level (Note 13)

Differential LVPECL Output

156.25 MHz

-65

-63

-76

-74

-72

-63

PSRR_PECL

PSRR_LVDS

PSRR_HCSL

dBc

312.5 MHz

Ripple-Induced

Phase Spur Level (Note 13)

Differential LVDS Output

100 kHz, 100 mVpp

Ripple Injected on

Vcco, Vcco = 2.5 V

156.25 MHz

312.5 MHz

156.25 MHz

312.5 MHz

Ripple-Induced

Phase Spur Level (Note 13)

Differential HCSL Output

CMOS Control Inputs (CLKin_SELn, CLKoutX_TYPEn, REFout_EN)

V_IH

V_IL

I_IH

High-Level Input Voltage

1.6

Vcc

0.4

Low-Level Input Voltage

High-Level Input Current

Low-Level Input Current

GND

V_IH= Vcc, Internal pull-down resistor

V_IL= 0 V, Internal pull-down resistor

µA

I_IL

-5

0.1

Clock Inputs (CLKin0/CLKin0*, CLKin1/CLKin1*)

Functional up to 3.1 GHz

Input Frequency Range

Output frequency range and timing specified

per output type (refer to LVPECL, LVDS,

HCSL, LVCMOS output specifications)

f_CLKin

3.1

GHz

(Note 20)

V_IHD

V_ILD

Differential Input High Voltage

Differential Input Low Voltage

Vcc

GND

0.15

CLKin driven differentially

Differential Input Voltage Swing

V_ID

1.3

(Note 14)

Vcc -

1.2

V_ID= 150 mV

V_ID= 350 mV

V_ID= 800 mV

0.5

Differential Input

Common Mode Voltage

Vcc -

1.1

V_CMD

Vcc -

0.9

V_CM

Single-Ended Input

High Voltage

V_IH

V_IL

Vcc

0.15

CLKinX driven single-ended,

CLKinX* AC coupled to GND

V_CM

Single-Ended Input

Low Voltage

GND

0.5

-0.15

Single-Ended Input

Common Mode Voltage

Vcc -

1.2

V_CM

f_CLKin0= 100 MHz

-84

-82

-71

-65

f_CLKin0= 200 MHz

f_OFFSET> 50 kHz,

Mux Isolation,

CLKin0 to CLKin1

ISO_MUX

dBc

P_CLKinX= 0 dBm

f_CLKin0= 500 MHz

f_CLKin0= 1000 MHz

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Symbol

Parameter

Conditions

Min

Typ

Max

Units

Crystal Interface (OSCin, OSCout)

External Clock

Frequency Range

(Note 20)

OSCin driven single-ended,

OSCout floating

F_CLK

250

MHz

Fundamental mode crystal

ESR ≤ 200 Ω (10 to 30 MHz)

F_XTAL

Crystal Frequency Range

MHz

ESR ≤ 125 Ω (30 to 40 MHz)

(Note 15)

C_IN

OSCin Input Capacitance

LVPECL Outputs (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*)

Vcco = 3.3 V ± 5%,

1.0

1.2

1.0

3.1

2.3

Maximum Output Frequency

V_OD≥ 600 mV,

R_L= 100 Ω

differential

R_T= 160 Ω to GND

f_{CLKout_FS}

Full V_ODSwing

GHz

Vcco = 2.5 V ± 5%,

(Note 20, Note 21)

0.75

1.5

R_T= 91 Ω to GND

Vcco = 3.3 V ± 5%,

Maximum Output Frequency

Reduced V_ODSwing

V_OD≥ 400 mV,

R_L= 100 Ω

differential

R_T= 160 Ω to GND

f_{CLKout_RS}

Vcco = 2.5 V ± 5%,

(Note 20, Note 21)

1.5

R_T= 91 Ω to GND

CLKin: 100 MHz, Slew

rate ≥ 3 V/ns

R_T= 160 Ω to GND, CLKin: 156.25 MHz,

Vcco = 3.3 V,

Additive RMS Jitter

Integration Bandwidth

1 MHz to 20 MHz

(Note 16)

Jitter_ADD

Slew rate ≥ 2.7 V/ns

CLKin: 625 MHz, Slew

rate ≥ 3 V/ns

R_L= 100 Ω

differential

CLKin: 156.25 MHz,

J_SOURCE= 190 fs RMS

(10 kHz to 1 MHz)

Vcco = 3.3 V,

R_T= 160 Ω to GND,

R_L= 100 Ω

Additive RMS Jitter with

LVPECL clock source from

LMK03806

Jitter_ADD

CLKin: 156.25 MHz,

J_SOURCE= 195 fs RMS

(12 kHz to 20 MHz)

(Note 16, Note 17)

differential

CLKin: 100 MHz, Slew

-162.5

-158.1

-154.4

rate ≥ 3 V/ns

R_T= 160 Ω to GND, CLKin: 156.25 MHz,

Vcco = 3.3 V,

Noise Floor

dBc/Hz

f_OFFSET≥ 10 MHz

Slew rate ≥ 2.7 V/ns

CLKin: 625 MHz, Slew

rate ≥ 3 V/ns

R_L= 100 Ω

differential

DUTY

V_OH

Duty Cycle (Note 20)

50% input clock duty cycle

Vcco - Vcco - Vcco -

1.2 0.9 0.7

Vcco - Vcco - Vcco -

Output High Voltage

T_A= 25 °C, DC Measurement,

V_OL

V_OD

t_R

Output Low Voltage

2.0

1.75

1.5

R_T= 50 Ω to Vcco - 2 V

Output Voltage Swing

600

830

1000

(Note 14)

Output Rise Time

20% to 80%

175

R_T= 160 Ω to GND,

R_L= 100 Ω differential

Output Fall Time

80% to 20%

t_F

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Symbol

f_{CLKout_FS}

f_{CLKout_RS}

Parameter

Conditions

Min

Typ

Max

Units

LVDS Outputs (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*)

Maximum Output Frequency

V_OD≥ 250 mV,

R_L= 100 Ω differential

Full V_ODSwing

1.0

1.5

1.6

2.1

GHz

(Note 20, Note 21)

Maximum Output Frequency

Reduced V_ODSwing

V_OD≥ 200 mV,

R_L= 100 Ω differential

(Note 20, Note 21)

CLKin: 100 MHz, Slew

rate ≥ 3 V/ns

CLKin: 156.25 MHz,

Slew rate ≥ 2.7 V/ns

CLKin: 625 MHz, Slew

rate ≥ 3 V/ns

Additive RMS Jitter

Integration Bandwidth

1 MHz to 20 MHz

(Note 16)

Vcco = 3.3 V,

R_L= 100 Ω

differential

Jitter_ADD

CLKin: 100 MHz, Slew

-159.5

-157.0

-152.7

rate ≥ 3 V/ns

Vcco = 3.3 V,

R_L= 100 Ω

differential

Noise Floor

CLKin: 156.25 MHz,

Slew rate ≥ 2.7 V/ns

CLKin: 625 MHz, Slew

rate ≥ 3 V/ns

Noise Floor

dBc/Hz

f_OFFSET≥ 10 MHz

DUTY

V_OD

Duty Cycle (Note 20)

50% input clock duty cycle

Output Voltage Swing

250

400

450

(Note 14)

Change in Magnitude of V_ODfor

Complementary Output States

T_A= 25 °C,

ΔV_OD

V_OS

-50

1.125

-35

1.375

DC Measurement,

R_L= 100 Ω differential

Output Offset Voltage

1.25

Change in Magnitude of V_OSfor

Complementary Output States

ΔV_OS

I_SA

I_SB

T_A= 25 °C,

Output Short Circuit Current

Single Ended

-24

-12

Single ended outputs shorted to GND

Output Short Circuit Current

Differential

I_SAB

t_R

Complementary outputs tied together

Output Rise Time

20% to 80%

175

R_L= 100 Ω differential

Output Fall Time

80% to 20%

t_F

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Symbol

Parameter

Conditions

Min

Typ

Max

Units

HCSL Outputs (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*)

Output Frequency Range

f_CLKout

400

MHz

R_L= 50 Ω to GND, C_L≤ 5 pF

CLKin: 100 MHz, Slew

(Note 20)

Additive RMS Jitter

Integration Bandwidth

1 MHz to 20 MHz

(Note 16)

Vcco = 3.3 V,

rate ≥ 3 V/ns

CLKin: 156.25 MHz,

Slew rate ≥ 2.7 V/ns

CLKin: 100 MHz, Slew

rate ≥ 3 V/ns

Jitter_ADD

R_T= 50 Ω to GND

-161.3

-156.3

Noise Floor

Vcco = 3.3 V,

Noise Floor

dBc/Hz

R_T= 50 Ω to GND

f_OFFSET≥ 10 MHz

CLKin: 156.25 MHz,

Slew rate ≥ 2.7 V/ns

DUTY

V_OH

Duty Cycle (Note 20)

Output High Voltage

Output Low Voltage

50% input clock duty cycle

T_A= 25 °C, DC Measurement,

520

-150

810

0.5

920

150

R_T= 50 Ω to GND

V_OL

Absolute Crossing Voltage

V_CROSS

160

350

460

140

(Note 20, Note 22)

R_L= 50 Ω to GND,

C_L≤ 5 pF

Total Variation of V_CROSS

ΔV_CROSS

(Note 20, Note 22)

Output Rise Time

20% to 80% (Note 22)

t_R

t_F

300

250 MHz, R_L= 50 Ω to GND,

C_L≤ 5 pF

Output Fall Time

80% to 20% (Note 22)

LVCMOS Output (REFout)

Output Frequency Range

f_CLKout

250

MHz

C_L≤ 5 pF

(Note 20)

Additive RMS Jitter

Integration Bandwidth

1 MHz to 20 MHz

(Note 16)

Vcco = 3.3 V,

100 MHz, Input Slew

Jitter_ADD

C_L≤ 5 pF

rate ≥ 3 V/ns

Noise Floor

Vcco = 3.3 V,

100 MHz, Input Slew

Noise Floor

-159.3

dBc/Hz

f_OFFSET≥ 10 MHz

Duty Cycle (Note 20)

C_L≤ 5 pF

rate ≥ 3 V/ns

DUTY

V_OH

50% input clock duty cycle

1 mA load

Vcco = 3.3 V

Vcco -

0.1

Output High Voltage

Output Low Voltage

V_OL

0.1

I_OH

Output High Current (Source)

Vcco = 2.5 V

Vcco = 3.3 V

Vcco = 2.5 V

Vo = Vcco / 2

I_OL

t_R

Output Low Current (Sink)

Output Rise Time

20% to 80% (Note 22)

225

250 MHz, R_L= 50 Ω to GND,

C_L≤ 5 pF

Output Fall Time

80% to 20% (Note 22)

t_F

t_EN

Output Enable Time (Note 23)

Output Disable Time (Note 23)

cycles

C_L≤ 5 pF

t_DIS

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Symbol

Parameter

Conditions

Propagation Delay and Output Skew

R_T= 160 Ω to GND,

Min

Typ

Max

Units

Propagation Delay

CLKin-to-LVPECL

t_{PD_PECL}

t_{PD_LVDS}

t_{PD_HCSL}

t_{PD_CMOS}

360

400

590

R_L= 100 Ω differential

Propagation Delay

CLKin-to-LVDS

R_L= 100 Ω differential

R_T= 50 Ω to GND,

C_L≤ 5 pF

Propagation Delay

CLKin-to-HCSL (Note 22)

Vcco = 3.3 V

1475

1550

Propagation Delay

CLKin-to-LVCMOS (Note 22)

C_L≤ 5 pF

Vcco = 2.5 V

Output Skew

t_SK(O)

LVPECL/LVDS/HCSL

(Note 20, Note 22, Note 24)

Skew specified between any two CLKouts

with the same buffer type. Load conditions

per output type are the same as propagation

delay specifications.

Part-to-Part Output Skew

LVPECL/LVDS/HCSL

(Note 22, Note 24)

t_SK(PP)

Note 11: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified

or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.

Note 12: See Section 14.4 Power Supply and Thermal Considerations for more information on current consumption and power dissipation calculations.

Note 13: Power supply ripple rejection, or PSRR, is defined as the single-sideband phase spur level (in dBc) modulated onto the clock output when a single-tone

sinusoidal signal (ripple) is injected onto the Vcco supply. Assuming no amplitude modulation effects and small index modulation, the peak-to-peak deterministic

jitter (DJ) can be calculated using the measured single-sideband phase spur level (PSRR) as follows: DJ (ps pk-pk) = [ (2 * 10^{(PSRR / 20)}) / (π * f^CLK) ] * 1E12

Note 14: See Section 12.1 Differential Voltage Measurement Terminology for definition of V_IDand V_ODvoltages.

Note 15: The ESR requirements stated must be met to ensure that the oscillator circuitry has no startup issues. However, lower ESR values for the crystal may

be necessary to stay below the maximum power dissipation (drive level) specification of the crystal. Refer to Section 14.2 Crystal Interface for crystal drive level

considerations.

Note 16: For the 100 MHz and 156.25 MHz clock input conditions, Additive RMS Jitter (J_ADD) is calculated using Method #1: J_ADD= SQRT(J_OUT²- J_SOURCE²),

where J_OUTis the total RMS jitter measured at the output driver and J_SOURCEis the RMS jitter of the clock source applied to CLKin. For the 625 MHz clock input

condition, Additive RMS Jitter is approximated using Method #2: J_ADD= SQRT(2*10^dBc/10) / (2*π*f_CLK), where dBc is the phase noise power of the Output Noise

Floor integrated from 1 to 20 MHz bandwidth. The phase noise power can be calculated as: dBc = Noise Floor + 10*log₁₀(20 MHz - 1 MHz). The additive RMS

jitter was approximated for 625 MHz using Method #2 because the RMS jitter of the clock source was not sufficiently low enough to allow practical use of Method

#1. Refer to the “Noise Floor vs. CLKin Slew Rate” and “RMS Jitter vs. CLKin Slew Rate” plots in Section 13.0 Typical Performance Characteristics.

Note 17: 156.25 MHz LVPECL clock source from LMK03806 with 20 MHz crystal reference (crystal part number: ECS-200-20-30BU-DU). J_SOURCE= 190 fs RMS

(10 kHz to 1 MHz) and 195 fs RMS (12 kHz to 20 MHz). Refer to the LMK03806 datasheet for more information.

Note 18: The noise floor of the output buffer is measured as the far-out phase noise of the buffer. Typically this offset is ≥ 10 MHz, but for lower frequencies this

measurement offset can be as low as 5 MHz due to measurement equipment limitations.

Note 19: Phase noise floor will degrade as the clock input slew rate is reduced. Compared to a single-ended clock, a differential clock input (LVPECL, LVDS)

will be less susceptible to degradation in noise floor at lower slew rates due to its common mode noise rejection. However, it is recommended to use the highest

possible input slew rate for differential clocks to achieve optimal noise floor performance at the device outputs.

Note 20: Specification is guaranteed by characterization and is not tested in production.

Note 21: See Section 13.0 Typical Performance Characteristics for output operation over frequency.

Note 22: AC timing parameters for HCSL or CMOS are dependent on output capacitive loading.

Note 23: Output Enable Time is the number of input clock cycles it takes for the output to be enabled after REFout_EN is pulled high. Similarly, Output Disable

Time is the number of input clock cycles it takes for the output to be disabled after REFout_EN is pulled low. The REFout_EN signal should have an edge transition

much faster than that of the input clock period for accurate measurement.

Note 24: Output skew is the propagation delay difference between any two outputs with identical output buffer type and equal loading while operating at the same

supply voltage and temperature conditions.

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12.0 Measurement Definitions

12.1 Differential Voltage Measurement Terminology

The differential voltage of a differential signal can be described by two different definitions causing confusion when reading

datasheets or communicating with other engineers. This section will address the measurement and description of a differential

signal so that the reader will be able to understand and discern between the two different definitions when used.

The first definition used to describe a differential signal is the absolute value of the voltage potential between the inverting and

non-inverting signal. The symbol for this first measurement is typically V_IDor V_ODdepending on if an input or output voltage is being

described.

The second definition used to describe a differential signal is to measure the potential of the non-inverting signal with respect to

the inverting signal. The symbol for this second measurement is V_SSand is a calculated parameter. Nowhere in the IC does this

signal exist with respect to ground, it only exists in reference to its differential pair. V_SScan be measured directly by oscilloscopes

with floating references, otherwise this value can be calculated as twice the value of V_ODas described in the first description.

Figure 1 illustrates the two different definitions side-by-side for inputs and Figure 2 illustrates the two different definitions side-by-

side for outputs. The V_ID(or V_OD) definition show the DC levels, V_IHand V_OL(or V_OHand V_OL), that the non-inverting and inverting

signals toggle between with respect to ground. V_SSinput and output definitions show that if the inverting signal is considered the

voltage potential reference, the non-inverting signal voltage potential is now increasing and decreasing above and below the non-

inverting reference. Thus the peak-to-peak voltage of the differential signal can be measured.

V_IDand V_ODare often defined as volts (V) and V_SSis often defined as volts peak-to-peak (V_PP).

30177607

FIGURE 1. Two Different Definitions for Differential Input Signals

30177608

FIGURE 2. Two Different Definitions for Differential Output Signals

Note 25: Refer to Application Note AN-912 Common Data Transmission Parameters and their Definitions for more information.

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13.0 Typical Performance Characteristics Unless otherwise specified: Vcc = 3.3 V, Vcco = 3.3 V,

T_A= 25 °C, CLKin driven differentially, input slew rate ≥ 3 V/ns.

LVPECL Output Swing (V_OD) vs. Frequency

LVDS Output Swing (V_OD) vs. Frequency

1.0

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

Vcco=2.5 V, Rterm=91 Ω

Vcco=3.3 V, Rterm=160 Ω

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

100

1000

10000

100

1000

10000

FREQUENCY (MHz)

30177676

30177675

LVPECL Output Swing @ 156.25 MHz

LVDS Output Swing @ 156.25 MHz

0.8

0.4

0.6

0.4

0.3

0.2

0.1

0.0

-0.2

-0.4

-0.6

-0.8

-0.1

-0.2

-0.3

-0.4

0.0

2.5

5.0

TIME (ns)

7.5

10.0

0.0

2.5

5.0

TIME (ns)

7.5

10.0

30177691

30177692

LVPECL Output Swing @ 1.5 GHz

LVDS Output Swing @ 1.5 GHz

0.4

0.3

0.2

0.1

0.3

0.2

0.1

0.0

-0.1

-0.2

-0.3

-0.4

-0.1

-0.2

-0.3

-0.4

0.00

0.25

0.50

TIME (ns)

0.75

1.00

0.00

0.25

0.50

TIME (ns)

0.75

1.00

30177693

30177694

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HCSL Output Swing @ 250 MHz

1.0

LVCMOS Output Swing @ 250 MHz

1.00

Vcco=3.3 V, AC coupled, 50Ω load

Vcco=2.5 V, AC coupled, 50Ω load

0.75

0.8

0.6

0.4

0.2

0.0

-0.2

0.50

0.25

0.00

-0.25

-0.50

-0.75

-1.00

TIME (ns)

30177698

30177699

Noise Floor vs. CLKin Slew Rate @ 100 MHz

Noise Floor vs. CLKin Slew Rate @ 156.25 MHz

-140

-135

LVPECL

LVDS

Fclk=100 MHz

Fclk=156.25 MHz

Foffset=20 MHz

HCSL

-145

-150

-155

-160

-165

-170

-140

-145

-150

-155

-160

-165

Foffset=20 MHz

LVCMOS

CLKin Source

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.5

1.0

1.5

2.0

2.5

3.0

3.5

DIFFERENTIAL INPUT SLEW RATE (V/ns)

30177677

30177678

Noise Floor vs. CLKin Slew Rate @ 625 MHz

RMS Jitter vs. CLKin Slew Rate @ 100 MHz (Note 26)

-135

400

LVPECL

LVDS

Fclk=625 MHz

LVDS

Fclk=100 MHz

350

300

250

200

150

100

CLKin Source

HCSL

Foffset=20 MHz

-140

-145

-150

-155

-160

-165

Int. BW=1-20 MHz

LVCMOS

CLKin Source

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.5

1.0

1.5

2.0

2.5

3.0

3.5

DIFFERENTIAL INPUT SLEW RATE (V/ns)

30177679

30177680

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RMS Jitter vs. CLKin Slew Rate @ 625 MHz

RMS Jitter vs. CLKin Slew Rate @ 156.25 MHz (Note 26)

200

500

LVPECL

Fclk=625 MHz

LVDS

450

400

350

300

250

200

150

100

Fclk=156.25 MHz

Int. BW=1-20 MHz

175

150

125

100

CLKin Source

Int. BW=1-20 MHz

HCSL

CLKin Source

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.5

1.0

1.5

2.0

2.5

3.0

3.5

DIFFERENTIAL INPUT SLEW RATE (V/ns)

30177682

30177681

PSRR vs. Ripple Frequency @ 156.25 MHz

PSRR vs. Ripple Frequency @ 312.5 MHz

-50

LVPECL

Fclk=156.25 MHz

LVDS

Fclk=312.5 MHz

LVDS

HCSL

-55

-60

-65

-70

-75

-80

-85

-90

-55

-60

-65

-70

-75

-80

-85

-90

Vcco Ripple=100 mVpp

HCSL

Vcco Ripple=100 mVpp

RIPPLE FREQUENCY (MHz)

30177683

30177684

Propagation Delay vs. Temperature

LVPECL Phase Noise @ 100 MHz (Note 26)

850

1950

LVPECL (0.35 ps/°C)

LVDS (0.35 ps/°C)

HCSL (0.35 ps/°C)

LVCMOS (2.2 ps/°C)

750

650

550

450

350

250

1850

1750

1650

1550

1450

1350

Right Y-axis plot

-50 -25

75 100

TEMPERATURE (°C)

30177685

30177695

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LVDS Phase Noise @ 100 MHz (Note 26)

HCSL Phase Noise @ 100 MHz (Note 26)

30177696

30177697

Crystal Power Dissipation vs. R_LIM

LVDS Phase Noise in Crystal Mode

(Note 27, Note 28)

-60

200

20 MHz Crystal, Rlim = 1.5 kΩ

20 MHz Crystal

40 MHz Crystal, Rlim = 1.0 kΩ

-80

40 MHz Crystal

175

150

125

100

-100

-120

-140

-160

-180

100

10k 100k 1M 10M

500 1k 1.5k 2k 2.5k 3k 3.5k 4k

(Ω)

OFFSET FREQUENCY (Hz)

LIM

30177632

30177631

Note 26: The typical RMS jitter values in the plots show the total output RMS jitter (J_OUT) for each output buffer type and the source clock RMS jitter (J_SOURCE).

From these values, the Additive RMS Jitter can be calculated as: J_ADD= SQRT(J_OUT²- J_SOURCE²).

Note 27: 20 MHz crystal characteristics: Abracon ABL series, AT cut, C_L= 18 pF , C₀= 4.4 pF measured (7 pF max), ESR = 8.5 Ω measured (40 Ω max), and

Drive Level = 1 mW max (100 µW typical).

Note 28: 40 MHz crystal characteristics: Abracon ABLS2 series, AT cut, C_L= 18 pF , C₀= 5 pF measured (7 pF max), ESR = 5 Ω measured (40 Ω max), and

Drive Level = 1 mW max (100 µW typical).

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14.0 Application Information

14.1 Driving the Clock Inputs

The LMK00308 has two universal inputs (CLKin0/CLKin0*

and CLKin1/CLKin1*) that can accept AC- or DC-coupled

3.3V/2.5V LVPECL, LVDS, CML, SSTL, and other differential

and single-ended signals that meet the input requirements

specified in the Section 11.0 Electrical Characteristics. The

device can accept a wide range of signals due to its wide input

common mode voltage range (V_CM) and input voltage swing

(V_ID) / dynamic range. For 50% duty cycle and DC-balanced

signals, AC coupling may also be employed to shift the input

signal to within the V_CMrange. Refer to Section 14.3 Termi-

nation and Use of Clock Drivers for signal interfacing and

termination techniques.

30177629

FIGURE 4. Single-Ended LVCMOS Input, DC Coupling

with Common Mode Biasing

If the crystal oscillator circuit is not used, it is possible to drive

the OSCin input with an single-ended external clock as shown

in Figure 5. The input clock should be AC coupled to the OS-

Cin pin, which has an internally-generated input bias voltage,

and the OSCout pin should be left floating. While OSCin pro-

vides an alternative input to multiplex an external clock, it is

recommended to use either differential input (CLKinX) since

it offers higher operating frequency, better common mode and

power supply noise rejection, and greater performance over

supply voltage and temperature variations.

To achieve the best possible phase noise and jitter perfor-

mance, it is mandatory for the input to have high slew rate of

3 V/ns (differential) or higher. Driving the input with a lower

slew rate will degrade the noise floor and jitter. For this rea-

son, a differential signal input is recommended over single-

ended because it typically provides higher slew rate and

common-mode-rejection. Refer to the “Noise Floor vs. CLKin

Slew Rate” and “RMS Jitter vs. CLKin Slew Rate” plots in

Section 13.0 Typical Performance Characteristics.

While it is recommended to drive the CLKin0 and CLKin1 with

a differential signal input, it is possible to drive them with a

single-ended clock. Again, the single-ended input slew rate

should be as high as possible to minimize performance degra-

dation. The CLKin input has an internal bias voltage of about

1.4 V, so the input can be AC coupled as shown in Figure 3.

30177630

FIGURE 5. Driving OSCin with a Single-Ended Input

14.2 Crystal Interface

The LMK00308 has an integrated crystal oscillator circuit that

supports a fundamental mode, AT-cut crystal. The crystal in-

terface is shown in Figure 6.

30177628

FIGURE 3. Single-Ended LVCMOS Input, AC Coupling

A single-ended clock may also be DC coupled to CLKinX as

shown in Figure 4. If the DC coupled input swing has a com-

mon mode level near the device's internal bias voltage of 1.4

V, then only a 0.1 uF bypass cap is required on CLKinX*.

Otherwise, if the input swing is not optimally centered near

the internal bias voltage, then CLKinX* should be externally

biased to the midpoint voltage of the input swing. This can be

achieved using external biasing resistors, R_B1and R_B2, or an-

other low-noise voltage reference. The external bias voltage

should be within the specified input common voltage (V_CM

)

30177609

range. This will ensure the input swing crosses the threshold

voltage at a point where the input slew rate is the highest.

FIGURE 6. Crystal Interface

The load capacitance (C_L) is specific to the crystal, but usually

on the order of 18 - 20 pF. While C_Lis specified for the crystal,

the OSCin input capacitance (C_IN= 1 pF typical) of the device

and PCB stray capacitance (C_STRAY~ 1~3 pF) can affect the

discrete load capacitor values, C₁and C₂.

For the parallel resonant circuit, the discrete capacitor values

can be calculated as follows:

C_L= (C₁* C₂) / (C₁+ C₂) + C_IN+ C_STRAY

(1)

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Typically, C₁= C₂for optimum symmetry, so Equation 1 can

be rewritten in terms of C₁only:

C_L= C₁²/ (2 * C₁) + C_IN+ C_STRAY

Finally, solve for C₁:

C₁= (C_L- C_IN- C_STRAY)*2

(2)

(3)

30177620

Section 11.0 Electrical Characteristics provides crystal inter-

face specifications with conditions that ensure start-up of the

crystal, but it does not specify crystal power dissipation. The

designer will need to ensure the crystal power dissipation

does not exceed the maximum drive level specified by the

crystal manufacturer. Overdriving the crystal can cause pre-

mature aging, frequency shift, and eventual failure. Drive level

should be held at a sufficient level necessary to start-up and

maintain steady-state operation.

FIGURE 7. Differential LVDS Operation, DC Coupling,

No Biasing by the Receiver

For DC coupled operation of an HCSL driver, terminate with

50 Ω to ground near the driver output as shown in Figure 8.

Series resistors, Rs, may be used to limit overshoot due to

the fast transient current. Because HCSL drivers require a DC

path to ground, AC coupling is not allowed between the output

drivers and the 50 Ω termination resistors.

The power dissipated in the crystal, P_XTAL, can be computed

by:

P_XTAL= I_RMS²* R_ESR*(1 + C₀/C_L)²

(4)

Where:

•

I_RMSis the RMS current through the crystal.

R_ESRis the max. equivalent series resistance specified for

the crystal

•

C_Lis the load capacitance specified for the crystal

C₀is the min. shunt capacitance specified for the crystal

I_RMScan be measured using a current probe (e.g. Tektronix

CT-6 or equivalent) placed on the leg of the crystal connected

to OSCout with the oscillation circuit active.

As shown in Figure 6, an external resistor, R_LIM, can be used

to limit the crystal drive level, if necessary. If the power dissi-

pated in the selected crystal is higher than the drive level

specified for the crystal with R_LIMshorted, then a larger resis-

tor value is mandatory to avoid overdriving the crystal. How-

ever, if the power dissipated in the crystal is less than the drive

level with R_LIMshorted, then a zero value for R_LIMcan be used.

As a starting point, a suggested value for R_LIMis 1.5 kΩ.

30177690

FIGURE 8. HCSL Operation, DC Coupling

For DC coupled operation of an LVPECL driver, terminate

with 50 Ω to Vcco - 2 V as shown in Figure 9. Alternatively

terminate with a Thevenin equivalent circuit as shown in Fig-

ure 10 for Vcco (output driver supply voltage) = 3.3 V and 2.5

V. In the Thevenin equivalent circuit, the resistor dividers set

the output termination voltage (V_TT) to Vcco - 2 V.

14.3 Termination and Use of Clock Drivers

When terminating clock drivers keep in mind these guidelines

for optimum phase noise and jitter performance:

•

Transmission line theory should be followed for good

impedance matching to prevent reflections.

•

Clock drivers should be presented with the proper loads.

LVDS outputs are current drivers and require a closed

current loop.

HCSL drivers are switched current outputs and require

a DC path to ground via 50 Ω termination.

LVPECL outputs are open emitter and require a DC

—

path to ground.

•

Receivers should be presented with a signal biased to

their specified DC bias level (common mode voltage) for

proper operation. Some receivers have self-biasing inputs

that automatically bias to the proper voltage level; in this

case, the signal should normally be AC coupled.

30177621

It is possible to drive a non-LVPECL or non-LVDS receiver

with a LVDS or LVPECL driver as long as the above guide-

lines are followed. Check the datasheet of the receiver or

input being driven to determine the best termination and cou-

pling method to be sure the receiver is biased at the optimum

DC voltage (common mode voltage).

FIGURE 9. Differential LVPECL Operation, DC Coupling

14.3.1 Termination for DC Coupled Differential Operation

For DC coupled operation of an LVDS driver, terminate with

100 Ω as close as possible to the LVDS receiver as shown in

Figure 7.

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DC coupled example in Figure 10, since the voltage divider is

setting the input common mode voltage of the receiver.

30177622

30177624

FIGURE 10. Differential LVPECL Operation, DC Coupling,

Thevenin Equivalent

FIGURE 12. Differential LVPECL Operation, AC Coupling,

Thevenin Equivalent

14.3.2 Termination for AC Coupled Differential Operation

14.3.3 Termination for Single-Ended Operation

AC coupling allows for shifting the DC bias level (common

mode voltage) when driving different receiver standards.

Since AC coupling prevents the driver from providing a DC

bias voltage at the receiver, it is important to ensure the re-

ceiver is biased to its ideal DC level.

A balun can be used with either LVDS or LVPECL drivers to

convert the balanced, differential signal into an unbalanced,

single-ended signal.

It is possible to use an LVPECL driver as one or two separate

800 mV p-p signals. When DC coupling one of the LMK00308

LVPECL driver of a CLKoutX/CLKoutX* pair, be sure to prop-

erly terminate the unused driver. When DC coupling on of the

LMK00308 LVPECL drivers, the termination should be 50 Ω

to Vcco - 2 V as shown in Figure 13. The Thevenin equivalent

circuit is also a valid termination as shown in Figure 14 for

Vcco = 3.3 V.

When driving non-biased LVDS receivers with an LVDS driv-

er, the signal may be AC coupled by adding DC blocking

capacitors; however the proper DC bias point needs to be

established at the receiver. One way to do this is with the ter-

mination circuitry in Figure 11. When driving self-biased

LVDS receivers, the circuit shown in Figure 11 may be mod-

ified by replacing the 50 Ω terminations to Vbias with a single

100 Ω resistor across the input pins of the receiver. When

using AC coupling with LVDS outputs, there may be a startup

delay observed in the clock output due to capacitor charging.

The previous example uses a 0.1 μF capacitor, but this may

need to be adjusted to meet the startup requirements for the

particular application. Another variant of AC coupling to a self-

biased LVDS receiver is to move the 0.1 uF capacitors be-

tween the 100 Ω differential termination and the receiver

inputs.

30177625

FIGURE 13. Single-Ended LVPECL Operation, DC

Coupling

30177623

FIGURE 11. Differential LVDS Operation, AC Coupling,

No Biasing by the Receiver

LVPECL drivers require a DC path to ground. When AC cou-

pling an LVPECL signal use 160 Ω emitter resistors (or 91

Ω for Vcco = 2.5 V) close to the LVPECL driver to provide a

DC path to ground as shown in Figure 15. For proper receiver

operation, the signal should be biased to the DC bias level

(common mode voltage) specified by the receiver. The typical

DC bias voltage (common mode voltage) for LVPECL re-

ceivers is 2 V. Alternatively, a Thevenin equivalent circuit

forms a valid termination as shown in Figure 12 for Vcco = 3.3

V and 2.5 V. Note: this Thevenin circuit is different from the

30177626

FIGURE 14. Single-Ended LVPECL Operation, DC

Coupling, Thevenin Equivalent

When AC coupling an LVPECL driver use a 160 Ω emitter

resistor (or 91 Ω for Vcco = 2.5 V) to provide a DC path to

ground and ensure a 50 Ω termination with the proper DC bias

level for the receiver. The typical DC bias voltage for LVPECL

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receivers is 2 V. If the companion driver is not used, it should

be terminated with either a proper AC or DC termination. This

latter example of AC coupling a single-ended LVPECL signal

can be used to measure single-ended LVPECL performance

using a spectrum analyzer or phase noise analyzer. When

using most RF test equipment no DC bias point (0 VDC) is

required for safe and proper operation. The internal 50 Ω ter-

mination the test equipment correctly terminates the LVPECL

driver being measured as shown in Figure 15. When using

only one LVPECL driver of a CLKoutX/CLKoutX* pair, be sure

to properly terminated the unused driver.

30177627

FIGURE 15. Single-Ended LVPECL Operation, AC

Coupling

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14.4 Power Supply and Thermal Considerations

14.4.1 Current Consumption and Power Dissipation Calculations

The current consumption values specified in Section 11.0 Electrical Characteristics can be used to calculate the total power dis-

sipation and IC power dissipation for any device configuration. The total V_CCcore supply current (I_{CC_TOTAL}) can be calculated

using Equation 5:

I_{CC_TOTAL}= I_{CC_CORE}+ I_{CC_BANK_A}+ I_{CC_BANK_B}+ I_{CC_CMOS}

(5)

Where:

•

I_{CC_CORE}is the current for core logic and input blocks and depends on selected input (CLKinX or OSCin).

I_{CC_BANK_A}is the current for Bank A and depends on output type (I_{CC_PECL}, I_{CC_LVDS}, I_{CC_HCSL}, or 0 mA if disabled).

I_{CC_BANK_B}is the current for Bank B and depends on output type (I_{CC_PECL}, I_{CC_LVDS}, I_{CC_HCSL}, or 0 mA if disabled).

I_{CC_CMOS}is the current for the LVCMOS output (or 0 mA if REFout is disabled).

Since the output supplies (V_CCOA, V_CCOB, V_CCOC) can be powered from 3 independent voltages, the respective output supply

currents (I_{CCO_BANK_A}, I_{CCO_BANK_B}, and I_{CCO_CMOS}) should be calculated separately.

I_{CCO_BANK}for either Bank A or B can be directly taken from the corresponding output supply current spec (I_{CCO_PECL}, I_{CCO_LVDS}, or

I_{CCO_HCSL}) provided the output loading matches the specified conditions. Otherwise, I_{CCO_BANK}should be calculated as fol-

lows:

I_{CCO_BANK}= I_{BANK_BIAS}+ (N * I_{OUT_LOAD}

)

(6)

Where:

•

I_{BANK_BIAS}is the output bank bias current (fixed value).

I_{OUT_LOAD}is the DC load current per loaded output pair.

N is the number of loaded output pairs per bank (N = 0 to 4).

Table 5 shows the typical I_{BANK_BIAS}values and I_{OUT_LOAD}expressions for LVPECL, LVDS, and HCSL.

For LVPECL, it is possible to use a larger termination resistor (R_T) to ground instead of terminating with 50 Ω to V_TT= Vcco - 2 V;

this technique is commonly used to eliminate the extra termination voltage supply (V_TT) and potentially reduce device power

dissipation at the expense of lower output swing. For example, when Vcco is 3.3 V, a R_Tvalue of 160 Ω to ground will eliminate

the 1.3 V termination supply without sacrificing much output swing. In this case, the typical I_{OUT_LOAD}is 25 mA, so I_{CCO_PECL}for a

fully-loaded bank reduces to 126.5 mA (vs. 132 mA with 50 Ω resistors to Vcco - 2 V).

TABLE 5. Typical Output Bank Bias and Load Currents

Current Parameter

LVPECL

LVDS

HCSL

I_{BANK_BIAS}

26.5 mA

26 mA

4.8 mA

0 mA

(No DC load current)

I_{OUT_LOAD}

(V_OH- V_TT)/R_T+ (V_OL- V_TT)/R_T

V_OH/R_T

Once the current consumption is calculated for each supply, the total power dissipation (P_TOTAL) can be calculated as:

P_TOTAL= (V_CC*I_{CC_TOTAL}) + (V_CCOA*I_{CCO_BANK_A}) + (V_CCOB*I_{CCO_BANK_B}) + (V_CCOC*I_{CCO_CMOS}

)

(7)

If the device configuration is configured with LVPECL and/or HCSL outputs, then it is also necessary to calculate the power

dissipated in any termination resistors (P_{RT_ PECL}and P_{RT_HCSL}) and in any LVPECL termination voltages (P_{VTT_PECL}). The external

power dissipation values can be calculated as follows:

P_{RT_PECL}(per LVPECL pair) = (V_OH- V_TT)²/R_T+ (V_OL- V_TT)²/R_T

P_{VTT_PECL}(per LVPECL pair) = V_TT* [(V_OH- V_TT)/R_T+ (V_OL- V_TT)/R_T]

P_{RT_HCSL}(per HCSL pair) = V_OH²/ R_T

(8)

(9)

(10)

Finally, the IC power dissipation (P_DEVICE) can be computed by subtracting the external power dissipation values from P_TOTALas

follows:

P_DEVICE= P_TOTAL- N₁*(P_{RT_PECL}+ P_{VTT_PECL}) - N₂*P_{RT_HCSL}

(11)

Where:

•

N₁is the number of LVPECL output pairs with termination resistors to V_TT(usually Vcco - 2 V or GND).

N₂is the number of HCSL output pairs with termination resistors to GND.

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14.4.1.1 Power Dissipation Example: Worst-Case Dissipation

This example shows how to calculate IC power dissipation for a configuration to estimate worst-case power dissipation. In this

case, the maximum supply voltage and supply current values specified in Section 11.0 Electrical Characteristics are used.

•

V_CC= V_CCO= 3.465 V. Max I_CCand I_CCOvalues.

CLKin0/CLKin0* input is selected.

Banks A and B are configured for LVPECL: all outputs terminated with 50 Ω to V_T= Vcco - 2 V.

REFout is enabled with 5 pF load.

T_A= 85 °C

Using the power calculations from the previous section and maximum supply current specifications, we can compute P_TOTALand

P_DEVICE

•

From Equation 5: I_{CC_TOTAL}= 10.5 mA + 20 mA + 20 mA + 5.5 mA = 56 mA

From I_{CCO_PECL}max spec: I_{CCO_BANK_A}= I_{CCO_BANK_B}= 160 mA

From Equation 7: P_TOTAL= 3.465 V * (56 mA + 160 mA + 160 mA + 10 mA) = 1337 mW

From Equation 8: P_{RT_PECL}= ((2.57 V - 1.47 V)²/50 Ω) + ((1.72 V - 1.47 V)²/50 Ω) = 25.5 mW (per output pair)

From Equation 9: P_{VTT_PECL}= 1.47 V * [ ((2.57 V - 1.47 V) / 50 Ω) + ((1.72 V - 1.47 V) / 50 Ω) ] = 39.5 mW (per output pair)

From Equation 10: P_{RT_HCSL}= 0 mW (no HCSL outputs)

From Equation 11: P_DEVICE= 1337 mW - (8 * (25.5 mW + 39.5 mW)) – 0 mW = 817 mW

In this worst-case example, the IC device will dissipate about 817 mW or 61% of the total power (1337 mW), while the remaining

39% will be dissipated in the LVPECL emitter resistors (204 mW for 8 pairs) and termination voltage (316 mW into Vcco - 2 V).

Based on θ_JAof 31.4 °C/W, the estimated die junction temperature would be about 26 °C above ambient, or 111 °C when T_A= 85

°C.

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14.4.2 Power Supply Bypassing

phase spur levels for the differential output types at 156.25

MHz and 312.5 MHz . The LMK00308 exhibits very good and

well-behaved PSRR characteristics across the ripple frequen-

cy range for all differential output types. The phase spur levels

for LVPECL are below -64 dBc at 156.25 MHz and below -62

dBc at 312.5 MHz. Using Equation 12, these phase spur lev-

els translate to Deterministic Jitter values of 2.57 ps pk-pk at

156.25 MHz and 1.62 ps pk-pk at 312.5 MHz. Testing has

shown that the PSRR performance of the device improves for

Vcco = 3.3 V under the same ripple amplitude and frequency

conditions.

The Vcc and Vcco power supplies should have a high-fre-

quency bypass capacitor, such as 0.1 uF or 0.01 uF, placed

very close to each supply pin. 1 uF to 10 uF decoupling ca-

pacitors should also be placed nearby the device between the

supply and ground planes. All bypass and decoupling capac-

itors should have short connections to the supply and ground

plane through a short trace or via to minimize series induc-

tance.

14.4.2.1 Power Supply Ripple Rejection

In practical system applications, power supply noise (ripple)

can be generated from switching power supplies, digital

ASICs or FPGAs, etc. While power supply bypassing will help

filter out some of this noise, it is important to understand the

effect of power supply ripple on the device performance.

When a single-tone sinusoidal signal is applied to the power

supply of a clock distribution device, such as LMK00308, it

can produce narrow-band phase modulation as well as am-

plitude modulation on the clock output (carrier). In the single-

side band phase noise spectrum, the ripple-induced phase

modulation appears as a phase spur level relative to the car-

rier (measured in dBc).

14.4.3 Thermal Management

Power dissipation in the LMK00308 device can be high

enough to require attention to thermal management. For re-

liability and performance reasons the die temperature should

be limited to a maximum of 125 °C. That is, as an estimate,

T_A(ambient temperature) plus device power dissipation times

_JAshould not exceed 125 °C.

The package of the device has an exposed pad that provides

the primary heat removal path as well as excellent electrical

grounding to the printed circuit board. To maximize the re-

moval of heat from the package a thermal land pattern in-

cluding multiple vias to a ground plane must be incorporated

on the PCB within the footprint of the package. The exposed

pad must be soldered down to ensure adequate heat con-

duction out of the package.

For the LMK00308, power supply ripple rejection, or PSRR,

was measured as the single-sideband phase spur level (in

dBc) modulated onto the clock output when a ripple signal

was injected onto the Vcco supply. The PSRR test setup is

shown in Figure 16.

A recommended land and via pattern is shown in Figure 17.

More information on soldering LLP packages can be obtained

at: http://www.national.com/analog/packaging/.

A recommended footprint including recommended solder

mask and solder paste layers can be found at: http://

www.national.com/analog/packaging/gerber for the SQA40A

package.

30177640

FIGURE 16. PSRR Test Setup

A signal generator was used to inject a sinusoidal signal onto

the Vcco supply of the DUT board, and the peak-to-peak rip-

ple amplitude was measured at the Vcco pins of the device.

A limiting amplifier was used to remove amplitude modulation

on the differential output clock and convert it to a single-ended

signal for the phase noise analyzer. The phase spur level

measurements were taken for clock frequencies of 156.25

MHz and 312.5 MHz under the following power supply ripple

conditions:

30177673

FIGURE 17. Recommended Land and Via Pattern

To minimize junction temperature it is recommended that a

simple heat sink be built into the PCB (if the ground plane

layer is not exposed). This is done by including a copper area

of about 2 square inches on the opposite side of the PCB from

the device. This copper area may be plated or solder coated

to prevent corrosion but should not have conformal coating (if

possible), which could provide thermal insulation. The vias

shown in Figure 17 should connect these top and bottom

copper layers and to the ground layer. These vias act as “heat

pipes” to carry the thermal energy away from the device side

of the board to where it can be more effectively dissipated.

•

Ripple amplitude: 100 mVpp on Vcco = 2.5 V

Ripple frequencies: 100 kHz, 1 MHz, and 10 MHz

Assuming no amplitude modulation effects and small index

modulation, the peak-to-peak deterministic jitter (DJ) can be

calculated using the measured single-sideband phase spur

level (PSRR) as follows:

DJ (ps pk-pk) = [(2*10^{(PSRR / 20)}) / (π*f_CLK)] * 10¹²

(12)

The “PSRR vs. Ripple Frequency” plots in Section 13.0 Typ-

ical Performance Characteristics show the ripple-induced

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15.0 Physical Dimensions inches (millimeters) unless otherwise noted

40 Pin LLP (SQA40A) Package

Order Number

LMK00308SQX

LMK00308SQ

LMK00308SQE

Package Marking

Packing

2500 Unit Tape and Reel

1000 Unit Tape and Reel

250 Unit Tape and Reel

LMK00308

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Notes

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LMK00308SQX/NOPB [TI]

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