LMK1C1103PWR [TI]
3 通道输出 LVCMOS 1.8V 缓冲器 | PW | 8 | -40 to 125;
| 型号： | LMK1C1103PWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3 通道输出 LVCMOS 1.8V 缓冲器 | PW | 8 | -40 to 125 |
| 文件： | 总26页 (文件大小：1711K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMK1C1102, LMK1C1103, LMK1C1104
ZHCSKK6D –DECEMBER 2019 –REVISED FEBRUARY 2022
LMK1C110x 1.8V、2.5V 和3.3V LVCMOS 时钟缓冲器系列
1 特性
3 说明
• 高性能1:2、1:3 或1:4 LVCMOS 时钟缓冲器
• 输出偏斜极低，< 50ps
• 附加抖动极低，最大值< 50fs
– VDD = 3.3V 时，典型值为7.5fs
– VDD = 2.5V 时，典型值为10fs
– VDD = 1.8V 时，典型值为19.2fs
• 传播延迟极低，< 3ns
LMK1C110x 是德州仪器 (TI) 的一款模块化、高性能、
低偏斜、通用时钟缓冲器系列器件。整个系列采用模块
化方法设计。提供三个不同的扇出选项：1:2、1:3、
1:4。
该系列所有器件均互相引脚兼容， 并向后兼容
CDCLVC110x 系列，便于操作。
该系列所有器件均具有相同的高性能特性，如低附加抖
动、低偏斜和宽工作温度范围。
• 同步输出使能
• 电源电压：3.3V、2.5V 或1.8V
– 在所有的电源电压下3.3V 的容差输入
– 失效防护输入
• fmax = 250MHz (3.3V)
fmax = 200MHz（2.5V 和1.8V）
• 工作温度范围：–40°C 至125°C
• 采用8 引脚TSSOP 封装
• 采用8 引脚WSON 封装
LMK1C110x 具有同步输出使能控制端 (1G)，可在 1G
处于低电平时将输出切换为低电平状态。这些器件具有
失效防护输入，可防止在没有输入信号的情况下输出发
生振荡并允许在提供VDD 之前输入信号。
LMK1C110x 系列可在 1.8V、2.5V 和 3.3V 电压下工
作，其特点是可在–40°C 至125°C 的范围内运行。
器件信息(1)
2 应用
封装尺寸（标称值）
零件编号
LMK1C1102
封装
• 工厂自动化与控制
• 电信设备
• 数据中心和企业计算
• 电网基础设施
• 电机驱动器
LMK1C1103
LMK1C1104
LMK1C1102
LMK1C1104
TSSOP (8)
3.00mm × 4.40mm
2.00mm x 2.00mm
WSON (8)
• 医疗成像
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
CLKIN
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Y0
Y1
Y2
Y3
1G
功能框图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNAS791
LMK1C1102, LMK1C1103, LMK1C1104
ZHCSKK6D –DECEMBER 2019 –REVISED FEBRUARY 2022
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Table of Contents
9.3 Feature Description...................................................10
9.4 Device Functional Modes..........................................10
10 Application and Implementation................................ 11
10.1 Application Information............................................11
10.2 Typical Application.................................................. 11
11 Power Supply Recommendations..............................13
12 Layout...........................................................................14
12.1 Layout Guidelines................................................... 14
12.2 Layout Example...................................................... 14
13 Device and Documentation Support..........................15
13.1 接收文档更新通知................................................... 15
13.2 支持资源..................................................................15
13.3 Trademarks.............................................................15
13.4 Electrostatic Discharge Caution..............................15
13.5 术语表..................................................................... 15
14 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison.........................................................3
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................6
7.6 Timing Requirements..................................................7
7.7 Typical Characteristics................................................7
8 Parameter Measurement Information............................8
9 Detailed Description......................................................10
9.1 Overview...................................................................10
9.2 Functional Block Diagram.........................................10
Information.................................................................... 15
4 Revision History
Changes from Revision C (June 2021) to Revision D (February 2022)
Page
• 向说明部分中新增了失效防护输入详细信息...................................................................................................... 1
• Changed part-to-part skew maximum from 450 ps to 250 ps.............................................................................6
• Added the Fail-Safe Inputs section...................................................................................................................10
Changes from Revision B (June 2020) to Revision C (June 2021)
Page
• 更改了整个文档中的表、图和交叉参考的文本格式和编号格式...........................................................................1
• 新增了LMK1C1102/04 DQF (WSON) 封装........................................................................................................1
• Added the Device Comparison table.................................................................................................................. 3
• Added pinout diagrams for the DQF (WSON) package variant of the LMK1C1102 and LMK1C1104................3
• Added information pertaining to the layout of LMK1C1102/04 WSON package variant...................................14
• Removed Related Links section....................................................................................................................... 15
Changes from Revision A (February 2020) to Revision B (June 2020)
Page
• 向说明部分新增了扇出选项信息........................................................................................................................ 1
• 从第一页中删除LMK1C1104PW 引脚排列.........................................................................................................1
• Added LMK1C1102 and LMK1C1103 pinout diagrams...................................................................................... 3
Changes from Revision * (December 2019) to Revision A (February 2020)
Page
• 向数据表新增了LMK1C1102 和LMK1C1103.....................................................................................................1
• Changed the Power Supply Recommendations section...................................................................................13
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5 Device Comparison
表5-1. Device Comparison
DEVICE
NUMBER OF OUTPUTS
PACKAGE
LMK1C1102
LMK1C1103
LMK1C1104
LMK1C1106
LMK1C1108
LMK1C1102
LMK1C1104
2
3
4
6
8
2
4
TSSOP (8), 3.00 mm x 4.40 mm
TSSOP (14), 5.00 mm x 4.40 mm
TSSOP (16), 5.00 mm x 4.40 mm
WSON (8), 2.00 mm x 2.00 mm
6 Pin Configuration and Functions
CLKIN
1G
1
2
3
4
8
7
6
5
Y1
CLKIN
1G
1
2
Y1
8
7
NC
VDD
NC
NC
Y0
Y0
3
4
6
VDD
NC
GND
GND
5
Not to scale
Not to scale
1. The DQF (WSON) package is equivalent to the DFN
package of other vendors.
图6-1. LMK1C1102 PW Package 8-Pin TSSOP Top
View
图6-2. LMK1C1102 DQF Package 8-Pin WSON Top
View
CLKIN
1G
1
2
3
4
8
7
6
5
Y1
CLKIN
1G
1
2
3
4
8
7
6
5
Y1
NC
VDD
Y2
Y3
Y0
Y0
VDD
Y2
GND
GND
Not to scale
Not to scale
图6-3. LMK1C1103 PW Package 8-Pin TSSOP Top
图6-4. LMK1C1104 PW Package 8-Pin TSSOP Top
View
View
CLKIN
1G
1
2
Y1
Y3
8
7
Y0
3
4
6
VDD
Y2
GND
5
Not to scale
1. The DQF (WSON) package is equivalent to the DFN package of other vendors.
图6-5. LMK1C1104 DQF Package 8-Pin WSON Top View
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表6-1. Pin Functions
PIN
TYPE
DESCRIPTION
LMK1C
1102
LMK1C
1103
LMK1C
1104
NAME
LVCMOS CLOCK INPUT
CLKIN
CLOCK OUTPUT ENABLE
Single-ended clock input with internal 300-kΩ(typical) pulldown
resistor to GND. Typically connected to a single-ended clock input.
1
1
2
1
2
Input
Input
Global Output Enable with internal 300-kΩ (typical) pulldown resistor to
GND. Typically connected to VDD with external pullup resistor.
HIGH: outputs enabled
1G
2
LOW: outputs disabled
LVCMOS CLOCK OUTPUT
Y0
Y1
Y2
Y3
3
8
3
8
3
8
5
7
LVCMOS output. Typically connected to a receiver. Unused outputs
can be left floating.
Output
5
—
—
—
SUPPLY VOLTAGE
Power supply terminal. Typically connected to a 3.3-V, 2.5-V, or 1.8-V
supply. The VDD pin is typically connected to an external 0.1-μF
capacitor near the pin.
VDD
6
4
6
4
6
4
Power
GND
GROUND
GND
Power supply ground.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
VDD
VCLKIN
VIN
Supply voltage
Input voltage (CLKIN)
Input voltage (1G)
Output pins (Yn)
3.6
–0.5
V
VYn
IIN
VDD + 0.3
20
–0.5
–20
–50
–65
Input current
mA
mA
°C
IO
Continuous output current
Storage temperature
50
Tstg
150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±9000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.135
2.375
1.71
NOM
3.3
MAX
3.465
2.625
1.89
125
UNIT
3.3-V supply
2.5-V supply
1.8-V supply
VDD
Core supply voltage
2.5
V
1.8
TA
TJ
Operating free-air temperature
Operating junction temperature
°C
°C
–40
–40
150
7.4 Thermal Information
LMK1C1104
THERMAL METRIC(1)
DQF(WSON)
8 PINS
163
PW (TSSOP)
8 PINS
181.9
UNIT
RqJA
RqJC(top)
RqJB
YJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
105.7
84.2
76.6
111.6
Junction-to-top characterization parameter
Junction-to-board characterization parameter
16.7
16
YJB
83.9
110.1
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
VDD = 3.3 V ± 5 %, –40°C ≤TA ≤125°C. Typical values are at VDD = 3.3 V, 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT CONSUMPTION
IDD
Core supply current, static
Core supply current
All-outputs disabled, fIN = 0 V
25
8
45
15
µA
All-outputs disabled, fIN = 100 MHz
All-outputs active, fIN = 100 MHz, CL = 5pF,
VDD = 1.8 V
14
21
33
20
30
40
IDD
mA
All-outputs active, fIN = 100 MHz, CL = 5pF,
VDD = 2.5 V
All-outputs active, fIN = 100 MHz, CL = 5pF,
VDD = 3.3 V
CLOCK INPUT
VDD = 3.3 V
DC
DC
250
200
fIN_SE
Input frequency
MHz
V
VDD = 2.5 V and 1.8 V
VIH
Input high voltage
Input low voltage
Input slew rate
0.7 x VDD
VIL
0.3 x VDD
50
dVIN/dt
IIN_LEAK
CIN_SE
20% - 80% of input swing
at 25°C
0.1
V/ns
uA
Input leakage current
Input capacitance
–50
7
pF
CLOCK OUTPUT FOR ALL VDD LEVELS
VDD = 3.3 V
250
200
55
3
fOUT
Output frequency
MHz
VDD = 2.5 V and 1.8 V
With 50% duty cycle input (for all VDD)
ODC
Output duty cycle
45
%
tSTART
t1G_ON
t1G_OFF
Start-up time before output is active See (1)
ms
Output enable time
Output disable time
See (2)
See (3)
5
cycles
cycles
5
CLOCK OUTPUT FOR VDD = 3.3 V ± 5%
VOH
Output high voltage
Output low voltage
IOH = 1 mA
2.8
V
VOL
IOL = 1 mA
0.2
0.7
tRISE-FALL
Output rise and fall time
20/80%, CL= 5 pF, fIN = 156.25 MHz
0.35
25
ns
tOUTPUT-
Output-output skew
See (4)
50
SKEW
ps
ns
tPART-SKEW Part-to-part skew
tPROP-DELAY Propagation delay
250
2
See (5)
1.5
8
fIN = 156.25 MHz, Input slew rate = 2 V/ns,
Integration range = 12 kHz - 20 MHz
tJITTER-ADD Additive Jitter
20 fs, RMS
ROUT
Output impedance
50
Ω
CLOCK OUTPUT FOR VDD = 2.5 V ± 5%
VOH
Output high voltage
Output low voltage
IOH = 1 mA
0.8 x VDD
V
VOL
IOL = 1 mA
0.2 x VDD
0.8
tRISE-FALL
Output rise and fall time
20/80%, CL= 5 pF, fIN = 156.25 MHz
0.33
ns
ps
ns
tOUTPUT-
Output-output skew
See (4)
50
SKEW
tPART-SKEW Part-to-part skew
tPROP-DELAY Propagation delay
400
2.5
See (5)
1.5
11
fIN = 156.25 MHz, Input slew rate = 2 V/ns,
Integration range = 12 kHz - 20 MHz
tJITTER-ADD Additive Jitter
27 fs, RMS
ROUT
Output impedance
52.5
Ω
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VDD = 3.3 V ± 5 %, –40°C ≤TA ≤125°C. Typical values are at VDD = 3.3 V, 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CLOCK OUTPUT FOR VDD = 1.8 V ± 5%
VOH
Output high voltage
Output low voltage
IOH = 1 mA
IOL = 1 mA
0.8 x VDD
V
VOL
0.2 x VDD
1
tRISE-FALL
Output rise and fall time
20/80%, CL= 5 pF, fIN = 156.25 MHz
See (4)
0.38
ns
ps
tOUTPUT-
Output-output skew
50
SKEW
tPART-SKEW Part-to-part skew
tPROP-DELAY Propagation delay
900
3
ps
ns
See (5)
1.5
17.5
60
fIN = 156.25 MHz, Input slew rate = 2 V/ns,
Integration range = 12 kHz - 20 MHz
tJITTER-ADD Additive Jitter
50 fs, RMS
ROUT
Output impedance
Ω
GENERAL PURPOSE INPUT (1G)
0.75 x
VDD
VIH
VIL
High-level input voltage
Low-level input voltage
V
0.25 x
VDD
IIH
IIL
Input high-level current
Input low-level current
VIH = VDD_REF
VIL = GND
50
–50
–50
µA
50
(1) Measured from VDD stable to output active, when 1G = HIGH.
(2) Measured from 1G rising edge crossing VIH to first rising edge of Yn.
(3) Measured from 1G falling edge crossing VIL to last falling edge of Yn.
(4) Measured from rising edge of any Yn output to any other Ym output.
(5) Measured from rising edge of CLKIN to any Yn output.
7.6 Timing Requirements
VDD = 3.3 V ± 5 %, –40°C ≤TA ≤125°C
MIN
NOM
MAX
UNIT
POWER SUPPLY
V/tRAMP VDD ramp rate
0.1
50
V/ms
7.7 Typical Characteristics
80
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
VDD = 1.8 V
VDD = 2.5 V
VDD = 3.3 V
0
0
25
50
75
100
125
Frequency (MHz)
150
175
200
225
250
D001
图7-1. Device Power Consumption vs. Clock Frequency (Load 5 pF)
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8 Parameter Measurement Information
VDD = 3.3-V, 2.5-V,
or 1.8-V
LVCMOS
Output
Zo = 50 ꢀ
R = 50 Ω
C = 2 pF
Parasitic capacitance
From measurement
equipment
图8-1. Test Load Circuit
VDD
VDD = 3.3-V, 2.5-V,
or 1.8-V
R = 100 Ω
LVCMOS
Output
Zo = 50 ꢀ
Parasitic capacitance
R = 100 Ω
图8-2. Application Load With 50-ΩTermination
VDD = 3.3-V, 2.5-V,
or 1.8-V
LVCMOS
Output
Zo = 50 ꢀ
Parasitic capacitance
图8-3. Application Load With Termination
CLKIN
1G
tt1G_ONt
Yn
图8-4. t1G_ON Output Enable Time
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CLKIN
1G
tt1G_OFFt
Yn
图8-5. t1G_OFF Output Disable Time
CLKIN
Yn
tPROP-DELAY
tOUTPUT-SKEW
Yn+1
图8-6. Propagation Delay tPROP-DELAY and Output Skew tOUTPUT-SKEW
80% x VDD
Yn
20% x VDD
tRISE-FALL
tRISE-FALL
图8-7. Rise and Fall Time tRISE-FALL
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9 Detailed Description
9.1 Overview
The LMK1C110x family of devices is part of a low-jitter and low-skew LVCMOS fan-out buffer solution. For best
signal integrity, it is important to match the characteristic impedance of the LMK1C110x's output driver with that
of the transmission line.
9.2 Functional Block Diagram
CLKIN
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Y0
Y1
Y2
Y3
1G
9.3 Feature Description
The outputs of the LMK1C110x can be disabled by driving the synchronous output enable pin (1G) low. Unused
output can be left floating to reduce overall system component cost. Supply and ground pins must be connected
to VDD and GND, respectively.
9.3.1 Fail-Safe Inputs
The LMK1C110x family of devices is designed to support fail-safe input operation. This feature allows the user to
drive the device inputs before VDD is applied without damaging the device. Refer to Absolute Maximum Ratings
for more information on the maximum input supported by the device. The device also incorporates an input
hysteresis that prevents random oscillation in absence of an input signal, allowing the input pins to be left open.
9.4 Device Functional Modes
The LMK1C110x operates from 1.8-V, 2.5-V, or 3.3-V supplies. 表 9-1 shows the output logics of the
LMK1C110x.
表9-1. Output Logic Table
INPUTS
OUTPUTS
CLKIN
1G
L
Yn
L
X
L
H
L
H
H
H
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10 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
10.1 Application Information
The LMK1C110x family is a low additive jitter LVCMOS buffer solution that can operate up to 250-MHz at VDD
=
3.3 V and 200 MHz at VDD = 2.5 V to 1.8 V. Low output skew as well as the ability for synchronous output enable
is featured to simultaneously enable or disable buffered clock outputs as necessary in the application.
10.2 Typical Application
100-MHz
50-ꢀ Trace
LVCMOS Oscillator
V
CMOS
DD
Y0
Y1
CPU Clock
CLKIN
CMOS
FPGA Clock
100 ꢀ
100 ꢀ
50-ꢀ Trace
1G
PLL
Yn
From CPU
Reference
GND
图10-1. System Configuration Example
10.2.1 Design Requirements
The LMK1C110x shown in 图 10-1 is configured to fan out a 100-MHz signal from a local LVCMOS oscillator.
The CPU is configured to control the output state through 1G.
The configuration example is driving three LVCMOS receivers in a backplane application with the following
properties:
• The CPU clock can accept a full swing DC-coupled LVCMOS signal. A series resistor is placed near the
LMK1C110x to closely match the characteristic impedance of the trace to minimize reflections.
• The FPGA clock is similarly DC-coupled with an appropriate series resistor placed near the LMK1C110x.
• The PLL in this example can accept a lower amplitude signal, so a Thevenin's equivalent termination is used.
The PLL receiver features internal biasing, so AC coupling can be used when common-mode voltage is
mismatched.
10.2.2 Detailed Design Procedure
Unused outputs can be left floating. See the Power Supply Recommendations section for recommended filtering
techniques.
10.2.3 Application Curves
The low additive jitter of the LMK1C110x is shown in 图10-2.
图 10-3 shows the low-noise 156.25-MHz reference source with 25.6-fs RMS jitter driving the LMK1C110x,
resulting in 26.7-fs RMS jitter when integrated from 12 kHz to 20 MHz at 3.3-V supply. The resultant additive
jitter measured is a low 7.6-fs RMS for this configuration.
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图 10-4 shows the low-noise 156.25-MHz reference source with 25.6-fs RMS jitter driving the LMK1C110x,
resulting in 27.5-fs RMS jitter when integrated from 12 kHz to 20 MHz at 2.5-V supply. The resultant additive
jitter measured is a low 10-fs RMS for this configuration.
图 10-5 shows the low-noise 156.25-MHz reference source with 25.6-fs RMS jitter driving the LMK1C110x,
resulting in 32-fs RMS jitter when integrated from 12 kHz to 20 MHz at 1.8-V supply. The resultant additive jitter
measured is a low 19.2-fs RMS for this configuration.
图10-2. LMK1C110x Reference Phase Noise 25.6-fs
图10-3. LMK1C110x 3.3-V Output Phase Noise
(12 kHz to 20 MHz)
26.7-fs (12 kHz to 20 MHz)
图10-4. LMK1C110x 2.5-V Output Phase Noise
图10-5. LMK1C110x 1.8-V Output Phase Noise 32-
27.5-fs (12 kHz to 20 MHz)
fs (12 kHz to 20 MHz)
Copyright © 2022 Texas Instruments Incorporated
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ZHCSKK6D –DECEMBER 2019 –REVISED FEBRUARY 2022
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11 Power Supply Recommendations
High-performance clock buffers can be sensitive to noise on the power supply, which may dramatically increase
the additive jitter of the buffer. Thus, it is essential to manage any excessive noise from the system power
supply, especially for applications where the jitter and phase noise performance is critical.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass
capacitors provide the very low impedance path for high-frequency noise and guard the power supply system
against induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by
the device and should have low equivalent series resistance (ESR). To properly bypass the supply, the
decoupling capacitors must be placed very close to the power-supply terminals, be connected directly to the
ground plane, and laid out with short loops to minimize inductance. TI recommends adding as many high-
frequency (for example, 0.1 µF) bypass capacitors, as there are supply terminals in the package. TI
recommends, but does not require, inserting a ferrite bead between the board power supply and the chip power
supply that isolates the high-frequency switching noises generated by the clock buffer; these beads prevent the
switching noise from leaking into the board supply. It is imperative to choose an appropriate ferrite bead with
very low DC resistance to provide adequate isolation between the board supply and the chip supply, as well as
to maintain a voltage at the supply terminals that is greater than the minimum voltage required for proper
operation.
图11-1 shows this recommended power supply decoupling method.
V
CC
Chip
Supply
Board
Supply
Ferrite Bead
C
C
C
10 …F
1 …F
0.1 …F
GND
GND
GND
图11-1. Power Supply Decoupling
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ZHCSKK6D –DECEMBER 2019 –REVISED FEBRUARY 2022
www.ti.com.cn
12 Layout
12.1 Layout Guidelines
图 12-1 shows a conceptual layout detailing recommended placement of power supply bypass capacitors. For
component side mounting, use 0402 body size capacitors to facilitate signal routing. Keep the connections
between the bypass capacitors and the power supply on the device as short as possible. Ground the other side
of the capacitor using a low-impedance connection to the ground plane.
图 12-2 provides a visual representation of the WSON device; it can be seen from the figure that similar to a
DFN package, WSON doesn't have any leads.
12.2 Layout Example
Y1
Y3
CLKIN
1G
Y0
VDD
Y2
Decoupling capacitor
GND
图12-1. PCB Conceptual Layout
图12-2. Layout illustration for 8-pin WSON device
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LMK1C1102, LMK1C1103, LMK1C1104
ZHCSKK6D –DECEMBER 2019 –REVISED FEBRUARY 2022
www.ti.com.cn
13 Device and Documentation Support
13.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
13.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
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Product Folder Links: LMK1C1102 LMK1C1103 LMK1C1104
PACKAGE OPTION ADDENDUM
www.ti.com
18-Nov-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMK1C1102DQFR
LMK1C1102DQFT
LMK1C1102PWR
LMK1C1103PWR
LMK1C1104DQFR
LMK1C1104DQFT
LMK1C1104PWR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
TSSOP
TSSOP
WSON
WSON
TSSOP
DQF
DQF
PW
8
8
8
8
8
8
8
3000 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
L1C2
L1C2
NIPDAUAG
NIPDAU
2000 RoHS & Green
2000 RoHS & Green
3000 RoHS & Green
LMK1C2
LMK1C3
L1C4
PW
NIPDAU
DQF
DQF
PW
NIPDAUAG
NIPDAUAG
NIPDAU
250
RoHS & Green
L1C4
2000 RoHS & Green
LMK1C4
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Nov-2021
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMK1C1102DQFR
LMK1C1102DQFT
LMK1C1102PWR
LMK1C1103PWR
LMK1C1104DQFR
LMK1C1104DQFT
LMK1C1104PWR
WSON
WSON
TSSOP
TSSOP
WSON
WSON
TSSOP
DQF
DQF
PW
8
8
8
8
8
8
8
3000
250
178.0
178.0
330.0
330.0
178.0
178.0
330.0
8.4
8.4
2.25
2.25
7.0
2.25
2.25
3.6
1.0
1.0
1.6
1.6
1.0
1.0
1.6
4.0
4.0
8.0
8.0
4.0
4.0
8.0
8.0
8.0
Q2
Q2
Q1
Q1
Q2
Q2
Q1
2000
2000
3000
250
12.4
12.4
8.4
12.0
12.0
8.0
PW
7.0
3.6
DQF
DQF
PW
2.25
2.25
7.0
2.25
2.25
3.6
8.4
8.0
2000
12.4
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMK1C1102DQFR
LMK1C1102DQFT
LMK1C1102PWR
LMK1C1103PWR
LMK1C1104DQFR
LMK1C1104DQFT
LMK1C1104PWR
WSON
WSON
TSSOP
TSSOP
WSON
WSON
TSSOP
DQF
DQF
PW
8
8
8
8
8
8
8
3000
250
205.0
205.0
356.0
356.0
205.0
205.0
356.0
200.0
200.0
356.0
356.0
200.0
200.0
356.0
33.0
33.0
35.0
35.0
33.0
33.0
35.0
2000
2000
3000
250
PW
DQF
DQF
PW
2000
Pack Materials-Page 2
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
8
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
SEATING PLANE
TYP
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
5
1
3.1
2.9
NOTE 3
2X
1.95
4
0.30
0.19
8X
4.5
4.3
1.2 MAX
B
0.1
C A
B
NOTE 4
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
0 - 8
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
8X (0.45)
(R0.05)
1
4
TYP
8
SYMM
6X (0.65)
5
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
SYMM
(R0.05) TYP
8X (0.45)
1
4
8
SYMM
6X (0.65)
5
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DQF0008A
WSON - 0.8 mm max height
S
C
A
L
E
6
.
0
0
0
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.05 C
0.05
0.00
SYMM
(0.2) TYP
4
5
SYMM
2X 1.5
6X 0.5
8
1
0.3
8X
0.2
0.1
0.05
0.7
0.5
C A B
PIN 1 ID
0.6
0.4
7X
4220563/A 03/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DQF0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SEE SOLDER MASK
DETAIL
SYMM
(0.8)
8
8X (0.25)
1
SYMM
6X (0.5)
(R0.05) TYP
4
5
7X (0.7)
(1.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 30X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4220563/A 03/2021
NOTES: (continued)
3. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DQF0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.8)
8X (0.25)
1
8
SYMM
6X (0.5)
(R0.05) TYP
5
4
SYMM
(1.7)
7X (0.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 30X
4220563/A 03/2021
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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