LMK1D1204PRHDT [TI]

带引脚控制的 4 通道输出 LVDS 1.8V、2.5V 和 3.3V 缓冲器 | RHD | 28 | -40 to 105;


型号：	LMK1D1204PRHDT
厂家：	TEXAS INSTRUMENTS
描述：	带引脚控制的 4 通道输出 LVDS 1.8V、2.5V 和 3.3V 缓冲器 \| RHD \| 28 \| -40 to 105
文件：	总32页 (文件大小：1485K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LMK1D1204P

ZHCSP13A –SEPTEMBER 2021 –REVISED JUNE 2023

LMK1D1204P 引脚控制型OE 低附加抖动LVDS 缓冲器

1 特性

3 说明

• 具有2 路输入和4 路输出(2:4) 的高性能LVDS 时

钟缓冲器系列

• 输出频率最高可达2GHz

• 通过硬件引脚实现启用/禁用独立输出

• 电源电压：1.8V/2.5V/3.3V ± 5%

• 低附加抖动：156.25MHz 下小于12kHz 至20MHz

范围内的60fs rms 最大值

LMK1D1204P 时钟缓冲器能够以超小的时钟分配延

迟，将两个中的任一可选时钟输入（IN0 和 IN1）分配

给 4 对差分 LVDS 时钟输出（OUT0 至 OUT3）。输

入可以为 LVDS、LVPECL、LVCMOS、HCSL 或

CML。

LMK1D1204P 专为驱动 50Ω 传输线路而设计。在单端

模式下驱动输入时，对未使用的负输入引脚施加适当的

偏置电压（请参阅图 9-6）。IN_SEL 引脚用于选择要

发送到输出的输入。该器件支持失效防护输入功能。该

器件还整合了输入迟滞，可防止在没有输入信号的情况

下输出随机振荡。

– 超低相位本底噪声：-164dBc/Hz（典型值）

• 超低传播延迟：< 575ps（最大值）

• 输出偏斜：20ps（最大值）

• 失效防护输入

• 通用输入接受LVDS、LVPECL、LVCMOS、HCSL

和CML

• LVDS 基准电压(V_{AC_REF}) 适用于容性耦合输入

• 工业温度范围：–40°C 至105°C

• 可用封装：

各个 LVDS 差分输出均可通过将对应的 OEx 引脚设置

为逻辑高电平“1”来实现。如果此引脚设置为逻辑低

电平“0”，输出将被禁用，呈现高阻态，从而降低功

耗。

– 5mm × 5mm 28 引脚VQFN (RHD) 封装

该器件可在 1.8V、2.5V 或 3.3V 电源环境下工作，额

定温度范围是–40°C 至105°C（环境温度）。

2 应用

封装信息

• 电信及网络

• 医疗成像

封装尺寸（标称值）

封装⁽¹⁾

器件型号

(2)

• 测试和测量

• 无线基础设施

• 专业音频、视频和标牌

LMK1D1204P

VQFN (28)

5.00mm × 5.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

(2) 封装尺寸（长× 宽）为标称值，并包括引脚（如适用）。

ADC CLOCK

500 MHz

156.25 MHz

Oscillator

LMK1D1204P

LVDS Buffer

IN_SEL

FPGA CLOCK

0Ex

应用示例

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNAS830

LMK1D1204P

ZHCSP13A –SEPTEMBER 2021 –REVISED JUNE 2023

www.ti.com.cn

Table of Contents

9.2 Functional Block Diagram.........................................13

9.3 Feature Description...................................................14

9.4 Device Functional Modes..........................................14

10 Application and Implementation................................17

10.1 Application Information........................................... 17

10.2 Typical Application.................................................. 17

10.3 Power Supply Recommendations...........................20

10.4 Layout..................................................................... 21

11 Device and Documentation Support..........................23

11.1 Documentation Support.......................................... 23

11.2 支持资源..................................................................23

11.3 Trademarks............................................................. 23

11.4 静电放电警告...........................................................23

11.5 术语表..................................................................... 23

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Device Comparison.........................................................3

6 Pin Configuration and Functions...................................4

7 Specifications.................................................................. 6

7.1 Absolute Maximum Ratings........................................ 6

7.2 ESD Ratings............................................................... 6

7.3 Recommended Operating Conditions.........................6

7.4 Thermal Information....................................................7

7.5 Electrical Characteristics.............................................7

7.6 Typical Characteristics..............................................10

8 Parameter Measurement Information.......................... 11

9 Detailed Description......................................................13

9.1 Overview...................................................................13

Information.................................................................... 23

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision * (September 2021) to Revision A (June 2023)

Page

• 更新了数据表格式以与LMK1D1208P 数据表版本保持一致...............................................................................1

• 将表标题从“器件信息”更改为“封装信息”....................................................................................................1

• Added information to the Fail-Safe Input section..............................................................................................14

• Removed the word 'or' in the phrase 'In this example, the PHY, ASIC, FPGA and CPU'.................................18

• Moved the Power Supply Recommendations and Layout section to the Application and Implementation

section.............................................................................................................................................................. 20

• Changed 0.1 µF (x3) to 0.1 µF (x4) in 图10-4 .................................................................................................20

English Data Sheet: SNAS830

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5 Device Comparison

表5-1. Device Comparison

DEVICE

OUTPUT

DEVICE

TYPE

FEATURES

SWING

PACKAGE

BODY SIZE

350 mV

500 mV

Global output enable and swing

control via pin control

LMK1D2108

Dual 1:8

VQFN (48)

7.00 mm × 7.00 mm

350 mV

500 mV

350 mV

500 mV

350 mV

500 mV

350 mV

500 mV

350 mV

500 mV

350 mV

500 mV

350 mV

500 mV

Global output enable and swing

control via pin control

LMK1D2106

LMK1D2104

LMK1D2102

LMK1D1216

LMK1D1212

LMK1D1208P

Dual 1:6

Dual 1:4

Dual 1:2

2:16

VQFN (40)

VQFN (28)

VQFN (16)

VQFN (48)

VQFN (40)

VQGN (40)

6.00 mm × 6.00 mm

5.00 mm × 5.00 mm

3.00 mm × 3.00 mm

7.00 mm × 7.00 mm

6.00 mm × 6.00 mm

Global output enable and swing

control via pin control

Global output enable and swing

control via pin control

Global output enable control via

pin control

Global output enable control via

pin control

2:12

Individual output enable control via

pin control

2:8

Individual output enable control via

I2C

LMK1D1208I

LMK1D1208

LMK1D1204P

LMK1D1204

2:8

2:4

VQFN (40)

VQFN (28)

VQGN (28)

VQFN (16)

6.00 mm × 6.00 mm

5.00 mm × 5.00 mm

3.00 mm × 3.00 mm

Global output enable control via

pin control

350 mV

Individual output enable control via

pin control

Global output enable control via

pin control

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English Data Sheet: SNAS830

LMK1D1204P

ZHCSP13A –SEPTEMBER 2021 –REVISED JUNE 2023

www.ti.com.cn

6 Pin Configuration and Functions

OUT2_P

OUT2_N

OE2

GND

OE0

DAP

ꢀ

AC_REF0

OUT3_P

OUT3_N

IN0_N

IN0_P

ꢀ

Not to scale

图6-1. LMK1D1204P: RHD Package 28-Pin VQFN Top View

表6-1. Pin Functions

NAME

NO.

TYPE⁽¹⁾

DESCRIPTION

DIFFERENTIAL/SINGLE-ENDED CLOCK INPUT

IN0_P

Primary: Differential input pair or single-ended input

Secondary: Differential input pair or single-ended input.

IN0_N

IN1_P

Note that INP0, INN0 are used indistinguishably with IN0_P, IN0_N.

IN1_N

INPUT SELECT

Input Selection with an internal 500-kΩpullup and 320-kΩpulldown,

selects input port. See 表9-1.

IN_SEL

OUTPUT ENABLE

Output Enable for channel 0

OE0

OE1

OE2

OE3

HIGH (default): Enable output channel 0

LOW: Disable output channel 0 in Hi-Z state

Output Enable for channel 1

HIGH (default): Enable output channel 1

LOW: Disable output channel 1 in Hi-Z state

Output Enable for channel 2

HIGH (default): Enable output channel 2

LOW: Disable output channel 2 in Hi-Z state

Output Enable for channel 3

HIGH (default): Enable output channel 3

LOW: Disable output channel 3 in Hi-Z state

BIAS VOLTAGE OUTPUT

V_{AC_REF0}

Bias voltage output for capacitive-coupled inputs. If used, TI recommends

using a 0.1-µF capacitor to GND on this pin.

V_{AC_REF1}

DIFFERENTIAL CLOCK OUTPUT

OUT0_P

Differential LVDS output pair number 0

OUT0_N

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English Data Sheet: SNAS830

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表6-1. Pin Functions (continued)

NAME

NO.

TYPE⁽¹⁾

DESCRIPTION

OUT1_P

OUT1_N

OUT2_P

OUT2_N

OUT3_P

OUT3_N

SUPPLY VOLTAGE

V_DD

Differential LVDS output pair number 1

Differential LVDS output pair number 2

Differential LVDS output pair number 3

8, 15, 28

1, 14

Device power supply (1.8 V, 2.5 V, or 3.3 V)

Ground

GROUND

GND

MISC

DAP

GND

Die Attach Pad. Connect to the printed circuit board (PCB) ground plane for

heat dissipation.

DAP

4, 12, 18, 25

No Connection. Leave floating

(1) G = Ground, I = Input, O = Output, P = Power

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English Data Sheet: SNAS830

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–20

–50

MAX

3.6

UNIT

V_DD

V_IN

V_O

I_IN

Supply voltage

Input voltage

3.6

Output voltage

V_DD+ 0.3

Input current

°C

I_O

Continuous output current

Junction temperature

Storage temperature ⁽²⁾

T_J

135

T_stg

150

–65

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) Device unpowered

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/

JEDEC JS-001, all pins⁽¹⁾

±3000

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per ANSI/ESDA/

JEDEC JS-002, all pins⁽²⁾

±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

3.135

2.375

1.71

NOM

3.3

MAX

3.465

2.625

1.89

UNIT

3.3-V supply

V_DD

Core supply voltage

Supply voltage ramp

2.5-V supply

2.5

1.8-V supply

1.8

Supply

Ramp

Requires monotonic ramp (10-90% of

0.1

V_DD

)

T_A

T_J

Operating free-air temperature

Operating junction temperature

105

135

°C

–40

English Data Sheet: SNAS830

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7.4 Thermal Information

LMK1D1204P

THERMAL METRIC⁽¹⁾

RHD (VQFN)

28 PINS

38.9

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

32.1

18.7

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

Ψ_JT

18.7

Ψ_JB

R_θJC(bot)

8.2

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

7.5 Electrical Characteristics

V_DD= 1.8 V ± 5 %, –40°C ≤T_A≤105°C. Typical values are at V_DD= 1.8 V, 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER SUPPLY CHARACTERISTICS

All-outputs enabled and

unterminated, f = 0 Hz ⁽¹⁾

IDD_STAT

IDD_100M

LMK1D1204P

All-outputs enabled, R_L= 100 Ω, f

=100 MHz

INPUT CHARACTERISTICS (Applies to V_DD= 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%)

Vd_I3

V_IH

3-state input

Open

0.4 × V_CC

Minimum input voltage for a

logical "1" state

Input high voltage

0.7 × V_CC

V_CC+ 0.3

0.3 × V_CC

Maximum input voltage for a

logical "0" state

V_IL

I_IH

Input low voltage

Input high current

–0.3

V_DDcan be 1.8V/2.5V/3.3V with

V_IH= V_DD

µA

V_DDcan be 1.8V/2.5V/3.3V with

V_IH= V_DD

I_IL

Input low current

–30

R_pull-up(EN)

Input pullup resistor

500

320

kΩ

R_{pull-down(EN)}Input pulldown resistor

SINGLE-ENDED LVCMOS/LVTTL CLOCK INPUT (Applies to V_DD= 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%)

f_IN

Input frequency

Clock input

0.4

250

MHz

Assumes a square wave input

with two levels

V_{IN_S-E}

Single-ended Input Voltage Swing

3.465

Input Slew Rate (20% to 80% of the

amplitude)

dVIN/dt

0.05

V/ns

I_IH

Input high current

Input low current

Input capacitance

V_DD= 3.465 V, V_IH= 3.465 V

V_DD= 3.465 V, V_IL= 0 V

at 25°C

µA

I_IL

–30

C_{IN_SE}

3.5

DIFFERENTIAL CLOCK INPUT (Applies to V_DD= 1.8 V ± 5%, 2.5 V ± 5% and 3.3 V ± 5%)

f_IN

Input frequency

Clock input

2.4

GHz

V_PP

V_ICM= 1 V (V_DD= 1.8 V)

V_ICM= 1.25 V (V_DD= 2.5 V/3.3 V)

0.3

Differential input voltage peak-to-peak

{2*(V_INP-V_INN)}

V_IN,DIFF(p-p)

V_IN,DIFF(P-P)> 0.4 V (V_DD= 1.8

V/2.5/3.3 V)

V_ICM

Input common mode voltage

0.25

2.3

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English Data Sheet: SNAS830

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V_DD= 1.8 V ± 5 %, –40°C ≤T_A≤105°C. Typical values are at V_DD= 1.8 V, 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_DD= 3.465 V, V_INP= 2.4 V, V_INN

= 1.2 V

I_IH

Input high current

µA

V_DD= 3.465 V, V_INP= 0 V, V_INN

1.2 V

I_IL

Input low current

µA

–30

C_{IN_S-E}

Input capacitance (Single-ended)

at 25°C

3.5

LVDS DC OUTPUT CHARACTERISTICS

Differential output voltage magnitude |

V_OUTP- V_OUTN

V_IN,DIFF(P-P)= 0.3 V, R_LOAD= 100

|VOD|

250

350

450

Change in differential output voltage

magnitude. Per output, defined as the

difference between VOD in logic hi/lo

states.

V_IN,DIFF(P-P)= 0.3 V, R_LOAD= 100

ΔVOD

–15

V_IN,DIFF(P-P)= 0.3 V, R_LOAD= 100

Ω(V_DD= 1.8 V)

1.2

Steady-state common mode output

voltage

V_OC(SS)

V_IN,DIFF(P-P)= 0.3 V, R_LOAD= 100

Ω(V_DD= 2.5 V/3.3 V)

1.1

1.375

Change in steady-state common mode

output voltage. Per output, defined as the

difference in VOC in logic hi/lo states.

V_IN,DIFF(P-P)= 0.3 V, R_LOAD= 100

Δ_VOC(SS)

–15

LVDS AC OUTPUT CHARACTERISTICS

V_IN,DIFF(P-P)= 0.3 V, R_LOAD= 100

Ω, f_OUT= 491.52 MHz

V_ring

Output overshoot and undershoot

0.1

V_OD

–0.1

V_IN,DIFF(P-P)= 0.3 V, R_LOAD= 100

V_OS

Output AC common mode

100

mV_pp

I_OS

Short-circuit output current (differential)

V_OUTP= V_OUTN

–12

–24

Short-circuit output current (common-

mode)

I_OS(cm)

V_OUTP= V_OUTN= 0

V_IN,DIFF(P-P)= 0.3 V, R_LOAD= 100

t_PD

Propagation delay

Output skew

0.3

0.575

Ω⁽²⁾

Skew between outputs with the

same load conditions

t_{SK, O}

Skew between outputs on

different parts subjected to the

same operating conditions with

the same input and output

t_{SK, PP}

Part-to-part skew

250

50% duty cycle input, crossing

t_{SK, P}

Pulse skew

point-to-crossing-point distortion

–20

(4)

f_IN= 156.25 MHz with 50% duty-

cycle, Input slew rate = 1.5V/ns,

Integration range = 12 kHz –20

t_RJIT(ADD)

Random additive Jitter (rms)

60 fs, RMS

MHz, with output load R_LOAD

100 Ω

PN_1kHz

PN_10kHz

PN_100kHz

PN_1MHz

PN_floor

–143

–152

–157

–160

–164

Phase Noise for a carrier frequency of

156.25 MHz with 50% duty-cycle, Input

slew rate = 1.5V/ns with output load

R_LOAD= 100 Ω

Phase noise

dBc/Hz

English Data Sheet: SNAS830

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V_DD= 1.8 V ± 5 %, –40°C ≤T_A≤105°C. Typical values are at V_DD= 1.8 V, 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f_IN= 156.25 MHz. The difference

in power level at f_INwhen the

selected clock is active and the

unselected clock is static versus

when the selected clock is inactive

and the unselected clock is active.

MUX_ISO

Mux Isolation

ODC

Output duty cycle

With 50% duty cycle input

300

t_R/t_F

Output rise and fall time

Reference output voltage

20% to 80% with R_LOAD= 100 Ω

VDD = 2.5 V, I_LOAD= 100 µA

V_{AC_REF}

0.9

1.25

1.375

POWER SUPPLY NOISE REJECTION (PSNR) V_DD= 2.5 V/ 3.3 V

10 kHz, 100 mVpp ripple injected

–70

–50

on V_DD

Power Supply Noise Rejection (f_carrier

156.25 MHz)

PSNR

dBc

1 MHz, 100 mVpp ripple injected

on V_DD

(1) A typical 4-mA current reduction per disabled output can be expected.

(2) Measured between single-ended/differential input crossing point to the differential output crossing point.

(3) Defined as the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.

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English Data Sheet: SNAS830

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7.6 Typical Characteristics

图7-1 captures the variation of the LMK1D1204P current consumption with input frequency and supply voltage. 图7-2 shows

the variation of the differential output voltage (VOD) swept across frequency.

V_DD= 1.8 V, T_A= -40

V_DD= 1.8 V, T_A= 25

V_DD= 1.8 V,T_A= 105

V_DD= 2.5 V, T_A= -40

V_DD= 2.5 V, T_A= 25

V_DD= 2.5 V,T_A= 105

V_DD= 3.3 V, T_A= -40

V_DD= 3.3 V, T_A= 25

V_DD= 3.3 V,T_A=105

100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000

Frequency (MHz)

图7-1. LMK1D1204P Current Consumption vs Frequency

380

370

360

350

340

330

320

310

300

290

280

270

260

250

240

V_DD= 1.8 V, T_A= -40

V_DD= 1.8 V, T_A= 25

V_DD= 1.8 V, T_a= 105

V_DD= 2.5 V, T_A= -40

V_DD= 2.5 V, T_A= 25

V_DD= 2.5 V, T_A= 105

V_DD= 3.3 V, T_A= -40

V_DD= 3.3 V, T_A= 25

V_DD= 3.3 V, T_A= 105

100

200

300

400

500

600 700 800 9001000

2000

Frequency (MHz)

图7-2. LMK1D1204P VOD vs Frequency

English Data Sheet: SNAS830

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8 Parameter Measurement Information

Oscilloscope

100 W

LVDS

图8-1. LVDS Output DC Configuration During Device Test

Phase Noise/

Spectrum Analyzer

LMK1D1204P

Balun

100 Ω

图8-2. LVDS Output AC Configuration During Device Test

图8-3. DC-Coupled LVCMOS Input During Device Test

OUTNx

OUTPx

80%

(= 2 x V

)

20%

0 V

OUT,DIFF,PP

图8-4. Output Voltage and Rise/Fall Time

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INNx

INPx

PLH0

PHL0

PHL1

OUTN0

OUTP0

PLH1

OUTN1

OUTP1

PLH2

PHL2

OUTN2

OUTP2

PHL7

PLH7

OUTN7

OUTP7

A. Output skew is calculated as the greater of the following: the difference between the fastest and the slowest t_PLHnor the difference

between the fastest and the slowest t_PHLn(n = 0, 1, 2, ..7)

B. Part to part skew is calculated as the greater of the following: the difference between the fastest and the slowest t_PLHnor the difference

between the fastest and the slowest t_PHLnacross multiple devices (n = 0, 1, 2, ..7)

图8-5. Output Skew and Part-to-Part Skew

ring

OUTNx

0 V Differential

OUTPx

图8-6. Output Overshoot and Undershoot

GND

图8-7. Output AC Common Mode

English Data Sheet: SNAS830

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9 Detailed Description

9.1 Overview

The LMK1D1204P LVDS drivers use CMOS transistors to control the output current. Therefore, proper biasing

and termination are required to ensure correct operation of the device and to maximize signal integrity.

The proper LVDS termination for signal integrity over two 50-Ω lines is 100 Ω between the outputs on the

receiver end. Either DC-coupled termination or AC-coupled termination can be used for LVDS outputs. TI

recommends placing a termination resistor close to the receiver. If the receiver is internally biased to a voltage

different than the output common-mode voltage of the LMK1D1204P, AC coupling must be used. If the LVDS

receiver has internal 100-Ωtermination, external termination must be omitted.

9.2 Functional Block Diagram

VDD

1.8 to 3.3 V

OE0

OUT0

LVDS

OE1

Reference

Generator

V_{AC_REF}

OE1

IN0

IN1

LVDS

OUT1

IN_MUX

VDD

OE2

R_pull-up

IN_SEL

OE2

LVDS

OUT2

R_pull-down

OE3

OUT3

LVDS

GND

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9.3 Feature Description

The LMK1D1204P is a low additive jitter LVDS fan-out buffer that can generate up to four copies of two

selectable LVPECL, LVDS, HCSL, CML, or LVCMOS inputs. The LMK1D1204P can accept reference clock

frequencies up to 2 GHz while providing low output skew.

9.3.1 Fail-Safe Input

The LMK1D120x family of devices is designed to support fail-safe input operation feature. This feature allows the

user to drive the device inputs before V_DDis applied without damaging the device. Refer to Specifications for

more information on the maximum input supported by the device. The user should note that incorporating the

fail-safe inputs also results in a slight increase in clock input pin capacitance. The device also incorporates an

input hysteresis which prevents random oscillation in absence of an input signal. Furthermore, this feature allows

the input pins to be left open.

9.4 Device Functional Modes

The two inputs of the LMK1D1204P are internally muxed together and can be selected through the control pin

(see 表 9-1). Unused inputs can be left floating to reduce overall component cost. Both AC- and DC-coupling

schemes can be used with the LMK1D1204P to provide greater system flexibility.

表9-1. Input Selection Table

IN_SEL

ACTIVE CLOCK INPUT

IN0_P, IN0_N

IN1_P, IN1_N

None ⁽¹⁾

Open

(1) The input buffers are disabled and the state of the outputs are

dependent on the state of OEx (see 表9-2). If OEx = 0, the

corresponding output will be disabled in Hi-Z state, whereas if

OEx = 1 (default), the corresponding output will be logic low.

The outputs of the LMK1D1204P can be individually enabled or disabled using the OEx hardware pins (see 表

9-2). The disabled state of the outputs is Hi-Z (high impedance) as this reduces the power consumption and also

prevents back-biasing of the devices connected to these outputs.

Unused outputs should be disabled to eliminate the need for a termination resistor. In the case of enabled

unused outputs, TI recommends a 100-Ωtermination for optimal performance.

表9-2. Output Control

OEx

CLOCK OUTPUTS

OUTPx, OUTNx disabled in Hi-Z

state

1 (default)

OUTPx, OUTNx enabled

9.4.1 LVDS Output Termination

TI recommends that unused outputs are terminated differentially with a 100-Ωresistor for optimum performance,

although unterminated outputs are also okay but will result in slight degradation in performance (Output AC

common-mode V_OS) in the outputs being used.

The LMK1D1204P can be connected to LVDS receiver inputs with DC and AC coupling as shown in 图 9-1 and

图9-2, respectively.

English Data Sheet: SNAS830

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Z = 50 W

100 W

LVDS

LMK1D120xP

Z = 50 W

图9-1. Output DC Termination

100 nF

Z = 50 W

100 W

LVDS

LMK1D120xP

Z = 50 W

100 nF

图9-2. Output AC Termination (With the Receiver Internally Biased)

9.4.2 Input Termination

The LMK1D1204P inputs can be interfaced with LVDS, LVPECL, HCSL, or LVCMOS drivers.

LVDS drivers can be connected to LMK1D1204P inputs with DC and AC coupling as shown 图 9-3 and 图 9-4,

respectively.

Z = 50 W

100 W

LVDS

LMK1D120xP

Z = 50 W

图9-3. LVDS Clock Driver Connected to LMK1D1204P Input (DC-Coupled)

100 nF

Z = 50 W

LVDS

LMK1D120xP

Z = 50 W

100 nF

50 W

AC_REF

图9-4. LVDS Clock Driver Connected to LMK1D1204P Input (AC-Coupled)

图 9-5 shows how to connect LVPECL inputs to the LMK1D1204P. The series resistors are required to reduce

the LVPECL signal swing if the signal swing is >1.6 V_PP

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75 W

100 nF

Z = 50 W

LMK1D120xP

LVPECL

Z = 50 W

100 nF

50 W

75 W

150 W

50 W

AC_REF

图9-5. LVPECL Clock Driver Connected to LMK1D1204P Input

图9-6 shows how to couple a LVCMOS clock input to the LMK1D1204P directly.

LVCMOS

(1.8/2.5/3.3 V)

Z = 50 ꢀ

LMK1D120XP

图9-6. 1.8-V, 2.5-V, or 3.3-V LVCMOS Clock Driver Connected to LMK1D1204P Input

For unused input, TI recommends grounding both input pins (INP, INN) using 1-kΩresistors.

English Data Sheet: SNAS830

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10 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

10.1 Application Information

The LMK1D1204P is a low additive jitter universal to LVDS fan-out buffer with two selectable inputs and pin

controlled output enables. The small package size, low output skew, low propagation delay and low additive jitter

of this device is designed for applications that require high-performance clock distribution as well as for low-

power and space-constraint applications.

10.2 Typical Application

1.8 V / 2.5 V / 3.3 V

PHY

PRIREF_P

156.25 MHz LVDS

From Backplane

100

PRIREF_N

V_{AC_REF}

ASIC

100

156.25 MHz LVCMOS

Oscillator

SECREF_P

FPGA

100

2.5 V

SECREF_N

CPU

100

图10-1. Fan-Out Buffer for Line Card Application

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10.2.1 Design Requirements

The LMK1D1204P shown in 图 10-1 is configured to select two inputs: a 156.25-MHz LVDS clock from the

backplane, or a secondary 156.25-MHz, LVCMOS, 2.5-V oscillator. The LVDS clock is AC-coupled and biased

using the integrated reference voltage generator. A resistor divider is used to set the threshold voltage correctly

for the LVCMOS clock. 0.1-µF capacitors are used to reduce noise on both V_{AC_REF}and SECREF_N. Either

input signal can be then fanned out to desired devices, as shown. The configuration example is driving 4 LVDS

receivers in a line card application with the following properties:

• The PHY device is capable of DC coupling with an LVDS driver such as the LMK1D1204P. This PHY device

features internal termination so no additional components are required for proper operation.

• The ASIC LVDS receiver features internal termination and operates at the same common-mode voltage as

the LMK1D1204P. Again, no additional components are required.

• The FPGA requires external AC coupling, but has internal termination. 0.1-µF capacitors are placed to

provide AC coupling. Similarly, the CPU is internally terminated, and requires only external AC-coupling

capacitors.

• The unused outputs of the LMK1D1204P can be disabled using the corresponding OEx pin. This results in a

lower power consumption.

10.2.2 Detailed Design Procedure

See Input Termination for proper input terminations, dependent on single-ended or differential inputs.

See LVDS Output Termination for output termination schemes depending on the receiver application.

Unused outputs can be disabled using the corresponding OEx pin setting according to 表 9-2. Disabling the

outputs also eliminates requirement of termination resistors.

In this example, the PHY, ASIC, FPGA and CPU require different schemes. Power supply filtering and bypassing

is critical for low-noise applications.

See Power Supply Recommendations for recommended filtering techniques. A reference layout is provided in

Low-Additive Jitter, Four LVDS Outputs Clock Buffer Evaluation Board user's guide (SCAU043).

English Data Sheet: SNAS830

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10.2.3 Application Curves

This section shows the low additive noise for the LMK1D1204P. The low noise 156.25-MHz source with 24-fs

RMS jitter shown in 图 10-2 drives the LMK1D1204P, resulting in 46.4-fs RMS when integrated from 12 kHz to

20 MHz (see 图10-3). The resultant additive jitter is 39.7-fs RMS for this configuration.

Note: Reference signal is a low-noise Rhode and Schwarz SMA100B

图10-2. LMK1D1204P Reference Phase Noise, 156.25 MHz, 24-fs RMS (12 kHz to 20 MHz)

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图10-3. LMK1D1204P Output Phase Noise, 156.25 MHz, 46.4-fs RMS (12 kHz to 20 MHz)

10.3 Power Supply Recommendations

High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the

additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when

jitter or phase noise is critical to applications.

Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass

capacitors provide the low impedance path for high-frequency noise and guard the power-supply system against

the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by the

device and must have low equivalent series resistance (ESR). To properly use the bypass capacitors, they must

be placed close to the power-supply pins and laid out with short loops to minimize inductance. TI recommends

adding as many high-frequency (for example, 0.1-µF) bypass capacitors as there are supply pins in the package.

TI recommends, but does not require, inserting a ferrite bead between the board power supply and the chip

power supply that isolates the high-frequency switching noises generated by the clock driver. These ferrite beads

prevent the switching noise from leaking into the board supply. Choose an appropriate ferrite bead with low DC

resistance because it is imperative to provide adequate isolation between the board supply and the chip supply,

as well as to maintain a voltage at the supply pins that is greater than the minimum voltage required for proper

operation.

图10-4 shows this recommended power-supply decoupling method.

Board

Supply

Chip

Supply

Ferrite Bead

1 μF

0.1 μF (x4)

10 μF

GND

图10-4. Power Supply Decoupling

English Data Sheet: SNAS830

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10.4 Layout

10.4.1 Layout Guidelines

For reliability and performance reasons, the die temperature must be limited to a maximum of 135°C.

The device package has an exposed pad that provides the primary heat removal path to the PCB. To maximize

the heat dissipation from the package, a thermal landing pattern including multiple vias to a ground plane must

be incorporated into the PCB within the footprint of the package. The thermal pad must be soldered down to

ensure adequate heat conduction to of the package. 图 10-5 and 图 10-6 show the recommended land and via

patterns for the 28-pin LMK1D1204P device.

10.4.2 Layout Examples

图10-5. Recommended PCB Layout, Top Layer

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图10-6. Recommended PCB Layout, GND Layer

English Data Sheet: SNAS830

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11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

For related documentation see the following:

• Texas Instruments, Low-Additive Jitter, Four LVDS Outputs Clock Buffer Evaluation Board user's guide

• Texas Instruments, Power Consumption of LVPECL and LVDS Analog Design Journal

• Texas Instruments, Using Thermal Calculation Tools for Analog Components application note

11.2 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.3 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.4 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

11.5 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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10-Apr-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

LMK1D1204PRHDR

LMK1D1204PRHDT

ACTIVE

VQFN

RHD

3000 RoHS & Green

250 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-40 to 105

LMK1D

1204P

Samples

ACTIVE

RHD

NIPDAU

LMK1D

1204P

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

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10-Apr-2023

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

29-Jun-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

LMK1D1204PRHDR

LMK1D1204PRHDT

VQFN

RHD

3000

250

330.0

180.0

12.4

5.3

1.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

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29-Jun-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

LMK1D1204PRHDR

LMK1D1204PRHDT

VQFN

RHD

3000

250

367.0

210.0

367.0

185.0

35.0

Pack Materials-Page 2

PACKAGE OUTLINE

RHD0028B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

5.15

4.85

PIN 1 INDEX AREA

5.15

4.85

1.0

0.8

SEATING PLANE

0.08 C

0.05

0.00

3.15 0.1

2X 3

SYMM

(0.2) TYP

EXPOSED

THERMAL PAD

SYMM

2X 3

3.15 0.1

24X 0.5

PIN 1 ID

0.30

0.18

28X

0.1

C A B

0.65

0.45

28X

0.05

4226146/A 08/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RHD0028B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

3.15)

SYMM

SEE SOLDER MASK

DETAIL

28X (0.75)

28X (0.24)

24X (0.5)

SYMM

(4.65)

(1.325)

(R0.05) TYP

(

0.2) TYP

VIA

(1.325)

(4.65)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 18X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4226146/A 08/2020

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

RHD0028B

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(0.785) TYP

28X (0.75)

28X (0.24)

24X (0.5)

(0.785) TYP

(4.65)

SYMM

(R0.05) TYP

4X (1.37)

SYMM

(4.65)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 20X

EXPOSED PAD 29

76% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

4226146/A 08/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

LMK1D1204PRHDT [TI]

相关型号：

LMK1D1204RGTR

LMK1D1204RGTT

LMK1D1208

LMK1D1208I

LMK1D1208IRHAR

LMK1D1208IRHAT

LMK1D1208P

LMK1D1208PRHAR

LMK1D1208PRHAT

LMK1D1208RHDR

LMK1D1208RHDT

LMK1D120X