LMK1C1108PWR [TI]
LMK1C110x 1.8-V, 2.5-V, and 3.3-V LVCMOS Clock Buffer Family;
| 型号： | LMK1C1108PWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LMK1C110x 1.8-V, 2.5-V, and 3.3-V LVCMOS Clock Buffer Family |
| 文件： | 总25页 (文件大小：2230K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMK1C1106, LMK1C1108
SNAS814 – DECEMBER 2020
LMK1C110x 1.8-V, 2.5-V, and 3.3-V LVCMOS Clock Buffer Family
1 Features
3 Description
•
High-performance 1:6 and 1:8 LVCMOS clock
buffer
Very low output skew < 55 ps
Extremely low additive jitter < 25-fs nominal
– 12-fs typical at VDD = 3.3 V
The LMK1C110x is a modular, high-performance, low-
skew, general-purpose clock buffer family from Texas
Instruments.
•
•
The entire family is designed with a modular approach
in mind. Five different fan-out variations, 1:2, 1:3, 1:4,
1:6 and 1:8 are available.
– 15-fs typical at VDD = 2.5 V
– 28-fs typical at VDD = 1.8 V
Very low propagation delay < 3 ns
Synchronous output enable
All of the devices within this family are pin-compatible
to each other and backwards compatible to the
CDCLVC110x family for easy handling.
•
•
•
Supply voltage: 3.3 V, 2.5 V, or 1.8 V
– 3.3-V tolerant input at all supply voltages
Industry high ESD rating of 9000 V HBM
fmax = 250 MHz for 3.3 V
fmax = 200-MHz for 2.5 V and 1.8 V
Operating temperature range: –40 °C to 125 °C
Available in 14-pin and 16-pin TSSOP package
All family members share the same high performing
characteristics such as low additive jitter, low skew,
and wide operating temperature range.
•
•
The LMK1C110x supports a synchronous output
enable control (1G) which switches the outputs into a
low state when 1G is low.
•
•
The LMK1C110x family operates in a 1.8-V, 2.5-V and
3.3-V environment and are characterized for operation
from – 40 °C to 125 °C.
2 Applications
•
•
•
•
•
•
Factory automation & control
Telecommunications equipment
Data center & enterprise computing
Grid infrastructure
Motor drives
Medical imaging
Device Information
PART NUMBER
LMK1C1106
PACKAGE
TSSOP (14)
TSSOP (16)
BODY SIZE (NOM)
5.00 mm x 4.40 mm
5.00 mm x 4.40 mm
LMK1C1108
CLKIN
1G
1
2
3
4
5
6
7
14
13
12
11
10
9
Y1
Y3
CLKIN
LVCMOS
LVCMOS
Y0
Y0
VDD
Y2
GND
VDD
Y4
LMK1C1106
GND
Y5
LVCMOS
Y1
GND
8
VDD
CLKIN
1G
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Y1
Y3
Y0
VDD
Y2
GND
VDD
Y4
LMK1C1108
GND
Y5
LVCMOS
Y7
GND
Y6
VDD
Y7
1G
Functional Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMK1C1106, LMK1C1108
SNAS814 – DECEMBER 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................4
6.5 Electrical Characteristics ............................................5
6.6 Timing Requirements .................................................6
6.7 Typical Characteristics................................................6
7 Parameter Measurement Information............................7
8 Detailed Description........................................................9
8.1 Overview.....................................................................9
8.2 Functional Block Diagram...........................................9
8.3 Feature Description.....................................................9
8.4 Device Functional Modes..........................................10
9 Application and Implementation.................................. 11
9.1 Application Information..............................................11
9.2 Typical Application.................................................... 11
10 Power Supply Recommendations..............................13
11 Layout...........................................................................14
11.1 Layout Guidelines................................................... 14
11.2 Layout Example...................................................... 14
12 Device and Documentation Support..........................15
12.1 Documentation Support.......................................... 15
12.2 Receiving Notification of Documentation Updates..15
12.3 Support Resources................................................. 15
12.4 Trademarks.............................................................15
12.5 Electrostatic Discharge Caution..............................15
12.6 Glossary..................................................................15
13 Mechanical, Packaging, and Orderable
Information.................................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
December 2020
*
Initial Release
Copyright © 2020 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: LMK1C1106 LMK1C1108
LMK1C1106, LMK1C1108
www.ti.com
SNAS814 – DECEMBER 2020
5 Pin Configuration and Functions
CLKIN
1G
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Y1
Y3
Y0
VDD
Y2
GND
VDD
Y4
LMK1C 1106
LMK1C 1108
GND
Y5
GND
Y6
VDD
Y7
Not to scale
Figure 5-1. LMK1C1106 and LMK1C1108 PW Package 14-Pin TSSOP and 16-Pin TSSOP Top View
Table 5-1. Pin Functions
PIN
TYPE
DESCRIPTION
LMK1C
1106
LMK1C
1108
NAME
LVCMOS CLOCK INPUT
CLKIN
CLOCK OUTPUT ENABLE
Single-ended clock input with internal 300-kΩ (typical) pulldown resistor to
GND. Typically connected to a single-ended clock input.
1
1
2
Input
Global Output Enable with internal 300k-Ohm (typ) pulldown resistor to GND.
Typically connected to VDD with external pullup resistor.
HIGH: outputs enabled
1G
2
Input
LOW: outputs disabled
LVCMOS CLOCK OUTPUT
Y0
3
14
11
13
6
3
16
13
15
6
Y1
Y2
Y3
LVCMOS output. Typically connected to a receiver. Unused outputs can be
left floating.
Output
Y4
Y5
9
11
8
Y6
–
Y7
–
9
SUPPLY VOLTAGE
5
8
5
Power supply terminal. Typically connected to a 3.3-V, 2.5-V, or 1.8-V supply.
The VDD pin is typically connected to an external 0.1-μF capacitor near the
pin.
VDD
10
14
Power
GND
12
GROUND
GND
4
7
4
7
Device ground.
10
12
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: LMK1C1106 LMK1C1108
LMK1C1106, LMK1C1108
SNAS814 – DECEMBER 2020
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
VDD
VCLKIN
VIN
Supply voltage
Input voltage (CLKIN)
Input voltage (1G)
Output pins (Yn)
–0.5
3.6
V
VYn
IIN
–0.5
–20
–50
–65
VDD + 0.3
20
Input current
mA
mA
°C
IO
Continuous output current
Storage temperature
50
Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±9000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.135
2.375
1.71
–40
NOM
3.3
MAX
3.465
2.625
1.89
125
UNIT
3.3-V supply
2.5-V supply
1.8-V supply
VDD
Core supply voltage
2.5
V
1.8
TA
TJ
Operating free-air temperature
Operating junction temperature
°C
°C
–40
150
6.4 Thermal Information
LMK1C1106
PW (TSSOP)
14 PINS
114.4
LMK1C1108
PW(TSSOP)
16 PINS
123.4
THERMAL METRIC(1)
UNIT
RqJA
RqJC(top)
RqJB
YJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
45.2
53.1
60.6
66.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
5.9
8.9
YJB
60
65.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2020 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: LMK1C1106 LMK1C1108
LMK1C1106, LMK1C1108
www.ti.com
SNAS814 – DECEMBER 2020
6.5 Electrical Characteristics
VDD = 3.3 V ± 5 %, –40°C ≤ TA ≤ 125°C. Typical values are at VDD = 3.3 V, 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT CONSUMPTION
IDD
IDD
IDD
IDD
Core supply current, static
Core supply current
All-outputs disabled, fIN = 0 V
25
2
45
6
µA
All-outputs disabled, fIN = 100 MHz, VDD
1.8 V
=
=
=
mA
All-outputs disabled, fIN = 100 MHz, VDD
2.5 V
Core supply current
Core supply current
6.5
15
3.2
4.6
6
10
21
3.5
5.5
7
mA
All-outputs disabled, fIN = 100 MHz, VDD
3.3 V
Per output, fIN = 100 MHz, CL = 5pF, VDD
1.8 V
=
=
=
mA
Per output, fIN = 100 MHz, CL = 5pF, VDD
2.5 V
IDD
Output current
Per output, fIN = 100 MHz, CL = 5pF, VDD
3.3 V
CLOCK INPUT
VDD = 3.3 V
DC
DC
250
200
fIN_SE
Input frequency
MHz
V
VDD = 2.5 V and 1.8 V
VIH
Input high voltage
Input low voltage
Input slew rate
0.7 x VDD
VIL
0.3 x VDD
50
dVIN/dt
IIN_LEAK
CIN_SE
20% - 80% of input swing
at 25°C
0.1
V/ns
uA
Input leakage current
Input capacitance
–50
7
pF
CLOCK OUTPUT FOR ALL VDD LEVELS
VDD = 3.3 V
250
200
55
5
fOUT
Output frequency
MHz
VDD = 2.5 V and 1.8 V
With 50% duty cycle input
See (1)
ODC
Output duty cycle
Output enable time
Output disable time
45
%
t1G_ON
t1G_OFF
cycles
cycles
See (2)
5
CLOCK OUTPUT FOR VDD = 3.3 V ± 5%
VOH
Output high voltage
Output low voltage
IOH = 1 mA
2.8
V
VOL
IOL = 1 mA
0.2
0.7
tRISE-FALL
Output rise and fall time
20/80%, CL= 5 pF, fIN = 156.25 MHz
0.3
35
ns
tOUTPUT-
Output-output skew
See (3)
55
SKEW
ps
ns
tPART-SKEW Part-to-part skew
tPROP-DELAY Propagation delay
950
2.2
See (4)
1.3
12
50
fIN = 156.25 MHz, Input slew rate = 1.6
V/ns, Integration range = 12 kHz - 20 MHz
tJITTER-ADD Additive Jitter
20 fs, RMS
Ω
ROUT
Output impedance
CLOCK OUTPUT FOR VDD = 2.5 V ± 5%
VOH
Output high voltage
Output low voltage
IOH = 1 mA
0.8 x VDD
V
VOL
IOL = 1 mA
0.2 x VDD
0.8
tRISE-FALL
Output rise and fall time
20/80%, CL= 5 pF, fIN = 156.25 MHz
0.33
1.5
ns
ps
ns
tOUTPUT-
Output-output skew
See (3)
55
SKEW
tPART-SKEW Part-to-part skew
tPROP-DELAY Propagation delay
450
2.5
See (4)
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: LMK1C1106 LMK1C1108
LMK1C1106, LMK1C1108
SNAS814 – DECEMBER 2020
www.ti.com
VDD = 3.3 V ± 5 %, –40°C ≤ TA ≤ 125°C. Typical values are at VDD = 3.3 V, 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
27 fs, RMS
Ω
fIN = 156.25 MHz, Input slew rate = 1.2
V/ns, Integration range = 12 kHz - 20 MHz
tJITTER-ADD Additive Jitter
15
ROUT
Output impedance
55
CLOCK OUTPUT FOR VDD = 1.8 V ± 5%
VOH
Output high voltage
Output low voltage
IOH = 1 mA
0.8 x VDD
V
VOL
IOL = 1 mA
0.2 x VDD
tRISE-FALL
Output rise and fall time
20/80%, CL= 5 pF, fIN = 156.25 MHz
0.38
1
ns
ps
tOUTPUT-
Output-output skew
See (3)
55
SKEW
tPART-SKEW Part-to-part skew
tPROP-DELAY Propagation delay
930
3
ps
ns
See (4)
1.5
28
64
fIN = 156.25 MHz, Input slew rate = 1.2
V/ns, Integration range = 12 kHz - 20 MHz
tJITTER-ADD Additive Jitter
60 fs, RMS
Ω
ROUT
Output impedance
GENERAL PURPOSE INPUT (1G)
0.75 x
VDD
VIH
VIL
High-level input voltage
Low-level input voltage
V
0.25 x
VDD
IIH
IIL
Input high-level current
Input low-level current
VIH = VDD_REF
VIL = GND
–50
–50
50
µA
50
(1) Measured from 1G rising edge crossing VIH to first rising edge of Yn.
(2) Measured from 1G falling edge crossing VIL to last falling edge of Yn.
(3) Measured from rising edge of any Yn output to any other Ym output.
(4) Measured from rising edge of CLKIN to any Yn output.
6.6 Timing Requirements
VDD = 3.3 V ± 5 %, –40°C ≤ TA ≤ 125°C
MIN
NOM
MAX
UNIT
POWER SUPPLY
V/tRAMP VDD ramp rate
0.1
50
V/ms
6.7 Typical Characteristics
140
120
100
80
60
40
1.8
2.5
3.3
20
0
0
25
50
75 100 125 150 175 200 225 250
Frequency (MHz)
D001
Figure 6-1. Device Power Consumption vs Clock Frequency (Load 5 pF)
Copyright © 2020 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: LMK1C1106 LMK1C1108
LMK1C1106, LMK1C1108
www.ti.com
SNAS814 – DECEMBER 2020
7 Parameter Measurement Information
VDD = 3.3-V, 2.5-V,
or 1.8-V
LVCMOS
Output
Zo = 50 ꢀ
R = 50 Ω
C = 2 pF
Parasitic capacitance
From measurement
equipment
Figure 7-1. Test Load Circuit
VDD
VDD = 3.3-V, 2.5-V,
or 1.8-V
R = 100 Ω
LVCMOS
Output
Zo = 50 ꢀ
Parasitic capacitance
R = 100 Ω
Figure 7-2. Application Load With 50-Ω Termination
VDD = 3.3-V, 2.5-V,
or 1.8-V
LVCMOS
Output
Zo = 50 ꢀ
Parasitic capacitance
Figure 7-3. Application Load With Termination
CLKIN
1G
tt1G_ONt
Yn
Figure 7-4. t1G_ON Output Enable Time
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: LMK1C1106 LMK1C1108
LMK1C1106, LMK1C1108
SNAS814 – DECEMBER 2020
www.ti.com
CLKIN
1G
tt1G_OFFt
Yn
Figure 7-5. t1G_OFF Output Disable Time
CLKIN
Yn
tPROP-DELAY
tOUTPUT-SKEW
Yn+1
Figure 7-6. Propagation Delay tPROP-DELAY and Output Skew tOUTPUT-SKEW
80% x VDD
Yn
20% x VDD
tRISE-FALL
tRISE-FALL
Figure 7-7. Rise and Fall Time tRISE-FALL
Copyright © 2020 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: LMK1C1106 LMK1C1108
LMK1C1106, LMK1C1108
www.ti.com
SNAS814 – DECEMBER 2020
8 Detailed Description
8.1 Overview
The LMK1C110x family of devices is part of a low-jitter and low-skew LVCMOS fan-out buffer solution. For best
signal integrity, it is important to match the characteristic impedance of the LMK1C110x's output driver with that
of the transmission line.
8.2 Functional Block Diagram
CLKIN
LVCMOS
LVCMOS
Y0
LVCMOS
Y1
LVCMOS
Y2
LVCMOS
Y3
LVCMOS
LVCMOS
LVCMOS
Y4
Y5
Y6
LVCMOS
Y7
1G
8.3 Feature Description
The outputs of the LMK1C110x can be disabled by driving the synchronous output enable pin (1G) low. Unused
output can be left floating to reduce overall system component cost. Supply and ground pins must be connected
to VDD and GND, respectively.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: LMK1C1106 LMK1C1108
LMK1C1106, LMK1C1108
SNAS814 – DECEMBER 2020
www.ti.com
8.4 Device Functional Modes
The LMK1C110x operates from 1.8-V, 2.5-V, or 3.3-V supplies. Table 8-1 shows the output logics of the
LMK1C110x.
Table 8-1. Output Logic Table
INPUTS
OUTPUTS
CLKIN
1G
L
Yn
L
X
L
H
L
H
H
H
Copyright © 2020 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: LMK1C1106 LMK1C1108
LMK1C1106, LMK1C1108
www.ti.com
SNAS814 – DECEMBER 2020
9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The LMK1C110x family is a low additive jitter LVCMOS buffer solution that can operate up to 250-MHz at VDD
=
3.3 V and 200 MHz at VDD = 2.5 V to 1.8 V. Low output skew as well as the ability for synchronous output enable
is featured to simultaneously enable or disable buffered clock outputs as necessary in the application.
9.2 Typical Application
100-MHz
50-ꢀ Trace
LVCMOS Oscillator
V
CMOS
DD
Y0
Y1
CPU Clock
CLKIN
CMOS
FPGA Clock
100 ꢀ
100 ꢀ
50-ꢀ Trace
1G
PLL
Yn
From CPU
Reference
GND
Figure 9-1. System Configuration Example
9.2.1 Design Requirements
The LMK1C110x shown in Figure 9-1 is configured to fan out a 100-MHz signal from a local LVCMOS oscillator.
The CPU is configured to control the output state through 1G.
The configuration example is driving three LVCMOS receivers in a backplane application with the following
properties:
•
The CPU clock can accept a full swing DC-coupled LVCMOS signal. A series resistor is placed near the
LMK1C110x to closely match the characteristic impedance of the trace to minimize reflections.
The FPGA clock is similarly DC-coupled with an appropriate series resistor placed near the LMK1C110x.
The PLL in this example can accept a lower amplitude signal, so a Thevenin's equivalent termination is used.
The PLL receiver features internal biasing, so AC coupling can be used when common-mode voltage is
mismatched.
•
•
9.2.2 Detailed Design Procedure
Unused outputs can be left floating. See Section 10 for recommended filtering techniques.
9.2.3 Application Curves
The low additive jitter of the LMK1C110x is shown in Figure 9-2.
Figure 9-3 shows the low-noise 156.25-MHz reference source with 24.8-fs RMS jitter driving the LMK1C110x,
resulting in 27.3-fs RMS jitter when integrated from 12 kHz to 20 MHz at 3.3-V supply. The resultant additive
jitter measured is a low 11.4-fs RMS for this configuration.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: LMK1C1106 LMK1C1108
LMK1C1106, LMK1C1108
SNAS814 – DECEMBER 2020
www.ti.com
Figure 9-4 shows the low-noise 156.25-MHz reference source with 24.8-fs RMS jitter driving the LMK1C110x,
resulting in 29-fs RMS jitter when integrated from 12 kHz to 20 MHz at 2.5-V supply. The resultant additive jitter
measured is a low 15-fs RMS for this configuration.
Figure 9-5 shows the low-noise 156.25-MHz reference source with 24.8-fs RMS jitter driving the LMK1C110x,
resulting in 34-fs RMS jitter when integrated from 12 kHz to 20 MHz at 1.8-V supply. The resultant additive jitter
measured is a low 23.25-fs RMS for this configuration.
Figure 9-2. LMK1C110x Reference Phase Noise
24.8-fs (12 kHz to 20 MHz)
Figure 9-3. LMK1C110x 3.3-V Output Phase Noise
27.3-fs (12 kHz to 20 MHz)
Figure 9-4. LMK1C110x 2.5-V Output Phase Noise
29-fs (12 kHz to 20 MHz)
Figure 9-5. LMK1C110x 1.8-V Output Phase Noise
34-fs (12 kHz to 20 MHz)
Copyright © 2020 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: LMK1C1106 LMK1C1108
LMK1C1106, LMK1C1108
www.ti.com
SNAS814 – DECEMBER 2020
10 Power Supply Recommendations
High-performance clock buffers can be sensitive to noise on the power supply, which may dramatically increase
the additive jitter of the buffer. Thus, it is essential to manage any excessive noise from the system power
supply, especially for applications where the jitter and phase noise performance is critical.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass
capacitors provide the very low impedance path for high-frequency noise and guard the power supply system
against induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by
the device and should have low equivalent series resistance (ESR). To properly bypass the supply, the
decoupling capacitors must be placed very close to the power-supply terminals, be connected directly to the
ground plane, and laid out with short loops to minimize inductance. TI recommends adding as many high-
frequency (for example, 0.1 µF) bypass capacitors, as there are supply terminals in the package. TI
recommends, but does not require, inserting a ferrite bead between the board power supply and the chip power
supply that isolates the high-frequency switching noises generated by the clock buffer; these beads prevent the
switching noise from leaking into the board supply. It is imperative to choose an appropriate ferrite bead with
very low DC resistance to provide adequate isolation between the board supply and the chip supply, as well as
to maintain a voltage at the supply terminals that is greater than the minimum voltage required for proper
operation.
Figure 10-1 shows this recommended power supply decoupling method.
V
CC
Chip
Supply
Board
Supply
Ferrite Bead
C
C
C
10 …F
1 …F
0.1 …F
GND
GND
GND
Figure 10-1. Power Supply Decoupling
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: LMK1C1106 LMK1C1108
LMK1C1106, LMK1C1108
SNAS814 – DECEMBER 2020
www.ti.com
11 Layout
11.1 Layout Guidelines
Figure 11-1 shows a conceptual layout detailing recommended placement of power supply bypass capacitors.
For component side mounting, use 0402 body size capacitors to facilitate signal routing. Keep the connections
between the bypass capacitors and the power supply on the device as short as possible. Ground the other side
of the capacitor using a low-impedance connection to the ground plane.
11.2 Layout Example
Figure 11-1. PCB Conceptual Layout
Copyright © 2020 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: LMK1C1106 LMK1C1108
LMK1C1106, LMK1C1108
www.ti.com
SNAS814 – DECEMBER 2020
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
LMK1C1108EVM User Guide
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2020 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: LMK1C1106 LMK1C1108
PACKAGE OPTION ADDENDUM
www.ti.com
24-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMK1C1106PWR
LMK1C1108PWR
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
PW
14
16
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 105
-40 to 105
LMK1C6
LMK1C8
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Dec-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMK1C1106PWR
LMK1C1108PWR
TSSOP
TSSOP
PW
PW
14
16
3000
3000
330.0
330.0
12.4
12.4
6.9
6.9
5.6
5.6
1.6
1.6
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Dec-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMK1C1106PWR
LMK1C1108PWR
TSSOP
TSSOP
PW
PW
14
16
3000
3000
853.0
853.0
449.0
449.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明