LMP92018SQE/NOPB [TI]
LMP92018 Analog System Monitor and Controller;
| 型号： | LMP92018SQE/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LMP92018 Analog System Monitor and Controller |
| 文件： | 总33页 (文件大小：919K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMP92018
www.ti.com
SNAS514B –NOVEMBER 2011–REVISED MAY 2013
LMP92018 Analog System Monitor and Controller
Check for Samples: LMP92018
1
FEATURES
APPLICATIONS
2
•
8 ANALOG VOLTAGE MONITORING
CHANNELS
•
•
•
Communication Infrastructure
System Monitoring and Control
Industrial Monitoring and Control
–
–
–
10-Bit ADC with Programmable Input MUX
Internal/External Reference
DESCRIPTION
Tolerates High-Source Impedance at Lower
Sampling Rates
LMP92018 is a complete analog monitoring and
control circuit which integrates an eight channel 10-bit
Analog-to-Digital Converter (ADC), four 10-bit Digital-
to-Analog Converters (DACs), an internal reference,
an internal temperature sensor, a12-bit GPIO port,
and a 10MHz SPI interface.
•
•
4 PROGRAMMABLE ANALOG VOLTAGE
OUTPUTS
–
–
–
Four 10-Bit DACs
Internal/External Reference
Drives Loads up to 1nF
The eight channels of the ADC can be used to
monitor rail voltages, current sense amplifier outputs,
health monitors or sensors while the four DACs can
be used to control PA (Power Amplifier) bias points,
control actuators, potentiometers, etc.
VOLTAGE REFERENCE
–
–
User-Selectable Source: External or Internal
Internal Reference 2.5V
•
•
TEMPERATURE SENSOR
±2.5°C Accuracy
12-BIT GPIO PORT
Both the ADC and DACs can use either the internal
–
2.5V
reference
or
an
external
reference
independently allowing for flexibility in system design.
–
–
Each Bit Individually Programmable
User-Selectable Rail
The built-in digital temperature sensor enables
accurate (±2.5°C) local temperature measurement
whose value is captured in the user accessible
register.
•
SPI-COMPATIBLE BUS
User-Selectable Rail
–
Block Diagram
OUT3
OUT0
IN[7:0]
8
VDD
Multiplexer
Temp. Sensor
Int/Ext
Ref
SPI
Interface
GPIO
12
4
LMP92018
VIO
GND
CSB
REF
DRDYB
GPIO[11:0]
VGPIO
SCLK
DIN
DOUT
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
LMP92018
SNAS514B –NOVEMBER 2011–REVISED MAY 2013
www.ti.com
DESCRIPTION (CONTINUED)
The LMP92018 also includes a 12-bit GPIO port which allows for the resources of the microcontroller to be
further extended, thus providing even more flexibility and reducing the number of signal interfacing to the
microcontroller.
Both the GPIO port and the SPI compatible interface have independent supply pins enabling the LMP92018 to
interface with low voltage microcontrollers.
The LMP92018 is available in a space saving 36-pin WQFN package and is specified over the full -30°C to
+85°C temperature range.
Typical Application
5V
48V
5V
VDD
REF
Scaled
Voltage
Sensing
Ratiometric
Sensing
Voltage
Sense
Channels
IN[7:0]
8
LM94023
Temp
LMP8640
1.8V
VIO
Analog
Sensors
Current
sensing
ROUT<10k
DRDYB
+
-
Voltage
Source
uC
LMP92018
CSB
SCLK
DIN
DOUT
SPI
4
Servo
Actuator
Control
Analog
Voltage
Control
OUT[3:0]
4
PA
Bias
Control
3.3V
VGPIO
Digital
Control
Bidirectional
Digital Bus
GPIO[11:0]
12
Digital
Status
Indicators
2
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SNAS514B –NOVEMBER 2011–REVISED MAY 2013
OUT3
OUT0
IN[7:0]
8
VDD
Multiplexer
Temp. Sensor
Int/Ext
Ref
SPI
Interface
GPIO
12
4
LMP92018
VIO
GND
CSB
REF
DRDYB
GPIO[11:0]
VGPIO
SCLK
DIN
DOUT
Overview
The LMP92018 has a flexible, feature-rich functionality which makes it ideally suited for many analog monitoring
and control applications, for example, base-station PA subsystems. This device provides the analog interface
between a programmable supervisor, such as a microcontroller, and an analog system whose behavior is to be
monitored and controlled by the supervisor.
To facilitate the analog monitoring functionality, the device contains a single 10-bit ADC preceded by a 8-input
multiplexor.
The analog control functionality is served by four 10-bit voltage output DACs.
Additional digital monitoring and control can be realized via the General Purpose I/O port GPIO[11:0].
Two more blocks are present for added functionality: a local temperature sensor and an internal reference
voltage generator.
8-CHANNEL ANALOG SENSE WITH 10-BIT ADC
The user can monitor up to 8 external voltages with the 10-bit ADC and its 8-channel input MUX. Typically these
voltages will be generated by the analog sensors, instrumentation amplifiers, current sense amplifiers, or simply
resistive dividers if high potentials need to be measured.
PROGRAMMABLE ANALOG CONTROL VOLTAGE OUTPUTS
Four identical individually programmable 10-bit DAC blocks are available to generate analog voltages, which can
be used to control bias conditions of external circuits, position of servos, etc.
INTERNAL DIGITAL TEMPERATURE SENSOR
An on-board digital temperature sensor is available to report the device's own temperature. The temperature
sensor output is stored in the internal register for user readback via the SPI interface.
INTERNAL VOLTAGE REFERENCE SOURCE
The user can choose to enable the internal reference of 2.5V to use with the ADC and/or DACs. The internal
reference source can also drive an external load.
12-BIT GENERAL PURPOSE I/O
The GPIO port can be used to expand the microcontroller capabilities. This port is memory mapped to the
internal register, which in turn is accessible via the SPI interface. Each bit is individually programmable as an
input or an output
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SPI INTERFACE
The microcontroller communicates with LMP92018 via a popular SPI interface. This interface provides the user
full access to all Data, Status and Control registers of the device.
Connection Diagram
GPIO0
VDD
GND
GND
VGPIO
VIO
1
2
3
4
5
6
7
8
9
27
26
25
24
23
22
21
20
19
GPIO1
GPIO2
GPIO3
GPIO4
DAP
CSB
GPIO5
GPIO6
SCLK
DIN
GPIO7
DOUT
DRDYB
Figure 1. 36-Pin WQFN (Top View)
See NJK0036A Package
PIN DESCRIPTIONS
Function
Name
VDD
Pin
1
ESD Structures
Supply rail
ESD+
VGPIO
4
GPIO rail
VIO
5
SPI rail
GND
DAP
2, 3 14
*
Device Ground
Die Attach Pad. For best thermal
conductivity and best noise immunity
DAP should be soldered to the PCB pad
which is connected directly to circuit
common node (GND).
ESD+
IN[7:0]
35:28
Analog input
4
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PIN DESCRIPTIONS (continued)
Name
OUT[3:0]
DOUT
Pin
10:13
9
Function
ESD Structures
Analog output
SPI Data Output
ESD+
General Purpose Digital I/O. Logic level
is referenced to VGPIO pin.
GPIO[11:0]
15:18; 20:27
CSB
SCLK
DIN
6
7
8
SPI Chip Select, Active LO
SPI Data Clock
SPI Data Input
DRBYB
19
Data Ready, open-drain active LO
ESD+
ADC/DAC Voltage Reference Input or
Output
REF
36
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)(3)
VDD Relative to GND
−0.3V to 6.0V
−0.3V to VDD
−0.3V to VDD
6.0V
VIO Relative to GND
VGPIO Relative to GND
Voltage between any 2 pins(4)
Current in or out of any pin(4)
5mA
32mA, TA = 125°C
44mA, TA = 85°C
20mA, TA = 125°C
54mA, TA = 125°C
66mA, TA = 85°C
+150°C
Current through VDD
Current through VGPIO
Current through GND
Junction Temperature
Storage Temperature Range
−65°C to +150°C
2500V
Human Body Model
Machine Model
ESD Susceptibility(5)
200V
Charged Device Model
1500V
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) All voltages are measured with respect to GND = 0V, unless otherwise specified.
(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(4) When the input voltage (VIN) at any pin exceeds power supplies (VIN < GND or VIN > VDD), the current at that pin must not exceed
5mA, and the voltage (VIN) at that pin relative to any other pin must not exceed 6.0V. See Pin Descriptions for additional details of input
circuit structures.
(5) The Human Body Model (HBM) is a 100 pF capacitor charged to the specified voltage then discharged through a 1.5kΩ resistor into
each pin. The Machine Model (MM) is a 200 pF capacitor charged to specified voltage then discharged directly into each pin. The
Charged Device Model (CDM) is a specified circuit characterizing an ESD event that occurs when a device acquires charge through
some triboelectric (frictional) or electrostatic induction process and then abruptly touches a grounded object or surface.
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Operating Conditions(1)(2)
Operating Ambient Temperature
VDD Voltage Range
VIO Voltage Range
VGPIO Voltage Range
DAC Output Load C
θJA
−40°C to 125°C
4.75V to 5.25V
1.8V to VDD
1.8V to VDD
0nF to 1nF
25.2°C/W
θJC
2.4°C/W
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) All voltages are measured with respect to GND = 0V, unless otherwise specified.
Electrical Characteristics
Unless otherwise noted, these specifications apply for VDD=4.75V to 5.25V, REF=VDD, TA=25°C. Boldface limits are over
the temperature range of −30°C ≤ TA ≤ 85°C unless otherwise noted. DAC input code range 12 to 1012. DAC output
CL = 200 pF unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
ADC CHARACTERISTICS
Resolution with No Missing
Codes
10
10
Bits
DNL
INL
Differential Non-Linearity
Integral Non-Linearity
Offset Error
−0.9
−1
+1
1
LSB
OE
−2
+2
OEDRIFT
OEMTCH
GE
Offset Error Temperature Drift
Offset Error Match(1)
Gain Error
0.001
0.001
LSB/°C
LSB
−1
−2
1
2
GEDRIFT
GEMTCH
SINAD
THD
Gain Error Temperature Drift
Gain Error Match(1)
LSB/°C
LSB
−1
58
1
Signal-to-Noise Ratio
Total Harmonic Distortion
Spurious Free Dynamic Range
10 kHz Sine Wave
10 kHz Sine Wave, up to 5th harmonic
10 kHz Sine Wave
dB
dBc
dB
−69
70
SFDR
Offset Error change with VDD
Gain Error change with VDD
−150
−150
PSRR
Power Supply Rejection Ratio
DAC CHARACTERISTICS
Resolution
10
10
10
Bits
Bits
Monotonicity
DNL
INL
Differential Non-Linearity
RL = 100k
RL = 100k
RL = 100k
RL = 100k
−0.5
−2
+0.5
+2
LSB
Integral Non-Linearity
Offset Error(2)
OE
10
mV
OEDRIFT
Offset Error Temperature Drift
1
µV/°C
VDD = 5.25V, REF=5, RL = 100k,
CODE=3FFh
FSE
Full-Scale Error
-0.4
+0.3
+0.2
%FS
GE
Gain Error(3)
RL = 100k
RL = 100k
−0.2
GEDRIFT
Gain Error Temperature Drift
1.4
7
ppm/° C
mV
IOUT = 200 µA
IOUT = 1mA
ZCO
Zero Code Output
31
(1) Device Specification is guaranteed by characterization and is not tested in production.
(2) DAC Offset is the y-intercept of the straight line defined by DAC output at code 0d12 and 0d1011points of the measured transfer
characteristic.
(3) DAC Gain Error is the difference in slope of the straight line defined by DAC output at code 0d12 and 0d1011 points of transfer
characteristic, and that of the ideal characteristic.
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Electrical Characteristics (continued)
Unless otherwise noted, these specifications apply for VDD=4.75V to 5.25V, REF=VDD, TA=25°C. Boldface limits are over
the temperature range of −30°C ≤ TA ≤ 85°C unless otherwise noted. DAC input code range 12 to 1012. DAC output
CL = 200 pF unless otherwise noted.
Symbol
Parameter
Conditions
IOUT = 200 µA
IOUT = 1mA
RL = 100k
Min
Typ
Max
Units
4.975
4.975
4.975
FSO
Full Scale Output at code 3FFh
V
Output Short Circuit Current
(Source)(4)
VDD = 5V, OUT = 0V,
Input Code =3 FFh
IOS
IOS
−67
Output Short Circuit Current
(Sink)(4)
VDD = 5V, OUT = DREF,
Input Code = 000h
76
mA
TA = 85° C
TA = 125° C
RL = 2k or ∞
Enabled
10
Continuous Output Current per
Channel (to prevent damage)
IO
CL
6.5
Maximum Load Capacitance
DC Output Impedance
1000
1.7
pF
Ω
ROUT
Disabled
>20
MΩ
ANALOG INPUT CHARACTERISTICS
VIN
FS Input Range
REF
+1
V
ILEAK
ADC in HOLD or Power Down
−1
µA
In Acquisition mode
In Conversion mode
33
3
CINA
Input Capacitance
pF
V
REFERENCE CHARACTERISTICS
ADC Reference Input Range
2.5
2.5
VDD
VDD
DAC Reference Input Range
DAC Reference Input Resistance
DAC Reference Input Current
50
kΩ
125
1
µA
ADC Reference Current, during
conversion, average value
IVREF(ADC)
IVREF(PD)
External Reference, REF = VDD
µA
REF pin Current in Powerdown
REF Output Voltage
10
µA
V
2.5
Internal Reference Tolerance
REF Output Temperature Drift
REF Output Maximum Current
REF Output Load Regulation
REF Output Rail Regulation
–0.15
0.15
–0.6
%
17
1
ppm/°C
mA
%
4.75V≤VDD≤5.25V
−40°C to +125°C
±0.04
%
TEMPERATURE SENSOR
Resolution
Temperature Error(5)
0.0625
°C
°C
−2.5
+2.5
DIGITAL INPUT CHARACTERISTICS (GPIO[11:0])
VIH
VIL
Input HIGH Voltage
Input LO Voltage
0.7x VGPIO
V
0.3x
VGPIO
Hysteresis
250
±0.005
4
mV
µA
pF
IIND
Digital Input Current
Input Capacitance
±1
CIND
(4) Indicates the typical internal short circuit current limit. Sustained operation at this level will lead to device damage.
(5) Device Specification is guaranteed by characterization and is not tested in production.
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Electrical Characteristics (continued)
Unless otherwise noted, these specifications apply for VDD=4.75V to 5.25V, REF=VDD, TA=25°C. Boldface limits are over
the temperature range of −30°C ≤ TA ≤ 85°C unless otherwise noted. DAC input code range 12 to 1012. DAC output
CL = 200 pF unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DIGITAL INPUT CHARACTERISTICS (CSB, DIN, SCLK)
VIH
VIL
Input HIGH Voltage
Input LO Voltage
Hysteresis
0.7 x VIO
V
V
0.3 x VIO
±1
250
±0.005
4
mV
µA
pF
IIND
Digital Input Current
Input Capacitance
CIND
DIGITAL OUTPUT CHARACTERISTICS (GPIO[11:0])
IOUT = 200 µA
0.01
0.07
0.4
0.4
VOL Output LO Voltage
V
V
IOUT = 1.6 mA
VGPIO = VDD = 5V
IOUT = 200µA
VGPIO-0.2
VGPIO-0.5
VOH
Output HI Voltage
IOUT = 1.6 mA
VGPIO = VDD = 5V
TRI-STATE Output Leakage
Current
IOZH, IOZL
COUT
VGPIO=VDD
±5
µA
pF
Output Capacitance
4
DIGITAL OUTPUT CHARACTERISTICS (DOUT)
IOUT = 200 µA
0.01
0.07
0.4
0.6
V
V
VOL Output LO Voltage
IOUT = 1.6 mA
VIO = 3.3V
IOUT = 200 µA
VIO-0.2
VIO-0.5
VOH
Output HI Voltage
V
IOUT = 1.6 mA
VIO = 3.3V
TRI-STATE Output Leakage
Current
IOZH, IOZL
COUT
VGPIO = 1.8V =VDD
±5
µA
pF
Output Capacitance
4
DIGITAL OUTPUT CHARACTERISTICS (DRDYB)
IOUT = 1.6 mA
VIO = 3.3V to VDD
VOH_MAX
VOL
Maximum Output HI Voltage
Output LO Voltage
VIO-0.5
µA
V
Force 0V or VDD
0.01
5
POWER SUPPLY CHARACTERISTICS
VDD
VGPIO
VIO
Supply Voltage Range
GPIO Rail Range
4.75
1.8
5.5
VDD
VDD
4
V
SPI Rail Range
1.8
IDD
Supply Current, Conversion Mode
OUT[3:0] pins RL = ∞
OUT[3:0] pins RL = ∞
mA
Power Consumption, Conversion
Mode
PWRCONV
21
mW
Supply Current, Power-Down
Mode
Power-On Reset(6)
IPD
50
µA
V
VPOR
1.9
2.7
AC ELECTRICAL CHARACTERISTICS
tTRACK
tHOLD
ADC Track Time
ADC Hold Time
Dictated by SPI bus activity
Dictated by SPI bus activity
t8+9×t1
15×t1
µs
µs
25%FS to 75%FS code change,
RL = 2K, CL = 200 pF
ts
DAC Settling Time(7)
20
µs
(6) During the power up the supply rail must ramp up beyond VPOR MIN for the device to acquire default state. After the supply rail has
reached the nominal level, the rail can drop as low as VPOR MAX for the current state to be maintained.
(7) Device Specification is guaranteed by characterization and is not tested in production.
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Electrical Characteristics (continued)
Unless otherwise noted, these specifications apply for VDD=4.75V to 5.25V, REF=VDD, TA=25°C. Boldface limits are over
the temperature range of −30°C ≤ TA ≤ 85°C unless otherwise noted. DAC input code range 12 to 1012. DAC output
CL = 200 pF unless otherwise noted.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tCONV
Temperature Conversion Time
25.85
ms
SPI TIMING CHARACTERISTICS
SPI Clock Period during ADC
data access
t1
t1
178
178
12500
5000
ns
ns
SPI Clock Period during
Temperature Sensor access
SPI Clock Period for all
t1
transactions not involving ADC or
Temperature Sensor
100
ns
tr
tf
SCLK Rise Time
SCLK Fall Time
SCLK HIGH Time
SCLK LOW Time
2
2
ns
ns
ns
ns
t2
t3
8
8
CSB set-up time to SCLK falling
edge
t4
5
ns
t5
t6
DIN Set-up time
DIN Hold time
5
4
ns
ns
CSB hold time after 24th falling
edge of SCLK
t7
t8
10
ns
ns
CSB High Pulse Width
30
10
5
CL=30pF, VIO=1.8
DOUT hold time after SCLK
Rising Edge
tDH
ns
CL=30pF, 3V≤VIO≤5.25V
DOUT Delay after SCLK Rising
Edge
tDD
t11
tDOZ
tZDO
CL=30pF
40
ns
ns
SCLK Delay after CSB Rising
Edge
3
5
CSB Rising Edge to DOUT TRI-
STATE
4
10
14
ns
ns
CSB Falling Edge to DOUT active
sink/source 200uA, CL=150pF
SPI Interface Timing Diagram
t
2
t
1
70%
30%
70%
SCLK
1
2
23
24
t
t
t
f
3
70%
r
70%
70%
CSB
DIN
t
11
t
8
PD0
D23
D22
D1
D0
DOUT
PD23
PD22
PD1
PD0
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70%
SCLK
CSB
30%
30%
30%
t
4
t
7
70%
CSB
SDO
30%
t
t
ZDO
DOZ
70%
30%
SCLK
SDI
70%
30%
t
t
6
5
70%
70%
SCLK
SDO
70%
30%
70%
30%
t
t
DD
DH
10
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Typical Performance Characteristics
ADC: DNL
ADC: INL
1.0
0.8
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0.0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
256
512
768
1024
0
256
512
768
1024
OUTPUT CODE
OUTPUT CODE
Figure 2.
Figure 3.
DAC: DNL
DAC: INL
1.0
0.8
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0.0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0 1002003004005006007008009001000
INPUT CODE
0
256
512
INPUT CODE
768
1024
Figure 4.
Figure 5.
ADC: DNL vs. Temperature
ADC: INL vs. Temperature
0.5
0.4
0.5
0.4
Min DNL
Max DNL
Min INL
Max INL
0.3
0.3
0.2
0.2
0.1
0.1
0.0
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
-30
-10
10
30
50
70
90
-30
-10
10
30
50
70
90
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 6.
Figure 7.
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Typical Performance Characteristics (continued)
DAC: DNL vs. Temperature
DAC: INL vs. Temperature
0.5
0.4
0.5
0.4
Min DNL
Max DNL
Min INL
Max INL
0.3
0.3
0.2
0.2
0.1
0.1
0.0
0.0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
-30
-10
10
30
50
70
90
-30
-10
10
30
50
70
90
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 8.
Figure 9.
OUTx Output Load Regulation
Temperature Sensor Error
20
15
10
5
1.5
1.0
0.5
0.0
-0.5
0
-5
-10
-15
-20
-10 -8 -6 -4 -2
0
2
4
6
8
10
-40 -20
0
20 40 60 80 100 120
DAC OUTPUT CURRENT (mA)
TEMPERATURE (°C)
Figure 10.
Figure 11.
Internal Reference Output
Temperature Drift
15
10
5
0
-5
-40 -20
0
20 40 60 80 100 120
TEMPERATURE (°C)
Figure 12.
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INSTRUCTION SET
The following is a complete listing of the instruction set supported by the LMP92018. Where applicable the
default state or register content is indicated in bold type.
The digital interface (SPI) protocol is described in SERIAL INTERFACE. The interface timing diagram is in SPI
Interface Timing Diagram
NOTE: the tables in following sections detail the data transfers of 2 subsequent SPI frames . The FRAME
1 column shows the user input into pin DIN of the device. The FRAME 2 column in the device output at
DOUT.
TEMPERATURE SENSOR CONFIGURE
A single bit, TSS, controls the mode of operation of the internal temperature sensor. The bit can be set and
tested via the SPI transactions shown in the following table. The internal temperature sensor is described in
DIGITAL TEMPERATURE SENSOR.
FRAME 1: DIN
Payload
15:1
FRAME 2: DOUT
Payload
Command
22:16
Command
22:16
Bit→
READ
WRITE
23
1
0
x
23
1
15:1
0
TSS
0
0010000
0010000
x
0010000
0010000
000000000000000
000000000000000
0
000000000000000
TSS
0
x
Don't Care
1: Temperature Sensor in Continuous Conversion Mode
TSS
0: Temperature Sensor In One Shot Mode
REFERENCE CONFIGURE
The internal reference mode of operation is controlled by a 3 bit sequence, CREF. The sequence can be set and
tested via the SPI transactions shown in the following table. The reference block is described in INTERNAL
VOLTAGE REFERENCE SOURCE.
FRAME 1: DIN
Payload
FRAME 2: DOUT
Command
22:16
Command
22:16
Payload
15:3
Bit→
READ
WRITE
23
1
15:3
2:0
x
23
1
2:0
CREF
000
0010001
0010001
x
0010001
0010001
0000000000000
0000000000000
0
0000000000000
CREF
0
x
Don't care
Reference Mode Selector
000: AREF external, DREF internal
001: AREF and DREF internal; REF pin is internally disconnected
010: AREF and DREF external
CREF
011: AREF internal, DREF external
100: Deep Sleep
101: AREF and DREF internal; REF driven by internal reference
110: Deep Sleep
111: Deep Sleep
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DAC CONFIGURE
The individual DACs can be enabled by setting a corresponding bit in the 4–bit CDAC word. The CDAC word can
be set and tested via the SPI transactions shown in the following table. The DAC block is described in
PROGRAMMABLE ANALOG OUTPUT SUBSYSTEM.
FRAME 1: DIN
FRAME 2: DOUT
Payload
Command
22:16
Payload
15:4
Command
22:16
Bit→
READ
WRITE
23
1
3:0
x
23
1
15:4
3:0
0011000
0011000
x
0011000
0011000
000000000000
000000000000
CDAC
0000
0
000000000000
CDAC
0
x
Don't care
1: enables DAC corresponding to bit position
0: disables corresponding DAC
CDAC
e.g. CDAC=[0101] enables DAC2 and DAC0
UPDATE ALL DACs
All 4 DAC channels' outputs can be simultaneously set to the same level corresponding to a 10–bit DDATA code.
The sequence in the following table provides a WRITE only functionality. The DAC block is described in
PROGRAMMABLE ANALOG OUTPUT SUBSYSTEM.
FRAME 1: DIN
FRAME 2: DOUT
Payload
Command
22:16
0011001
Payload
11:2
Command
22:16
0011001
Bit→
WRITE
23
15:12
1:0
23
15:12
11:2
1:0
0
0000
DDATA
00
0
0000
0000000000
00
x
Don't care
DDATA will be loaded into all all DACs' input registers simultaneously. DDATA is a 10–bit unsigned integer.
DDATA
GENERAL CONFIGURATION
The device can indicate to the new ADC conversion data availability via the DRDYB pin. This functionality is
enabled by setting the internal DRDY bit. The bit can be set and tested via the SPI transactions shown in the
following table. Details of the DRDYB pin functionality are described in Conversion Sequence and DIGITAL
TEMPERATURE SENSOR
FRAME 1: DIN
FRAME 2: DOUT
15:1
Command
22:16
Payload
Command
22:16
Payload
Bit→
READ
23
1
15:1
0
x
23
1
0
DRDY
0
0011110
0011110
x
0011110
0011110
000000000000000
000000000000000
WRITE
0
000000000000000
DRDY
0
x
Don't Care
1: Disables the DRDYB pin function
DRDY
0: Enables the DRDYB pin function
GPIO CONFIGURE
Individual bits of the general purpose digital I/O port can be configured to drive (output), or sense (input) only.
Setting a corresponding bit in the 12–bit CGPIO word will enable that pin to drive. The sequences in the following
table provide a READ and WRITE capability for the internal CGPIO register. The GPIO block is described in
GENERAL PURPOSE DIGITAL I/O.
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FRAME 1: DIN
FRAME 2: DOUT
Command
22:16
Payload
Command
Payload
Bit→
READ
23
1
15:12
x
11:0
x
23
1
22:16
15:12
0000
0000
11:0
0011111
0011111
0011111
0011111
CGPIO
WRITE
0
0000
CGPIO
0
000000000000
x
Don't Care
1: sets corresponding GPIO pin as output
CGPIO
0: sets corresponding GPIO pin as input
e.g. CGPIO=[000011110000] enables GPIO[7:4] pins as outputs, all other GPIO pins are inputs
STATUS
Internal bit, RDY, indicates when the device has completed its power-up sequence. The RDY bit can be tested
via the SPI transaction shown in the following table.
FRAME 1: DIN
FRAME 2: DOUT
Command
22:16
0100000
Payload
Command
22:16
0100000
Payload
Bit→
READ
23
15:1
0
23
15:1
0
1
x
x
1
000000000000000
RDY
x
Don't Care
Internal Power On Reset circuit sets this bit
1: device ready
RDY
0: device not ready
GPI STATE
The logic state present at the GPIO pins of the device is always reported in the SGPI register. The SGPI register
contents can be tested via the SPI transaction shown in the following table. The GPIO block is described in
GENERAL PURPOSE DIGITAL I/O.
FRAME 1: DIN
FRAME 2: DOUT
Command
22:16
0110000
Payload
Command
22:16
0110000
Payload
Bit→
READ
23
15:12
11:0
23
15:12
11:0
1
x
x
1
0000
SGPI
x
Don't Care
Each bit Indicates the state at the corresponding GPIO pins of the device
SGPI
GPO DATA
The GPIO pins configured to drive, will drive the state indicated in the CGPO register. The CGPO register can be
set or tested via the SPI transactions shown in the following table. The GPIO block is described in GENERAL
PURPOSE DIGITAL I/O.
FRAME 1: DIN
FRAME 2: DOUT
Command
22:16
Payload
Command
22:16
Payload
Bit→
READ
WRITE
23
1
15:12
x
11:0
x
23
1
15:12
0000
0000
11:0
CGPO
12'b0
0110001
0110001
0110001
0110001
0
0000
CGPO
0
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x
Don't Care
Each bit will be forced at the corresponding GPIO pin of the device. Bits corresponding to GPIO pins configured as inputs
will be ignored. CGPO[11:0]=0x000
CGPO
VENDOR ID
The 16–bit ID sequence is factory set, and can only be tested via the SPI transaction shown in the table below.
FRAME 1: DIN
FRAME 2: DOUT
Command
22:16
Payload
15:0
x
Command
22:16
1000000
Payload
15:0
Bit→
READ
23
23
1
1000000
1
ID
x
Don't Care
ID
Vendor ID number. ID = 0x0028.
VERSION/STEPPING
Version and Stepping words are factory set and can only be tested via the SPI transaction shown in the table
below.
FRAME 1: DIN
FRAME 2: DOUT
Command
22:16
Payload
Command
22:16
Payload
Bit→
READ
23
15:4
3:0
23
15:4
3:0
1
1000001
x
x
1
1000001
VER
STEP
x
Don't Care
VER
Indicates the device version number. VER=0x000
Indicates stepping number. STEP = 0x0
STEP
DAC DATA REGISTER ACCESS
Each DAC's input data register, DDATA, is individually addressable, and its contents can be updated without
affecting remaining 3 DACs. The content of each DDATA can be tested and set via the SPI transactions shown
in the following table. The DAC block is described in PROGRAMMABLE ANALOG OUTPUT SUBSYSTEM.
FRAME 1: DIN
FRAME 2: DOUT
Command
22:18
Payload
11:2
Command
22:18
Payload
11:2
Bit→
READ
WRITE
23
1
17:16
15:12
x
1:0
x
23
1
17:16
15:12
0000
0000
1:0
00
00
10100
ADR
ADR
x
10100
ADR
ADR
DDATA
10'b0
0
10100
0000
DDATA
00
0
10100
x
Don't Care
DAC address:
00: DAC0
01: DAC1
10: DAC2
11: DAC3
ADR
DDATA
DAC input data. DDATA is a 10–bit unsigned integer. DDATA=0x000
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ADC INPUT MUX SELECT DATA READ COMMAND
The selection of the analog input, and the read-back of the ADC conversion result are completed by the SPI
transaction shown in the following table. The ADC block is described in ANALOG SENSE SUBSYSTEM.
FRAME 1: DIN
FRAME 2: DOUT
Command
22:19
Payload
11:2
x
Command
23 22:19 18:16
1100 ADR
Payload
11:2
ADATA
Bit→
READ
23
18:16
ADR
15:12
1:0
15:12
1:0
1
1100
x
x
1
0000
00
x
Don't Care
ADC Input Address:
000: IN0
001: IN1
010: IN2
ADR
011: IN3
100: IN4
101: IN5
110: IN6
111: IN7
ADATA
ADC output Data. ADATA is a 10–bit unsigned integer.
TEMPERATURE SENSOR OUTPUT REGISTER
The contents of the internal temperature sensor output register can be tested by the SPI transaction shown in the
following table. The internal temperature sensor is described in DIGITAL TEMPERATURE SENSOR.
FRAME 1: DIN
FRAME 2: DOUT
Payload
Command
22:16
1110000
Payload
Command
22:16
Bit→
READ
23
15:12
11:0
23
15:12
11:0
1
x
x
1
1110000
0000
TDATA
x
Don't Care
Temperature Sensor Output Data. TDATA is a 12–bit signed integer.
TDATA
NOOP — No Operation
NOOP offers no functionality of its own. It is provided as the means of completing the pending READ operation
i.e. “pushing out” the data requested in the previous transaction.
FRAME 1: DIN
FRAME 2: DOUT
Command
23:16
Payload
15:0
x
Command
23:16
Payload
15:0
Bit→
NOOP
00000000
00000000
16'b0
x
Don't Care
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FUNCTIONAL DESCRIPTION
ANALOG SENSE SUBSYSTEM
The device is capable of monitoring up to 8 externally applied voltages. The system is centered around a 10-bit
SAR ADC fronted by an 8-input mux.
Sampling and Conversion
The external voltage is sampled onto the internal CHOLD capacitor during the TRACK period, see Figure 13. Once
acquired, the stored charge is measured using the Successive Approximation Register (SAR) method. The timing
of the internal state machine is governed by the user defined signals CSB and SCLK. The sequence of the
events is described in Conversion Sequence.
Attention should be paid to the output impedance of the sensed voltage source and the capacitance present at
the INx input of the device (which is dominated by CHOLD during TRACK time). The combined circuit's RC limits
the bandwidth and settling time of the input signal. At maximum SPI bus data rate, it is recommended to limit the
output resistance ROUT of the signal source to assure the accuracy of the conversion.
During the HOLD period (duration of t
specified in Electrical Characteristics ) , all mux switches are OFF,
HOLD
and the charge captured on CHOLD is measured to produce an ADC output code. This charge is never lost during
the conversion, unless the SCLK is so slow that the charge is lost due to the internal capacitor's leakage. Under
normal conditions the charge stored is modified only during TRACK period.
Below is a typical ADC output code as a function of input voltage at device pin INx, x=0...7:
VINX
AREF
x 1023
ADATA = INT
(
)
(1)
In the expression above AREF is the reference voltage input to the internal ADC. See INTERNAL VOLTAGE
REFERENCE SOURCE.
Sampling
Switch
ROUT< 4k
VDD/2
INx
C
HOLD
+
-
Voltage
Source
Device Pin
Figure 13. ADC During TRACK Period
Sampling Transient
As noted in Sampling and Conversion the charge acquired during TRACK period is maintained throughout the
conversion process. Since the successive sample operations will involve different input potentials an
instantaneous current will flow at the beginning of TRACK period. This always leads to temporary disturbance of
the input potential. This current, and resulting disturbance, will vary with the magnitude of the sampled signal and
source impedance ROUT, see Figure 13. If ROUT is excessive, and resulting RC time constant of the input
circuit too long, the preceding sample may affect the new sample's accuracy.
If high ROUT cannot be avoided, another method of improving the acquisitin accuracy is to lengthen the TRACK
time. The ADC TRACK time is fully controlled by the user inputs CSB and SCLK, see Figure 14. The time
allotted for the CHOLD to settle can be arbitrarily adjusted via the length of the CSB=High period and the
frequency of SCLK, subject to limitations on CSB and SCLK timing as shown in Electrical Characteristics .
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Conversion Sequence
The ADC conversion sequence and output activity are shown in Figure 14. The ADC readback occupies 2 SPI
frames. The first frame is used to issue a read command and connect the ADC input to the specified device input
pin INx. At the end of the first frame, at the rising edge of the CSB, the ADC sampling capacitor is connected to
the signal source, INx, and the TRACK period begins. The second frame executes the SAR algorithm (the HOLD
period) on the acquired sample and shifts the resulting data out through the DOUT output. The TRACK period
extends for 9 SCLK cycles, then the mux disconnects the sampling capacitor from the signal source, and the
SAR operation begins. The data is shifted out MSB first. Once the SAR operation is completed, the ADC powers
down for the remainder of the second frame.
If DRDYB output pin functionality is enabled, see GENERAL CONFIGURATION, then DRDYB output will be low
while ADC output data is present at DOUT.
If the ADC is not in TRACK or HOLD, the internal PD (Power Down) signal of the ADC is asserted thus powering
down all the active circuits of the ADC, and opening all analog input mux switches. See the PD period in the
Figure 14.
Frame 1
Frame 2
CSB
DIN
READ IN0
dummy payload
COMMAND
READ IN0
PAYLOAD
ADATA
DOUT
Echo Previous
previous DATA IF ANY
TRACK
HOLD
PD
CSB
SCLK
1
9
12
DRDYB
Figure 14. ADC Sequence Diagram
ADC Reference Selection
By default, the ADC operates from the external reference voltage applied at the REF pin of the device. It should
be noted that due to the architecture of the ADC the DC current flowing into the REF input is zero during
conversion. However, the transient currents ( see IVREF in Electrical Characteristics ) during the HOLD time can
be significant. For further details of reference source selection see INTERNAL VOLTAGE REFERENCE
SOURCE
Selection of the ADC reference source automatically dictates the attenuation level of the input signal. Figure 15
shows the ADC input configuration during the TRACK period when the REF pin is chosen as the source of the
reference voltage. The entire CHOLD available is used to acquire the signal. The transfer function of the ADC in
this configuration remains as shown in Sampling and Conversion
15 pF
Sampling
Switch
INx
VDD/2
15 pF
Device Pin
Figure 15. ADC Sampling when AREF is Externally Supplied
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In contrast, the Figure 16 shows the sampling capacitor during TRACK period when the internally generated
reference is selected as the reference source of the ADC. In this configuration ½CHOLD is used to sample the
input signal effectively attenuating it by a factor of 2. The resulting overall ADC transfer function becomes:
VINX
2 x AREF
x 1023
ADATA = INT
(
)
(2)
15 pF
Sampling
Switch
INx
VDD/2
15 pF
Device Pin
Figure 16. ADC Sampling when AREF is Internally Supplied
PROGRAMMABLE ANALOG OUTPUT SUBSYSTEM
This subsystem consists of 4 identical DACs whose output is a function of the user programmable registers
DACx. This functionality is described in DAC Core. The DAC input registers are individually addressable, as
described DAC DATA REGISTER ACCESS. The user can also update all of the DAC input registers to the same
value with a single SPI command. See UPDATE ALL DACs
Each DAC channel can be individually enabled/disabled via the SPI interface command. See DAC CONFIGURE.
When a channel is disabled, its output OUTx is in HiZ state, but the DAC input register still maintains its data.
User can select the source of the reference input to all DACs. This functionality is described in DAC Reference
Selection
DAC Core
The DAC core is based on a Resistive String architecture which guarantees monotonicity of its transfer function.
The input data is single-registered, meaning that the OUTx of the DAC is updated as soon as the data is updated
in the DAC input data register at the end of the SPI transaction.
The functional diagram of the DAC Core is shown in Figure 17
DREF
VDD
0
1
R
R
R
DECODER
DDATAx
10
Buffer
OUTx
R
ä(R) = 200k
R
0
1
0
1
PD
Device Pin
Figure 17. DAC Block Diagram
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The ideal DAC core transfer function from DATAx to OUTx , x=0...3, can be expressed as:
DDATAx
1024
(
)
OUTx = DREF
(3)
The above expression is subject to non-idealities of the resistor string and limitations of the output buffer. These
limitations are tabulated in Electrical Characteristics
In Figure 17, the PD (Power Down) signal is asserted when the given channel is disabled via the SPI command.
The PD causes the DAC buffer bias currents to shut down, and it breaks the current path through the resistive
string.
DAC Reference Selection
All DAC channels operate from the same, user selectable, reference source. In Figure 17, DREF input can be
supplied by the external source, applied to the REF pin of the device, or from the internal reference generator
block. The reference block functionality is described in INTERNAL VOLTAGE REFERENCE SOURCE.
Reference selection automatically forces configuration of the DACs' output buffers. If the external reference
source, which is DREF driven by the REF device pin, is selected then all of the DAC output buffers are in 1x
configuration, as seen inFigure 18. In the external reference mode, each active DAC presents a resistive load to
the source attached to the device's REF pin, see Figure 17 and Figure 21.
The overall DAC transfers function remains as shown in DAC Core
+
-
600
Figure 18. DAC Buffer when DREF Externally Supplied
If the internal reference generator is selected to drive the DAC's DREF input, then all of the DACs' buffers are
automatically forced into 2x gain configuration as shown in Figure 19. This results in an overall transfer function
of the DACs to change to:
DDATAx
1024
OUTx = 2 x DREF
(
)
(4)
+
-
100k
100k
Figure 19. DAC Buffer when DREF Internally Supplied
DIGITAL TEMPERATURE SENSOR
The local temperature sensor (TS) operates in one of the 2 possible modes: Continuous or One-Shot. The user
selects the mode of operation via the SPI instruction, see TEMPERATURE SENSOR CONFIGURE. The output
of the temperature sensor is a 12 bit signed integer, where each LSB represents 0.0625°C. Temperature
sensor's output code (TDATA) examples are shown in Table 1.
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Table 1. Temperature Readout Examples
Temperature
125°C
TDATA
0111.1101.0000
0001.1001.0000
0000.0000.0001
0000.0000.0000
1111.1111.1111
1101.1000.0000
25°C
0.0625°C
0°C
−0.0625°C
−40°C
In Continuous mode, the temperature sensor operates in the background and independently of the SPI bus
activity. Subsequent temperature conversion results are stored in the output register which can be accessed by
the user via the SPI interface.
In One-Shot mode temperature sensor is inactive until the user issues an instruction, via SPI interface, to read
the temperature sensor data. The temperature conversion commences at the rising edge of CSB following the
read instruction. After the delay of tCONV, the new temperature data is available in the temperature sensor output
register. If configured, the DRDYB output indicates when the temperature conversion has been completed, see
Figure 20.
The SPI instruction for accessing the temperature data is described in TEMPERATURE SENSOR OUTPUT
REGISTER
In Figure 20 below a One-Shot temperature read transaction is shown. The temperature readback occupies 2
SPI frames: the first frame is used to issue temperature sensor read instruction, the second frame is used for the
data readback. The falling edge of the DRDYB signal indicates the instance the new temperature data is present
in the output register. The DRDYB is deasserted by the rising edge of the CSB.
NOTE: The DRDYB output in One-Shot temperature conversion mode is asynchronous to the SCLK of
the SPI interface. DRDYB functionality is not provided in the Continuous mode of the temperature sensor
operation.
READ TS COMMAND
CSB
1
8
24
1
12
24
SCLK
DIN
arb.
arb.
arbitrary activity
DOUT
DRDYB
arbitrary activity
arb.
TDATA
t
CONV
Figure 20. One-Shot Temperature Read Sequence
INTERNAL VOLTAGE REFERENCE SOURCE
The device has a built in precision 2.5V reference block which can be used to provide reference potential to
either the ADC (AREF) or the DACs (DREF), both at once, or to external load via REF pin. The precision
reference is always isolated from its loads by individual buffers, see Figure 21.
The CREF register sets the reference block mode of operation. The SPI instruction to update or read contents of
the CREF register is shown in REFERENCE CONFIGURE. The switch activity due to the CREF content is
tabulated in Table 2.
The modes corresponding to CREF=(100) or (110) or (111) are the Deep Sleep modes. In these modes the
internal temperature sensor, the ADC, the DACs, and the reference block buffers (but not the 2.5V reference) are
powered down.
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CREF
A
B
REF
C
D
E
Reference
AREF
DREF
SPI Control Word
Device Pin
Figure 21. Reference Selector Diagram
Table 2. Reference Selector Functionality
(1 to CLOSE Switch)
Switch
CREF
000
001
010
011
100
101
110
111
A
1
0
1
0
0
0
0
0
B
0
0
1
1
0
0
0
0
C
0
0
0
0
0
1
0
0
D
0
1
0
1
0
1
0
0
E
1
1
0
0
0
1
0
0
GENERAL PURPOSE DIGITAL I/O
The GPIO[11:0] port is memory mapped to registers SGPI and CGPO. Both registers are accessible through the
SPI interface.
The SGPI register content reflects at all times the digital state at the GPIOx device pins. The format of the read
command of the General Purpose Digital I/O is shown in GPI STATE.
The GPIOx pins can be configured as outputs by setting the individual bits in the CGPIO registers. Each bit in
CGPIO register enables corresponding output buffer in the GPIOx port. See GPIO CONFIGURE. Once the drive
is enabled, the logic state at the outputs is dictated by the contents of the CGPO register. See GPO DATA.
The functional diagram of the General Purpose Digital I/O is shown in Figure 22.
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SGPI[x]
GPIO[x]
CGPO[x]
CGPIO[x]
EN
SPI Control Word
Device Pin
Figure 22. General Purpose Digital I/O Diagram
SERIAL INTERFACE
The 4-wire interface is compatible with SPI, QSPI and MI- CROWIRE, as well as most DSPs. See the SPI
Interface Timing Diagram for timing information of the read and write sequences. The serial interface uses four
signals CSB, SCLK, DIN and DOUT.
A bus transaction is initiated by the falling edge of the CSB. Once CSB is low, the input data is sampled at the
DIN pin by the falling edge of the SCLK, and shifted into the internal shift register (FIFO). The output data is put
out on the DOUT pin on the rising edge of SCLK. At least 24 SCLK cycles are required for a valid transfer to
occur. If CSB is raised before 24th rising edge of the SCLK, the transfer is aborted and preceding data ignored. If
the CSB is held low after the 24th falling edge of the SCLK, the data will continue to flow through the internal
shift register (FIFO) and out the DOUT pin. When CSB transitions high, the internal controller decodes the FIFO
contents — most recent 24 bits that were received before the rising edge of CSB.
While CSB is high, DOUT is in a high-Z state. At the falling edge of CSB, DOUT presents the MSB of the data
present in the shift register. DOUT is updated on every subsequent falling edge of SCLK (note — the first DOUT
transition will happen on the first rising edge AFTER the first falling edge of SCLK when CSB is low).
The 24 bits of data contained in the FIFO are interpreted as an 8 bit COMMAND word followed by 16 bits of
DATA. The general format of the 24 bit data stream is shown in Figure 23. The full Instruction Set is tabulated in
Instruction Set.
COMMAND/PAYLOAD DECODE
CSB
COMMAND
8 bits
PAYLOAD
16 bits
DIN
Figure 23. General SPI Frame Format
SPI Write
SPI write operation occupies a single 24–bit frame, as shown in Figure 24. Write operation always starts with a
leading 0 (zero) in the 8–bit COMMAND sequence. The format of the data transfer and user instruction set is
shown in Instruction Set.
Note that write operation also produces DOUT activity. The DOUT output echoes back the previous frame's
COMMAND byte, followed by 16 zeros.
24
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Frame 1
Frame 2
CSB
DIN
WRITE COMMAND
8 bits
DATA
16 bits
PAYLOAD
16 bits
Next Command
8 bits
HiZ
HiZ
HiZ
WRITE COMMAND
8 bits
All zero
16 bits
Prior COMMAND
8 bits
PAYLOAD
16 bits
DOUT
Figure 24. SPI Write Transaction
SPI Read
The read operation requires all 4 wires of the SPI interface: SCLK, CSB, DIN, DOUT. The simplest read
operation occurs automatically during any valid transaction on the SPI bus since DOUT pin always shifts out the
leading 8 bits (COMMAND) of the previous transaction — this is regardless of the RW bit setting in the
COMMAND byte. This functionality gives the user an easy method of verifying the SPI link.
Reading of the specific content requires 2 SPI frames, as shown in Figure 25. The first frame is used to issue a
read command, which always begins with RW bit set in the COMMAND byte. The second frame echoes back the
first frame's COMMAND byte, followed by the 16–bit PAYLOAD containing the requested data. Consult
Instruction Set for the COMMAND format and returned data alignment within PAYLOAD.
Frame 1
Frame 2
CSB
DIN
PAYLOAD
16 bits
READ COMMAND
Arbitrary
16 bits
Next Command
8 bits
8 bits
HiZ
HiZ
HiZ
READ COMMAND
8 bits
PAYLOAD
16 bits
Prior COMMAND
8 bits
PAYLOAD
16 bits
DOUT
Figure 25. SPI Read Transaction
SPI Daisy Chain
It is possible to control multiple LMP92018s with a single master equipped with one SPI interface. This is
accomplished by connecting the multiple LMP92018 devices in a Daisy Chain. The scheme is depicted in
Figure 26. A chain of arbitrary length can be constructed since individual devices do not count the data bits
shifted in. Instead, they wait to decode the contents of their respective shift registers until CSB is raised high.
SYNC
CLK
(1)
(2)
(3)
SPI/QSPI
MICROWIRE
CSB
CSB
CSB
MASTER
SCLK
SCLK
SCLK
MOSI
DIN DOUT
LMP92018
DIN DOUT
LMP92018
DIN DOUT
LMP92018
MISO
Figure 26. SPI Daisy Chain
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A typical bus cycle for this scheme is initiated by the falling CSB. After the 24 SCLK cycles new data starts to
appear at the DOUT pin of the first device in the chain, and starts shifting into the second device. After the 72
SCLK cycles following the falling CSB edge, all three devices in this example will contain new data in their input
shift registers. Raising CSB will begin the process of decoding data in each device. When in the Daisy Chain the
full READ and WRITE capability of every device is maintained.
A sample of SPI data transfer appropriate for a 3 device Daisy Chain is shown in Figure 27.
72 Clock Cycles
CSB
MOSI
DATA (3)
DATA (1)
DATA (2)
Figure 27. SPI Daisy Chain Transaction
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Application Circuit Example
5V
0.01
0.1
0.1
10u
+
+
499
VDD
REF
LM4050-4.1
0.01
10u
48V
222k
IN0
3.3V
3.3V
1n
10k
10k
5V
3.33k
LM8640
DRDYB
IN1
Details of
Current
Sense
1n
Omitted
12V
LM8262
LMP92018
3.33k
OUT1
To Analog
Input
uC
3.3V
10k
VIO
4.99k
CSB
SCLK
DIN
1.8V
DOUT
VGPIO
GPIO0
From Digital
Output
To Digital
Input
GPIO1
GND
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REVISION HISTORY
Changes from Revision A (May 2013) to Revision B
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 27
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PACKAGE OPTION ADDENDUM
www.ti.com
3-May-2013
PACKAGING INFORMATION
Orderable Device
LMP92018SQ/NOPB
LMP92018SQE/NOPB
LMP92018SQX/NOPB
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
WQFN
WQFN
WQFN
NJK
36
36
36
1000
Green (RoHS
& no Sb/Br)
CU SN
CU SN
CU SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
L92018SQ
ACTIVE
ACTIVE
NJK
NJK
250
Green (RoHS
& no Sb/Br)
-40 to 125
L92018SQ
L92018SQ
2500
Green (RoHS
& no Sb/Br)
-40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Nov-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMP92018SQ/NOPB
LMP92018SQE/NOPB
LMP92018SQX/NOPB
WQFN
WQFN
WQFN
NJK
NJK
NJK
36
36
36
1000
250
330.0
178.0
330.0
16.4
16.4
16.4
6.3
6.3
6.3
6.3
6.3
6.3
1.5
1.5
1.5
12.0
12.0
12.0
16.0
16.0
16.0
Q2
Q2
Q2
2500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Nov-2014
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMP92018SQ/NOPB
LMP92018SQE/NOPB
LMP92018SQX/NOPB
WQFN
WQFN
WQFN
NJK
NJK
NJK
36
36
36
1000
250
367.0
213.0
367.0
367.0
191.0
367.0
38.0
55.0
38.0
2500
Pack Materials-Page 2
MECHANICAL DATA
NJK0036A
SQA36A (Rev A)
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相关型号：
LMP92064
Precision Low-Side, 125 kSps Simultaneous Sampling,Current Sensor and Voltage Monitor with SPI
TI
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