LMR23610-Q1 [TI]
通过汽车级认证的 SIMPLE SWITCHER 4V 至 36V、1A 同步降压转换器;型号: | LMR23610-Q1 |
厂家: | TEXAS INSTRUMENTS |
描述: | 通过汽车级认证的 SIMPLE SWITCHER 4V 至 36V、1A 同步降压转换器 转换器 |
文件: | 总38页 (文件大小:2795K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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LMR23610-Q1
ZHCSFU7A –DECEMBER 2016–REVISED APRIL 2017
LMR23610-Q1 SIMPLE SWITCHER® 36V、1A 同步降压转换器
1 特性
2 应用
1
•
符合汽车应用 要求
•
•
•
•
汽车电池稳压
•
符合 AEC-Q100 标准,其中包括以下内容:
- 器件温度等级 1:-40°C 至 125°C 的环境工作温
度范围
工业用电源
电信和数据通信系统
通用宽 VIN 稳压
空白
- 器件 HBM ESD 分类等级 H1C
- 器件 CDM ESD 分类等级 C4A
•
•
•
•
•
•
•
•
•
•
•
•
•
4V 至 36V 输入范围
3 说明
LMR23610-Q1 SIMPLE SWITCHER®是一款易于使用
的 36V、1A 同步降压转换器。该器件具有 4V 到 36V
的宽输入电压范围, 适用于 从工业到汽车各类应用中
非稳压电源的电源调节。该器件采用峰值电流模式控制
来实现简单控制环路补偿和逐周期电流限制。其静态电
流低至 75µA,因此适用于电池供电类系统。内部环路
补偿意味着用户不用承担设计环路补偿组件的枯燥工
作。这样还能够以最大限度减少外部元件数。扩展系列
产品能够以引脚到引脚兼容封装提供 1.5A
1A 持续输出电流
集成同步整流
电流模式控制
最短导通时间:60ns
内置补偿功能,便于使用
400kHz 开关频率,支持 PFM 模式
与外部时钟频率同步
无负载条件下的静态电流为 75µA
针对预偏置负载的软启动
支持高占空比运行
(LMR23615-Q1)、2.5A (LMR23625-Q1) 和 3A
(LMR23630-Q1) 负载电流选项,实现简单、优化的
PCB 布局。精密使能输入简化了稳压器控制和系统电
源排序。保护 功能 包括逐周期限流和断续模式短路保
护,以及功耗超量情况下的热关断保护。
具有断续模式的输出短路保护
8 引脚 HSOIC PowerPAD™的封装选项:8 引脚
HSOIC 和 12 引脚 WSON
使用 LMR23610-Q1 并借助 WEBENCH® 电源设计
器创建定制设计
•
器件信息(1)
器件型号
封装
封装尺寸(标称值)
LMR23610AQDDARQ1
HSOIC (8)
4.9mm x 3.9mm
(1) 如需了解所有可用封装,请参阅产品说明书末尾的可订购产品
附录。
简化电路原理图
效率与负载间的关系,VIN = 12V
VIN up to 36 V
CIN
100
VIN
BOOT
SW
90
80
70
60
EN/SYNC
AGND
CBOOT
L
VOUT
RFBT
COUT
RFBB
VCC
FB
CVCC
PGND
50
VOUT = 5 V
VOUT = 3.3 V
40
0.0001
0.001
0.01
0.1
1
IOUT (A)
D000
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SNVSAR4
LMR23610-Q1
ZHCSFU7A –DECEMBER 2016–REVISED APRIL 2017
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions ...................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Timing Characteristics............................................... 6
6.7 Switching Characteristics.......................................... 7
6.8 Typical Characteristics.............................................. 8
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 10
7.3 Feature Description................................................. 11
7.4 Device Functional Modes........................................ 17
8
9
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Applications ................................................ 18
Power Supply Recommendations...................... 24
10 Layout................................................................... 24
10.1 Layout Guidelines ................................................. 24
10.2 Compact Layout for EMI Reduction...................... 24
10.3 Ground Plane and Thermal Considerations.......... 25
10.4 Feedback Resistors .............................................. 25
10.5 Layout Example .................................................... 26
11 器件和文档支持 ..................................................... 27
11.1 使用 WEBENCH® 工具创建定制设计 ................... 27
11.2 接收文档更新通知 ................................................. 27
11.3 社区资源................................................................ 27
11.4 商标....................................................................... 27
11.5 静电放电警告......................................................... 27
11.6 Glossary................................................................ 27
12 机械、封装和可订购信息....................................... 28
7
4 修订历史记录
请注意:前一修订版的页码可能与当前版本的页码不同。
Changes from Original (December 2016) to Revision A
Page
•
Changed the value for HBM from ±2500 to ±2000................................................................................................................. 4
2
Copyright © 2016–2017, Texas Instruments Incorporated
LMR23610-Q1
www.ti.com.cn
ZHCSFU7A –DECEMBER 2016–REVISED APRIL 2017
5 Pin Configuration and Functions
DDA Package
8-Pin HSOIC
Top View
SW
1
8
PGND
BOOT
VCC
FB
2
3
4
7
6
5
VIN
Thermal Pad
(9)
AGND
EN/SYNC
Pin Functions
PIN
(1)
I/O
DESCRIPTION
NAME
NO.
Switching output of the regulator. Internally connected to both power MOSFETs. Connect to
power inductor.
SW
1
P
Boot-strap capacitor connection for high-side driver. Connect a high quality 100 nF capacitor
from BOOT to SW.
BOOT
2
P
Internal bias supply output for bypassing. Connect a 2.2 μF/ 16 V or higher capacitance
bypass capacitor from this pin to AGND. Do not connect external loading to this pin. Never
short this pin to ground during operation.
VCC
FB
3
4
P
A
Feedback input to regulator, connect the feedback resistor divider tap to this pin.
Enable input to regulator. High = On, Low = Off. Can be connected to VIN. Do not float.
Adjust the input under voltage lockout with two resistors. The internal oscillator can be
synchronized to an external clock by coupling a positive pulse into this pin through a small
coupling capacitor. See Enable/Sync for detail.
EN/SYNC
5
A
Analog ground pin. Ground reference for internal references and logic. Connect to system
ground.
AGND
VIN
6
7
8
G
P
Input supply voltage.
Power ground pin, connected internally to the low side power FET. Connect to system
ground, PAD, AGND, ground pins of CIN and COUT. Path to CIN must be as short as possible.
PGND
G
Low impedance connection to AGND. Connect to PGND on PCB. Major heat dissipation
path of the die. Must be used for heat sinking to ground plane on PCB.
PAD
9
G
(1) A = Analog, P = Power, G = Ground
Copyright © 2016–2017, Texas Instruments Incorporated
3
LMR23610-Q1
ZHCSFU7A –DECEMBER 2016–REVISED APRIL 2017
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of -40 °C to 125 °C (unless otherwise noted)
(1)
PARAMETER
VIN to PGND
MIN
-0.3
-5.5
-0.3
-0.3
-1
MAX
UNIT
42
EN/SYNC to AGND
FB to AGND
VIN + 0.3
4.5
Input Voltages
V
AGND to PGND
0.3
SW to PGND
VIN + 0.3
42
SW to PGND less than 10 ns transients
BOOT to SW
-5
Output Voltages
V
-0.3
-0.3
-40
-65
5.5
(2)
VCC to AGND
4.5
TJ
Junction temperature
Storage temperature
150
150
°C
°C
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) In shutdown mode, the VCC to AGND maximum value is 5.25 V.
6.2 ESD Ratings
VALUE
±2000
±1000
UNIT
(1)
Human-body model (HBM)
Charged-device model (CDM)
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of -40 °C to 125 °C (unless otherwise noted)
(1)
MIN
4
MAX
36
UNIT
VIN
Input Voltage
EN/SYNC
-5
36
V
FB
-0.3
1
1.2
28
Output Voltage
Output Current
Temperature
VOUT
V
A
IOUT
0
1
Operating junction temperature, TJ
-40
125
°C
(1) Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits.
For guaranteed specifications, see Electrical Characteristics.
4
Copyright © 2016–2017, Texas Instruments Incorporated
LMR23610-Q1
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ZHCSFU7A –DECEMBER 2016–REVISED APRIL 2017
6.4 Thermal Information
(1) (2)
THERMAL METRIC
DDA (8 PINS)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (top) thermal resistance
Junction-to-case (bottom) thermal resistance
Junction-to-board thermal resistance
42.0
5.9
ψJT
ψJB
23.4
45.8
3.6
°C/W
RθJC(top)
RθJC(bot)
RθJB
23.4
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) Power rating at a specific ambient temperature TA should be determined with a maximum junction temperature (TJ) of 125 °C, which is
illustrated in Recommended Operating Conditions section.
6.5 Electrical Characteristics
Limits apply over the recommended operating junction temperature (TJ) range of -40 °C to +125 °C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25 °C, and are provided for reference purposes only.
PARAMETER
POWER SUPPLY (VIN PIN)
TEST CONDITIONS
MIN
TYP
MAX UNIT
VIN
Operation input voltage
4
36
3.9
3.5
4.0
V
V
VIN_UVLO
Under voltage lockout thresholds
Rising threshold
Falling threshold
3.3
2.9
3.7
3.3
2.0
ISHDN
IQ
Shutdown supply current
VEN = 0 V, VIN = 12 V, TJ = -40 °C to 125
°C
μA
μA
Operating quiescent current (non-
switching)
VIN =12 V, VFB = 1.1 V, TJ = -40 °C to
125 °C, PFM mode
75
ENABLE (EN PIN)
VEN_H
Enable rising threshold Voltage
Enable hysteresis voltage
Wake-up threshold
1.4
0.4
1.55
0.4
1.7
V
V
VEN_HYS
VWAKE
V
VIN = 4 V to 36 V, VEN= 2 V
VIN = 4 V to 36 V, VEN= 36 V
10
100
1
nA
μA
IEN
Input leakage current at EN pin
VOLTAGE REFERENCE (FB PIN)
VIN = 4 V to 36 V, TJ = 25 °C
VIN = 4 V to 36 V, TJ = -40 °C to 125 °C
VFB= 1 V
0.985
0.980
1.0
1.0
10
1.015
1.020
VREF
Reference voltage
V
ILKG_FB
Input leakage current at FB pin
nA
INTERNAL LDO (VCC PIN)
VCC
Internal LDO output voltage
4.1
3.2
2.8
V
V
Rising threshold
Falling threshold
2.8
2.4
3.6
3.2
VCC_UVLO
VCC under voltage lockout thresholds
CURRENT LIMIT
IHS_LIMIT
Peak inductor current limit
Valley inductor current limit
Zero cross current limit
1.4
1.0
2.0
1.5
2.6
2.1
A
A
A
ILS_LIMIT
IL_ZC
-0.04
INTEGRATED MOSFETS
RDS_ON_HS High-side MOSFET ON-resistance
RDS_ON_LS Low-side MOSFET ON-resistance
THERMAL SHUTDOWN
TSHDN Thermal shutdown threshold
THYS Hysteresis
VIN = 12 V, IOUT = 1 A
VIN = 12 V, IOUT = 1 A
185
105
mΩ
mΩ
162
170
15
178
°C
°C
Copyright © 2016–2017, Texas Instruments Incorporated
5
LMR23610-Q1
ZHCSFU7A –DECEMBER 2016–REVISED APRIL 2017
www.ti.com.cn
6.6 Timing Characteristics
Over the recommended operating junction temperature range of -40 °C to 125 °C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
HICCUP MODE
(1)
NOC
Number of cycles that LS current limit is
tripped to enter Hiccup mode
64
Cycles
TOC
Hiccup retry delay time
5
2
ms
ms
SOFT START
TSS
Internal soft-start time
The time of internal reference to increase
from 0 V to 1.0 V
1
3
(1) Guaranteed by design.
6
Copyright © 2016–2017, Texas Instruments Incorporated
LMR23610-Q1
www.ti.com.cn
ZHCSFU7A –DECEMBER 2016–REVISED APRIL 2017
6.7 Switching Characteristics
Over the recommended operating junction temperature range of -40 °C to 125 °C (unless otherwise noted)
PARAMETER
MIN
TYP
MAX UNIT
SW (SW PIN)
fSW
Default switching frequency
340
400
60
460
90
kHz
ns
TON_MIN
Minimum turn-on time
Minimum turn-off time
(1)
TOFF_MIN
100
ns
SYNC (EN/SYNC PIN)
fSYNC
SYNC frequency range
200
2.8
2200
5.5
kHz
V
VSYNC
Amplitude of SYNC clock AC signal (measured at SYNC pin)
Minimum sync clock ON and OFF time
TSYNC_MIN
100
ns
(1) Guaranteed by design.
Copyright © 2016–2017, Texas Instruments Incorporated
7
LMR23610-Q1
ZHCSFU7A –DECEMBER 2016–REVISED APRIL 2017
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6.8 Typical Characteristics
Unless otherwise specified the following conditions apply: VIN = 12 V, fSW = 400 kHz, L = 22 µH, COUT = 47 µF × 2, TA = 25°C.
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 8 V
VIN = 8 V
VIN = 12 V
VIN = 24 V
VIN = 36 V
VIN = 12 V
VIN = 24 V
VIN = 36 V
1E-5
0.0001
0.001
IOUT (A)
0.01
0.1 0.2 0.5
1
1E-5
0.0001
0.001
IOUT (A)
0.01
0.1
1
D002
D001
fSW = 400 kHz
VOUT = 3.3 V
fSW = 400 kHz
VOUT = 5 V
Figure 2. Efficiency vs. Load Current
Figure 1. Efficiency vs. Load Current
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN = 8 V
VIN = 8 V
VIN = 12 V
VIN = 24 V
VIN = 36 V
VIN = 12 V
VIN = 24 V
VIN = 36 V
1E-5
0.0001
0.001
IOUT (A)
0.01
0.1
1
1E-5
0.0001
0.001
IOUT (A)
0.01
0.1
1
D003
D004
fSW = 1000 kHz
(Sync)
VOUT = 5 V
fSW = 1000 kHz
(Sync)
VOUT = 3.3 V
Figure 3. Efficiency vs. Load Current
Figure 4. Efficiency vs. Load Current
5.09
5.08
5.07
5.06
5.05
5.04
5.03
5.02
5.01
5
5.02
5.015
5.01
VIN = 8 V
IOUT = 0.3 A
VIN = 12 V
VIN = 24 V
VIN = 36 V
IOUT = 0.5 A
IOUT = 0.8 A
IOUT = 1.0 A
5.005
0
5
10
15
20
VIN (V)
25
30
35
40
0
0.2
0.4
0.6
0.8
1
IOUT (A)
D006
D005
VOUT = 5 V
Figure 6. Line Regulation
VOUT = 5 V
Figure 5. Load Regulation
8
Copyright © 2016–2017, Texas Instruments Incorporated
LMR23610-Q1
www.ti.com.cn
ZHCSFU7A –DECEMBER 2016–REVISED APRIL 2017
Typical Characteristics (continued)
Unless otherwise specified the following conditions apply: VIN = 12 V, fSW = 400 kHz, L = 22 µH, COUT = 47 µF × 2, TA = 25°C.
5.5
3.6
3.3
3
5
4.5
4
3.5
3
IOUT = 0.2 A
IOUT = 0.5 A
IOUT = 1.0 A
IOUT = 0.2 A
IOUT = 0.5 A
IOUT = 1.0 A
2.7
4
4.5
5
5.5
6
3.3
3.4
3.5
3.6
3.7
3.8
3.9
VIN (V)
VIN (V)
D007
D008
VOUT = 5 V
VOUT = 3.3 V
Figure 8. Dropout Curve
Figure 7. Dropout Curve
80
75
70
65
60
3.67
3.66
3.65
3.64
3.63
3.62
3.61
-50
0
50
100
150
-50
0
50
100
150
Temperature (°C)
Temperature (°C)
D008
D009
VIN = 12 V
VFB = 1.1 V
Figure 9. IQ vs. Junction Temperature
Figure 10. VIN UVLO Rising Threshold vs. Junction
Temperature
0.425
2.4
2.2
2
LS Limit
HS Limit
0.42
0.415
0.41
1.8
1.6
1.4
1.2
-50
0
50
100
150
-50
0
50
100
150
Temperature (°C)
Temperature (èC)
D010
D009
VIN = 12 V
Figure 11. VIN UVLO Hysteresis vs. Junction Temperature
Figure 12. HS & LS Current Limit vs. Junction Temperature
Copyright © 2016–2017, Texas Instruments Incorporated
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LMR23610-Q1
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7 Detailed Description
7.1 Overview
The LMR23610-Q1 SIMPLE SWITCHER® regulator is an easy to use synchronous step-down DC-DC converter
operating from 4 V to 36 V supply voltage. It is capable of delivering up to 1 A DC load current with good thermal
performance in a small solution size. An extended family is available in multiple current options from 1 A to 3 A in
pin-to-pin compatible packages.
The LMR23610-Q1 employs fixed frequency peak current mode control. The device enters PFM mode at light
load to achieve high efficiency. The device is internally compensated, which reduces design time, and requires
few external components. The LMR23610-Q1 is capable of synchronization to an external clock within the range
of 200 kHz to 2.2 MHz.
Additional features such as precision enable and internal soft-start provide a flexible and easy to use solution for
a wide range of applications. Protection features include thermal shutdown, VIN and VCC under-voltage lockout,
cycle-by-cycle current limit, and hiccup mode short-circuit protection.
The family requires very few external components and has a pin-out designed for simple, optimum PCB layout.
7.2 Functional Block Diagram
EN/SYNC
VCC
SYNC Signal
SYNC
VCC
LDO
VIN
Detector
Enable
Precision
Enable
BOOT
Internal
SS
HS I Sense
EA
REF
Rc
Cc
TSD
UVLO
PWM CONTROL LOGIC
PFM
SW
Detector
OV/UV
Detector
FB
Slope
Comp
Freq
Foldback
Zero
Cross
HICCUP
Detector
SYNC Signal
Oscillator
LS I Sense
FB
PGND
AGND
10
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LMR23610-Q1
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ZHCSFU7A –DECEMBER 2016–REVISED APRIL 2017
7.3 Feature Description
7.3.1 Fixed Frequency Peak Current Mode Control
The following operating description of the LMR23610-Q1 will refer to the Functional Block Diagram and to the
waveforms in Figure 13. LMR23610-Q1 is a step-down synchronous buck regulator with integrated high-side
(HS) and low-side (LS) switches (synchronous rectifier). The LMR23610-Q1 supplies a regulated output voltage
by turning on the HS and LS NMOS switches with controlled duty cycle. During high-side switch ON time, the
SW pin voltage swings up to approximately VIN, and the inductor current iL increase with linear slope (VIN – VOUT
)
/ L. When the HS switch is turned off by the control logic, the LS switch is turned on after an anti-shoot-through
dead time. Inductor current discharges through the LS switch with a slope of –VOUT / L. The control parameter of
a buck converter is defined as Duty Cycle D = tON / TSW, where tON is the high-side switch ON time and TSW is
the switching period. The regulator control loop maintains a constant output voltage by adjusting the duty cycle
D. In an ideal buck converter, where losses are ignored, D is proportional to the output voltage and inversely
proportional to the input voltage: D = VOUT / VIN.
VSW
D = tON/ TSW
VIN
tON
tOFF
t
0
-VD
TSW
iL
ILPK
IOUT
DiL
t
0
Figure 13. SW Node and Inductor Current Waveforms in
Continuous Conduction Mode (CCM)
The LMR23610-Q1 employs fixed frequency peak current mode control. A voltage feedback loop is used to get
accurate DC voltage regulation by adjusting the peak current command based on voltage offset. The peak
inductor current is sensed from the high-side switch and compared to the peak current threshold to control the
ON time of the high-side switch. The voltage feedback loop is internally compensated, which allows for fewer
external components, makes it easy to design, and provides stable operation with almost any combination of
output capacitors. The regulator operates with fixed switching frequency at normal load condition. At light load
condition, the LMR23610-Q1 will operate in PFM mode to maintain high efficiency.
7.3.2 Adjustable Output Voltage
A precision 1.0 V reference voltage is used to maintain a tightly regulated output voltage over the entire
operating temperature range. The output voltage is set by a resistor divider from output voltage to the FB pin. It
is recommended to use 1% tolerance resistors with a low temperature coefficient for the FB divider. Select the
low-side resistor RFBB for the desired divider current and use Equation 1 to calculate high-side RFBT. RFBT in the
range from 10 kΩ to 100 kΩ is recommended for most applications. A lower RFBT value can be used if static
loading is desired to reduce VOUT offset in PFM operation. Lower RFBT will reduce efficiency at very light load.
Less static current goes through a larger RFBT and might be more desirable when light load efficiency is critical.
But RFBT larger than 1 MΩ is not recommended because it makes the feedback path more susceptible to noise.
Larger RFBT value requires more carefully designed feedback path on the PCB. The tolerance and temperature
variation of the resistor dividers affect the output voltage regulation.
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Feature Description (continued)
V
OUT
R
FBT
FBB
FB
R
Figure 14. Output Voltage Setting
VOUT - VREF
RFBT
=
ìRFBB
VREF
(1)
7.3.3 Enable/Sync
The voltage on the EN pin controls the ON or OFF operation of LMR23610-Q1. A voltage less than 1 V (typ) will
shut-down the device while a voltage higher than 1.6 V (typ) is required to start the regulator. The EN pin is an
input and can not be left open or floating. The simplest way to enable the operation of the LMR23610-Q1 is to
connect the EN to VIN. This allows self-start-up of the LMR23610-Q1 when VIN is within the operation range.
Many applications will benefit from the employment of an enable divider RENT and RENB (Figure 15) to establish a
precision system UVLO level for the converter. System UVLO can be used for supplies operating from utility
power as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply protection,
such as a battery discharge level. An external logic signal can also be used to drive EN input for system
sequencing and protection.
VIN
RENT
EN/SYNC
RENB
Figure 15. System UVLO by Enable Divider
The EN pin also can be used to synchronize the internal oscillator to an external clock. The internal oscillator can
be synchronized by AC coupling a positive edge into the EN pin. The AC coupled peak-to-peak voltage at the EN
pin must exceed the SYNC amplitude threshold of 2.8 V (typ) to trip the internal synchronization pulse detector,
and the minimum SYNC clock ON and OFF time must be longer than 100ns (typ). A 3.3 V or a higher amplitude
pulse signal coupled through a 1 nF capacitor CSYNC is a good starting point. Keeping RENT // RENB (RENT parallel
with RENB) in the 100 kΩ range is a good choice. RENT is required for this synchronization circuit, but RENB can be
left unmounted if system UVLO is not needed. LMR23610-Q1 switching action can be synchronized to an
external clock from 200 kHz to 2.2 MHz. Figure 17 and Figure 18 show the device synchronized to an external
system clock.
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Feature Description (continued)
VIN
RENT
CSYNC
EN/SYNC
RENB
Clock
Source
Figure 16. Synchronize to external clock
Figure 17. Synchronizing in PWM Mode
Figure 18. Synchronizing in PFM Mode
7.3.4 VCC, UVLO
The LMR23610-Q1 integrates an internal LDO to generate VCC for control circuitry and MOSFET drivers. The
nominal voltage for VCC is 4.1 V. The VCC pin is the output of an LDO and must be properly bypassed. A high
quality ceramic capacitor with a value of 2.2 µF to 10 µF, 16 V or higher rated voltage should be placed as close
as possible to VCC and grounded to the exposed PAD and ground pins. The VCC output pin should not be
loaded, or shorted to ground during operation. Shorting VCC to ground during operation may cause damage to
the LMR23610-Q1.
VCC under voltage lockout (UVLO) prevents the LMR23610-Q1 from operating until the VCC voltage exceeds 3.2
V (typ). The VCC UVLO threshold has 400 mV (typ) of hysteresis to prevent undesired shutdown due to
temporary VIN drops.
7.3.5 Minimum ON-time, Minimum OFF-time and Frequency Foldback at Drop-out Conditions
Minimum ON-time, TON_MIN, is the smallest duration of time that the HS switch can be on. TON_MIN is typically 60
ns in the LMR23610-Q1. Minimum OFF-time, TOFF_MIN, is the smallest duration that the HS switch can be off.
TOFF_MIN is typically 100 ns in the LMR23610-Q1. In CCM operation, TON_MIN and TOFF_MIN limit the voltage
conversion range given a selected switching frequency.
The minimum duty cycle allowed is:
DMIN = TON_MIN x fSW
(2)
And the maximum duty cycle allowed is:
DMAX = 1 - TOFF_MIN x fSW
(3)
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Feature Description (continued)
Given fixed TON_MIN and TOFF_MIN, the higher the switching frequency the narrower the range of the allowed duty
cycle. In the LMR23610-Q1, a frequency foldback scheme is employed to extend the maximum duty cycle when
TOFF_MIN is reached. The switching frequency will decrease once longer duty cycle is needed under low VIN
conditions. Wide range of frequency foldback allows the LMR23610-Q1 output voltage stay in regulation with a
much lower supply voltage VIN. This leads to a lower effective drop-out voltage.
Given an output voltage, the choice of the switching frequency affects the allowed input voltage range, solution
size and efficiency. The maximum operation supply voltage can be found by:
VOUT
V
=
IN_MAX
f
ì TON_MIN
SW
(4)
At lower supply voltage, the switching frequency will decrease once TOFF_MIN is tripped. The minimum VIN without
frequency foldback can be approximated by:
VOUT
V
=
IN_MIN
1- f
ì TOFF _MIN
SW
(5)
Taking considerations of power losses in the system with heavy load operation, VIN_MAX is higher than the result
calculated in Equation 4. With frequency foldback, VIN_MIN is lowered by decreased fSW
.
450
400
350
300
250
200
150
IOUT = 0.4 A
IOUT = 0.6 A
IOUT = 0.8 A
IOUT = 1.0 A
100
50
0
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
VIN (V)
D010
Figure 19. Frequency Foldback at Dropout (VOUT = 5 V, fSW = 400 kHz)
7.3.6 Internal Compensation and CFF
The LMR23610-Q1 is internally compensated as shown in Functional Block Diagram. The internal compensation
is designed such that the loop response is stable over the entire operating frequency and output voltage range.
Depending on the output voltage, the compensation loop phase margin can be low with all ceramic capacitors.
An external feed-forward capacitor CFF is recommended to be placed in parallel with the top resistor divider RFBT
for optimum transient performance.
VOUT
CFF
RFBT
FB
RFBB
Figure 20. Feedforward Capacitor for Loop Compensation
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Feature Description (continued)
The feed-forward capacitor CFF in parallel with RFBT places an additional zero before the cross over frequency of
the control loop to boost phase margin. The zero frequency can be found by
1
fZ _ CFF
=
2pìCFF ìRFBT
(6)
An additional pole is also introduced with CFF at the frequency of
1
fP _ CFF
=
2pìCFF ìRFBT //RFBB
(7)
The zero fZ_CFF adds phase boost at the crossover frequency and improves transient response. The pole fP-CFF
helps maintaining proper gain margin at frequency beyond the crossover. Table 1 lists the combination of COUT
,
CFF and RFBT for typical applications, designs with similar COUT but RFBT other than recommended value, please
adjust CFF such that (CFF × RFBT) is unchanged and adjust RFBB such that (RFBT / RFBB) is unchanged.
Designs with different combinations of output capacitors need different CFF. Different types of capacitors have
different Equivalent Series Resistance (ESR). Ceramic capacitors have the smallest ESR and need the most
CFF. Electrolytic capacitors have much larger ESR and the ESR zero frequency
1
fZ _ESR
=
2pìC
ìESR
OUT
(8)
would be low enough to boost the phase up around the crossover frequency. Designs using mostly electrolytic
capacitors at the output may not need any CFF.
The CFF creates a time constant with RFBT that couples in the attenuate output voltage ripple to the FB node. If
the CFF value is too large, it can couple too much ripple to the FB and affect VOUT regulation. Therefore, CFF
should be calculated based on output capacitors used in the system. At cold temperatures, the value of CFF
might change based on the tolerance of the chosen component. This may reduce its impedance and ease noise
coupling on the FB node. To avoid this, more capacitance can be added to the output or the value of CFF can be
reduced.
7.3.7 Bootstrap Voltage (BOOT)
The LMR23610-Q1 provides an integrated bootstrap voltage regulator. A small capacitor between the BOOT and
SW pins provides the gate drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the
high-side MOSFET is off and the low-side switch conducts. The recommended value of the BOOT capacitor is
0.1 μF. A ceramic capacitor with an X7R or X5R grade dielectric with a voltage rating of 16V or higher is
recommended for stable performance over temperature and voltage.
7.3.8 Over Current and Short Circuit Protection
The LMR23610-Q1 is protected from over-current conditions by cycle-by-cycle current limit on both the peak and
valley of the inductor current. Hiccup mode will be activated if a fault condition persists to prevent over-heating.
High-side MOSFET over-current protection is implemented by the nature of the Peak Current Mode control. The
HS switch current is sensed when the HS is turned on after a set blanking time. The HS switch current is
compared to the output of the Error Amplifier (EA) minus slope compensation every switching cycle. Please refer
to Functional Block Diagram for more details. The peak current of HS switch is limited by a clamped maximum
peak current threshold IHS_LIMIT which is constant. So the peak current limit of the high-side switch is not affected
by the slope compensation and remains constant over the full duty cycle range.
The current going through LS MOSFET is also sensed and monitored. When the LS switch turns on, the inductor
current begins to ramp down. The LS switch will not be turned OFF at the end of a switching cycle if its current is
above the LS current limit ILS_LIMIT. The LS switch will be kept ON so that inductor current keeps ramping down,
until the inductor current ramps below the LS current limit ILS_LIMIT. Then the LS switch will be turned OFF and
the HS switch will be turned on after a dead time. This is somewhat different than the more typical peak current
limit, and results in Equation 9 for the maximum load current.
V - V
(
)
ì
VOUT
IN
OUT
IOUT _MAX = ILS _LIMIT
+
2ì fSW ìL
V
IN
(9)
15
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Feature Description (continued)
If the current of the LS switch is higher than the LS current limit for 64 consecutive cycles, hiccup current
protection mode will be activated. In hiccup mode, the regulator will be shut down and kept off for 5 ms typically
before the LMR23610-Q1 tries to start again. If over-current or short-circuit fault condition still exist, hiccup will
repeat until the fault condition is removed. Hiccup mode reduces power dissipation under severe over-current
conditions, prevents over-heating and potential damage to the device.
7.3.9 Thermal Shutdown
The LMR23610-Q1 provides an internal thermal shutdown to protect the device when the junction temperature
exceeds 170 °C (typ). The device is turned off when thermal shutdown activates. Once the die temperature falls
below 155 °C (typ), the device reinitiates the power up sequence controlled by the internal soft-start circuitry.
16
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7.4 Device Functional Modes
7.4.1 Shutdown Mode
The EN pin provides electrical ON and OFF control for the LMR23610-Q1. When VEN is below 1 V (typ), the
device is in shutdown mode. The LMR23610-Q1 also employs VIN and VCC under voltage lock out protection. If
VIN or VCC voltage is below their respective UVLO level, the regulator will be turned off.
7.4.2 Active Mode
The LMR23610-Q1 is in Active Mode when VEN is above the precision enable threshold, VIN and VCC are above
their respective UVLO level. The simplest way to enable the LMR23610-Q1 is to connect the EN pin to VIN pin.
This allows self startup when the input voltage is in the operating range: 4 V to 36 V. Please refer to VCC, UVLO
and Enable/Sync for details on setting these operating levels.
In Active Mode, depending on the load current, the LMR23610-Q1 will be in one of three modes:
1. Continuous conduction mode (CCM) with fixed switching frequency when load current is above half of the
peak-to-peak inductor current ripple.
2. Discontinuous conduction mode (DCM) with fixed switching frequency when load current is lower than half of
the peak-to-peak inductor current ripple in CCM operation.
3. Pulse frequency modulation mode (PFM) when switching frequency is decreased at very light load.
7.4.3 CCM Mode
CCM operation is employed in the LMR23610-Q1 when the load current is higher than half of the peak-to-peak
inductor current. In CCM operation, the frequency of operation is fixed, output voltage ripple will be at a minimum
in this mode and the maximum output current of 1 A can be supplied by the LMR23610-Q1.
7.4.4 Light Load Operation
When the load current is lower than half of the peak-to-peak inductor current in CCM, the LMR23610-Q1 will
operate in Discontinuous Conduction Mode (DCM), also known as Diode Emulation Mode (DEM). In DCM, the
LS switch is turned off when the inductor current drops to IL_ZC (-40 mA typ). Both switching losses and
conduction losses are reduced in DCM, compared to forced PWM operation at light load.
At even lighter current loads, Pulse Frequency Modulation (PFM) is activated to maintain high efficiency
operation. When either the minimum HS switch ON time (tON_MIN ) or the minimum peak inductor current IPEAK_MIN
(300 mA typ) is reached, the switching frequency will decrease to maintain regulation. In PFM, switching
frequency is decreased by the control loop when load current reduces to maintain output voltage regulation.
Switching loss is further reduced in PFM operation due to less frequent switching actions. The external clock
synchronizing will not be valid when LMR23610-Q1 enters into PFM mode.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMR23610-Q1 is a step down DC-to-DC regulator. It is typically used to convert a higher DC voltage to a
lower DC voltage with a maximum output current of 1 A. The following design procedure can be used to select
components for the LMR23610-Q1. Alternately, the WEBENCH® software may be used to generate complete
designs. When generating a design, the WEBENCH® software utilizes iterative design procedure and accesses
comprehensive databases of components. Please go to ti.com for more details.
8.2 Typical Applications
The LMR23610-Q1 only requires a few external components to convert from a wide voltage range supply to a
fixed output voltage. Figure 21 shows a basic schematic.
VIN 12 V
CBOOT
BOOT
SW
VIN
0.1 ꢀF
L
VOUT
5 V/1 A
CIN
10 ꢀF
22 ꢀH
EN/
SYNC
PAD
CFF
75 pF
RFBT
88.7 kΩ
COUT
68 ꢀF
FB
RFBB
22.1 kΩ
CVCC
2.2 ꢀF
VCC
PGND
AGND
Copyright © 2016, Texas Instruments Incorporated
Figure 21. Application Circuit
The external components have to fulfill the needs of the application, but also the stability criteria of the device's
control loop. Table 1 can be used to simplify the output filter component selection.
Table 1. L, COUT and CFF Typical Values
fSW (kHz)
400
VOUT (V)
L (µH)
15
COUT (µF)
CFF (pF)
100
RFBT (kΩ)
51
3.3
5
82
68
33
22
400
22
75
88.7
400
12
24
47
See note (5)
See note (5)
243
400
47
510
1. Inductance value is calculated based on VIN = 36 V.
2. All the COUT values are after derating. Add more when using ceramic capacitors.
3. RFBT = 0 Ω for VOUT = 1 V. RFBB = 22.1 kΩ for all other VOUT setting.
4. For designs with RFBT other than recommended value, please adjust CFF such that (CFF × RFBT) is
unchanged and adjust RFBB such that (RFBT / RFBB) is unchanged.
5. High ESR COUT will give enough phase boost and CFF not needed.
8.2.1 Design Requirements
Detailed design procedure is described based on a design example. For this design example, use the
parameters listed in Table 2 as the input parameters.
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Table 2. Design Example Parameters
Input Voltage, VIN
Output Voltage, VOUT
12 V typical, range from 8 V to 28 V
5 V
1 A
Maximum Output Current IO_MAX
Transient Response 0.1 A to 1 A
Output Voltage Ripple
5%
50 mV
400 mV
400 kHz
Input Voltage Ripple
Switching Frequency fSW
8.2.2 Detailed Design Procedure
8.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMR23610-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
•
•
•
•
Run electrical simulations to see important waveforms and circuit performance
Run thermal simulations to understand board thermal performance
Export customized schematic and layout into popular CAD formats
Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.2.2 Output Voltage Set-Point
The output voltage of LMR23610-Q1 is externally adjustable using a resistor divider network. The divider network
is comprised of top feedback resistor RFBT and bottom feedback resistor RFBB. Equation 10 is used to determine
the output voltage:
VOUT - VREF
RFBT
=
ìRFBB
VREF
(10)
Choose the value of RFBB to be 22.1 kΩ. With the desired output voltage set to 5 V and the VREF = 1.0 V, the
RFBB value can then be calculated using Equation 10. The formula yields to a value 88.7 kΩ.
8.2.2.3 Switching Frequency
The default switching frequency of the LMR23610-Q1 is 400 kHz. For other switching frequency, the device must
be synchronized to an external clock, please refer to Enable/Sync for more details.
8.2.2.4 Inductor Selection
The most critical parameters for the inductor are the inductance, saturation current and the rated current. The
inductance is based on the desired peak-to-peak ripple current ΔiL. Since the ripple current increases with the
input voltage, the maximum input voltage is always used to calculate the minimum inductance LMIN. Use
Equation 12 to calculate the minimum value of the output inductor. KIND is a coefficient that represents the
amount of inductor ripple current relative to the maximum output current of the device. A reasonable value of
KIND should be 30% to 50%. During an instantaneous short or over current operation event, the RMS and peak
inductor current can be high. The inductor current rating should be higher than the current limit of the device.
VOUT ì V
- VOUT
(
)
IN_MAX
DiL =
VIN_MAX ìL ì fSW
(11)
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V
- VOUT
VOUT
VIN_MAX ì fSW
IN_MAX
LMIN
=
ì
IOUT ìKIND
(12)
In general, it is preferable to choose lower inductance in switching power supplies, because it usually
corresponds to faster transient response, smaller DCR, and reduced size for more compact designs. But too low
of an inductance can generate too large of an inductor current ripple such that over current protection at the full
load could be falsely triggered. It also generates more conduction loss and inductor core loss. Larger inductor
current ripple also implies larger output voltage ripple with same output capacitors. With peak current mode
control, it is not recommended to have too small of an inductor current ripple. A larger peak current ripple
improves the comparator signal to noise ratio.
For this design example, choose KIND = 0.5, the minimum inductor value is calculated to be 20.5 µH. Choose the
nearest standard 22 μH ferrite inductor with a capability of 2 A RMS current and 2.5 A saturation current.
8.2.2.5 Output Capacitor Selection
The output capacitor(s), COUT, should be chosen with care since it directly affects the steady state output voltage
ripple, loop stability and the voltage over/undershoot during load current transients.
The output ripple is essentially composed of two parts. One is caused by the inductor current ripple going
through the Equivalent Series Resistance (ESR) of the output capacitors:
DVOUT_ESR = DiL ìESR = KIND ìIOUT ìESR
(13)
The other is caused by the inductor current ripple charging and discharging the output capacitors:
DiL
KIND ìIOUT
DVOUT _C
=
=
8ì f ìCOUT
8ì f ìCOUT
SW
SW
(14)
The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than the
sum of two peaks.
Output capacitance is usually limited by transient performance specifications if the system requires tight voltage
regulation with presence of large current steps and fast slew rate. When a fast large load increase happens,
output capacitors provide the required charge before the inductor current can slew up to the appropriate level.
The regulator’s control loop usually needs six or more clock cycles to respond to the output voltage droop. The
output capacitance must be large enough to supply the current difference for six clock cycles to maintain the
output voltage within the specified range. Equation 15 shows the minimum output capacitance needed for
specified output undershoot. When a sudden large load decrease happens, the output capacitors absorb energy
stored in the inductor. which results in an output voltage overshoot. Equation 16 calculates the minimum
capacitance required to keep the voltage overshoot within a specified range.
6ì IOH -IOL
(
)
COUT
>
fSW ì VUS
(15)
(16)
IO2 H -IO2 L
COUT
>
ìL
2
V
+ VOS - VO2UT
OUT
where
•
•
•
•
•
KIND = Ripple ratio of the inductor ripple current (ΔiL / IOUT
IOL = Low level output current during load transient
IOH = High level output current during load transient
VUS = Target output voltage undershoot
)
VOS = Target output voltage overshoot
For this design example, the target output ripple is 50 mV. Presuppose ΔVOUT_ESR = ΔVOUT_C = 50 mV, and
chose KIND = 0.5. Equation 13 yields ESR no larger than 100 mΩ and Equation 14 yields COUT no smaller than
3.1 μF. For the target over/undershoot range of this design, VUS = VOS = 5% × VOUT = 250 mV. The COUT can be
calculated to be no smaller than 54 μF and 8.5 μF by Equation 15 and Equation 16 respectively. Consider of
derating, one 82 μF, 16 V ceramic capacitor with 5 mΩ ESR is used.
20
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8.2.2.6 Feed-Forward Capacitor
The LMR23610-Q1 is internally compensated. Depending on the VOUT and frequency fSW, if the output capacitor
COUT is dominated by low ESR (ceramic types) capacitors, it could result in low phase margin. To improve the
phase boost an external feedforward capacitor CFF can be added in parallel with RFBT. CFF is chosen such that
phase margin is boosted at the crossover frequency without CFF. A simple estimation for the crossover frequency
(fX) without CFF is shown in Equation 17, assuming COUT has very small ESR, and COUT value is after derating.
8.32
fX
=
VOUT ìCOUT
(17)
The following equation for CFF was tested:
1
CFF
=
2pì fX ìRFBT
(18)
For designs with higher ESR, CFF is not needed when COUT has very high ESR and CFF calculated from
Equation 18 should be reduced with medium ESR. Table 1 can be used as a quick starting point.
For the application in this design example, a 75 pF, 50 V, COG capacitor is selected.
8.2.2.7 Input Capacitor Selection
The LMR23610-Q1 device requires high frequency input decoupling capacitor(s) and a bulk input capacitor,
depending on the application. The typical recommended value for the high frequency decoupling capacitor is 4.7
μF to 10 μF. A high-quality ceramic capacitor type X5R or X7R with sufficiency voltage rating is recommended.
To compensate the derating of ceramic capacitors, a voltage rating of twice the maximum input voltage is
recommended. Additionally, some bulk capacitance can be required, especially if the LMR23610-Q1 circuit is not
located within approximately 5 cm from the input voltage source. This capacitor is used to provide damping to the
voltage spike due to the lead inductance of the cable or the trace. For this design, two 4.7 μF, 50 V, X7R ceramic
capacitors are used. A 0.1 μF for high-frequency filtering and place it as close as possible to the device pins.
8.2.2.8 Bootstrap Capacitor Selection
Every LMR23610-Q1 design requires a bootstrap capacitor (CBOOT). The recommended capacitor is 0.1 μF and
rated 16 V or higher. The bootstrap capacitor is located between the SW pin and the BOOT pin. The bootstrap
capacitor must be a high-quality ceramic type with an X7R or X5R grade dielectric for temperature stability.
8.2.2.9 VCC Capacitor Selection
The VCC pin is the output of an internal LDO for LMR23610-Q1. To insure stability of the device, place a
minimum of 2.2 μF, 16 V, X7R capacitor from this pin to ground.
8.2.2.10 Under Voltage Lockout Set-Point
The system undervoltage lockout (UVLO) is adjusted using the external voltage divider network of RENT and
RENB. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down
or brown outs when the input voltage is falling. The following equation can be used to determine the VIN UVLO
level.
RENT + RENB
V
= VENH ì
IN_RISING
RENB
(19)
The EN rising threshold (VENH) for LMR23610-Q1 is set to be 1.55 V (typ). Choose the value of RENB to be 287
kΩ to minimize input current from the supply. If the desired VIN UVLO level is at 6.0 V, then the value of RENT can
be calculated using the equation below:
V
≈
’
IN_RISING
RENT
=
-1 ìR
∆
∆
÷
ENB
÷
VENH
«
◊
(20)
The above equation yields a value of 820 kΩ. The resulting falling UVLO threshold, equals 4.4 V, can be
calculated by below equation, where EN hysteresis (VEN_HYS) is 0.4 V (typ).
RENT + RENB
V
= VENH - VEN_HYS
(
ì
)
IN_FALLING
RENB
(21)
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8.2.3 Application Curves
Unless otherwise specified the following conditions apply: VIN = 12 V, fSW = 400 kHz, L = 22 µH, COUT = 47 µF × 2, TA = 25
°C.
VOUT = 5 V
VIN = 12 V
VIN = 12 V
IOUT = 1 A
fSW = 400 kHz
VOUT = 5 V
IOUT = 0 mA
fSW = 400 kHz
Figure 22. CCM Mode
Figure 23. PFM Mode
VOUT = 5 V
IOUT = 1 A
VIN = 12 V
VOUT = 5 V
IOUT = 1 A
Figure 24. Start Up by VIN
Figure 25. Start Up by EN
VOUT = 5 V
IOUT = 0.1 A to 1 A,
VOUT = 7 V to 36
VOUT = 5 V
IOUT = 1 A
100 mA / μs
V, 2 V / μs
Figure 26. Load Transient
Figure 27. Line Transient
22
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Unless otherwise specified the following conditions apply: VIN = 12 V, fSW = 400 kHz, L = 22 µH, COUT = 47 µF × 2, TA = 25
°C.
VOUT = 5 V
IOUT = 1 A to short
VOUT = 5 V
IOUT = short to 1 A
Figure 28. Short Protection
Figure 29. Short Recovery
Copyright © 2016–2017, Texas Instruments Incorporated
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LMR23610-Q1
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www.ti.com.cn
9 Power Supply Recommendations
The LMR23610-Q1 is designed to operate from an input voltage supply range between 4 V and 36 V. This input
supply should be able to withstand the maximum input current and maintain a stable voltage. The resistance of
the input supply rail should be low enough that an input current transient does not cause a high enough drop at
the LMR23610-Q1 supply voltage that can cause a false UVLO fault triggering and system reset. If the input
supply is located more than a few inches from the LMR23610-Q1, additional bulk capacitance may be required in
addition to the ceramic input capacitors. The amount of bulk capacitance is not critical, but a 47 μF or 100 μF
electrolytic capacitor is a typical choice.
10 Layout
10.1 Layout Guidelines
Layout is a critical portion of good power supply design. The following guidelines will help users design a PCB
with the best power conversion performance, thermal performance, and minimized generation of unwanted EMI.
1. The input bypass capacitor CIN must be placed as close as possible to the VIN and PGND pins. Grounding
for both the input and output capacitors should consist of localized top side planes that connect to the PGND
pin and PAD.
2. Place bypass capacitors for VCC close to the VCC pin and ground the bypass capacitor to device ground.
3. Minimize trace length to the FB pin net. Both feedback resistors, RFBT and RFBB should be located close to
the FB pin. Place CFF directly in parallel with RFBT. If VOUT accuracy at the load is important, make sure VOUT
sense is made at the load. Route VOUT sense path away from noisy nodes and preferably through a layer on
the other side of a shielded layer.
4. Use ground plane in one of the middle layers as noise shielding and heat dissipation path.
5. Have a single point ground connection to the plane. The ground connections for the feedback and enable
components should be routed to the ground plane. This prevents any switched or load currents from flowing
in the analog ground traces. If not properly handled, poor grounding can result in degraded load regulation or
erratic output voltage ripple behavior.
6. Make VIN, VOUT and ground bus connections as wide as possible. This reduces any voltage drops on the
input or output paths of the converter and maximizes efficiency.
7. Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to the
ground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal vias can also be
connected to inner layer heat-spreading ground planes. Ensure enough copper area is used for heat-sinking
to keep the junction temperature below 125 °C.
10.2 Compact Layout for EMI Reduction
Radiated EMI is generated by the high di/dt components in pulsing currents in switching converters. The larger
area covered by the path of a pulsing current, the more EMI is generated. High frequency ceramic bypass
capacitors at the input side provide primary path for the high di/dt components of the pulsing current. Placing
ceramic bypass capacitor(s) as close as possible to the VIN and PGND pins is the key to EMI reduction.
The SW pin connecting to the inductor should be as short as possible, and just wide enough to carry the load
current without excessive heating. Short, thick traces or copper pours (shapes) should be used for high current
conduction path to minimize parasitic resistance. The output capacitors should be placed close to the VOUT end
of the inductor and closely grounded to PGND pin and exposed PAD.
The bypass capacitors on VCC should be placed as close as possible to the pin and closely grounded to PGND
and the exposed PAD.
24
Copyright © 2016–2017, Texas Instruments Incorporated
LMR23610-Q1
www.ti.com.cn
ZHCSFU7A –DECEMBER 2016–REVISED APRIL 2017
10.3 Ground Plane and Thermal Considerations
It is recommended to use one of the middle layers as a solid ground plane. Ground plane provides shielding for
sensitive circuits and traces. It also provides a quiet reference potential for the control circuitry. The AGND and
PGND pins should be connected to the ground plane using vias right next to the bypass capacitors. PGND pin is
connected to the source of the internal LS switch. They should be connected directly to the grounds of the input
and output capacitors. The PGND net contains noise at switching frequency and may bounce due to load
variations. PGND trace, as well as VIN and SW traces, should be constrained to one side of the ground plane.
The other side of the ground plane contains much less noise and should be used for sensitive routes.
It is recommended to provide adequate device heat sinking by utilizing the PAD of the IC as the primary thermal
path. Use a minimum 4 by 2 array of 12 mil thermal vias to connect the PAD to the system ground plane heat
sink. The vias should be evenly distributed under the PAD. Use as much copper as possible, for system ground
plane, on the top and bottom layers for the best heat dissipation. Use a four-layer board with the copper
thickness for the four layers, starting from the top of, 2 oz / 1 oz / 1 oz / 2 oz. Four layer boards with enough
copper thickness provides low current conduction impedance, proper shielding and lower thermal resistance.
The thermal characteristics of the LMR23610-Q1 are specified using the parameter θJA, which characterize the
junction temperature of silicon to the ambient temperature in a specific system. Although the value of θJA is
dependent on many variables, it still can be used to approximate the operating junction temperature of the
device. To obtain an estimate of the device junction temperature, one may use the following relationship:
TJ = PD x θJA + TA
(22)
where
TJ = Junction temperature in °C
PD = VIN x IIN x (1 - Efficiency) - 1.1 x IOUT2 x DCR in Watt
DCR = Inductor DC parasitic resistance in Ω
θJA = Junction to ambient thermal resistance of the device in °C/W
TA = Ambient temperature in °C
The maximum operating junction temperature of the LMR23610-Q1 is 125 °C. θJA is highly related to PCB size
and layout, as well as environmental factors such as heat sinking and air flow.
10.4 Feedback Resistors
To reduce noise sensitivity of the output voltage feedback path, it is important to place the resistor divider and
CFF close to the FB pin, rather than close to the load. The FB pin is the input to the error amplifier, so it is a high
impedance node and very sensitive to noise. Placing the resistor divider and CFF closer to the FB pin reduces the
trace length of FB signal and reduces noise coupling. The output node is a low impedance node, so the trace
from VOUT to the resistor divider can be long if short path is not available.
If voltage accuracy at the load is important, make sure voltage sense is made at the load. Doing so will correct
for voltage drops along the traces and provide the best output accuracy. The voltage sense trace from the load to
the feedback resistor divider should be routed away from the SW node path and the inductor to avoid
contaminating the feedback signal with switch noise, while also minimizing the trace length. This is most
important when high value resistors are used to set the output voltage. It is recommended to route the voltage
sense trace and place the resistor divider on a different layer than the inductor and SW node path, such that
there is a ground plane in between the feedback trace and inductor/SW node polygon. This provides further
shielding for the voltage feedback path from EMI noises.
Copyright © 2016–2017, Texas Instruments Incorporated
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LMR23610-Q1
ZHCSFU7A –DECEMBER 2016–REVISED APRIL 2017
www.ti.com.cn
10.5 Layout Example
Output Bypass
Capacitor
Output Inductor
Input Bypass
Capacitor
SW
PGND
VIN
BOOT Capacitor
BOOT
VCC
FB
AGND
VCC
Capacitor
EN/
SYNC
UVLO Adjust Resistor
Output Voltage Set
Resistor
Thermal VIA
VIA (Connect to GND Plane)
Figure 30. Layout
26
版权 © 2016–2017, Texas Instruments Incorporated
LMR23610-Q1
www.ti.com.cn
ZHCSFU7A –DECEMBER 2016–REVISED APRIL 2017
11 器件和文档支持
11.1 使用 WEBENCH® 工具创建定制设计
请单击此处,使用 LMR23610-Q1 器件并借助 WEBENCH® 电源设计器创建定制设计。
1. 在开始阶段键入输出电压 (VIN)、输出电压 (VOUT) 和输出电流 (IOUT) 要求。
2. 使用优化器拨盘优化关键设计参数,如效率、封装和成本。
3. 将生成的设计与德州仪器 (TI) 的其他解决方案进行比较。
WEBENCH Power Designer 提供一份定制原理图以及罗列实时价格和组件可用性的物料清单。
在多数情况下,可执行以下操作:
•
•
•
•
运行电气仿真,观察重要波形以及电路性能
运行热性能仿真,了解电路板热性能
将定制原理图和布局方案导出至常用 CAD 格式
打印设计方案的 PDF 报告并与同事共享
有关 WEBENCH 工具的详细信息,请访问 www.ti.com/WEBENCH。
11.2 接收文档更新通知
要接收文档更新通知,请导航至 TI.com 上的器件产品文件夹。请单击右上角的通知我进行注册,即可收到所有的
产品更改信息每周摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
11.3 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范,
并且不一定反映 TI 的观点;请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中,您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.4 商标
PowerPAD, E2E are trademarks of Texas Instruments.
WEBENCH, SIMPLE SWITCHER are registered trademarks of Texas Instruments.
11.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
版权 © 2016–2017, Texas Instruments Incorporated
27
LMR23610-Q1
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www.ti.com.cn
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。这些数据如有变更,恕不另行通知
和修订此文档。如欲获取此数据表的浏览器版本,请参阅左侧的导航。
28
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LMR23610-Q1
www.ti.com.cn
ZHCSFU7A –DECEMBER 2016–REVISED APRIL 2017
版权 © 2016–2017, Texas Instruments Incorporated
29
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMR23610AQDDAQ1
LMR23610AQDDARQ1
ACTIVE SO PowerPAD
ACTIVE SO PowerPAD
DDA
DDA
8
8
75
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
F10AQ
F10AQ
2500 RoHS & Green
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMR23610AQDDARQ1
SO
Power
PAD
DDA
8
2500
330.0
12.8
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SO PowerPAD DDA
SPQ
Length (mm) Width (mm) Height (mm)
366.0 364.0 50.0
LMR23610AQDDARQ1
8
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
DDA HSOIC
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
LMR23610AQDDAQ1
8
75
517
7.87
635
4.25
Pack Materials-Page 3
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