LMV7231SQE/NOPB [TI]
精密微功耗十六路比较器 | RTW | 24 | -40 to 125;
| 型号： | LMV7231SQE/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 精密微功耗十六路比较器 | RTW | 24 | -40 to 125 比较器 |
| 文件： | 总28页 (文件大小：1639K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMV7231
SNOSB45F –FEBRUARY 2010–REVISED JANUARY 2016
LMV7231 Hex Window Comparator With 1.5% Precision and 400-mV Reference
1 Features
3 Description
The LMV7231 device is a 1.5% accurate Hex
Window Comparator which can be used to monitor
power supply voltages or any other analog output,
such as an analog temperature sensor or current-
sense amplifier. The device uses an internal 400-mV
reference for the comparator trip value. The
comparator set points can be set through external
resistor dividers. The LMV7231 has 6 outputs (CO1
to CO6) that signal an undervoltage or overvoltage
event for each power supply input. An output (AO) is
also provided to signal when any of the power supply
inputs have an overvoltage or undervoltage event.
This ability to signal an undervoltage or overvoltage
event for the individual power supply inputs, in
addition to an output to signal such an event on any
of the power supply inputs, adds unparalleled system
protection capability.
1
•
(For VS = 3.3 V ±10%, Typical Unless Otherwise
Noted)
•
•
•
•
•
•
•
•
•
•
Undervoltage and Overvoltage Detection
High Accuracy Voltage Reference: 400 mV
Threshold Accuracy: ±1.5% (Maximum)
Wide Supply Voltage Range 2.2 V to 5.5 V
Input and Output Voltage Range Above V+
Internal Hysteresis: 6 mV
Propagation Delay: 2.6 µs to 5.6 µs
Supply Current 7.7 µA Per Channel
24-Lead WQFN Package
Temperature Range: –40°C to +125°C
2 Applications
The 2.2-V to 5.5-V power supply voltage range, low
supply current, and input or output voltage range
above V+ make the LMV7231 ideal for a wide range
of power supply monitoring applications. Operation is
ensured over the –40°C to +125°C temperature
range. The device is available in a 24-pin WQFN
package.
•
•
•
•
•
Power Supply Voltage Monitoring
Battery Monitoring
Handheld Instruments
Relay Driving
Industrial Control Systems
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LMV7231
WQFN (24)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Typical Application
V+
Monitored Voltage #1
COPOL
Channel 1
+
-
+IN1
*
*
CO1
+
-
Monitored Voltage #6
-IN1
COPOL
REF
OV1 UV1
Controller
(FPGA)
CO6
+IN6
-IN6
Channel 6
OV6 UV6
REF
REF
AOSEL
AO
OV1
OV2
OV3
OV4
OV5
OV6
+400mV
*
UV1
UV2
UV3
UV4
UV5
UV6
* Open Drain
LMV7231
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMV7231
SNOSB45F –FEBRUARY 2010–REVISED JANUARY 2016
www.ti.com
Table of Contents
7.4 Device Functional Modes........................................ 13
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Application .................................................. 17
Power Supply Recommendations...................... 19
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 3.3-V Electrical Characteristics ................................. 5
6.6 Typical Characteristics.............................................. 6
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 13
8
9
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Example .................................................... 19
11 Device and Documentation Support ................. 20
11.1 Device Support...................................................... 20
11.2 Documentation Support ....................................... 20
11.3 Community Resources.......................................... 20
11.4 Trademarks........................................................... 20
11.5 Electrostatic Discharge Caution............................ 20
11.6 Glossary................................................................ 20
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (March 2013) to Revision F
Page
•
Added Device Information table, Pin Configuration and Functions section, ESD Ratings and Thermal Information
tables, Feature Description section, Device Functional Modes, Application and Implementation section, Power
Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section ..................................................................................................................... 1
Changes from Revision D (March 2013) to Revision E
Page
•
Changed layout of National Data Sheet to TI format ........................................................................................................... 17
2
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SNOSB45F –FEBRUARY 2010–REVISED JANUARY 2016
5 Pin Configuration and Functions
RTW Package
24-Pin WQFN
Top View
-IN1
+IN1
-IN2
+IN2
-IN3
+IN3
CO6
AO
AOSEL
COPOL
GND
LMV7231
RESERVED
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
1
NAME
–IN1
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Analog Input
Digital Input
Power
Negative input for window comparator 1
Positive input for window comparator 1
Negative input for window comparator 2
Positive input for window comparator 2
Negative input for window comparator 3
Positive input for window comparator 3
Negative input for window comparator 4
Positive input for window comparator 4
Negative input for window comparator 5
Positive input for window comparator 5
Negative input for window comparator 6
Positive input for window comparator 6
Connect to GND
2
+IN1
3
–IN2
4
+IN2
5
–IN3
6
+IN3
7
–IN4
8
+IN4
9
–IN5
10
11
12
13
14
+IN5
–IN6
+IN6
RESERVED
GND
Ground reference pin for the power supply voltage
The state of this pin determines whether the CO1-CO6 pins are active “HIGH” or “LOW”. When tied LOW the
CO1-CO6 outputs go LOW to indicate an out-of-window comparison.
15
16
17
18
19
20
21
22
23
COPOL
AOSEL
AO
Digital Input
Digital Input
The state of this pin determines whether the AO pin is active on an overvoltage or undervoltage event. When
tied LOW the AO output is active upon an overvoltage event.
Open-Drain NMOS This output is the ANDED combination of either the overvoltage comparator outputs or the undervoltage
Digital Output
comparator outputs and is controlled by the state of the AOSEL. AO pin is active-low.
Open-Drain NMOS
Digital Output
CO6
Window comparator 6 NMOS open-drain output
Open-Drain NMOS
Digital Output
CO5
Window comparator 5 NMOS open-drain output
Window comparator 4 NMOS open-drain output
Window comparator 3 NMOS open-drain output
Window comparator 2 NMOS open-drain output
Window comparator 1 NMOS open-drain output
Open-Drain NMOS
Digital Output
CO4
Open-Drain NMOS
Digital Output
CO3
Open-Drain NMOS
Digital Output
CO2
Open-Drain NMOS
Digital Output
CO1
24
V+
Power
Power supply pin
DAP
DAP
Thermal Pad
Die Attach Paddle (DAP). Connect to GND.
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6 Specifications
6.1 Absolute Maximum Ratings
(1)(2)(3)
See
.
MIN
MAX
6
UNIT
V
Supply voltage
Voltage at input / output pin
Output current
GND − 0.3
6
V
10
mA
mA
°C
Total package current
Junction temperature(4)
Storage temperature, Tstg
50
150
150
–65
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) For soldering specifications, see Absolute Maximum Ratings for Soldering (SNOA549).
(4) The maximum power dissipation is a function of TJ(MAX), RθJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA) / RθJA. All numbers apply for packages soldered directly onto a PCB.
6.2 ESD Ratings
VALUE
±2000
±200
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(2)
Machine model
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
6.3 Recommended Operating Conditions
MIN
2.2
MAX
5.5
UNIT
V
Supply voltage
Junction temperature(1)
–40
125
°C
(1) The maximum power dissipation is a function of TJ(MAX), RθJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA) / RθJA. All numbers apply for packages soldered directly onto a PCB.
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6.4 Thermal Information
LMV7231
THERMAL METRIC(1)
RTW (WQFN)
24 PINS
37.4
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
40.2
16.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.6
ψJB
16.2
RθJC(bot)
5.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 3.3-V Electrical Characteristics
Unless otherwise specified, all limits ensured for TA = 25°C, V+ = 3.3 V ±10%, GND = 0 V, and RL > 1 MΩ.
PARAMETER
TEST CONDITION
TA = –10°C to +70°C
TA = –10°C to +70°C
MIN(1)
TYP(2)
MAX(1)
406
408.6
401
403.2
8.8
UNIT
394
400
VTHR
Threshold: input rising
RL = 10 kΩ
mV
391.4
386
394
VTHF
VHYST
IBIAS
Threshold: input falling
Hysteresis (VTHR − VTHF
Input bias current
RL = 10 kΩ
RL = 10 kΩ
mV
mV
nA
383.8
3.9
)
6.0
–5
0.05
5
VIN = V+, GND, and
5.5 V
TA = –10°C to +70°C
TA = –10°C to +70°C
TA = –10°C to +70°C
–15
15
160
200
250
0.4
VOL
Output low voltage
IL = 5 mA
mV
VOUT = V+, 5.5 V and
40 mV of overdrive
IOFF
Output leakage current
μA
1
High-to-low propagation
delay (+IN falling)
2.6
5.4
5.6
2.8
0.5
6
tPDHL1
tPDHL2
10 mV of overdrive
10 mV of overdrive
10 mV of overdrive
μs
μs
μs
High-to-low propagation
delay (-IN rising)
10
10
6
Low-to-high propagation
delay (+IN rising)
tPDLH1
tPDLH2
Low-to-high propagation
delay (-IN falling)
10 mV of overdrive
μs
μs
tr
tf
Output rise time
CL= 10 pF, RL= 10 kΩ
0.25
0.3
0.2
1
CL = 100 pF, RL = 10
kΩ
Output fall time
μs
μA
μA
TA = –10°C to +70°C
Digital input logic 1 leakage
current
IIN(1)
TA = –10°C to +70°C
0.2
1
Digital input logic 0 leakage
current
IIN(0)
TA = –10°C to +70°C
TA = –10°C to +70°C
TA = –10°C to +70°C
VIH
VIL
Digital input logic 1 voltage
Digital input logic 0 voltage
0.7 × V+
V
V
0.3 × V+
60
46
No loading (outputs
high)
IS
Power supply current
μA
TA = –10°C to +70°C
84
V+ ramp rate = 1.1 ms
V+ step = 2.5 V to 4.5 V
400
μV
μV
VTH power supply
sensitivity(3)
VTHPSS
V+ ramp rate = 1.1 ms
V+ step = 4.5 V to 2.5 V
–400
(1) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using the
Statistical Quality Control (SQC) method.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and also depends on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(3) VTH power supply sensitivity is defined as the temporary shift in the internal voltage reference due to a step on the V+ pin.
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6.6 Typical Characteristics
V+ = 3.3 V and TA =25°C unless otherwise noted.
40
35
30
25
20
15
10
5
40
35
30
25
20
15
10
5
0
0
396 397 398 399 400 401 402 403 404
396 397 398 399 400 401 402 403 404
Input Rising Threshold (mV)
Input Rising Threshold (mV)
Figure 2. −IN Input Rising Threshold Distribution
Figure 1. +IN Input Rising Threshold Distribution
40
40
35
30
25
20
15
10
5
35
30
25
20
15
10
5
0
0
390 391 392 393 394 395 396 397 398
390 391 392 393 394 395 396 397 398
Input Falling Threshold (mV)
Input Falling Threshold (mV)
Figure 3. +IN Input Falling Threshold Distribution
Figure 4. −IN Input Falling Threshold Distribution
50
50
45
40
35
30
25
20
15
10
5
45
40
35
30
25
20
15
10
5
0
0
4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0
4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0
Hysteresis (mV)
Hysteresis (mV)
Figure 5. +IN Hysteresis Distribution
Figure 6. −IN Hysteresis Distribution
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Typical Characteristics (continued)
V+ = 3.3 V and TA =25°C unless otherwise noted.
405
405
404
403
402
401
400
399
398
397
396
395
404
403
402
401
+IN
400
+IN
399
398
-IN
-IN
397
396
395
2
3
4
5
6
-40 -20
0
20 40 60 80 100 120
Temperature (°C)
Supply Voltage (V)
Figure 7. Input Rising Threshold Voltage vs Temperature
Figure 8. Input Rising Threshold Voltage vs Supply Voltage
400
400
399
398
397
396
395
399
398
397
396
395
-IN
394
-IN
394
393
392
393
392
+IN
+IN
391
391
390
390
2
3
4
5
6
-40 -20
0
20 40 60 80 100 120
Temperature (°C)
Supply Voltage (V)
Figure 10. Input Falling Threshold Voltage vs Supply
Voltage
Figure 9. Input Falling Threshold Voltage vs Temperature
10
9
10
9
+IN
8
8
+IN
7
6
5
7
6
5
-IN
-IN
4
4
3
2
1
0
3
2
1
0
-40 -20
0
20 40 60 80 100 120
Temperature (°C)
2
3
4
5
6
Supply Voltage (V)
Figure 11. Hysteresis vs Temperature
Figure 12. Hysteresis vs Supply Voltage
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Typical Characteristics (continued)
V+ = 3.3 V and TA =25°C unless otherwise noted.
60
50
49
48
47
46
45
44
43
42
41
40
125°C
T
= 25°C
A
50
85°C
40
25°C
5.5V
30
-40°C
20
10
0
3.3V
2.2V
8
1
2
3
4
5
6
0
1
2
3
4
5
6
7
9
10
Supply Voltage (V)
Output Sink Current (mA)
Figure 13. Supply Current vs Supply Voltage and
Temperature
Figure 14. Supply Current vs Output Sink Current
40
55
T
A
= -40°C
T = 85°C
A
39
38
37
36
35
34
33
32
31
30
54
53
52
51
50
49
48
47
46
45
5.5V
5.5V
3.3V
3.3V
2.2V
2.2V
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
Output Sink Current (mA)
Output Sink Current (mA)
Figure 15. Supply Current vs Output Sink Current
Figure 16. Supply Current vs Output Sink Current
60
5
T
A
= 125°C
-40°C
+IN, -IN
59
58
57
56
55
54
53
52
51
50
0
5.5V
85°C
+IN, -IN
-5
3.3V
-10
-15
-20
25°C
+IN, -IN
2.2V
25°C
+IN, -IN
0
1
2
3
4
5
6
7
8
9
10
-0.3
-0.2
Input Voltage (V)
-0.1
Output Sink Current (mA)
Figure 17. Supply Current vs Output Sink Current
Figure 18. Bias Current vs Input Voltage
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Typical Characteristics (continued)
V+ = 3.3 V and TA =25°C unless otherwise noted.
0.4
2.0
125°C -IN
1.6
1.2
0.8
0.4
0.0
0.3
125°C +IN
25°C -IN
0.2
-40°C -IN
85°C -IN
0.1
25°C +IN
-40°C +IN
0.0
0.0
85°C +IN
3.0 3.6
0.6
1.2
1.8
2.4
3.0
3.6
0.0
0.6
1.2
1.8
2.4
Input Voltage (V)
Input Voltage (V)
Figure 19. Bias Current vs Input Voltage
Figure 20. Bias Current vs Input Voltage
450
600
T
A
= 25°C
T = 85°C
A
400
350
300
250
200
150
100
50
V+ = 2.2V
500
400
300
200
100
0
V+ = 2.2V
V+ = 3.3V
V+ = 3.3V
V+ = 5.5V
6
V+ = 5.5V
6
0
0
2
4
8
10
0
2
4
8
10
Ouput Sink Current (mA)
Output Sink Current (mA)
Figure 21. Output Voltage Low vs Output Sink Current
Figure 22. Output Voltage Low vs Output Sink Current
350
700
T
A
= -40°C
T = 125°C
A
300
250
200
150
100
50
600
500
400
300
200
100
0
V+ = 2.2V
V+ = 2.2V
V+ = 3.3V
V+ = 3.3V
V+ = 5.5V
V+ = 5.5V
0
0
2
4
6
8
10
0
2
4
6
8
10
Output Sink Current (mA)
Output Sink Current (mA)
Figure 23. Output Voltage Low vs Output Sink Current
Figure 24. Output Voltage Low vs Output Sink Current
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Typical Characteristics (continued)
V+ = 3.3 V and TA =25°C unless otherwise noted.
100
70
60
50
40
30
20
10
0
V+ = 3.3V
T
A
= 25°C
-40°C
25°C
80
60
40
20
0
V+ = 5.5V
85°C
V+ = 3.3V
125°C
V+ = 2.2V
0
1
2
4
5
6
0
1
1
2
3
Output Voltage (V)
Output Voltage (V)
Figure 25. Output Short Circuit Current vs Output Voltage
Figure 26. Output Short Circuit Current vs Output Voltage
40
1e2
V+ = 3.3V
RISE
CL = 10 pF
T
A
= 25°C
1e1
1
30
20
10
0
1e-1
1e-2
1e-3
FALL
HL +IN
0
10 20 30 40 50 60 70 80 90 100
Input Overdrive (mV)
1e-1
1
1e1
1e2
1e3
Output Pull-Up Resistor (kW)
Figure 28. Rise and Fall Times vs Output Pullup Resistor
Figure 27. Propagation Delay vs Input Overdrive
when
V
OUT
V+ = 3.3V
10
t
t
+IN = V
PDHL1
PDLH1
IN
-IN = GND
2V/DIV
DC
1
t
t
PDHL2
PDLH2
V when
OUT
+IN = V+
-IN = V
IN
2V/DIV
DC
0.1
0.01
V
IN
R
C
= 10 kW
= 10 pF
L
L
10 mV/DIV
AC
10 mV OF OVERDRIVE
0
1
2
4
5
6
4 ms/DIV
Output Voltage (V)
Figure 30. Output Leakage Current vs Output Voltage
Figure 29. Propagation Delay
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Typical Characteristics (continued)
V+ = 3.3 V and TA =25°C unless otherwise noted.
V+ = 3.3 V
10
1
0.1
0.01
0
1
2
4
5
6
Output Voltage (V)
Figure 31. Output Leakage Current vs Output Voltage
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7 Detailed Description
7.1 Overview
The LMV7231 is Hex Window Comparator which can be used to monitor power supply voltages and other critical
system voltage levels.
The LMV7231 contains 6 identical window comparators where the upper and lower trip points are set through
external resistor dividers. Each input of the comparator is compared to a internal 1.5% accurate 400-mV
reference voltage (VREF).
The 6 window comparator outputs (CO1-CO6) signal an undervoltage or overvoltage event for each power
supply input. The COPOL pin sets the inside or outside of the window indication.
A combined OR'ed output (AO) is also provided to signal when any of the power supply inputs have an
overvoltage or undervoltage event. AOSEL sets the logic polarity to create a power-good or error signal.
7.2 Functional Block Diagram
COPOL
*
CO1
UV
+IN1
+
-
1
*
B
*
*
CO2
CO3
Ref
+
-
OV
1
A
*
*
-IN1
+IN2
UV
2
+
-
*
*
B
CO4
CO5
*
*
+
-
OV
2
A
B
-IN2
*
*
+IN3
+
-
UV
3
CO6
+
-
OV
UV
A
3
OV
1
-IN3
AOSEL
OV
OV
OV
OV
2
3
4
5
+IN4
+
-
4
B
OV
6
AO
+
-
OV
4
A
*
-IN4
+IN5
UV
UV
UV
UV
UV
1
2
3
4
5
6
* Open
Drain
+
-
UV
5
B
UV
+
-
OV
A
5
-IN5
+IN6
+
-
UV
6
B
OV
+
-
6
A
-IN6
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7.3 Feature Description
The LMV7231 Hex Window Comparator with 1.5% precision can accurately monitor up to 6 power rails or
batteries at one time. The input and output voltages of the device can exceed the supply voltage, V+, of the
comparator, and can be up to the maximum ratings listed in the Absolute Maximum Ratings without causing
damage or performance degradation. The typical microcontroller input pin with crowbar diode ESD protection
circuitry does not allow the input to go above V+, and thus its usefulness is limited in power supply supervision
applications.
7.3.1 Input and Output Voltage Range Above V+
The supply independent inputs of the window comparator blocks allow the LMV7231 to be tolerant of system
faults. For example, if the power is suddenly removed from the LMV7231 due to a system malfunction while a
voltage still exists on the input, it is not an issue as long as the monitored input voltage does not exceed the
absolute maximum ratings. Another example where this feature comes in handy is a battery-sense application
such as the one in Figure 32. The boards may be sitting on the shelf unbiased with V+ grounded, and yet have a
fully charged battery onboard. If the comparator measuring the battery had crowbar diodes, the diode from –IN to
V+ would turn on, sourcing current from the battery, eventually draining the battery. However, when using the
LMV7231 no current, except the low input bias current of the device, flows into the chip, and the battery charge
is preserved.
V+ = 3.3V
R1
499k
R2
1M
+
-
V
OUT
VBATT
R3
3.01k
Figure 32. Battery-Sense Application
The output pin voltages of the device can also exceed the supply voltage, V+, of the comparator. This provides
extra flexibility and enables designs which pull up the outputs to higher voltage levels to meet system
requirements. For example, it is possible to run the LMV7231 at its minimum operating voltage, V+ = 2.2 V, but
to bias a blue LED, pull up the output listed in the Absolute Maximum Ratings, with a forward voltage of VF = 4 V.
In a power supply supervision application, the hardwired LMV7231 is a sound solution compared to the
microcontroller with software alternative for several reasons. First, start-up is faster. During start-up, code loading
time, oscillator ramp time, and reset time do not need to be accounted for. Second, operation is quick. The
LMV7231 has a maximum propagation delay and is not affected by sampling and conversion delays related to
reading data, calculating data, and setting flags. Third, the device has less overhead. The LMV7231 does not
require an expensive power-consuming microcontroller nor is it dependent on controller code which could get
damaged or crash.
7.4 Device Functional Modes
7.4.1 +IN1 through +IN6 Input Pins
These inputs set the upper threshold voltage of the channel window comparator. The input voltage is compared
to the internal 400-mV reference. These inputs are capable of input voltages up to the Absolute Maximum
Ratings (6 V), independent of the V+ supply voltage.
7.4.2 –IN1 through –IN6 Input Pins
These inputs set the lower threshold voltage of the channel window comparator. The input voltage is compared
to the internal 400-mV reference. These inputs are capable of input voltages up to the Absolute Maximum
Ratings (6 V), independent of the V+ supply voltage.
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Device Functional Modes (continued)
7.4.3 CO1 through C06 Output Pins
These are the open-drain outputs of the individual comparators. A pullup resistor is required or several outputs
may be logic OR'ed together with a common pullup resistor. The polarity is determined by the COPOL input pin
setting.
7.4.4 COPOL Input Pin
The state of this comparator output polarity select input pin determines whether the CO1-CO6 pins are active-
high or active-low. When tied LOW, the CO1-CO6 outputs go LOW to indicate an out-of-window comparison.
When tied HIGH, the outputs go LOW to indicate a within-window comparison.
7.4.5 AO Output Pin
This output is the AND'ed combination of either the overvoltage comparator outputs or the undervoltage
comparator outputs and is controlled by the state of the AOSEL. The AO pin is active-low.
7.4.6 AOSEL Input Pin
The state of this AND output level select pin determines whether the AO pin is active on an overvoltage or
undervoltage event. When tied LOW the AO output is active upon an overvoltage event.
7.4.7 Three-Resistor Voltage Divider Selection
The LMV7231 trip points can be set by external resistor dividers as shown in Figure 33.
V+
V
IN
0.1 mF
COPOL
R1
Ch. 1
+
-
+IN1
10k
*
V
OUT
R2
R3
*
CO1
+
-
-IN1
COPOL
REF
OV1 UV1
OV6 UV6
CO6
+IN6
-IN6
Ch. 6
REF
REF
REF
AOSEL
OV1
OV2
OV3
OV4
OV5
OV6
10k
AO
*
UV1
UV2
UV3
UV4
UV5
UV6
* Open
Drain
LMV7231
RESERVED
GND
Figure 33. External Resistor Dividers
Each trip point, overvoltage (VOV) and undervoltage (VUV), can be optimized for a falling supply (VTHF), or a rising
supply (VTHR).
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Device Functional Modes (continued)
Therefore, there are 22 = 4 different optimization cases:
1. Exiting the voltage detection window (Figure 34)
2. Rising into and out of the window (Figure 35)
3. Entering the window (Figure 36)
4. Falling into and out of the window (Figure 37)
V
V
OV
V
V
OV
UV
UV
V
V
OUT
OUT
V
IN
V
IN
R3 set
R3 set
R2 = R3(V /V
OV UV
ꢀ1
R2 = R3((V
/V )V /V
THF THR OV UV
ꢀ)
Rꢀ = R3((ꢀ/V
1V
THR OV
- V /V
OV UV
1
Rꢀ = R3((ꢀ/V
)V
THR OV
- (V
/V )V /V
THF THR OV UV
)
Ex. V = 3.465 V, V
OV
= 3.ꢀ35 V, that is, V
= 3.3 V 5ꢁ
RANGE
Ex. V = 3.465 V, V = 3.ꢀ35 V, that is, V
OV UV
= 3.3 V 5ꢁ
UV
RANGE
R3 set to ꢀ0 kΩ
R3 set to ꢀ0 kΩ
R2 = ꢀ0k((3.465/3.ꢀ351 ꢀ1 ≈ ꢀ.05 kΩ
Rꢀ = ꢀ0k((ꢀ/0.413.465 3.465/3.ꢀ351 ≈ 75 kΩ
R2 = ꢀ0k((0.394/0.4)3.465/3.ꢀ35 ꢀ) ≈ 887 Ω
Rꢀ = ꢀ0k((ꢀ/0.4)3.465 - (0.394/0.4)3.465/3.ꢀ35) ≈ 75 kΩ
Figure 34. Exiting the Voltage Detection Window
Figure 35. Rising into and out of the Voltage
Detection Window
V
V
V
V
OV
UV
OV
UV
V
V
OUT
OUT
V
IN
V
IN
R3 set
R3 set
R2 = R3((V
/V )V /V
THR THF OV UV
ꢀ)
R2 = R3(V /V
OV UV
ꢀ1
Rꢀ = R3((ꢀ/V
)V
THF OV
- (V
/V )V /V
THR THF OV UV
)
Rꢀ = R3((ꢀ/V
1V
THF OV
- V /V 1
OV UV
= 3.ꢀ35 V, that is, V
= 3.3 V 5ꢁ
RANGE
Ex. V = 3.465 V, V = 3.ꢀ35 V, that is, V
OV UV
Ex. V = 3.465 V, V
OV
= 3.3 V 5ꢁ
UV
RANGE
R3 set to ꢀ0 kΩ
R3 set to ꢀ0 kΩ
R2 = ꢀ0k((0.4/0.394)3.465/3.ꢀ35 ꢀ) ≈ ꢀ.2ꢀ kΩ
R2 = ꢀ0k((3.465/3.ꢀ351 ꢀ1
≈ ꢀ.05 kΩ
Rꢀ = ꢀ0k((ꢀ/0.394)3.465 - (0.4/0.394)3.465/3.ꢀ35) ≈ 76.8 kΩ
Rꢀ = ꢀ0k((ꢀ/0.39413.465 3.465/3.ꢀ351 ≈ 76.8 kΩ
Figure 36. Entering the Voltage Detection Window
Figure 37. Falling into and out of the Voltage
Detection Window
NOTE
For each case, each trip point can be optimized for either a rising or falling signal, but not
both.
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Device Functional Modes (continued)
The governing equations make it such that if the same resistor, R3, and overvoltage-to-undervoltage ratio,
VOV/VUV, is used across the channels, the same nominal current travels through the resistor ladder. As a result,
R2 is also the same across all channels, and only R1 needs to change to set voltage detection window
maximizing reuse of resistor values and minimizing design complexity.
Select the R3 resistor value to be below 100 kΩ so the resistor current through the divider ladder is much greater
than the LMV7231 bias current (15 nA worst case, 50 pA typical). If the current traveling through the resistor
divider is on the same magnitude of the LMV7231 IBIAS, the IBIAS current creates an error in the circuit and
causes trip voltage shifts. The greatest error due to IBIAS is caused when that current passes through the greatest
equivalent resistance, REQ = R1‖(R2+R3), which is detected by the positive input of the window comparator,
+IN.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LMV7231 is specified for operation from 2.2 V to 5.5 V. Some of the specifications apply from –10°C to
+70°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are
presented in the Typical Characteristics and the 3.3-V Electrical Characteristics.
8.2 Typical Application
Figure 38 shows a typical power supply supervision circuit using the LMV7231 and the efficient, easy to use
LM25007 step-down switching regulator.
Input = 9V-42V
VIN
VCC
C4
0.1µF
C3
C1
R1
115k
BST
1.0 µF 0.1 µF
0.01µF
L1 100 µH
C5
LM25007
C6
R6
121k
RON/SD
RCL
SW
V
OUT
= 5V
ON/OFF
2200
pF
D1
R2
3k
C7
0.01 µF
R5
200k
FB
C2
22 µF
RTN
R3
3k
V+ = 3.3V
C8
COPOL
0.1 µF
R7
1.15k
V+
Ch. 1
R10
10k
+
-
+IN1
*
*
Controller
(FPGA)
CO1
R8
10
C9
*optional
+
-
-IN1
R9
95.3
V+
R11
10k
COPOL
UV1 OV1
REF
CO6
+IN6
-IN6
Ch. 6
UV6 OV6
OV1
REF
AOSEL
OV2
OV3
OV4
OV5
OV6
REF
REF
V+
R12
10k
AO
*
UV1
UV2
UV3
UV4
UV5
UV6
* Open
Drain
LMV7231
GND
RESERVED
Figure 38. Power Supply Supervision
8.2.1 Design Requirements
Table 1 describes the requested design parameters.
Table 1. Design Parameters
PARAMETER
Logic Supply Voltage
Monitored Voltage
EXAMPLE VALUE
3.3 V
5 V
Monitored Voltage Tolerance
Window
±5% (4.75 V to 5.25 V)
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8.2.2 Detailed Design Procedure
The regulators output voltage is set to 5 V, according to the LM25007 data sheet, SNVS401.
VOUT = 2.5 × (R2 + R3) / R3
(1)
(2)
VOUT = 2.5 × (3 kΩ + 3 kΩ) / 3 kΩ = 5 V
Resistor R6 and capacitors C6, C7 are utilized to minimize output ripple voltage per the AN-1453 LM25007
Evaluation Board, (SNVA152).
The comparator voltage window is set to 5 V ±5%. This requires input voltages of 420 mV and 380 mV, which
calculates to R7 = 1.15 kΩ , R8 = 10 Ω, R9 = 95.3 Ω. See the Three-Resistor Voltage Divider Selection section
for details on how to set the comparator voltage window.
With the components selected, the output ripple voltage on the LM25007 is approximately 30 to 35 mV and is
reduced to about 4 mV at the comparator input, +IN1, by the resistor divider. This ripple voltage can be reduced
multiple ways. First, user can operate the device in continuous conduction mode rather than discontinuous
conduction mode. To do this increase the load current of the device (see SNVS401 for more details). However,
the power rating of the resistors in the resistor ladder must not be exceeded. Second, ripple can be reduced
further with a bypass capacitor, C9, at the resistor divider. If desired, select a 1-µF capacitor to achieve less than
3-mV ripple at +IN1. However, there is a trade-off that adding capacitance at this node lowers the system
response time.
8.2.3 Application Curve
Figure 39 shows the results of sweeping the regulator output voltage through the undervoltage and overvoltage
thresholds. COPOL is set LOW so that the output goes LOW while the regulator voltage is within the ±5%
thresholds.
6.0
COPOL = LOW
5.5
+5% V
OV
5.0
-5% V
UV
CO1 Output
Regulator Output
4.5
4.0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Time (Seconds)
C001
Figure 39. Power Supply Supervisor Thresholds
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9 Power Supply Recommendations
Bypass the supply pin, V+, with a 0.1-μF ceramic capacitor placed close to the V+ pin. If transients with rise or
fall times of hundreds of μs and magnitudes of hundreds of mV are expected on the power supply line, an RC
lowpass filter network as shown in Figure 40 is recommended for additional bypassing. If no such bypass
network is used power supply transients can cause the internal voltage reference of the comparator to
temporarily shift potentially resulting in a brief incorrect comparator output. For example, if an RC network with
100-Ω resistance and 10-μF capacitance (1.1-ms rise time) is used the voltage reference temporarily shifts the
amount, VTH power supply sensitivity (VTHPSS), specified in the 3.3-V Electrical Characteristics table.
R1
100
V
SUPPLY
C1
10 mF
C2
0.1 mF
V+
LMV7231
Figure 40. Power Supply Bypassing
10 Layout
10.1 Layout Guidelines
Proper grounding and the use of a ground plane helps to ensure the specified performance of the LMV7231.
Minimizing trace lengths, reducing unwanted parasitic capacitance, and using surface-mount components also
helps. Comparators are very sensitive to input noise.
1. Use a printed-circuit-board with a good, unbroken low-inductance ground plane.
2. Place a decoupling capacitor (0.1-µF ceramic surface mount capacitor) as close to V+ pin as possible.
3. On the inputs and the outputs, keep lead lengths and the divider resistors as short possible to avoid noise
pick-up.
The DAP pad is connected to the bottom of the die and is not designed to carry current. The DAP thermal pad
must be connected directly to the GND pin to avoid noise and possible voltage gradients. The primary grounding
pin is the GND pin.
10.2 Layout Example
Figure 41. Example Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
LMV7231 Evaluation Board, http://www.ti.com/tool/lmv7231eval
11.2 Documentation Support
11.2.1 Related Documentation
•
•
•
LMV7231 Evaluation Board Manual, SNOU008
LM25007 42-V, 0.5-A Step-Down Switching Regulator, SNVS401
AN-1453 LM25007 Evaluation Board, SNVA152
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMV7231SQ/NOPB
LMV7231SQE/NOPB
LMV7231SQX/NOPB
ACTIVE
ACTIVE
ACTIVE
WQFN
WQFN
WQFN
RTW
RTW
RTW
24
24
24
1000 RoHS & Green
250 RoHS & Green
4500 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
L7231SQ
SN
SN
L7231SQ
L7231SQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Nov-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMV7231SQ/NOPB
LMV7231SQE/NOPB
LMV7231SQX/NOPB
WQFN
WQFN
WQFN
RTW
RTW
RTW
24
24
24
1000
250
178.0
178.0
330.0
12.4
12.4
12.4
4.3
4.3
4.3
4.3
4.3
4.3
1.3
1.3
1.3
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
4500
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Nov-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMV7231SQ/NOPB
LMV7231SQE/NOPB
LMV7231SQX/NOPB
WQFN
WQFN
WQFN
RTW
RTW
RTW
24
24
24
1000
250
208.0
208.0
367.0
191.0
191.0
367.0
35.0
35.0
35.0
4500
Pack Materials-Page 2
PACKAGE OUTLINE
RTW0024A
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
B
A
PIN 1 INDEX AREA
4.1
3.9
C
0.8 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 2.5
(0.1) TYP
EXPOSED
THERMAL PAD
7
12
20X 0.5
6
13
2X
25
2.5
2.6 0.1
1
18
0.3
24X
0.2
24
19
PIN 1 ID
(OPTIONAL)
0.1
C A B
C
0.05
0.5
0.3
24X
4222815/A 03/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RTW0024A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
2.6)
SYMM
24
19
24X (0.6)
1
18
24X (0.25)
(1.05)
SYMM
25
(3.8)
20X (0.5)
(R0.05)
TYP
6
13
(
0.2) TYP
VIA
7
12
(1.05)
(3.8)
LAND PATTERN EXAMPLE
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222815/A 03/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RTW0024A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.15)
(0.675) TYP
19
(R0.05) TYP
24
24X (0.6)
1
18
24X (0.25)
(0.675)
TYP
SYMM
20X (0.5)
25
(3.8)
6
13
METAL
TYP
7
12
SYMM
(3.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 25:
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4222815/A 03/2016
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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