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LMX2571

ZHCSDH8 –MARCH 2015

LMX2571 低功耗、高性能 PLLatinum™ RF 合成器，采用 FSK 调制

1 特性

3 说明

1

•

输出频率范围：10MHz 至 1344MHz

LMX2571 是一款低功耗、高性能、宽带 PLLatinum™

射频 (RF) 合成器，该合成器集成了 Δ-Σ 分数 N PLL、

多核压控振荡器 (VCO)、可编程输出分压器以及两个

输出缓冲器。 VCO 内核的工作频率高达 5.376GHz，

持续输出频率范围为 10MHz 至 1344MHz。

•

低相位噪声和毛刺

–

12.5kHz 偏移 @ 480MHz 时为 –123dBc/Hz

1MHz 偏移 @ 480MHz 时为 –145dBc/Hz

标准化锁相环 (PLL) 噪底为 –231dBc/Hz

杂散优于 –75dBc/Hz

该合成器还可搭配外部 VCO 使用。在此配置下，需

使用专用的 5V 电荷泵和输出分压器。

•

新型 FastLock 技术，缩短了锁定时间

新型整数边界毛刺去除技术

该合成器还包含一个独特的可编程乘法器，有助于去除

毛刺，即使毛刺落在整数边界，系统也仍能够使用任一

通道。

集成 5V 电荷泵和输出驱动器，用于外部压控振荡

器 (VCO) 操作

•

2、4 和 8 电平或者任意电平数直接数字移频键控

(FSK) 调制

其输出具有 SPDT 开关，可用作 FDD 无线电应用中的

发送/接收开关。并且可同时导通两个开关，以便同时

提供双输出。

•

一个 TX/RX 输出或两个扇出输出

晶振、XO 或差分参考时钟输入

低电流消耗

LMX2571 通过编程或相应引脚来支持直接数字 FSK

调制。该器件支持离散电平 FSK、脉冲成形 FSK 以

及模拟 FM 调制。

–

39mA 典型合成器模式（内部 VCO）

9mA 典型 PLL 模式（外部 VCO）

•

24 位分数 N Δ-Σ 调制器

该器件采用了一项全新的 FastLock 技术，即使在外部

VCO 与窄带回路滤波器搭配使用时，用户也能够在不

到 1.5ms 的时间内从一个频率切换至另一频率。

2 应用

•

双工模式数字专业双向无线电

dPMR、DMR、PDT、P25 Phase I

低功耗无线电通信系统

–

器件信息⁽¹⁾

•

器件型号

LMX2571

封装

封装尺寸（标称值）

–

卫星通信调制解调器

无线麦克风

WQFN (36)

6.00mm x 6.00mm

(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。

专有无线连接

•

手持式测试和测量设备

3.3V

3.3V/5V

0.1µF

LMX2571

100pF

Vcc3p3

VccIO

5V CP

supply

CP

MUX

Int. charge

pump

Output

divider

OP

To driver amplifier

MUX

XO

Phase

detector

R-divider

Prescaler

VrefVCO

VregVCO

N-divider

2.2µF

0.1µF

100pF

G4ꢀ

modulator

Fast

lock

5V charge

pump

VCO

MUX

Output

divider

Lock

dect

µWIRE

SPI

Enable

To receive mixer

FLout CPoutExt

Fin

FSK

MUXout CE

TrCtl

SoC / DSP

1

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

English Data Sheet: SNAS654

LMX2571

ZHCSDH8 –MARCH 2015

www.ti.com.cn

7.5 Programming .......................................................... 15

7.6 Register Maps......................................................... 16

Application and Implementation ........................ 34

8.1 Application Information............................................ 34

8.2 Typical Applications ............................................... 43

8.3 Do's and Don'ts....................................................... 52

Power Supply Recommendations...................... 53

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 5

6.6 Timing Requirements ............................................... 7

6.7 Typical Characteristics.............................................. 8

Detailed Description ............................................ 10

7.1 Overview ................................................................. 10

7.2 Functional Block Diagram ....................................... 10

7.3 Feature Description................................................. 11

7.4 Device Functional Modes........................................ 14

8

9

10 Layout................................................................... 54

10.1 Layout Guidelines ................................................. 54

10.2 Layout Example .................................................... 54

11 器件和文档支持 ..................................................... 55

11.1 器件支持 ............................................................... 55

11.2 文档支持 ............................................................... 55

11.3 商标....................................................................... 55

11.4 静电放电警告......................................................... 55

11.5 术语表 ................................................................... 55

12 机械封装和可订购信息 .......................................... 55

7

4 修订历史记录

日期

修订版本

注释

2015 年 3 月

*

最初发布。

2

LMX2571

www.ti.com.cn

ZHCSDH8 –MARCH 2015

5 Pin Configuration and Functions

WQFN (NJK) Package

36 Pins

Top View

1

27

26

25

24

23

22

21

20

19

Vcc3p3

NC

2

Bypass1

3

Bypass2

CPout

Fin

4

FSK_DV

0

DAP

5

FSK_D2

GND

6

FSK_D1

VrefVCO

VregVCO

Vcc3p3

CE

7

FSK_D0

8

NC

9

Vcc3p3

Pin Functions

TYPE

DESCRIPTION

NAME

Bypass1

Bypass2

CE

NO.

2

Bypass Place a 100-nF capacitor to GND.

3

19

11

25

30

0

Input

Chip Enable input. Active HIGH powers on the device.

CLK

Input

MICROWIRE clock input.

CPout

CPoutExt

DAP

Output Internal VCO charge pump access point to connect to a 2^ndorder loop filter.

Output 5-V charge pump output used in PLL mode (external VCO).

GND

Input

The DAP should be grounded.

MICROWIRE serial data input.

DATA

12

High frequency AC coupled input pin for an external VCO. Leave it open or AC coupled to GND if not

being used.

Fin

24

Input

FSK_D0

FSK_D1

FSK_D2

FSK_DV

FLout1

FLout2

GND

7

6

Input

FSK data bit 0 (FSK PIN mode) / I2S FS input (FSK I2S mode).

FSK data bit 1 (FSK PIN mode) / I2S DATA input (FSK I2S mode).

FSK data bit 2 (FSK PIN mode).

5

4

FSK data valid input (FSK PIN mode) / I2S CLK input (FSK I2S mode).

29

28

23

31

35

13

10

8,14, 26

34

36

16

17

18

Output FastLock output control 1 for external switch. Output is HIGH when F1 is selected.

Output FastLock output control 2 for external switch. Output is HIGH when F2 is selected.

GND

Input

VCO ground.

GND

Charge pump ground.

OSCin ground.

GND

LE

MICROWIRE latch enable input.

MUXout

NC

Output Multiplexed output that can be assigned to lock detect or readback serial data output.

NC

Do not connect these pins.

Reference clock input.

OSCin

OSCin*

RFoutRx

RFoutTx

TrCtl

Input

Complementary reference clock input.

Output RF output used to drive receive mixer. Selectable open drain or push-pull output.

Output RF output used to drive transmit signal. Selectable open drain or push-pull output.

Input

Transmit/Receive control. This pin controls the RF output port and the output frequency selection.

3

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ZHCSDH8 –MARCH 2015

www.ti.com.cn

Pin Functions (continued)

TYPE

Supply Connect to 3.3-V supply.

Supply Supply for digital logic interface. Connect to 3.3-V supply.

DESCRIPTION

NAME

Vcc3p3

NO.

1, 9, 20,

27

VccIO

15, 33

Supply for 5-V charge pump. Connect to 5-V supply in PLL mode. Connect to either 3.3-V or 5-V

supply in synthesizer mode.

VcpExt

32

Supply

VrefVCO

VregVCO

22

21

Bypass LDO output. Place a 100-nF capacitor to GND.

Bypass Bias circuitry for the VCO. Place a 2.2-µF capacitor to GND.

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)

(1)

MIN

–0.3

MAX

3.6

UNIT

V

V_CCPower supply voltage

V_IO

V_IN

IO supply voltage

IO input voltage

3.6

V

V_CC+ 0.3

5.25

V

V_CPCharge pump supply voltage

T_JJunction temperature

T_STGStorage temperature

V

150

°C

–65

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±1500

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)

MIN

MAX

3.45

V_CC

5

UNIT

V_CCPower supply voltage

V_IOIO supply voltage

3.15

V

PLL mode (external VCO)

V_CPCharge pump supply voltage

V

Synthesizer mode (internal VCO)

V_CC

–40

5

T_A

T_J

Ambient temperature

Junction Temperature

85

°C

125

4

LMX2571

www.ti.com.cn

ZHCSDH8 –MARCH 2015

6.4 Thermal Information

LMX2571

THERMAL METRIC⁽¹⁾

WQFN (NJK)

36 PINS

32.9

UNIT

R_θJA

Junction-to-ambient thermal resistance

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

14.5

6.3

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JB

6.3

R_θJC(bot)

2.0

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

3.15 V ≤ V_CC≤ 3.45 V, V_IO= V_CC, –40 °C ≤ T_A≤ 85 °C, except as specified. Typical values are at V_CC= V_IO= 3.3 V, V_CP= 3.3

V or 5 V in synthesizer mode, V_CP= 5 V in PLL mode, T_A= 25 °C.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

CURRENT CONSUMPTION

Configuration A⁽¹⁾

39

44

46

51

9

Configuration B⁽²⁾

Configuration C⁽³⁾

Configuration D⁽⁴⁾

Configuration E⁽⁵⁾

Configuration F⁽⁶⁾

Configuration G⁽⁷⁾

Total current in synthesizer mode (internal

VCO)

I_CC

f_OUT= 480 MHz

SE OSCin

mA

I_PLL

Total current in PLL mode (external VCO)

Power down current

15

21

CE = 0V or POWERDOWN bit = 1

V_CC= 3.3 V, Push-pull output

I_CCPD

0.9

OSCIN REFERENCE INPUT

f_OSCin

OSCin frequency range

OSCin input voltage⁽⁸⁾

Single-ended or differential input

Single-ended input

10

1.4

150

3.3

1.5

MHz

V

V_OSCin

Differential input

0.15

CRYSTAL REFERENCE INPUT

f_XTAL

C_IN

Crystal frequency range

OSCin input capacitance

Fundamental model, ESR < 200 Ω

10

40

MHz

pF

1

MULT

f_MULTin

f_MULTout

PLL

MULT input frequency

MULT output frequency

10

60

30

MHz

MULT > Pre-divider

Not supported with crystal reference input

130

f_PD

Phase detector frequency

Charge pump current⁽⁹⁾

130

MHz

Internal charge pump

312.5

625

Programmable minimum

value

5-V charge pump

Internal charge pump

5-V charge pump

Internal charge pump

5-V charge pump

312.5

625

K_PD

Per programmable step

µA

7187.5

6875

Programmable maximum

value

(1) f_OSCin= 19.44 MHz, MULT = 1, Prescaler = 4, f_PD= 19.44 MHz, one RF output, output type = push pull, output power = –3 dBm

(2) f_OSCin= 19.44 MHz, MULT = 1, Prescaler = 2, f_PD= 19.44 MHz, one RF output, output type = push pull, output power = –3 dBm

(3) f_OSCin= 19.44 MHz, MULT = 5, Prescaler = 2, f_PD= 19.44 MHz, one RF output, output type = push pull, output power = –3 dBm

(4) f_OSCin= 19.44 MHz, MULT = 5, Prescaler = 2, f_PD= 97.2 MHz, one RF output, output type = push pull, output power = –3 dBm

(5) f_OSCin= 19.44 MHz, MULT = 1, f_PD= 19.44 MHz, output from VCO

(6) f_OSCin= 19.44 MHz, MULT = 1, f_PD= 19.44 MHz, one RF output, output type = push pull, output power = –3 dBm

(7) f_OSCin= 19.44 MHz, MULT = 1, f_PD= 19.44 MHz, two RF outputs, output type = push pull, output power = –3 dBm

(8) See OSCin Configuration for definition of OSCin input voltage.

(9) This is referring to the total base charge pump current. In PLL mode, this is equal to EXTVCO_CP_IDN + EXTVCO_CP_IUP. In

synthesizer mode, this is equal to CP_IDN + CP_IUP. See Table 5, Table 6 and Table 7 for details.

5

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ZHCSDH8 –MARCH 2015

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Electrical Characteristics (continued)

3.15 V ≤ V_CC≤ 3.45 V, V_IO= V_CC, –40 °C ≤ T_A≤ 85 °C, except as specified. Typical values are at V_CC= V_IO= 3.3 V, V_CP= 3.3

V or 5 V in synthesizer mode, V_CP= 5 V in PLL mode, T_A= 25 °C.

PARAMETER

TEST CONDITIONS

MIN

TYP

–124

–120

–231

–226

MAX UNIT

Internal charge pump

PN_{PLL_1/f}

Normalized PLL 1/f noise⁽¹⁰⁾

dBc/Hz

5-V charge pump

Internal charge pump

5-V charge pump

At maximum charge pump

current

PN_{PLL_Flat}

f_RFin

Normalized PLL noise floor⁽¹⁰⁾

External VCO input frequency

External VCO input power

dBc/Hz

100

–10

–5

1400

MHz

dBm

f_RFin< 1 GHz

P_RFin

f_RFin≥ 1 GHz

VCO

f_VCO

VCO frequency

VCO gain⁽¹¹⁾

Allowable temperature drift⁽¹²⁾

4300

5376

125

MHz

MHz/V

°C

K_VCO

f_VCO= 4800 MHz

56

| ΔT_CL

|

VCO not being re-calibrated, –40 °C ≤ T_A≤ 85 °C

f_OSCin= f_PD= 100 MHz

100 Hz offset

t_VCOCal

VCO calibration time

140

–32.4

µs

1 kHz offset

–62.3

10 kHz offset

f_OUT= 480 MHz

–92.1

PN_VCO

Open loop VCO phase noise

dBc/Hz

100 kHz offset

–121.1

–144.5

–156.8

1 MHz offset

10 MHz offset

RF OUTPUT

Synthesizer mode

10

1344

1400

f_OUT

RF output frequency

MHz

PLL mode, RF output from buffer

P_TX, P_RX

H2_RFout

RF output power

Second harmonic

0

dBm

dBc

f_OUT= 480 MHz

Power control bit = 6

–25

DIGITAL FSK MODULATION

FSK_Level

FSK_Baud

FSK_Dev

FSK level⁽¹³⁾

FSK baud rate⁽¹⁴⁾

FSK PIN mode

2

8

Loop bandwidth = 200 kHz

Configuration H⁽¹⁵⁾

100

±39

kSPs

kHz

FSK deviation

DIGITAL INTERFACE

V_IH

V_IL

I_IH

High level input voltage

1.4

V_IO

0.4

25

V

Low level input voltage

High level input current

Low level input current

High level output voltage

Low level output voltage

V_IH= 1.75 V

V_IL= 0 V

–25

2

µA

V

I_IL

25

V_OH

V_OL

I_OH= 500 µA

I_OL= –500 µA

0

0.4

V

(10) Measured with a clean OSCin signal with a high slew rate using a wide loop bandwidth. The noise metrics model the PLL noise for an

infinite loop bandwidth as:

PLL_Total = 10 * log[10^{(PLL_Flat / 10)}+ 10^{(PLL_Flicker / 10)}

PLL_Flat = PN1Hz + 20 * log(N) + 10 * log(f_PD

]

)

PLL_Flicker = PN10kHz – 10 * log(Offset / 10 kHz) + 20 * log(f_OUT/ 1 GHz)

(11) The VCO gain changes as a function of the VCO core and frequency. See Integrated VCO for details.

(12) Not tested in production. Ensured by characterization. Allowable temperature drift refers to programming the device at an initial

temperature and allowing this temperature to drift WITHOUT reprogramming the device, and still have the device stay in lock. This

change could be up or down in temperature and the specification does not apply to temperatures that go outside the recommended

operating temperatures of the device.

(13) The data showed here simply specifies the range of discrete FSK level that is supported in PIN mode. PIN mode supports 2-, 4- and 8-

level of FSK modulation. If arbitrary level of FSK modulation is desired, use FSK SPI™ FAST mode or FSK I2S mode. See Direct Digital

FSK Modulation for details.

(14) The baud rate is limited by the loop bandwidth of the PLL loop. As a general rule of thumb, it is desirable to have the loop bandwidth at

least twice the baud rate.

(15) f_PD= 100 MHz, DEN = 2²⁴, CHDIV1 = 5, CHDIV2 = 2, Prescaler = 2, FSK step value = 32716, 32819. The maximum achievable

frequency deviation depends on the configuration, see Direct Digital FSK Modulation for details.

6

LMX2571

www.ti.com.cn

ZHCSDH8 –MARCH 2015

6.6 Timing Requirements

3.15 V ≤ V_CC≤ 3.45 V, V_IO= V_CC, –40 °C ≤ T_A≤ 85 °C, except as specified. Typical values are at V_CC= V_IO= 3.3 V, T_A= 25

°C.

MIN NOM

MAX UNIT

MICROWIRE TIMING

t_ES

Clock to enable low time

5

2

5

2

ns

t_CS

Data to clock setup time

Data to clock hold time

Clock pulse width high

Clock pulse width low

Enable to clock setup time

Enable pulse width high

t_CH

t_CWH

t_CWL

t_CES

t_EWH

See Figure 1

MSB

LSB

DATA

t_CS

t_CH

CLK

LE

t_CWL

t_CWH

t_ES

t_CES

t_EWH

Figure 1. MICROWIRE Timing Diagram

There are several other considerations for programming:

•

A slew rate of at least 30 V/µs is recommended for the CLK, DATA and LE. The same apply for other digital

control signals such as FSK_D[0:2] and FSK_DV signals.

•

The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the LE

signal, the data is sent from the shift register to an active register.

•

The LE pin may be held high after programming, causing the LMX2571 to ignore clock pulses.

When CLK or DATA lines are shared between devices, it is recommended to divide down the voltage to the

CLK, DATA, and LE pins closer to the minimum voltage. This provides better noise immunity.

•

If the CLK and DATA lines are toggled while the VCO is in lock, as is sometimes the case when these lines

are shared with other parts, the phase noise may be degraded during the time of this programming.

7

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ZHCSDH8 –MARCH 2015

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6.7 Typical Characteristics

At T_A= 25 °C, unless otherwise noted

OSCin = 19.44 MHz

f_OUT= 200 MHz

Synthesizer mode

OSCin = 19.44 MHz

f_OUT= 500 MHz

Synthesizer mode

Figure 2. Typical Close Loop Phase Noise

Figure 3. Typical Close Loop Phase Noise

OSCin = 19.44 MHz

f_OUT= 900 MHz

Synthesizer mode

OSCin = 19.44 MHz

f_OUT= 1200 MHz

Synthesizer mode

Figure 4. Typical Close Loop Phase Noise

Figure 5. Typical Close Loop Phase Noise

FSK_Baud= 4.8 kSPS

FSK PIN mode

Reference clock is a FM modulated signal with f_MOD= 2.4 kHz

Figure 6. 4FSK Direct Digital Modulation

Figure 7. FM Modulation via Reference Clock

8

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ZHCSDH8 –MARCH 2015

Typical Characteristics (continued)

At T_A= 25 °C, unless otherwise noted

Switching between int. and ext. VCO as well as Tx and Rx port

Freq. jump = 50 MHz

LBW = 4 kHz

PLL mode

Figure 8. Output Port and VCO Switching

Figure 9. FastLock with SPST Switch

Start: 100 MHz

Stop: 2000 MHz

Figure 10. Fin input impedance

Start: 10 MHz

Stop: 300 MHz

Figure 11. OSCin input impedance

-80

-90

Modeled flicker noise

Modeled flat noise

OSCin noise

Modeled flicker noise

Modeled flat noise

OSCin noise

Modeled total noise

Actual measurement

-90

-100

-110

-120

-130

-140

-150

-160

Model total noise

Actual measurement

-100

-110

-120

-130

-140

-150

-160

10²

10³

10⁴

10⁵

10⁶

10⁷

10³

10⁴

10⁵

10⁶

10⁷

Offset /Hz

f_PD= 122.88 MHz

Offset /Hz

f_PD= 61.44 MHz

f_OUT= 1228.8 MHz

Synthesizer mode

f_OUT= 430.08 MHz

PLL mode

Figure 12. Normalized PLL 1/f Noise and Noise Floor

Figure 13. Normalized PLL 1/f Noise and Noise Floor

9

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ZHCSDH8 –MARCH 2015

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7 Detailed Description

7.1 Overview

The LMX2571 is a frequency synthesizer with low-noise, high-performance integrated VCOs. The 5-GHz VCO

cores, together with the output channel dividers, can produce frequencies from 10 MHz to 1344 MHz. The

LMX2571 supports two operation modes, synthesizer mode and PLL mode. In synthesizer mode, the entire

device is utilized; in PLL mode the internal VCO is bypassed, and an external VCO is required to implement a

complete synthesizer.

The reference clock input supports a crystal used for the on-chip oscillator, AC-coupled differential clock signals,

and DC-coupled single-ended clock signals such as XO or CMOS clock devices.

The PLL is a fractional-N PLL with programmable Delta Sigma modulator (first order to fourth order). The

fractional denominator is of variable length and up to 24-bits long, providing a frequency step with very fine

resolution.

The internal VCO can be bypassed, allowing the use of an external VCO. A separate 5-V charge pump is

dedicated for the external VCO, eliminating the need for an op-amp to support 5-V VCOs. A new advanced

FastLock technique is developed to shorten the lock time to less than 1.5 ms, even there is a very narrow loop

bandwidth.

A unique programmable multiplier is incorporated in the R-divider. The multiplier is used to avoid and reduce

integer boundary spurs or to increase the phase detector frequency for higher performance.

The LMX2571 supports direct digital FSK modulation, thus allowing a change in the output frequency by

changing the N-divider value. The N-divider value can be programmed through MICROWIRE interface or through

pins. Discrete 2-, 4- and 8-level FSK, as well as arbitrary-level FSK, are supported. Arbitrary-level FSK can be

used to construct pulse-shaping FSK or analog-FM modulation.

The output has an integrated T/R switch, and the divided-down internal or external VCO signal can be output to

either the TX port or the RX port. The switch can also be configured as a 1:2 fanout buffer, providing the signal

on both outputs at the same time. In addition to port switching, the output frequency can be switched between

two pre-defined frequencies, F1 and F2, simultaneously. This feature is ideal for use in FDD duplex system

where the TX frequency is different from RX (LO) frequency.

The LMX2571 requires only a single 3.3-V power supply. Digital logic interface is 1.8-V input compatible. The

analog blocks power supplies use integrated LDOs, eliminating the need for high performance external LDOs.

Programming of the device is achieved through the MICROWIRE interface. The device can be powered down

through a register programming or toggling the Chip Enable (CE) pin.

7.2 Functional Block Diagram

Vcc3p3

VcpExt

CPout

VccIO

Power

supply

5V CP

supply

CP

MUX

Int. charge

pump

Output

divider

OP

MUX

RFoutTx

Phase

detector

R-divider

Prescaler

OSCin

N-divider

G4ꢀ

modulator

Fast

lock

5V charge

pump

VCO

MUX

Output

divider

Lock

dect

µWIRE

Enable

RFoutRx

SPI

FSK

FLout CPoutExt

Fin

MUXout CE

TrCtl

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7.3 Feature Description

7.3.1 Reference Oscillator Input

The OSCin and OSCin* pins are used as frequency reference inputs to the device. The OSCin pin can be driven

single-ended with a CMOS clock or a crystal oscillator. The on-chip crystal oscillator can also be used with an

external crystal as the reference clock. Differential clock input is also supported, making it easily to interface with

high performance system clock devices such as TI’s LMK series clock devices.

Because the OSCin or OSCin* signal is used as a clock for VCO calibration, a proper signal needs to be applied

at the OSCin and/or OSCin* pin at the time of programming the R0 register. A higher slew rate tends to yield the

best fractional spurs and phase noise, so a square wave signal is best for the OSCin and/or OSCin*pins. If using

a sine wave, higher frequencies tend to yield better phase noise and fractional spurs due to their higher slew

rates.

7.3.2 R-Dividers and Multiplier

The R-divider consists of a Pre-divider, a Multiplier (MULT), and a Post-divider.

Pre-

divider

Post-

divider

MULT

OSCin

Phase detector

Figure 14. R-Divider

Both the Pre- and Post-dividers divide frequency down while the MULT multiplies frequency up. The purpose of

adding a multiplier is to avoid and reduce integer boundary spurs or to increase the phase-detector frequency for

higher performance. See MULT Multiplier for details. The phase detector frequency, f_PD, is therefore equal to

f_PD= (f_OSCin/ Pre-divider) * (MULT / Post-divider)

(1)

When using the Multiplier (MULT > 1), there are some points to remember:

•

The Multiplier must be greater than the Pre-divider.

Crystal mode must be disabled (XTAL_EN=0).

Using the multiplier may add noise, especially for multiplier values greater than 6.

7.3.3 PLL Phase Detector and Charge Pump

The phase detector compares the outputs of the Post-divider and N-divider and generates a correction current

corresponding to the phase error. This charge pump current is programmable to different strengths.

7.3.4 PLL N-Divider and Fractional Circuitry

The total N-divider value is determined by N_integer+ NUM / DEN. The N-divider includes fractional compensation

and can achieve any fractional denominator (DEN) from 1 to 16,777,215 (2²⁴– 1). The integer portion, N_integer, is

the whole part of the N-divider value and the fractional portion, N_frac= NUM / DEN, is the remaining fraction.

N_integer, NUM and DEN are programmable.

The order of the delta sigma modulator is also programmable from integer mode to fourth order. There are

several dithering modes that are also programmable. Dithering is used to reduce fractional spurs. In order to

make the fractional spurs consistent, the modulator is reset any time that the R0 register is programmed.

7.3.5 Partially Integrated Loop Filter

The LMX2571 integrates the third and fourth pole of the loop filter. The values for the resistors can be

programmed independently through the MICROWIRE interface. The larger the values of the resistors, the

stronger the attenuation of the internal loop filter. This partially integrated loop filter can only be used in

synthesizer mode.

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Feature Description (continued)

CPout

Int. charge

pump

100pF

50pF

Figure 15. Integrated Loop Filter

7.3.6 Low-Noise, Fully Integrated VCO

The LMX2571 includes a fully integrated VCO. The VCO generates a frequency which varies with the tuning

voltage from the loop filter. Output of the VCO is fed to a prescaler before going to the N-divider. The prescaler

value is selectable between 2 and 4. In general, prescaler equals 2 will result in better phase noise especially

when the PLL is operated in fractional-N mode. If the prescaler equals 4, however, the device will consume less

current. The VCO frequency is related to the other frequencies and Prescaler as follows:

f_VCO= f_PD* N-divider * Prescaler

(2)

In order to reduce the VCO tuning gain, thus improving the VCO phase noise performance, the VCO frequency

range is divided into several different frequency bands. This creates the need for frequency calibration in order to

determine the correct frequency band given a desired output frequency. The VCO is also calibrated for amplitude

to optimize phase noise. These calibration routines are activated any time that the R0 register is programmed

with the FCAL_EN bit equals one. It is important that a valid OSCin signal must present before VCO calibration

begins.

This device will support a full sweep of the valid temperature range of 125°C (–40°C to 85°C) without having to

re-calibrate the VCO. This is important for continuous operation of the synthesizer under the most extreme

temperature variation.

7.3.7 External VCO Support

The LMX2571 supports an external VCO in PLL mode. In PLL mode, the internal VCO and its associated charge

pump are powered down, and a 5-V charge pump is switched in to support external VCO. No extra external low

noise op-amp is required to support 5-V tuning range VCO. The external VCO output can be obtained directly

from the VCO or from the device’s RF output buffer.

7.3.8 Programmable RF Output Divider

The internal VCO RF output divider consists of two sub-dividers; the total division value is equal to the

multiplication of them. As a result, the minimum division is 4 while the maximum division is 448.

Int.

VCO

Ext.

VCO

CHDIV1

4,5,6,7

CHDIV2

1,2,4,8,16,32,64

CHDIV3

1,2,3,Y,9,10

OP MUX

Figure 16. VCO Output Divider

There is only one output divider when external VCO is being used. This divider supports even and odd division,

and its values are programmable between 1 and 10.

7.3.9 Programmable RF Output Buffer

The RF output buffer type is selectable between push-pull and open drain. If open drain buffer is selected,

external pullup to VccIO is required. Regardless of output type, output power can be programmed to various

levels. The RF output buffer can be disabled while still keeping the PLL in lock. See RF Output Buffer Type for

details.

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Feature Description (continued)

7.3.10 Integrated TX, RX Switch

The LMX2571 integrates a T/R switch which is controlled by the TrCtl pin. The output from the internal VCO or

external VCO divider will be routed to either the RFoutTx or RFoutRx ports, depending on the state of the TrCtl

pin. The TrCtl pin not only controls the output port, but may also switch the output frequency simultaneously. For

example, if TrCtl = 1, the active port is RFoutTx with an output frequency of F1. When TrCtl changes from 1 to 0,

the active port could be RFoutRx with an output frequency of F2. LMX2571 has two sets of register to store the

configurations for F1 and F2.

The T/R switch could also be configured as a fanout buffer to output the same signal at both RFoutTx and

RFoutRx ports at the same time. All of these features are also programmable, see Programming and Frequency

and Output Port Switching with TrCtl Pin for details.

7.3.11 Powerdown

The LMX2571 can be powered up and down using the CE pin or the POWERDOWN bit. All registers are

preserved in memory while it is powered down. When the device comes out of the powered down state, either by

resuming the POWERDOWN bit to zero or by pulling back CE pin HIGH (if it was powered down by CE pin), it is

required that register R0 with FCAL_EN=1 be programmed again to re-calibrate the device.

7.3.12 Lock Detect

The MUXout pin of the LMX2571 can be configured to output a signal that indicates when the PLL is being

locked. If lock detect is enabled while the MUXout pin is configured as a lock-detect output, when the device is

locked the MUXout pin output is a logic HIGH voltage. When the device is unlocked, MUXout output is a logic

LOW voltage.

7.3.13 FSK Modulation

Direct digital FSK modulation is supported in LMX2571. FSK modulation is achieved by changing the output

frequency by changing the N-divider value. The LMX2571 supports four different types of FSK operation.

1. FSK PIN mode. LMX2571 supports 2-, 4- and 8-level FSK modulation in PIN mode. In this mode, symbols

are directly fed to the FSK_D0, FSK_D1, and FSK_D2 pins. Symbol clock is fed to the FSK_DV pin. Symbols

are latched into the device on the rising edge of the symbol clock. The maximum supported symbol clock

rate is 1 MHz. The device has eight dedicated registers to pre-store the desired FSK frequency deviations,

with each register corresponding to one of the FSK symbols. The LMX2571 will change its output frequency

according to the states on the FSK pins; no extra register programming is required.

2. FSK SPI mode. This mode is identical to the FSK PIN mode with the exception that the control for the

selected FSK level is not performed with external pins but with register R34. Each time when register R34 is

programmed, change only the FSK_DEV_SEL field to select the desired FSK frequency deviation as stored

in the dedicated registers.

3. FSK SPI FAST mode. In this mode, instead of selecting one of the pre-stored FSK level, change the FSK

deviation directly by writing to the register R33, FSK_DEV_SPI_FAST field. As a result, this mode supports

arbitrary-FSK level, which is useful to construct pulse-shaping or analog-FM modulation.

4. FSK I2S mode. This mode is similar to the FSK SPI FAST mode, but the programming format is an I2S

format on dedicated pins instead of SPI. The benefit of using I2S is that this interface could be shared and

synchronous to other digital audio interfaces. The same FSK data input pins that are used in FSK PIN mode

are re-used to support I2S programming. In this mode only the 16 bits of DATA field is required to program.

The data is transmitted on the high or low side of the frame sync (programmable in register R34,

FSK_I2S_FS_POL). The unused side of the frame sync needs to be at least one clock cycle. In other words,

17 (16 + 1) CLK cycles are required at a minimum for one I2S frame. Maximum I2S clock rate is 100 MHz.

I2S DATA

(FSK_D1)

MSB

Bit 15

LSB

Bit 0

FSK_D[0:2]

FSK_DV

I2S CLK

(FSK_DV)

I2S FS

(FSK_D0)

Figure 17. FSK PIN Mode Timing

Figure 18. FSK I2S Mode Timing

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Feature Description (continued)

See Direct Digital FSK Modulation for FSK operation details.

7.3.14 FastLock

The LMX2571 includes a FastLock feature that can be used to improve the lock times in PLL mode when the

loop bandwidth is small. In general, the lock time is approximately equal to 4 divided by the loop bandwidth. If the

loop bandwidth is 1 kHz, then the lock time would be 4 ms. However, if the f_PDis much higher than the loop

bandwidth, cycle slipping may occur, and the actual lock time will be much longer. Traditional fastlock usually

reduces lock time by increasing loop bandwidth during frequency switching. However, there is a limitation on the

achievable maximum loop bandwidth due to limitation on charge-pump current and loop filter component values.

In some cases, this kind of fastlock technique will make cycle slip even worse.

The LMX2571 adopts a new FastLock approach that eliminates the cycle slip problem. With an external analog

SPST switch in conjunction with LMX2571’s FastLock control, the lock time for a 100-MHz frequency switch

could be settled in less than 1.5 ms. See FastLock with External VCO for details.

7.3.15 Register Readback

The LMX2571 allows any of its registers to be read back. The MUXout pin can be programmed to support either

lock-detect output or register-readback serial-data output. To read back a certain register value, follow the

following steps:

1. Set the R/W bit to 1; the data field contents are ignored.

2. Send the register to the device; readback serial data will be output starting at the 9^thclock cycle.

R/W

= 1

Address

7-bit

Data

= Ignored

DATA

CLK

1^st

2^nd-8^th

9^th-24^th

Read back register value

16-bit

MUXout

LE

Figure 19. Register Readback Timing Diagram

7.4 Device Functional Modes

7.4.1 Operation Mode

The device can be operated in synthesizer mode or PLL mode.

1. Synthesizer mode. The internal VCO will be adopted.

2. PLL mode. The device is operated as a standalone PLL; an external VCO is required to complete the loop.

7.4.2 Duplex Mode

LMX2571 supports fast frequency switching between two pre-defined register sets, F1 and F2. This feature is

good for duplex operation. The device supports three duplex modes:

1. Synthesizer duplex mode. Both F1 and F2 are operated in synthesizer mode.

2. PLL duplex mode. Both F1 and F2 are operated in PLL mode.

3. Synthesizer/PLL duplex mode. In this mode, F1 and F2 will be operated in different operation mode.

7.4.3 FSK Mode

LMX2571 supports four direct digital FSK modulation modes.

1. FSK PIN mode. 2-, 4- and 8-level FSK modulation. Modulation data is fed to the device through dedicated

pins.

2. FSK SPI mode. 2-, 4- and 8-level FSK modulation. Pre-defined FSK deviation is selected through SPI

programming.

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Device Functional Modes (continued)

3. FSK SPI FAST mode. This mode supports arbitrary-level FSK modulation. Desired FSK deviation is written

to the device through SPI programming.

4. FSK I2S mode. Arbitrary-level FSK modulation is supported. Desired FSK deviation is fed to the device

through dedicated pins.

7.5 Programming

The LMX2571 is programmed using several 24-bit registers. A 24-bit shift register is used as a temporary register

to indirectly program the on-chip registers. The shift register consists of a data field, an address field, and a R/W

bit. The MSB is the R/W bit. 0 means register write while 1 means register read. The following 7 bits, ADDR[6:0],

form the address field which is used to decode the internal register address. The remaining 16 bits form the data

field DATA[15:0]. While LE is low, serial data is clocked into the shift register upon the rising edge of clock. Serial

data is shifted MSB first into the shift register when programming. When LE goes high, data is transferred from

the data field into the selected active register bank. See Figure 1 for timing diagram details.

7.5.1 Recommended Initial Power on Programming Sequence

When the device is first powered up, it needs to be initialized, and the ordering of this programming is important.

The sequence is listed below. After this sequence is completed, the device should be running and locked to the

proper frequency.

1. Apply power to the device and ensure the Vcc pins are at the proper levels.

2. If CE is LOW, pull it HIGH.

3. Wait 100 µs for the internal LDOs to become stable.

4. Ensure that a valid reference is applied to the OSCin pin.

5. Program register R0 with RESET=1. This will ensure all the registers are reset to their default values.

6. Program in sequence registers R60, R58, R53, …, R1 and then R0.

7.5.2 Recommended Sequence for Changing Frequencies

The recommended sequence for changing frequencies in different scenarios is as follows:

1. If the N-divider is changing, program the relevant registers, then program R0 with FCAL_EN = 1.

2. In FSK SPI mode, FSK SPI FAST mode, and FSK I2S mode, the fractional numerator is changing; program

the relevant registers only.

3. If switching frequency between F1 and F2, program the relevant control registers only or toggle the TrCtl pin.

See Frequency and Output Port Switching with TrCtl Pin for details.

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The POR value is the power-on reset value that is assigned when the device is powered up or the RESET bit is

asserted. POR is not a default working mode, all registers are required to program properly in order to make the

device works as desired.

7.6.1 R60 Register (offset = 3Ch) [reset = 4000h]

Figure 20. R60 Register

15

1

14

0

13

1

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W-4000h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 1. R60 Register Field Descriptions

Bit

Field

Type

Reset

Description

Program A000h to this field.

15-0

R/W

4000h

7.6.2 R58 Register (offset = 3Ah) [reset = C00h]

Figure 21. R58 Register

15

1

14

0

13

0

12

0

11

1

10

1

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

R/W-C00h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2. R58 Register Field Descriptions

Bit

Field

Type

Reset

Description

Program 8C00h to this field.

15-0

R/W

C00h

7.6.3 R53 Register (offset = 35h) [reset = 2802h]

Figure 22. R53 Register

15

0

14

1

13

1

12

1

11

1

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

1

0

R/W-2802h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 3. R53 Register Field Descriptions

Bit

Field

Type

Reset

Description

Program 7806h to this field.

15-0

R/W

2802h

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7.6.4 R47 Register (offset = 2Fh) [reset = 0h]

Figure 23. R47 Register

15

0

14

13

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

DITHERING

R/W-0h

R/W-

0h

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4. R47 Register Field Descriptions

Bit

Field

Type

Reset

Description

15

R/W

0h

Program 0h to this field.

14-13

DITHERING

R/W

0h

Set the level of dithering. This feature is used to mitigate spurs

level in certain use case by increasing the level of randomness

in the Delta Sigma modulator, typically done at the expense of

noise at certain offset.

0 = Disabled

1 = Weak

2 = Medium

3 = Strong

12-0

R/W

0h

Program 0h to this field.

7.6.5 R42 Register (offset = 2Ah) [reset = 210h]

Figure 24. R42 Register

15

0

14

0

13

0

12

0

11

0

10

0

9

1

8

0

7

0

6

0

5

4

3

2

1

0

EXTV

CO_C

P_PO

L

EXTVCO_CP_IDN

R/W-8h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

R/W-

0h

R/W-10h

Table 5. R42 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-6

R/W

8h

Program 8h to this field.

5

EXTVCO_CP_POL

R/W

0h

Sets the phase detector polarity for external VCO in PLL mode

operation. Positive means VCO frequency increases directly

proportional to Vtune voltage.

0 = Positive

1 = Negative

4-0

EXTVCO_CP_IDN

R/W

10h

Set the base charge pump current for external VCO in PLL

mode operation. The total base charge pump current is equal to

EXTVCO_CP_IDN

+

EXTVCO_CP_IUP. EXTVCO_CP_IDN

must be equal to EXTVCO_CP_IUP. Only even number values

are supported.

0 = Tri-state

2 = 312.5 µA

4 = 625 µA

...

30 = 3437.5 µA

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7.6.6 R41 Register (offset = 29h) [reset = 810h]

Figure 25. R41 Register

15

0

14

0

13

0

12

0

11

10

9

8

7

6

5

4

3

2

1

0

EXTVCO_CP_IUP

EXTVCO_CP_

GAIN

CP_IDN

R/W-0h

R/W-10h

R/W-0h

R/W-10h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6. R41 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-12

R/W

0h

Program 0h to this field.

11-7

EXTVCO_CP_IUP

R/W

10h

Set the base charge pump current for external VCO in PLL

mode operation. The total base charge pump current is equal to

EXTVCO_CP_IDN

+

EXTVCO_CP_IUP. EXTVCO_CP_IDN

must be equal to EXTVCO_CP_IUP. Only even number values

are supported.

0 = Tri-state

2 = 312.5 µA

4 = 625 µA

...

30 = 3437.5 µA

6-5

EXTVCO_CP_GAIN

R/W

0h

Set the multiplication factor to the base charge pump current for

external VCO in PLL mode operation. For example, if the gain

here is 2x and if the total base charge pump current

(EXTVCO_CP_IDN + EXTVCO_CP_IUP) is 2.5 mA, then the

final charge pump current applied to the loop filter is 5 mA. The

gain values are not precise. They are provided as a quick way to

boost the total charge pump current for debug purposes or

specific applications.

0 = 1x

1 = 2x

2 = 1.5x

3 = 2.5x

4-0

CP_IDN

R/W

10h

Set the base charge pump current for internal VCO in

synthesizer mode operation. The total base charge pump current

is equal to CP_IDN + CP_IUP. CP_IDN must be equal to

CP_IUP.

0 = Tri-state

1 = 156.25 µA

2 = 312.5 µA

3 = 468.75 µA

...

31 = 3593.75 µA

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7.6.7 R40 Register (offset = 28h) [reset = 101Ch]

Figure 26. R40 Register

15

0

14

0

13

0

12

11

10

9

8

7

6

5

0

4

1

3

1

2

1

0

CP_IUP

R/W-10h

CP_GAIN

R/W-0h

R/W-1Ch

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 7. R40 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-13

R/W

0h

Program 0h to this field.

12-8

CP_IUP

R/W

10h

Set the base charge pump current for internal VCO in

synthesizer mode operation. The total base charge pump current

is equal to CP_IDN + CP_IUP. CP_IDN must be equal to

CP_IUP.

0 = Tri-state

1 = 156.25 µA

2 = 312.5 µA

3 = 468.75 µA

...

31 = 3593.75 µA

7-6

CP_GAIN

R/W

0h

Set the multiplication factor to the base charge pump current for

internal VCO in synthesizer mode operation. For example, if the

gain here is 2x and if the total base charge pump current

(CP_IDN + CP_IUP) is 2.5 mA, then the final charge pump

current applied to the loop filter is 5 mA. The gain values are not

precise. They are provided as a quick way to boost the total

charge pump current for debug purposes or specific

applications.

0 = 1x

1 = 2x

2 = 1.5x

3 = 2.5x

5-0

R/W

1Ch

Program 1Ch to this field.

7.6.8 R39 Register (offset = 27h) [reset = 11F0h]

Figure 27. R39 Register

15

0

14

0

13

0

12

1

11

0

10

0

9

0

8

1

7

1

6

1

5

1

4

1

3

2

0

1

0

SDO_

LD_SE

L

LD_E

N

R/W-11Fh

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

R/W-

0h

R/W-0h

R/W-

0h

Table 8. R39 Register Field Descriptions

Bit

Field

Type

Reset

Description

Program 11Fh to this field.

15-4

R/W

11Fh

3

SDO_LD_SEL

R/W

0h

Defines the MUXout pin function.

0 = Register readback serial data output

1 = Lock detect output

2-1

Program 1h to this field.

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Table 8. R39 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

0

LD_EN

R/W

0h

Enables lock detect function.

0 = Disabled

1 = Enabled

7.6.9 R35 Register (offset = 23h) [reset = 647h]

Figure 28. R35 Register

15

0

14

0

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MULT_WAIT

OUTB OUTB OUTB

UF_A UF_TX UF_R

UTOM _TYPE X_TYP

UTE

E

R/W-0h

R/W-C8h

R/W-

1h

R/W-

1h

R/W-

1h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9. R35 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-14

R/W

0h

Program 0h to this field.

13-3

MULT_WAIT

R/W

C8h

A 20-µs settling time is required for MULT, if it is enabled. These

bits set the correct settling time according to the OSCin

frequency. For example, if OSCin frequency is 100 MHz, set

these bits to 2000. No matter if MULT is enabled or not, the

configured MULT settling time forms part of the total frequency

switching time.

0 = Do not use this setting

1 = 1 OSCin clock cycle

...

2047 = 2047 OSCin clock cycles

2

OUTBUF_AUTOMUTE

R/W

1h

If this bit is set, the output buffers will be muted until PLL is

locked. This bit applies to the following events: (a) device

initialization (b) manually change VCO frequency, and (c) F1F2

switching. However, if the PLL is unlocked afterward (for

example, OSCin is removed), the output buffers will not be

muted and will remain active.

0 = Disabled

1 = Enabled

1

0

OUTBUF_TX_TYPE

OUTBUF_RX_TYPE

R/W

1h

Sets the output buffer type of RFoutTx. If the buffer is open drain

output, a pullup to VccIO is required. See RF Output Buffer Type

for details.

0 = Open drain

1 = Push pull

Sets the output buffer type of RFoutRx. If the buffer is open

drain output, a pullup to VccIO is required. See RF Output Buffer

Type for details.

0 = Open drain

1 = Push pull

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7.6.10 R34 Register (offset = 22h) [reset = 1000h]

Figure 29. R34 Register

15

14

13

12

11

10

9

0

8

7

6

5

4

3

2

1

0

IPBUF IPBUF

DIFF_ _SE_D

TERM IFF_S

EL

XTAL_PWRCTRL

XTAL_

EN

FSK_I FSK_I

2S_FS 2S_CL

_POL K_PO

L

FSK_LEVEL

FSK_DEV_SEL

FSK_ FSK_

MODE MODE

_SEL0 _SEL1

R/W-

0h

R/W-

0h

R/W-2h

R/W-

0h

R/W-

0h

R/W-

0h

R/W-

0h

R/W-0h

R/W-

0h

R/W-

0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 10. R34 Register Field Descriptions

Bit

Field

Type

Reset

Description

15

IPBUFDIFF_TERM

R/W

0h

Enables independent 50 Ω input termination on both OSCin and

OSCin* pins. This function is valid even if OSCin input is

configured as single-ended input.

0 = Disabled

1 = Enabled

14

IPBUF_SE_DIFF_SEL

XTAL_PWRCTRL

R/W

0h

2h

Selects between single-ended and differential OSCin input.

0 = Single-ended input

1 = Differential input

13-11

Set the value of the series resistor being used to limit the power

dissipation through the crystal when crystal is being used as

OSCin input. See OSCin Configuration for details.

0 = 0 Ω

1 = 100 Ω

2 = 200 Ω

3 = 300 Ω

4-7 = Reserved

10

XTAL_EN

R/W

0h

Enables the crystal oscillator buffer for use as OSCin input. This

bit will overwrite IPBUF_SE_DIFF_SEL.

0 = Disabled

1 = Enabled

9

8

R/W

0h

Program 0h to this field.

FSK_I2S_FS_POL

FSK_I2S_CLK_POL

FSK_LEVEL

Sets the polarity of the I2S Frame Sync input in FSK I2S mode.

0 = Active HIGH

1 = Active LOW

7

R/W

0h

Sets the polarity of the I2S CLK input in FSK I2S mode.

0 = Rising edge strobe

1 = Falling edge strobe

6-5

Define the desired FSK level in FSK PIN mode and FSK SPI

mode. When this bit is zero, FSK operation in these modes is

disabled even if FSK_EN_Fx = 1.

0 = Disabled

1 = 2FSK

2 = 4FSK

3 = 8FSK

4-2

FSK_DEV_SEL

R/W

0h

In FSK SPI mode, these bits select one of the FSK deviations as

defined in registers R25-32 or R9-16.

0 = FSK_DEV0_Fx

1 = FSK_DEV1_Fx

...

7 = FSK_DEV7_Fx

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Table 10. R34 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

1

FSK_MODE_SEL0

R/W

0h

FSK_MODE_SEL0 and FSK_MODE_SEL1 define the FSK

operation mode. FSK_MODE_SEL[1:0] =

00 = FSK PIN mode

01 = FSK SPI mode

10 = FSK I2S mode

11 = FSK SPI FAST mode

0

FSK_MODE_SEL1

R/W

0h

Same as above.

7.6.11 R33 Register (offset = 21h) [reset = 0h]

Figure 30. R33 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

FSK_DEV_SPI_FAST

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 11. R33 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

FSK_DEV_SPI_FAST

R/W

0h

Define the desired frequency deviation in FSK SPI FAST mode.

See Direct Digital FSK Modulation for details.

7.6.12 R25 to R32 Register (offset = 19h to 20h) [reset = 0h]

Figure 31. R25 to R32 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

FSK_DEV0_F2 to FSK_DEV7_F2

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 12. R25 to R32 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

FSK_DEV0_F2 to FSK_DEV7_F2

R/W

0h

Define the desired frequency deviation in FSK PIN mode and

FSK SPI mode. See Direct Digital FSK Modulation for details.

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7.6.13 R24 Register (offset = 18h) [reset = 10h]

Figure 32. R24 Register

15

0

14

0

13

0

12

0

11

0

10

9

8

7

6

5

4

3

2

1

0

FSK_E

N_F2

EXTVCO_CHDIV_F2

EXTV

CO_S

EL_F2

OUTBUF_TX_PWR_F2

R/W-0h

R/W-

0h

R/W-0h

R/W-

0h

R/W-10h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 13. R24 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-11

R/W

0h

Program 0h to this field.

10

FSK_EN_F2

R/W

0h

Enables FSK operation in all FSK operation modes. When this

bit is set, fractional denominator DEN should be zero. See Direct

Digital FSK Modulation for details.

0 = Disabled

1 = Enabled

9-6

EXTVCO_CHDIV_F2

R/W

0h

Set the value of the output channel divider, CHDIV3, when using

external VCO in PLL mode.

0 = Divide by 1

1 = Reserved

2 = Divide by 2

3 = Divide by 3

...

10 = Divide by 10

11-15 = Reserved

5

EXTVCO_SEL_F2

R/W

0h

Selects synthesizer mode (internal VCO) or PLL mode (external

VCO) operation.

0 = Synthesizer mode

1 = PLL mode

4-0

OUTBUF_TX_PWR_F2

10h

Set the output power at RFoutTx port. See RF Output Buffer

Power Control for details.

25

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7.6.14 R23 Register (offset = 17h) [reset = 10A4h]

Figure 33. R23 Register

15

0

14

0

13

0

12

11

10

9

8

7

6

5

0

4

0

3

0

2

1

0

OUTBUF_RX_PWR_F2

OUTB OUTB

UF_TX UF_R

_EN_F X_EN_

LF_R4_F2

2

F2

R/W-0h

R/W-10h

R/W-

1h

R/W-

0h

R/W-4h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 14. R23 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-13

R/W

0h

Program 0h to this field.

12-8

OUTBUF_RX_PWR_F2

OUTBUF_TX_EN_F2

R/W

10h

Set the output power at RFoutRx port. See RF Output Buffer

Power Control for details.

7

R/W

1h

Enables RFoutTx port.

0 = Disabled

1 = Enabled

6

OUTBUF_RX_EN_F2

LF_R4_F2

R/W

0h

Enables RFoutRx port.

0 = Disabled

1 = Enabled

5-3

2-0

R/W

4h

Program 0h to this field.

Set the resistor value for the 4^thpole of the internal loop filter.

The shunt capacitor of that pole is 100 pF.

0 = Bypass

1 = 3.2 kΩ

2 = 1.6 kΩ

3 = 1.1 kΩ

4 = 800 Ω

5 = 640 Ω

6 = 533 Ω

7 = 457 Ω

7.6.15 R22 Register (offset = 16h) [reset = 8584h]

Figure 34. R22 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

LF_R3_F2

R/W-4h

CHDIV2_F2

R/W-1h

CHDIV1_F2

R/W-1h

PFD_DELAY_F2

R/W-4h

MULT_F2

R/W-4h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 15. R22 Register Descriptions

Bit

Field

Type

Reset

Description

Set the resistor value for the 3^rdpole of the internal loop filter.

15-13

LF_R3_F2

R/W

4h

The shunt capacitor of that pole is 50 pF.

0 = Bypass

1 = 3.2 kΩ

2 = 1.6 kΩ

3 = 1.1 kΩ

4 = 800 Ω

5 = 640 Ω

6 = 533 Ω

7 = 457 Ω

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Table 15. R22 Register Descriptions (continued)

Bit

Field

CHDIV2_F2

Type

Reset

Description

12-10

R/W

1h

Set the value of the output channel divider, CHDIV2, when using

internal VCO in synthesizer mode.

0 = Divide by 1

1 = Divide by 2

2 = Divide by 4

3 = Divide by 8

4 = Divide by 16

5 = Divide by 32

6 = Divide by 64

9-8

CHDIV1_F2

R/W

1h

Set the value of the output channel divider, CHDIV1, when using

internal VCO in synthesizer mode.

0 = Divide by 4

1 = Divide by 5

2 = Divide by 6

3 = Divide by 7

7-5

4-0

PFD_DELAY_F2

MULT_F2

R/W

4h

Used to optimize spurs and phase noise. Suggested values are:

Integer mode (NUM = 0): use PFD_DELAY ≤ 5

Fractional mode with N-divider < 22: use PFD_DELAY ≤ 4

Fractional mode with N-divider ≥ 22: use PFD_DELAY ≥ 3

Set the MULT multiplier value. MULT value must be greater than

Pre-divider value. MULT is not supported when crystal is being

used as the reference clock input. See MULT Multiplier for

details.

0 = Reserved

1 = Bypass

2 = 2x

...

13 = 13x

14-31 = Reserved

7.6.16 R21 Register (offset = 15h) [reset = 101h]

Figure 35. R21 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PLL_R_F2

R/W-1h

PLL_R_PRE_F2

R/W-1h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16. R21 Register Descriptions

Bit

Field

Type

Reset

Description

Set the OSCin buffer Post-divider value.

15-8

PLL_R_F2

R/W

1h

7-0

PLL_R_PRE_F2

R/W

1h

Set the OSCin buffer Pre-divider value. This value must be

smaller than MULT value.

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7.6.17 R20 Register (offset = 14h) [reset = 28h]

Figure 36. R20 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PLL_N

_PRE_

F2

FRAC_ORDER_F2

PLL_N_F2

R/W-

0h

R/W-0h

R/W-28h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17. R20 Register Descriptions

Bit

Field

Type

Reset

Description

15

PLL_N_PRE_F2

R/W

0h

Sets the Prescaler value.

0 = Divide by 2

1 = Divide by 4

14-12

FRAC_ORDER_F2

R/W

0h

Select the order of the Delta Sigma modulator.

0 = Integer mode

1 = 1^storder

2 = 2^ndorder

3 = 3^rdorder

4-7 = 4^thorder

11-0

PLL_N_F2

R/W

28h

Set the integer portion of the N-divider value. Maximum value is

1023.

7.6.18 R19 Register (offset = 13h) [reset = 0h]

Figure 37. R19 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PLL_DEN_F2[15:0]

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 18. R19 Register Field Descriptions

Bit

Field

Type

Reset

Description

Set the LSB bits of the fractional denominator of the N-divider.

15-0

PLL_DEN_F2[15:0]

R/W

0h

7.6.19 R18 Register (offset = 12h) [reset = 0h]

Figure 38. R18 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PLL_NUM_F2[15:0]

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 19. R18 Register Field Descriptions

Bit

Field

Type

Reset

Description

Set the LSB bits of the fractional numerator of the N-divider.

15-0

PLL_NUM_F2[15:0]

R/W

0h

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7.6.20 R17 Register (offset = 11h) [reset = 0h]

Figure 39. R17 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PLL_DEN_F2[23:16]

R/W-0h

PLL_NUM_F2[23:16]

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 20. R17 Register Descriptions

Bit

Field

Type

Reset

Description

15-8

PLL_DEN_F2[23:16]

R/W

0h

Set the MSB bits of the fractional denominator of the N-divider.

Set the MSB bits of the fractional numerator of the N-divider.

7-0

PLL_NUM_F2[23:16]

R/W

0h

7.6.21 R9 to R16 Register (offset = 9h to 10h) [reset = 0h]

Figure 40. R9 to R16 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

FSK_DEV0_F1 to FSK_DEV7_F1

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21. R9 to R16 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

FSK_DEV0_F1 to FSK_DEV7_F1

R/W

0h

See Table 12.

7.6.22 R8 Register (offset = 8h) [reset = 10h]

Figure 41. R8 Register

15

0

14

0

13

0

12

0

11

0

10

9

8

7

6

5

4

3

2

1

0

FSK_E

N_F1

EXTVCO_CHDIV_F1

EXTV

CO_S

EL_F1

OUTBUF_TX_PWR_F1

R/W-0h

R/W-

0h

R/W-0h

R/W-

0h

R/W-10h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 22. R8 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-11

R/W

0h

Program 0h to this field.

See Table 13.

10

9-6

5

FSK_EN_F1

R/W

0h

EXTVCO_CHDIV_F1

EXTVCO_SEL_F1

OUTBUF_TX_PWR_F1

0h

4-0

10h

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7.6.23 R7 Register (offset = 7h) [reset = 10A4h]

Figure 42. R7 Register

15

0

14

0

13

0

12

11

10

9

8

7

6

5

0

4

0

3

0

2

1

0

OUTBUF_RX_PWR_F1

OUTB OUTB

UF_TX UF_R

_EN_F X_EN_

LF_R4_F1

1

F1

R/W-0h

R/W-10h

R/W-

1h

R/W-

0h

R/W-4h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23. R7 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-13

R/W

0h

Program 0h to this field.

See Table 14.

12-8

7

OUTBUF_RX_PWR_F1

OUTBUF_TX_EN_F1

OUTBUF_RX_EN_F1

R/W

10h

1h

0h

4h

See Table 14.

6

See Table 14.

5-3

2-0

Program 0h to this field.

See Table 14.

LF_R4_F1

7.6.24 R6 Register (offset = 6h) [reset = 8584h]

Figure 43. R6 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

LF_R3_F1

R/W-4h

CHDIV2_F1

R/W-1h

CHDIV1_F1

R/W-1h

PFD_DELAY_F1

R/W-4h

MULT_F1

R/W-4h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 24. R6 Register Descriptions

Bit

Field

Type

Reset

Description

15-13

LF_R3_F1

R/W

4h

See Table 15.

12-10

9-8

CHDIV2_F1

CHDIV1_F1

PFD_DELAY_F1

MULT_F1

R/W

1h

4h

7-5

4-0

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7.6.25 R5 Register (offset = 5h) [reset = 101h]

Figure 44. R5 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PLL_R_F1

R/W-1h

PLL_R_PRE_F1

R/W-1h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 25. R5 Register Descriptions

Bit

Field

Type

Reset

Description

See Table 16.

15-8

PLL_R_F1

R/W

1h

7-0

PLL_R_PRE_F1

R/W

1h

7.6.26 R4 Register (offset = 4h) [reset = 28h]

Figure 45. R4 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PLL_N

_PRE_

F1

FRAC_ORDER_F1

PLL_N_F1

R/W-

0h

R/W-0h

R/W-28h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 26. R4 Register Descriptions

Bit

Field

Type

Reset

Description

15

PLL_N_PRE_F1

R/W

0h

See Table 17.

14-12

11-0

FRAC_ORDER_F1

PLL_N_F1

R/W

0h

28h

7.6.27 R3 Register (offset = 3h) [reset = 0h]

Figure 46. R3 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PLL_DEN_F1[15:0]

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 27. R3 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

PLL_DEN_F1[15:0]

R/W

0h

See Table 18.

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7.6.28 R2 Register (offset = 2h) [reset = 0h]

Figure 47. R2 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PLL_NUM_F1[15:0]

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 28. R2 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

PLL_NUM_F1[15:0]

R/W

0h

See Table 19.

7.6.29 R1 Register (offset = 1h) [reset = 0h]

Figure 48. R1 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PLL_DEN_F1[23:16]

R/W-0h

PLL_NUM_F1[23:16]

R/W-0h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 29. R1 Register Descriptions

Bit

Field

Type

Reset

Description

See Table 20.

15-8

PLL_DEN_F1[23:16]

R/W

0h

7-0

PLL_NUM_F1[23:16]

R/W

0h

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7.6.30 R0 Register (offset = 0h) [reset = 3h]

Figure 49. R0 Register

15

0

14

0

13

12

11

10

9

8

7

6

5

0

4

0

3

0

2

0

1

0

RESE POWE RXTX RXTX F1F2_I F1F2_ F1F2_ F1F2_

T

FCAL_

EN

RDOW _CTRL _POL

N

NIT

CTRL MODE SEL

R/W-0h

R/W-

0h

R/W-

0h

R/W-

0h

R/W-

0h

R/W-

0h

R/W-

0h

R/W-

0h

R/W-

0h

R/W-1h

R/W-

1h

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 30. R0 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-14

R/W

0h

Program 0h to this field.

13

12

RESET

R/W

0h

Resets all the registers to the default values. This bit is self-clearing.

0 = Normal operation

1 = Reset

POWERDOWN

Powers down the device. When the device comes out of the powered down state,

either by resuming this bit to zero or by pulling back CE pin HIGH (if it was

powered down by CE pin), it is required that register R0 with FCAL_EN = 1 be

programmed again to re-calibrate the device. A 100-µs wait-time is recommended

before programming R0.

0 = Normal operation

1 = Power down

11

10

9

RXTX_CTRL

RXTX_POL

F1F2_INIT

R/W

0h

Sets the control mode of TX/RX switching.

0 = Switching is controlled by register programming

1 = Switching is controlled by toggling the TrCtl pin

Defines the polarity of the TrCtl pin.

0 = Active LOW = TX

1 = Active HIGH = TX

Toggling this bit re-calibrates F1F2 if F1, F2 are modified after calibration. This bit

is not self-clear, so it is required to clear the bit value after use. See Register R0

F1F2_INIT, F1F2_MODE usage for details.

0 = Clear bit value

1 = Re-calibrate

8

7

F1F2_CTRL

F1F2_MODE

R/W

0h

Sets the control mode of F1/F2 switching. Switching by TrCtl pin requires

F1F2_MODE = 1.

0 = Switching is controlled by register programming

1 = Switching is controlled by toggling the TrCtl pin

Calibrates F1 and F2 during device initialization (initial power on programming). It

also enables F1-F2 switching with the TrCtl pin. Even if this bit is not set, F1-F2

switching is still possible but the first switching time will not be optimized because

either F1 or F2 will only be calibrated. If F1-F2 switching is not required, set this bit

to zero. See Register R0 F1F2_INIT, F1F2_MODE usage for details.

0 = Disable F1F2 calibration

1 = Enable F1F2 calibration

6

F1F2_SEL

FCAL_EN

R/W

0h

Selects F1 or F2 configuration registers.

0 = F1 registers

1 = F2 registers

5-1

0

R/W

1h

Program 1h to this field.

Activates all kinds of calibrations, suggest keep it enabled all the time. If it is

desired that the R0 register be programmed without activating this calibration, then

this bit can be set to zero.

0 = Disabled

1 = Enabled

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Direct Digital FSK Modulation

In fractional mode, the finest delta frequency difference between two programmable output frequencies is equal

to

f₁– f₂= Δf_min= f_PD* {[(N + 1) / DEN] – (N / DEN)} = f_PD/ DEN

(3)

In other words, when the fractional numerator is incremented by 1 (one step), the output frequency will change

by Δf_min. A two steps increment will therefore change the frequency by 2 * Δf_min

.

In FSK operation, the instantaneous carrier frequency is kept changing among some pre-defined frequencies. In

general, the instantaneous carrier frequency is defined as a certain frequency deviation from the nominal carrier

frequency. The frequency deviation could be positive and negative.

Nominal

carrier

frequency

4FSK symbol: 11 10 00

01

Instantaneous

carrier

frequency

Frequency

Negative

swing

Positive

swing

f_DEV0

f_DEV

1

Figure 50. General FSK Definition

Figure 51. Typical 4FSK Definition

The following equations define the number of steps required for the desired frequency deviation with respect to

the nominal carrier frequency output at the RFoutTx or RFoutRx port.

Table 31. FSK Step Equations

POLARITY

SYNTHESIZER MODE

PLL MODE

f_DEV* DEN CHDIV1 * CHDIV2

*

f_DEV* DEN

POSITIVE SWING

Round

CHDIV3

*

f_PD

Prescaler

f_PD

(4)

(5)

(7)

NEGATIVE SWING

2's complement of Equation 4

(6) 2's complement of Equation 5

In FSK PIN mode and FSK SPI mdoe, register R25-32 and R9-16 are used to store the desired FSK frequency

deviations in term of the number of step as defined in the above equations. The order of the registers, 0 to 7,

depends on the application system. A typical 4FSK definition is shown in Figure 51. In this case, FSK_DEV0_Fx

and FSK_DEV1_Fx shall be calculated using Equation 4 or Equation 5 while FSK_DEV2_Fx and FSK_DEV3_Fx

shall be calculated using Equation 6 or Equation 7.

For example, if FSK PIN mode is enabled in F1 to support 4FSK modulation, set

FSK_MODE_SEL1 = 0

FSK_MODE_SEL0 = 0

FSK_LEVEL = 2

FSK_EN_F1 = 1

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Table 32. FSK PIN Mode Example

RAW FSK DATA STREAM INPUT

EQUIVALENT SYMBOL INPUT

REGISTER SELECTED

RF OUTPUT

10

11

10

11

01

00

...

FSK_DEV2_F1

FSK_DEV3_F1

FSK_DEV2_F1

FSK_DEV3_F1

FSK_DEV1_F1

FSK_DEV0_F1

...

Freq.

FSK_D0

FSK_D1

FSK_DV

Time

FSK SPI mode assumes the user knows which symbol to send; user can directly write to register R34,

FSK_DEV_SEL to select the desired frequency deviation.

For example, to enable the device to support 4FSK modulation at F1 using FSK SPI mode, set

FSK_MODE_SEL1 = 0

FSK_MODE_SEL0 = 1

FSK_LEVEL = 2

FSK_EN_F1 = 1

Table 33. FSK SPI Mode Example

DESIRED SYMBOL

WRITE REGISTER FSK_DEV_SEL

REGISTER SELECTED

FSK_DEV2_F1

FSK_DEV3_F1

FSK_DEV2_F1

FSK_DEV3_F1

FSK_DEV1_F1

FSK_DEV0_F1

…

10

11

10

11

01

00

...

2

3

2

3

1

0

...

Both the FSK PIN mode and FSK SPI mode support up to 8 levels of FSK. To support an arbitrary-level FSK,

use FSK SPI FAST mode or FSK I2S mode. Constructing pulse-shaping FSK modulation by over-sampling the

FSK modulation waveform is one of the use cases of these modes.

Analog-FM modulation can also be produced in these modes. For example, with a 1-kHz sine wave modulation

signal with peak frequency deviation of ±2 kHz, the signal can be over-sampled, say 10 times. Each sample point

corresponding to a scaled frequency deviation.

Freq. dev.

+2kHz

t₅t₆t₇t₈t₉

Time

t₀t₁t₂t₃t₄

-2kHz

Figure 52. Over-Sampling Modulation Signal

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In FSK SPI FAST mode, write the desired FSK steps directly to register R33, FSK_DEV_SPI_FAST. To enable

this mode, set

FSK_MODE_SEL1 = 1

FSK_MODE_SEL0 = 1

FSK_EN_F1 = 1

Table 34. FSK SPI FAST Mode Example

TIME

FREQUENCY

DEVIATION

CORRESPONDING FSK

STEPS⁽¹⁾

BINARY EQUIVALENT

WRITE TO

FSK_DEV_SPI_FAST

t₀

t₁

618.034 Hz

1618.034 Hz

2000 Hz

…

518

1357

1678

…

0000 0010 0000 0110

0000 0101 0100 1101

0000 0110 1000 1110

…

518

1357

1678

…

t₂

…

t₆

–1618.034 Hz

–2000 Hz

…

64178

63857

…

1111 1010 1011 0010

1111 1001 0111 0001

…

64178

63857

…

t₇

…

(1) Synthesizer mode, f_VCO= 4800 MHz, f_OUT= 480 MHz, f_PD= 100 MHz, Prescaler = 2, DEN = 2²⁴, Use Equation 4 and Equation 6 to

calculate the step value.

In FSK I2S mode, clock in the desired binary format FSK steps in the FSK_D1 pin.

FSK_D1

FSK_DV

FSK_D0

t₀

t₁

Figure 53. FSK I2S Mode Example

To enable FSK I2S mode, set

FSK_MODE_SEL1 = 1

FSK_MODE_SEL0 = 0

FSK_EN_F1 =1

8.1.2 Frequency and Output Port Switching with TrCtl Pin

Register R0, RXTX_CTRL, and RXTX_POL are used to define the output port switching behavior with the TrCtl

pin. To enable switching with TrCtl pin, set RXTX_CTRL=1.

Table 35. TrCtl Pin Usage

RXTX_CTRL

RXTX_POL

TrCtl PIN

RFoutTx

RFoutRx

1

0

1

0

1

0

1

Active

Register R0, F1F2_CTRL, and F1F2_SEL define the operation of the frequency switching between the two pre-

defined frequencies F1 and F2. To switch frequency using the TrCtl pin, set F1F2_CTRL to 1. F1F2_SEL selects

the output frequency for the current status. For example, if the current active output frequency is F1, toggling

TrCtl pin will change the output frequency to F2. Toggling TrCtl pin again will change the output frequency back

to F1.

8.1.3 OSCin Configuration

OSCin supports single-end clock, differential clock as well as crystal. Register R34 defines OSCin configuration.

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Table 36. OSCin Configuration

SINGLE-ENDED CLOCK

DIFFERENTIAL CLOCK

CRYSTAL

Connection

Diagram

V_T

C₁

0.1µF

V_T

R_d

OSCin

OSCin*

50Qꢀ

OSCin*

50Qꢀ

C₂

Register Setting

IPBUF_SE_DIFF_SEL = 0

IPBUF_SE_DIFF_SEL = 1

IPBUFDIFF_TERM = 1

XTAL_EN = 1

XTAL_PWRCTRL = Crystal dependent

Single-ended and differential input clock definitions are as follows:

V_OSCin

CMOS

Sine wave

Figure 54. Input Clock Definition

Differential

The integrated crystal-oscillator circuit supports a fundamental mode, AT-cute crystal. The load capacitance, C_L,

is specific to the crystal, but usually on the order of 18 to 20 pF. While C_Lis specified for crystal, the OSCin input

capacitance, C_IN(1 pF typical), of the device and PCB stray capacitance, C_STRAY(approximately 1 to 3 pF), can

affect the discrete load capacitor values, C₁and C₂.

For the parallel resonant circuit, the discrete capacitor values can be calculated as follows:

C_L= (C₁* C₂) / (C₁+ C₂) + C_IN+ C_STRAY

(8)

(9)

Typically, C₁= C₂for optimum symmetry, so Equation 8 can be rewritten in terms of C₁only:

C_L= C₁²/ (2 * C₁) + C_IN+ C_STRAY

Finally, solve for C₁:

C₁= 2 * (C_L– C_IN– C_STRAY

)

(10)

Electrical Characteristics provide crystal interface specifications with conditions that ensure start-up of the crystal,

but it does not specify crystal power dissipation. The designer will need to ensure the crystal power dissipation

does not exceed the maximum drive level specified by the crystal manufacturer. Over-driving the crystal can

cause premature aging, frequency shift, and eventual failure. Drive level should be held at a sufficient level

necessary to start-up and maintain steady-state operation. The power dissipated in the crystal, P_XTAL, can be

computed by:

P_XTAL= I_RMS²* R_ESR* (1 + C_o/ C_L)²

where

•

I_RMSis the rms current through the crystal

R_ESRis the maximum equivalent series resistance specified for the crystal

C_Lis the load capacitance specified for the crystal

C_ois the minimum shunt capacitance specified for the crystal

I_RMScan be measured using a current probe (for example, Tektronix CT-6 or equivalent) placed on the leg of

the crystal connected to OSCin pin with the oscillation circuit active.

(11)

The internal configurable resistor, R_d, can be used to limit the crystal drive level, if necessary. If the power

dissipated in the selected crystal is higher than the drive level specified for the crystal with R_dshorted, then a

larger resistor value is mandatory to avoid over-driving the crystal. However, if the power dissipated in the crystal

is less than the drive level with R_dshorted, then a zero value for R_dcan be used. As a starting point, a suggested

value for R_dis 200 Ω.

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8.1.4 Register R0 F1F2_INIT, F1F2_MODE usage

These register bits are used to define the calibration behavior. Correct setting is important to ensure that every

F1-F2 switching time is optimized. Figure 55 illustrates the usage of these register bits.

Freq

F2'

F2

FCAL_EN=1

Change F1, F2

F1F2_INIT=1

F1F2_MODE=1

F1F2_INIT=0

F1

F1'

Time

t₀

t₁

t₂

t₃

t₄

t₅

t₆t₇

t₈t₉

t₁₀

t₁₁

Figure 55. F1F2_INIT, F1F2_MODE Usage

Before t₀: Device initialization

•

Power up the device.

Write all registers to the device.

–

Ensure FCAL_EN = 1 to enable calibration.

Set F1F2_MODE = 1 to make both F1 and F2 being calibrated during initialization. If F1F2_MODE = 0,

only the output frequency (F1 in this example) will be calibrated, F2 will not be calibrated. Furthermore, if

F1F2 switching is triggered by the TrCtl pin, F1F2_MODE must be equal to 1.

–

Set F1F2_INIT = 0. Although the setting of this bit is irrelevant and not important here but if F1F2_INIT =

1, change it back to zero before attempting to change the frequency from F1 to F2.

At t₀: Locked to F1

After initialization, both F1 and F2 are calibrated. The calibration data is stored in the internal memory.

At t₁: Switch to F2.

Since FCAL_EN = 1, calibration will start over again when the output is switching from F1 to F2. F2 calibration

begins based on the last calibration data, which is the calibration data obtained at t₀. If the environment (for

example, temperature) does not change much, the new calibration data will be similar to the old data. As a result,

the calibration time is minimal and therefore, the switching time will be short.

At t₂: Switch back to F1

Again, F1 calibration starts over and begins with the last calibration data as obtained at t₀. Calibration time is

again very short, as is the switching time.

At t₃: Switch again to F2

This time, the calibration begins with the calibration data obtained at t₁, which is the last calibration data.

At t₄: Switch back to F1

Calibration begins with the calibration data obtained at t₂, which is the last calibration data.

At t₅: Set new F1, F2 frequency

•

Write to the relevant registers to set the new F1 and F2 frequency (for example, change the N-divider values)

Initiate calibration by re-writing register R0

–

Set F1F2_INIT=1. Both F1' and F2' will be calibrated

At t₆: Locked to F1'

F1' and F2' calibration completed and their calibration data are ready.

At t₇: Release F1F2_INIT bit

This bit has to be reset to zero or otherwise both F1' and F2' will be calibrated every time they are toggling.

At t₈: F1' calibration data is updated

Since F1F2_INIT is located in register R0, when writing F1F2_INIT = 0 to the device, calibration is once again

triggered. However, only F1' will be re-calibrated, the calibration data of F2' remains unchanged.

At t₉: Switch to F2'

F2' calibration begins with the calibration data obtained at t₆, which is the last calibration data. Calibration time is

again very short, as is the switching time.

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At t₁₀: Switch back to F1'

F1' calibration starts over and begins with the last calibration data as obtained at t₈.

At t₁₁: Switch again to F2'

The calibration begins with the calibration data obtained at t₉, which is the last calibration data.

As illustrated above, register F1F2_INIT must be used properly in order to ensure that every F1-F2 switching

time is optimized.

8.1.5 FastLock with External VCO

Fastlock may be required in PLL mode where an external VCO with a narrow loop bandwidth is desired. The

LMX2571 adopts a new FastLock approach to support the very fast switching time requirement in PLL mode.

There are two control pins in the chip, FLout1 and FLout2. Each pin is used to control a SPST analog switch, S1

and S2. The loop filter value with or without FastLock is the same, except that with FastLock, one more C2 and

two SPST switches are needed.

Ordinary 2^nd

order loop filter

With FastLock

control switches

R2

C2

R2

C2a=C2b=C2

S1 S2

C2b

C2a

Figure 56. FastLock with SPST Switches

When LMX2571 is locked to F1, FLout1 will close the switch S1. When LMX2571 is locked to F2, either by

toggling the TrCtl pin or program register R0, F1F2_SEL, S1 will be released while S2 will be closed by FLout2.

Although S1 is released, the charge stored in C2a remains unchanged. Thus, when the output is switched back

to F1, the Vtune voltage is almost correct, no (or little) charging or discharging to C2a is required which speeds

up the switching time. For example, if Vtune for F1 and F2 are 1 V and 2 V, respectively, without FastLock, when

the switching frequency shifts from F1 to F2, C2 will have to be re-charged from 1 V to 2 V — this is a big

voltage jump. With FastLock, when S2 is closed, Vtune is almost equal to 2 V because C2b maintains the

charge. Only a tiny voltage jump (re-charge) is required to make it reach the final Vtune voltage.

Figure 57 and Figure 58 compare the frequency switching time using different switching methods. In both cases,

the loop bandwidth is 4 kHz while f_PDis 28 MHz. Figure 57 shows the switching time for a frequency jump from

430 MHz to 480 MHz with SPST switches. Frequency switching is toggled by the TrCtl pin. Switching time is

approximately 1 ms. Frequency switching in Figure 58 is done in the traditional way. That is, change the output

frequency by writing to the relevant registers such as N-divider values. In this case, because f_PDis very much

bigger than the loop bandwidth, cycle slipping jeopardizes the switching time to more than 20 ms.

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Figure 57. F1F2 Switching With SPST Switches

Figure 58. Change F1 Frequency Via SPI Programming

8.1.6 OSCin Slew Rate

A phase-lock loop consists of a clean reference clock, a PLL, and a VCO. Each of these contributes to the total

phase noise. The LMX2571 is a high-performance PLL with integrated VCO. Both PLL noise and VCO noise are

very good. Typical PLL 1/f noise and noise floor are –124 dBc/Hz and –231 dBc/Hz, respectively. To get the best

possible phase-noise performance from the device the quality of the reference clock is very important because it

may add noise to the loop. First of all, the phase noise of the reference clock must be good so that the final

performance of the system is not degraded. Furthermore, using reference clock with a rather high slew rate (such

as a square wave) is highly preferred. Driving the device input with a lower slew rate clock will degrade the

device phase noise.

For a given frequency, a sine wave clock has the slowest slew rate, especially when the frequency is low. A

CMOS clock or differential clock have much faster slew rates and are recommended. Figure 59 shows a phase-

noise comparison with different types of reference clocks. Output frequency is 480 MHz while the input clock

frequency is 26 MHz. As one can see there is a 5-dB difference in phase noise when using a clipped sine wave

TCXO compared to a differential LVPECL clock. The internal crystal oscillator of the LMX2571 performance is

also very good. If temperature compensation is not required, use crystal as the reference clock is a very good

price-performance option.

-80

Crystal

TCXO

LVPECL

-90

-100

-110

-120

-130

-140

-150

-160

10³

10⁴

10⁵

10⁶

10⁷

Offset /Hz

Figure 59. Phase Noise vs Input Clock

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8.1.7 RF Output Buffer Power Control

Registers OUTBUF_TX_PWR_Fx and OUTBUF_RX_PWR_Fx are used to set the output power at the RFoutTx

and RFoutRx ports. Figure 60 shows a typical output power vs power control bit plot in synthesizer mode. VCO

frequency was 4800 MHz, and channel dividers were set to produce the shown output frequencies.

6

60

58

56

54

52

50

48

46

44

fout=1200MHz

fout=480MHz

fout=150MHz

3

Current, fout=480MHz

0

-3

-6

-9

-12

-15

-18

0

3

6

9

12

15

18

21

24

27

30

33

Power control bit

Figure 60. Configurable RF Output Power

8.1.8 RF Output Buffer Type

Registers R35, OUTBUF_TX_TYPE, OUTBUF_RX_TYPE are used to configure the RF output buffer type

between open drain and push-pull. Push-pull is easy to use; all that is required is a DC-blocking capacitor at the

output. The output waveform is square wave and therefore, harmonics rich. Open-drain output provides an option

to reduce the harmonics using an LC resonant pullup network at its output. Table 37 summarizes an example an

open-drain vs push-pull application.

Table 37. RF Output Buffer Type

BUFFER TYPE

OPEN DRAIN

PUSH-PULL

VccIO

Connection

Diagram

39nH

100pF

2.7pF

RFoutTx

100pF

Output Power

470 MHz

480 MHz

2.8 dBm

490 MHz

2.8 dBm

470 MHz

–0.1 dBm

–30.4 dBc

–11.9 dBc

–28.5 dBc

–15.6 dBc

–29.5 dBc

480 MHz

0 dBm

490 MHz

0.1 dBm

f_o

2.7 dBm

–31 dBc

2f_o

3f_o

4f_o

5f_o

6f_o

–30.7 dBc

–17.9 dBc

–40.4 dBc

–17.8 dBc

–27.2 dBc

–30.5 dBc

–18.1 dBc

–41.6 dBc

–17.6 dBc

–28.5 dBc

–30.2 dBc

–12.1 dBc

–28.4 dBc

–15.6 dBc

–29.8 dBc

–30 dBc

–17.3 dBc

–39 dBc

–12.4 dBc

–28.1 dBc

–15.7 dBc

–29.3 dBc

–18.1 dBc

–27.6 dBc

Clearly, with a proper LC pull up in open drain architecture, the 3^rdto 5^thharmonics could be reduced.

8.1.9 MULT Multiplier

The main purpose of the multiplier, MULT, in the R–divider is to push the in-band fractional spurs far away from

the carrier such that the spurs could be filtered out by the loop filter. In a fractional engine, the fractional spurs

appear at a multiple of f_PD* N_frac. In cases where both f_PDand N_fracare small, the fractional spurs will appear

very close to the carrier. These kinds of spurs are called in-band spurs.

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Table 38. MULT Application Example

USE CASE

OSCin

PRE-DIVIDER

MULT

POST-DIVIDER

f_PD/MHz

VCO

/MHz

N_integer

N_frac

SPURS

/MHz

19.2

I

1

5

1

4

19.2

24

460.8

461

24

19

0

II

0.0104167

0.2083333

0.2

5

III

461

In Case I, the VCO frequency is an integer multiple of the f_PD, so N_fracis zero and there are no spurs. However,

in Case II, the spur appears at an offset of 200 kHz. If this spur cannot be reduced by other typical spur-

reduction techniques such as dithering, user can enable the MULT to overcome this problem. If the MULT is

enabled as depicted in Case III, the spurs can be pushed to an offset of 5 MHz. In this case, the MULT together

with the Post-divider changes the phase detector to a little bit higher frequency. As a consequence, the spurs are

pushed further away from the carrier and are reduced more by the loop filter.

Another use case of MULT is to make higher phase-detector frequency. For example, if OSCin is 20 MHz, user

can set MULT to 5 to make f_PDgo to 100 MHz. As a result, the N-divider value will be reduced by 5 times;

therefore, the PLL phase noise is reduced. A wide loop bandwidth can then be used to reduce the VCO noise.

Consequently, the synthesizer close-in phase noise would be very good.

The MULT multiplier is an active device in nature, whenever it is enabled, it will add noise to the loop. For best

phase noise performance, it is recommended to set MULT not greater than 6.

To use the MULT, beware of the restriction as indicated in the Electrical Characteristics table and Table 15.

8.1.10 Integrated VCO

The integrated VCO is composed of 3 VCO cores. The approximate frequency ranges for the three VCO cores

with their gains is as follows:

Table 39. Approximate VCO Ranges and VCO Gain

VCO CORE

TYPICAL FREQUENCY RANGE (MHz)

TYPICAL VCO GAIN (MHz/V)

LOW

4200

4560

4920

HIGH

4700

5100

5520

LOW

46

MID

52

HIGH

61

VCOL

VCOM

VCOH

50

56

65

55

63

73

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8.2 Typical Applications

8.2.1 Synthesizer Duplex Mode

In this example, the internal VCO is being used. The PLL will be put in fractional mode to support 4FSK direct

digital modulation using FSK PIN mode. Both frequency (F1, F2) switching as well as RF output port switching is

toggled by the TrCtl pin. MULT multiplier in the R-divider will be used to reduce spurs.

3.3V

0.1µF

XO

26MHz

Vcc3p3

VccIO

VcpExt

Bypass

100pF

RFoutTx

OSCin

OSCin*

RFoutRx

CPout

LMX2571

VrefVCO

VregVCO

2.2µF

680Q

0.1µF

390pF

4.7nF

Figure 61. Typical Synthesizer Duplex Mode Application Schematic

8.2.1.1 Design Requirements

OSCin frequency = 26 MHz, LVCMOS

RFoutTx frequency = 902 MHz

RFoutRx frequency = 928 MHz

Frequency switching time ≤ 500 µs

4FSK modulation on TX, baud rate = 20 kSPs

Frequency deviation = ±10 kHz and ±30 kHz

FSK error ≤ 1 %

Spurs ≤ –72 dBc

Lock detect is required to indicate lock status

Output power < 1 dBm

8.2.1.2 Detailed Design Procedure

First of all, calculate all the frequencies in each functional block.

OSCin

26MHz

Pre-div

1

MULT

4

Post-div

1

PDF

104MHz

VCO

4510MHz

CHDIV1

5

CHDIV2

1

Output

902MHz

N

21.68269231

Prescaler

2

Figure 62. F1 Frequency Plan

Assign F1 frequency to be 902 MHz. With CHDIV1 = 5 and CHDIV2 = 1, the total division is 5. As a result, the

VCO frequency will be 902 * 5 = 4510 MHz, which is within the VCO tuning range.

OSCin is 26 MHz, put Pre-divider = 1 to meet the MULT input frequency range requirement.

To meet the maximum MULT output frequency requirement, possible MULT values are 3 to 5. Play around the

allowable MULT values and Post-divider values to get the optimum phase noise and spurs performance.

Assuming MULT = 4 and Post-divider = 1 returns the best performance, then f_PD= 104 MHz.

N-divider = 21.68269231, that means N_integer= 21 while N_frac= 0.68269231. To use the direct digital modulation

feature, put fractional denominator, DEN = 0. The actual DEN value is, in fact, equal to 2²⁴= 16777216. So the

fractional numerator, NUM, is equal to N_frac* DEN = 11453676.

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Typical Applications (continued)

Use Equation 4 and Equation 6 to calculate the required FSK steps. For +10 kHz frequency deviation, the FSK

step value is equal to [10000 * 16777216 / (104 * 10⁶)] * (5 * 1 / 2) = 4033. For –10 kHz frequency deviation, the

FSK step value is equal to 2's complement of 4033 = 61502. Similarly, the FSK step values for ±30 kHz

frequency deviation are 12099 and 53436.

All the required configuration values for F2, 928 MHz can be calculated in the similar fashion and are

summarized as follows:

Table 40. Frequency Plan Summary

CONFIGURATION PARAMETER

F1 (902 MHz)

F2 (928 MHz)

Pre-divider

MULT

1

4

Post-divider

PDF

1

104 MHz

4510 MHz

21.68269231

21

1

104 MHz

VCO

4640 MHz

N-divider

N_integer

22.30769231

22

DEN

0

NUM

11453676

5

5162220

CHDIV1

CHDIV2

FSK_DEV0

FSK_DEV1

FSK_DEV2

FSK_DEV3

5

1

4033

12099

61502

53436

Assume here that the base charge pump current = 1250 µA, CP Gain = 1x and 3^rdorder Delta Sigma Modulator

without dithering is adopted in both frequency sets. The register settings are summarized as follows:

Table 41. Register Settings Summary

CONFIGURATION

PARAMETERS

REGISTER BIT

FCAL_EN

COMMON SETTING

1 = Enabled

F1 SPECIFIC SETTING

F2 SPECIFIC SETTING

VCO calibration

Lock detect

SDO_LE_SEL

LD_EN

1 = Lock detect output

1 = Enabled

OSCin buffer type

Dithering

IPBUF_SE_DIFF_SEL

DITHERING

0 = SE input buffer

0 = Disabled

Charge pump gain

Base charge pump current

CP_GAIN

1 = 1x

CP_IUP

8 = 1250 µA

CP_IDN

8 = 1250 µA

MULT settling time

Output buffer type

MULT_WAIT

OUTBUF_RX_TYPE

OUTBUF_TX_TYPE

OUTBUF_AUTOMUTE

RXTX_POL

520 = 20 µs

1 = Push pull

Output buffer auto mute

TrCtl pin polarity

0 = Disabled

0 = Active LOW = TX

1 = TrCtl pin control

1 = Enabled

TX RX switching mode

Enable F1 F2 initialization

F1 F2 switching mode

Pre-divider

RXTX_CTRL

F1F2_MODE

F1F2_CTRL

1 = Control by TrCtl pin

PLL_R_PRE_F1

PLL_R_PRE_F2

MULT_F1

1

4

1

4

MULT multiplier

MULT_F2

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Table 41. Register Settings Summary (continued)

CONFIGURATION

PARAMETERS

REGISTER BIT

PLL_R_F1

COMMON SETTING

F1 SPECIFIC SETTING

F2 SPECIFIC SETTING

Post-divider

1

PLL_R_F2

1

3 = 3^rdorder

5 = 8 clock cycles

1 = Divide by 5

0 = Divide by 1

4 = 800 Ω

ΔΣ modulator order

FRAC_ORDER_F1

FRAC_ORDER_F2

PFD_DELAY_F1

PFD_DELAY_F2

CHDIV1_F1

3 = 3^rdorder

5 = 8 clock cycles

1 = Divide by 5

0 = Divide by 1

4 = 800 Ω

PFD delay

CHDIV1 divider

CHDIV2 divider

CHDIV1_F2

CHDIV2_F1

CHDIV2_F2

Internal 3^rdpole loop filter

Internal 4^thpole loop filter

Output port selection

Output power control

FSK mode

LF_R3_F1

LF_R3_F2

LF_R4_F1

4 = 800 Ω

LF_R4_F2

4 = 800 Ω

OUTBUF_TX_EN_F1

OUTBUF_RX_EN_F2

OUTBUF_TX_PWR_F1

OUTBUF_RX_PWR_F2

1 = TX port enabled

6

1 = RX port enabled

6

FSK_MODE_SEL1

FSK_MODE_SEL0

00 = FSK PIN mode

2 = 4FSK

FSK level

FSK_LEVEL

Enable FSK modulation

FSK deviation at 00

FSK deviation at 01

FSK deviation at 10

FSK deviation at 11

Fractional denominator

FSK_EN_F1

1 = Enabled

4033 = +10 kHz

12099 = +30 kHz

61502 = -10 kHz

53436 = -30 kHz

0

FSK_DEV0_F1

FSK_DEV1_F1

FSK_DEV2_F1

FSK_DEV3_F1

PLL_DEN_F1[23:16]

PLL_DEN_F1[15:0]

PLL_DEN_F2[23:16]

PLL_DEN_F2[15:0]

PLL_NUM_F1[23:16]

PLL_NUM_F1[15:0]

PLL_NUM_F2[23:16]

PLL_NUM_F2[15:0]

PLL_N_F1

0

Fractional numerator

174

50412

78

50412

N_integer

21

PLL_N_F2

22

Prescaler

PLL_N_PRE_F1

PLL_N_PRE_F2

0 = Divide by 2

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8.2.1.3 Synthesizer Duplex Mode Application Curves

Figure 63. F1 (TX) Phase Noise and Spurs

Figure 64. F2 (RX) Phase Noise and Spurs

Figure 65. F1 (TX) to F2 (RX) Switching

Figure 66. F2 (RX) to F1 (TX) Switching

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Figure 67. F1 to F2 Switching Time

Figure 68. F2 to F1 Switching Time

Figure 70. 4FSK Modulation Quality

Figure 69. 4FSK Modulation

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8.2.2 PLL Duplex Mode

In this example, the internal VCO will be bypassed, and the device is used to lock to an external VCO. TI’s dual

SPST analog switch, TS5A21366 is used to facilitate FastLock between two frequencies.

3.3V

5V

0.1µF

XO

16.8MHz

Vcc3p3

VccIO

VcpExt

Bypass

100pF

RFoutTx

VCO

430-480MHz

OSCin

OSCin*

Fin

LMX2571

10Q 10Q

CPoutExt

100pF

VrefVCO

VregVCO

2.2µF

10Q

470nF 39nF 39nF

50Q

0.1µF

FLout1

FLout2

TS5A21366

4.7µF

Figure 71. Typical PLL Duplex Mode Application Schematic

8.2.2.1 Design Requirements

OSCin frequency = 16.8 MHz, LVCMOS

F1 frequency = 430 MHz

F2 frequency = 480 MHz

Frequency switching time ≤ 1.5 ms within 100-Hz frequency tolerance

8.2.2.2 Detailed Design Procedure

Again, we need to figure out all the frequencies in each functional block first.

OSCin

16.8MHz

Pre-div

1

MULT

5

Post-div

3

PDF

28MHz

VCO

430MHz

CHDIV3

1

Output

430MHz

N

15.35714286

Figure 72. Frequency Plan in PLL Duplex Mode

Follow the previous example to determine all the necessary configurations. Table 42 is the summary in this

example.

Table 42. PLL Duplex Mode Frequency Plan Summary

CONFIGURATION PARAMETER

F1 (430 MHz)

F2 (480 MHz)

Pre-divider

MULT

1

5

1

5

Post-divider

PDF

3

28 MHz

430 MHz

15.35714286

15

28 MHz

480 MHz

17.14285714

17

VCO

N-divider

N_integer

DEN

1234567

440917

1234567

176367

NUM

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To enable external VCO operation, set the following bits:

Table 43. PLL Duplex Mode Register Settings Summary

CONFIGURATION PARAMETER

Charge pump polarity

REGISTER BITS

EXTVCO_CP_POL

SETTING

0 = Positive

1 = 1x

External VCO charge pump gain

EXTVCO_CP_GAIN

EXTVCO_CP_IUP

8 = 1250 µA

1 = External VCO

Base charge pump current

EXTVCO_CP_IDN

Select PLL mode operation

CHDIV3 divider

EXTVCO_SEL_F1, EXTVCO_SEL_F2

EXTVCO_CHDIV_F1, EXTVCO_CHDIV_F2 0 = Bypass

Make sure that register R0, FCAL_EN is set so that FastLock is enabled.

The loop bandwidth had been design to be around 4 kHz, while phase margin is about 40 degrees.

8.2.2.3 PLL Duplex Mode Application Curves

Figure 73. F1 to F2 Switching

Figure 74. F2 to F1 Switching

Figure 75. F1 to F2 Switching Time

Figure 76. F2 to F1 Switching Time

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8.2.3 Synthesizer/PLL Duplex Mode

This example will demonstrate the device's capability in switching two frequencies using internal and external

VCO. VCO switching is toggled by the TrCtl pin. Direct digital FSK modulation is enabled in TX using FSK I2S

mode.

3.3V

5V

0.1µF

XO

19.2MHz

Vcc3p3

VccIO

VcpExt

Bypass

100pF

RFoutRx

RFoutTx

OSCin

OSCin*

100pF

VCO

430-480MHz

LMX2571

Fin

VrefVCO

VregVCO

10Q 10Q

100pF

2.2µF

CPoutExt

0.1µF

10Q

470nF 39nF 39nF

4.7µF

50Q

Figure 77. Typical Synthesizer/PLL Duplex Mode Application Schematic

8.2.3.1 Design Requirements

OSCin frequency = 19.2 MHz, LVCMOS

RFoutRX frequency = 440 MHz, external VCO = F1

RFoutTx frequency = 540 MHz, internal VCO = F2

Frequency switching time ≤ 1.5 ms within 100-Hz frequency tolerance

Arbitrary FSK modulation to simulate analog FM modulation (10 times and 20 times over-sampling rate)

FM modulation frequency = 1 kHz

Frequency deviation = ±2000 Hz

Spurs ≤ –72 dBc

8.2.3.2 Detailed Design Procedure

Frequency plans in TX and RX paths are as follows:

OSCin

19.2MHz

Pre-div

1

MULT

1

Post-div

1

PDF

19.2MHz

VCO

440MHz

CHDIV3

1

Output

440MHz

N

22.91666687

OSCin

19.2MHz

Pre-div

1

MULT

5

Post-div

PDF

96MHz

VCO

5400MHz

CHDIV1

5

CHDIV2

Output

540MHz

1

2

N

28.125

Prescaler

2

Figure 78. TX and RX Frequency Plans

Follow the previous examples to determine all the necessary configurations. To enable FSK I2S mode, set

FSK_MODE_SEL1=1

FSK_MODE_SEL=0

FSK_EN_F2=1

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8.2.3.3 Synthesizer/PLL Duplex Mode Application Curves

Figure 79. External VCO to Internal VCO Switching

Figure 80. Internal VCO to External VCO Switching

Figure 81. External VCO to Internal VCO Switching Time

Figure 82. Internal VCO to External VCO Switching Time

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Figure 83. Simulated FM Modulation (10 times over-

sampling)

Figure 84. Simulated FM Modulation (20 times over-

sampling)

8.3 Do's and Don'ts

INCORRECT

CORRECT

VregVCO

100nF

2.2µF

VregVCO DECOUPLING

VcpExt SUPPLY

DAP PIN

3.3V or 5V: Synthesizer mode

5V: PLL mode

VcpExt

DAP

VcpExt

DAP

Figure 85. Do's and Don'ts

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9 Power Supply Recommendations

It is recommended to place 100 nF capacitor close to each of the power supply pins. If fractional spurs are a

large concern, using a ferrite bead to each of these power supply pins may reduce spurs to a small degree.

VcpExt is the power supply pin for the 5-V charge pump. In PLL mode, the 5-V charge pump is active and a 5 V

is required at VcpExt pin. In synthesizer mode, although the 5-V charge pump is not active, either a 3.3-V

or 5-V supply is still needed at this pin.

Because LMX2571 has integrated LDOs, the requirement to external power supply is relaxed. In addition to LDO,

LMX2571 is able to operate with DC-DC converter. The switching noise from the DC-DC converter would not

affect performance of the LMX2571. Table 44 lists some of the suggested DC-DC converters.

Table 44. Recommended DC-DC Converters

PART NUMBER

TPS560200

TPS62050

TOPOLOGY

Buck

V_IN

V_OUT

I_OUT

500 mA

SWITCHING FREQUENCY

600 kHz

4.5 V to 17 V

2.7 V to 10 V

3 V to 17 V

4.5 V to 17 V

2.5 V to 5.5 V

0.8 V to 6.5 V

0.7 V to 6 V

0.9 V to 6 V

0.76 V to 7 V

2.5 V to 5.5 V

Buck

800 mA

1 MHz

TPS62160

Buck

1000 mA

2000 mA

500 mA to 1 A

2.25 MHz

TPS562200

TPS63050

Buck

650 kHz

Buck Boost

2.5 MHz

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10 Layout

10.1 Layout Guidelines

See EVM instructions for details. In general, the layout guidelines are similar to most other PLL devices. The

followings are some guidelines specific to the device.

•

It may be beneficial to separate main ground and OSCin ground, crosstalk spurs might be reduced.

Don't route any traces that carry switching signal close to the charge pump traces and external VCO.

When using FSK I2S mode on this device, care should be taken to avoid coupling between the I2S clock and

any of the PLL circuit.

10.2 Layout Example

Figure 86. Layout Example

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11 器件和文档支持

11.1 器件支持

11.1.1 开发支持

德州仪器 (TI) 提供了多种软件工具来协助开发过程，其中包括用于编程的 CodeLoader、用于回路滤波和相位噪声/

毛刺仿真的 Clock Design Tool、以及用于系统解决方案查找器的 Clock Architect。所有这些工具均可从以下网址

获得：www.ti.com。

11.2 文档支持

11.2.1 相关文档

SPRA953《半导体和 IC 封装热指标》

TS5A21366《具有 1.8V 兼容输入逻辑的 0.75Ω 双通道 SPST 模拟开关》

TPS560200《4.5V 至 17V 输入、500mA 同步降压 SWIFT™ 转换器》

TPS62050《800mA 同步降压转换器》

TPS62160《具有 DCS 控制系统的 3V-17V 1A 降压转换器》

TPS562200《采用 SOT-23 封装的 4.5V 至 17V 输入、2A 同步降压稳压器》

TPS63050《微型单电感降压/升压转换器》

11.3 商标

PLLatinum is a trademark of Texas Instruments.

SPI is a trademark of Motorola.

All other trademarks are the property of their respective owners.

11.4 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.5 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、首字母缩略词和定义。

12 机械封装和可订购信息

以下页中包括机械封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

55

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型号：	LMX2571
厂家：	TEXAS INSTRUMENTS
描述：	具有移频键控 (FSK) 调制功能的 1.34GHz、低功耗、极端温度 RF 合成器
文件：	总59页 (文件大小：2554K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LMX2571 [TI]

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