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LMX2594

ZHCSGL5C –MARCH 2017–REVISED APRIL 2019

LMX2594 15GHz 宽带 PLLATINUM™ 射频合成器

1 特性

3 说明

1

•

10MHz 至 15GHz 输出频率

LMX2594 是一款高性能宽带合成器，可在不使用内部

加倍器的情况下生成 10MHz 至 15GHz 范围内的任何

频率，因而无需使用分谐波滤波器。品质因数为

-236dBc/Hz 的高性能 PLL 和高相位检测器频率可实现

非常低的带内噪声和集成抖动。高速 N 分频器没有预

分频器，从而显著减少了杂散的振幅和数量。还有一个

可减轻整数边界杂散的可编程输入乘法器。

在 100KHz 偏频和 15GHz 载波的情况下具有

-110dBc/Hz 的相位噪声

•

7.5GHz 时，具有 45fs rms 抖动（100Hz 至

100MHz）

•

可编程输出功率

PLL 主要规格

–

品质因数：-236dBc/Hz

标称 1/f 噪声：-129dBc/Hz

最高相位检测器频率

LMX2594 允许用户同步多个器件的输出，并可在输入

和输出之间确定需要延迟的情况下应用。频率斜升发

生器可在自动斜坡生成选项或手动选项中最多合成 2

段斜坡，以实现最大的灵活性。通过快速校准算法可将

频率加快至 20μs 以上。LMX2594 增添了对生成或重

复 SYSREF（符合 JESD204B 标准）的支持，此

SYSREF 是高速数据转换器的理想低噪声时钟源。此

配置中提供了精细的延迟调节（9ps 分辨率），以解决

板迹线的延迟差异。

–

400MHz 整数模式

300MHz 分数模式

–

32 位分数 N 分频器

•

用可编程输入乘法器消除整数边界杂散

跨多个设备实现输出相位同步

支持具有 9ps 分辨率可编程延迟的 SYSREF

用于 FMCW 应用的频率斜升和线性调频脉冲生成

能力

LMX2594 中的输出驱动器在载波频率为 15GHz 时提

供高达 7dBm 的输出功率。该器件采用单个 3.3V 电源

供电，并具有集成的 LDO，无需板载低噪声 LDO。

•

小于 20µs VCO 校准速度

3.3V 单电源运行

器件信息⁽¹⁾

2 应用

器件型号

LMX2594

封装

VQFN (40)

封装尺寸（标称值）

•

5G 和毫米波无线基础设施

6.00mm × 6.00mm

测试和测量设备

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

雷达

MIMO

相控阵天线和波束形成

高速数据转换器时钟（支持 JESD204B）

简化原理图

Loop Filter

RFoutAP

CPout

Vtune

Phase

Detector

OSCinP

Input

signal

OSCin

Douber

Pre-R

Divider

Post-R

Divider

Multiplier

Charge

Pump

ϕ

MUX

Vcc

OSCinM

RFoutAM

RFoutBM

Channel

Divider

Sigma-Delta

Modulator

CSB

SCK

SDI

Vcc

Serial Interface

Control

RFoutBP

N Divider

SYSREF

MUXout

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNAS696

LMX2594

ZHCSGL5C –MARCH 2017–REVISED APRIL 2019

www.ti.com.cn

7.5 Programming........................................................... 40

7.6 Register Maps......................................................... 41

Application and Implementation ........................ 59

8.1 Application Information............................................ 59

8.2 Typical Application .................................................. 61

Power Supply Recommendations...................... 64

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 6

Specifications......................................................... 8

6.1 Absolute Maximum Ratings ...................................... 8

6.2 ESD Ratings.............................................................. 8

6.3 Recommended Operating Conditions....................... 8

6.4 Thermal Information.................................................. 8

6.5 Electrical Characteristics........................................... 9

6.6 Timing Requirements.............................................. 11

6.7 Typical Characteristics............................................ 14

Detailed Description ............................................ 18

7.1 Overview ................................................................. 18

7.2 Functional Block Diagram ....................................... 19

7.3 Feature Description................................................. 19

7.4 Device Functional Modes........................................ 39

8

9

10 Layout................................................................... 65

10.1 Layout Guidelines ................................................. 65

10.2 Layout Example .................................................... 66

11 器件和文档支持 ..................................................... 67

11.1 器件支持................................................................ 67

11.2 文档支持................................................................ 67

11.3 接收文档更新通知 ................................................. 67

11.4 社区资源................................................................ 67

11.5 商标....................................................................... 67

11.6 静电放电警告......................................................... 67

11.7 术语表 ................................................................... 67

12 机械、封装和可订购信息....................................... 68

7

4 修订历史记录

Changes from Revision B (March 2018) to Revision C

Page

•

Deleted the recommended bypass capacitor values for Vcc pins 7, 11, 15, 21, 26 and 37, as these capacitor values

are not mandatory and the power supply filtering design is up to the user............................................................................ 7

•

Changed all the 'FRAC_ORDER' to 'MASH_ORDER' to avoid confusion ............................................................................. 9

Changed the names of timing specs to align with timing diagram: changed t_CEto t_ES, t_CSto t_DCS, t_CHto t_CDH, and t_CES

to t_ECS.................................................................................................................................................................................... 11

•

Changed the names of timing specs to align with timing diagram: changed t_ESto t_CE, t_CESto t_ECS, added t_DCSand

t_CDH, and changed t_CSto t_CR.................................................................................................................................................. 12

•

Changed the serial data input timing diagram and corrected the typo for 'SCK'.................................................................. 12

Deleted the note 'The CSB transition from high to low must occur when SCK is low' from the serial data input timing

diagram, because SPI mode 4 (CPOL = 1, CPHA = 1) is also supported, and SCK is held high when idle in mode 4 ..... 12

•

Added note for the serial data input timing diagram to explain the t_CErequirement for mode 4 (CPOL = 1, CPHA = 1)

of SPI, because the diagram only indicated SPI mode 1 (CPOL = 0, CPHA = 0) ............................................................... 12

•

Changed the serial data readback timing diagram............................................................................................................... 13

Changed the note about MUXout clocking out and emphasized the effect of t_CRon the readback data available time ..... 13

Changed the f_OUTtest conditions in the Closed-Loop Phase Noise at 3.5 GHz graph from: 14 GHz / 2 = 3.5 GHz to:

to 14 GHz / 4 = 3.5 GHz ...................................................................................................................................................... 15

•

Added Normalized Output Power Across OUTA_PWR With Resistor Pullup graph............................................................ 15

Changed "Vtune" to "Indirect Vtune" when LD_TYPE = 1 ................................................................................................... 21

Changed description for LD_TYPE. .................................................................................................................................... 21

Added description of Indirect Vtune. ................................................................................................................................... 22

Added description for the 'no assist' mode, mphasized the effect of VCO_SEL, VCO_DACISET_STRT and

VCO_CAPCTRL_STRT under 'no assist' mode, and added recommended values for these registers.............................. 23

•

Added description for the 'full assist' mode to allow the user to set VCO amplitude and capcode using linear

interpolation under certain conditions................................................................................................................................... 23

•

Changed OUTx_PWR Recommendations for Resistor Pullup table ................................................................................... 25

Added description for category 3 of SYNC feature stating that FCAL_EN needs to be 1. .................................................. 29

Changed description of MASH_SEED ................................................................................................................................ 29

2

LMX2594

www.ti.com.cn

ZHCSGL5C –MARCH 2017–REVISED APRIL 2019

修订历史记录 (接下页)

•

Added 10-ms wait time before re-programming register R0 in recommended initial power-up sequence ......................... 40

Added the General Programming Requirements section based on frequently asked questions......................................... 40

Changed register R4 in the register map to: exposed ACAL_CMP_DLY ........................................................................... 41

Changed the register R20[14] value from 0 to 1 in the full register map to match the R20 register description ................ 41

Changed the default value of R25 to align with register map of LMX2595. This change has no impact on the LMX2594. 42

Changed the R0[14] register field name in the register map from VCO_PHASE_SYNC_EN to VCO_PHASE_SYNC.

to align with the rest of the data sheet ................................................................................................................................. 46

•

Added recommended value for register CAL_CLK_DIV when lock time is not of concern.................................................. 46

Changed the typo for register 'VCO_DACISET' in the register map. Bit 0 of this register was not included in the

map. The full register map and register description were correct ........................................................................................ 48

•

Added description to the R4[15:8]: ACAL_CMP_DLY register............................................................................................. 48

Deleted the bit description '0: disabled; 1: enabled' for register 'PLL_N' ............................................................................. 49

Added description to the R60[15:0] LD_DLY register .......................................................................................................... 51

Changed the R31[14] register name from CHDIV_DIV2 to SEG1_EN to align with the naming in the TICS Pro GUI ....... 53

Changed the R105[1:0] field name from RAMP_NEXT_TRIG to RAMP1_NEXT_TRIG..................................................... 58

Added the Bias Levels of Pins table..................................................................................................................................... 64

Changes from Revision A (August 2017) to Revision B

Page

•

Changed all the VCO Gain typical values in the Electrical Characteristics table. This is due to improved

measurement methods and NOT a change in the device itself ........................................................................................... 11

Moved the high-level output voltage parameter V_CC– 0.4 value from the MAX column to the MIN.................................... 11

Moved the high-level output current parameter 0.4 value from the MIN column to the MAX .............................................. 11

Changed bulleted text: data is clocked out on MUXout, not SDI pin ................................................................................... 13

Added comment that OSCin is clocked on rising edges of the signal. and reformatted with bulleted list ........................... 19

Added description of the state machine clock ..................................................................................................................... 20

Changed example from: 200 MHz / 2³²to: 200 MHz / (2³²– 1) .......................................................................................... 21

Changed LD_DLY description in Table 4 and removed duplicated text in the Lock Detect section.................................... 21

Changed name from VCO_AMPCAL to VCO_DACISET_STRT ........................................................................................ 23

Added more programmable settings to Table 5 ................................................................................................................... 23

Changed VCO Gain table..................................................................................................................................................... 24

Added that OUTx_PWR states 32 to 47 are redundant and reworded section ................................................................... 25

Added term "IncludedDivide" for clarity ............................................................................................................................... 26

Changed Fixed Diagram to show SEG0, SEG1, SEG2, and SEG3 ................................................................................... 27

•

Changed included channel divide to IncludedDivide and 2 X SEG0 to 2 X SEG1. Also clarified IncludedDivide

calculations........................................................................................................................................................................... 29

•

Added more description on conditions for phase adust ....................................................................................................... 29

Changed text from: (VCO_PHASE_SYNC = 1) to: (VCO_PHASE_SYNC = 0) ................................................................. 29

Changed text so the user does not incorrectly assume that MASH_SEED varies from part ot part ................................... 30

Changed the RAMP_THRESH programming from: 0 to ± 2³²to: 0 to ± 2³³– 1 .................................................................. 30

Removed comment that RAMP_TRIG_CAL only applies in automatic ramping mode........................................................ 30

Changed the RAMP_LOW and _HIGH programming from: 0 to ± 2³¹to: 0 to ± 2³³– 1...................................................... 30

Changed description to be in terms of state machine cycles............................................................................................... 31

Changed RAMP_MODE to RAMP_MANUAL in the Manual Pin Ramping and Automatic Ramping sections.................... 31

Added that the RampCLK pin input is reclocked to the phase detector frequency.............................................................. 31

Added that RampDir rising edges should be targeted away from rising edges of RampCLK pin........................................ 31

Changed programming enumerations for RAMP0_INC and RAMP1_INC .......................................................................... 33

3

LMX2594

ZHCSGL5C –MARCH 2017–REVISED APRIL 2019

www.ti.com.cn

•

Changed programming enumerations for RAMP_THRESH, RAMPx_LEN, and RAMP1_INC............................................ 34

Changed Figure 29 .............................................................................................................................................................. 34

Changed SysRef description ................................................................................................................................................ 35

Added divide by 2 to figure................................................................................................................................................... 35

Changed some entries in the table ...................................................................................................................................... 35

Changed f_INTERPOLATORSYSREF setup equation in Table 18 .............................................................................................. 35

Changed SysRef delay from: 224 and 225 to: 225 and 226................................................................................................ 36

Changed "generator" mode to "master" mode. They mean the same thing ........................................................................ 36

Changed description for SYSREF_DIV................................................................................................................................ 36

Changed Figure 31 .............................................................................................................................................................. 37

Changed wording for repeater mode and master mode....................................................................................................... 38

Changed description of a few of the steps ........................................................................................................................... 39

Changed typo in R17 and R19 ............................................................................................................................................ 48

Deleted reference to VCO_SEL_STRT_EN. This is always 1 ............................................................................................. 48

Added VCO_SEL_STRT_EN reference. This is always 1 ................................................................................................... 48

Changed the enumerations 0-3 and added content to the INPIN_LVL field description ..................................................... 50

Added Divide by 1' to SYSREF_DIV_PRE register description. Also fixed the name misspelling ...................................... 52

Deleted redundant formula for Fout and also clarified SYSREF_DIV starts at 4 and counts by 2 ...................................... 52

Deleted reference to VCO_CAPCTRL_EN, which is always 1, and clarified....................................................................... 54

Changed text from: f_MAXto: f_HIGH........................................................................................................................................... 55

Changed text from: RAMP_LIMIT_LOW=2³²- (f_LOW- f_VCO) / f_PD× 16777216 to: RAMP_LIMIT_LOW=2³³- 16777216

x (f_VCO- f_LOW) / f_PD................................................................................................................................................................ 55

•

Removed the OSCin Configuration table and added content to the OSCin Configuration section...................................... 59

Changed pin 27 recommendation from 10 µF to 1 µF in Figure 51..................................................................................... 61

Changes from Original (March 2017) to Revision A

Page

•

Added DAP pin described as "Die Attach Pad"...................................................................................................................... 7

Added H2 Spec for 11 GHz ................................................................................................................................................... 9

Clarified that output power assumes that load is matched and losses are de-embedded..................................................... 9

Changed "SDA" pin name mispelled. Should be "SDI". Also fixed in timing diagrams. Also added CE Pin ...................... 11

Swapped SDI and SCK in diagram ..................................................................................................................................... 12

Added graphs and reordered ............................................................................................................................................... 14

Added 12-GHz VCO frequency for PLL Noise Metrics Plot ................................................................................................ 14

Added Phase Noise plots vs. Temperature ......................................................................................................................... 15

Added Phase noise vs. Fpd Graph ..................................................................................................................................... 16

Moved second paragraph of Readback into Lock Detect section; deleted last paragraph of Readback (was in wrong

place).................................................................................................................................................................................... 22

•

Changed table to allow 11.5 GHz max frequency for divides >6 ......................................................................................... 24

Added Recommendations table .......................................................................................................................................... 25

Changed the IncludedDivide table........................................................................................................................................ 26

Added section on fine tune adjustments ............................................................................................................................. 30

Changed graphic and description......................................................................................................................................... 35

Added SYSREF_EN = 1 if and only if OUTB_MUX=2 ........................................................................................................ 36

Changed SysRef Example Description and Pictures .......................................................................................................... 38

Added recommendation to make f_Interpolatora multiple of f_OSC.............................................................................................. 39

Added SEG1_EN.................................................................................................................................................................. 42

Added INPIN_IGNORE, INPIN_LVL, and INPIN_HYST ...................................................................................................... 43

4

LMX2594

www.ti.com.cn

ZHCSGL5C –MARCH 2017–REVISED APRIL 2019

•

Removed RAMP0_FL from register map ............................................................................................................................. 45

Changed address for VCO_DACISET_STRT and VCO_CAPCTRL .................................................................................. 48

Clarified MASH_RESET_N. 0 = RESET (integer mode), 1 = Fractional mode .................................................................. 49

Changed OUT_ISEL to OUTI_SET ..................................................................................................................................... 50

Added SYSREF_EN=1 when OUTB_MUX=2 ..................................................................................................................... 50

Added section for input register descriptions ...................................................................................................................... 50

Added description for SEG1_EN ......................................................................................................................................... 53

Fixed TYPO table to match main register map. ................................................................................................................... 53

Added SEG1_EN.................................................................................................................................................................. 53

Corrected RAMP_BURST_TRIG description to match other place in data sheet................................................................ 56

Removed duplicate error in R101[2] .................................................................................................................................... 57

Changed RAMP1_INC from RAMP0 to RAMP1 .................................................................................................................. 57

Clarified that the delay was in state machine cycles............................................................................................................ 57

Swapped 1 and 3 in the R110[10:9] description .................................................................................................................. 58

Fixed pin names in schematic ............................................................................................................................................. 61

5

LMX2594

ZHCSGL5C –MARCH 2017–REVISED APRIL 2019

www.ti.com.cn

5 Pin Configuration and Functions

RHA Package

40-Pin VQFN

Top View

CE

GND

RampClk

VrefVCO2

VbiasVCO

GND

SysRefReq

VbiasVCO2

VccVCO2

GND

SYNC

GND

VccDIG

OSCinP

OSCinM

VregIN

CSB

RFoutAP

RFoutAM

VccBUF

6

LMX2594

www.ti.com.cn

ZHCSGL5C –MARCH 2017–REVISED APRIL 2019

Pin Functions

I/O

DESCRIPTION

NO.

NAME

1

CE

Input

Chip enable input. Active HIGH powers on the device.

VCO ground.

2, 4, 25, 31,

34, 39, 40

GND

Ground

3

VbiasVCO

SYNC

Bypass

Input

VCO bias. Requires a 10-µF capacitor connected to VCO ground. Place close to pin.

Phase synchronization pin. Has programmable threshold.

Digital ground.

5

6, 14

7

GND

Ground

Supply

VccDIG

Digital supply. TI recommends bypassing with decoupling capacitor to digital ground.

Reference input clock (+). High-impedance self-biasing pin. Requires AC-coupling capacitor.

(0.1 µF recommended)

8

OSCinP

OSCinM

VregIN

VccCP

Input

Reference input clock (–). High impedance self-biasing pin. Requires AC-coupling capacitor.

(0.1 µF recommended)

9

Input reference path regulator output. Requires a 1-µF capacitor connected to ground. Place

close to pin.

10

11

Bypass

Supply

Charge pump supply. TI recommends bypassing with decoupling capacitor to charge pump

ground.

12

13

15

16

17

CPout

GND

Output

Ground

Supply

Input

Charge pump output. TI recommends connecting C1 of loop filter close to pin.

Charge pump ground.

VccMASH

SCK

Digital supply. TI recommends bypassing with decoupling capacitor to digital ground.

SPI clock. High impedance CMOS input. 1.8-V to 3.3-V logic.

SPI data. High impedance CMOS input. 1.8-V to 3.3-V logic.

SDI

Input

Differential output B (–). Requires a pullup (typically 50-Ω resistor) connected to Vcc as close

to the pin as possible. Can be used as an output signal or SYSREF output.

18

19

RFoutBM

RFoutBP

Output

Differential output B (+). Requires a pullup (typically 50-Ω resistor) connected to Vcc as close

to the pin as possible. Can be used as an output signal or SYSREF output.

20

21

MUXout

VccBUF

Output

Supply

Multiplexed output pin — lock detect, readback, diagnostics, ramp status.

Output buffer supply. TI recommends bypassing with decoupling capacitor to RFout ground.

Differential output A (–). Requires connecting a 50-Ω resistor pullup to Vcc as close to the

pin as possible.

22

23

RFoutAM

RFoutAP

Output

Differential output A (+). Requires connecting a 50-Ω resistor pullup to Vcc as close to the

pin as possible.

24

26

27

28

29

CSB

Input

Supply

Bypass

Input

SPI latch. Chip Select Bar. High-impedance CMOS input. 1.8-V to 3.3-V logic.

VCO supply. TI recommends bypassing with decoupling capacitor to VCO ground.

VCO bias. Requires a 1-µF capacitor connected to VCO ground.

SYSREF request input for JESD204B support.

VccVCO2

VbiasVCO2

SysRefReq

VrefVCO2

Bypass

VCO supply reference. Requires a 10-µF capacitor connected to VCO ground.

Input pin for ramping mode that can be used to clock the ramp in manual ramping mode or

as a trigger input.

30

32

RampClk

RampDir

Input

Input pin for ramping mode that can be used to change ramp direction in manual ramping

mode or as a trigger input.

33

VbiasVARAC

Vtune

Bypass

Input

VCO Varactor bias. Requires a 10-µF capacitor connected to VCO ground.

VCO tuning voltage input.

35

36

VrefVCO

VccVCO

VregVCO

GND

Bypass

Supply

Bypass

Ground

VCO supply reference. Requires a 10-µF capacitor connected to VCO ground.

VCO supply. Recommend bypassing with decoupling capacitor to ground.

VCO regulator node. Requires a 1-µF capacitor connected to ground.

Die Attached Pad. Used for RFout ground.

37

38

DAP

7

LMX2594

ZHCSGL5C –MARCH 2017–REVISED APRIL 2019

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

–40

–65

MAX

3.6

UNIT

V

V_CC

T_J

Power supply voltage

Junction temperature

Storage temperature

150

°C

T_stg

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±2000

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±750

(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 500 V HBM is possible with the necessary precautions. Pins listed as ±XXX V may actually have higher performance.

(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 250 V CDM is possible with the necessary precautions. Pins listed as ±YYY V may actually have higher performance.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

3.15

–40

NOM

3.3

MAX

3.45

85

UNIT

V

V_CC

T_A

Power supply voltage

Ambient temperature

Junction temperature

25

°C

T_J

125

°C

6.4 Thermal Information

LMX2594

THERMAL METRIC⁽¹⁾

RHA (VQFN)

40 PINS

30.5

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

(2)

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

15.3

Junction-to-board thermal resistance

5.4

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JB

5.3

R_θJC(bot)

0.9

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report (SPRA953).

(2) DAP

8

LMX2594

www.ti.com.cn

ZHCSGL5C –MARCH 2017–REVISED APRIL 2019

6.5 Electrical Characteristics

3.15 V ≤ V_CC≤ 3.45 V, –40°C ≤ T_A≤ +85°C. Typical values are at V_CC= 3.3 V, 25°C (unless otherwise noted).

PARAMETER

POWER SUPPLY

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_CC

Supply voltage

3.15

3.3

3.45

V

OUTA_PD = 0, OUTB_PD = 1

OUTA_MUX = OUTB_MUX = 1

Supply current

OUTA_PWR = 31, CPG=7

340

f_OSC= f_PD= 100 MHz, f_VCO= f_OUT= 14 GHz

p_OUT= 3 dBm with 50-Ω resistor pullup

I_CC

mA

Power-on reset current

Power-down current

RESET=1

170

5

POWERDOWN=1

OUTPUT CHARACTERISTICS

f_OUT= 8 GHz

f_OUT= 15 GHz

f_OUT= 8 GHz

f_OUT= 15 GHz

5

2

50-Ω resistor pullup

OUTx_PWR = 50

p_OUT

Single-ended output power⁽¹⁾⁽²⁾

dBm

10

7

1-nH inductor pullup

OUTx_PWR = 50

Isolation between outputs A and OUTA_MUX = VCO

Xtalk

H2

–50

–20

–30

–50

dBc

B. Measured on output A

OUTB_MUX = channel divider

OUTA_MUX = VCO

f_VCO= 8 GHz

Second harmonic⁽²⁾

OUTA_MUX = VCO

f_VCO= 11 GHz

OUTA_MUX = VCO

f_VCO= 8 GHz

H3

Third harmonic⁽²⁾

dBc

INPUT SIGNAL PATH

f_OSCinReference input frequency

v_OSCin

OSC_2X = 0

5

1400

200

2

MHz

OSC_2X = 1

(3)

Reference input voltage

AC-coupled required

Input range

0.2

30

Vpp

Multiplier frequency (only

applies when multiplier is

enabled)

70

f_MULT

MHz

Output range

180

250

PHASE DETECTOR AND CHARGE PUMP

Integer mode

MASH_ORDER = 0

0.125

400

300

240

MASH_ORDER= 1, 2,

3

f_PD

Phase detector frequency⁽³⁾

Charge-pump leakage current

5

MHz

nA

Fractional mode

MASH_ORDER = 4

CPG = 0

CPG = 4

CPG = 1

CPG = 5

CPG = 3

CPG = 7

15

3

6

Effective charge pump current.

This is the sum of the up and

down currents

I_CPout

9

mA

12

15

PN_{PLL_1/f}Normalized PLL 1/f noise

PN_{PLL_flat}Normalized PLL noise floor

–129

–236

dBc/Hz

f_PD= 100 MHz, f_VCO= 12 GHz^(4)(4)(4)(4)

(1) Single ended output power obtained after de-embedding microstrip trace losses and matching with a manual tuner. Unused port

terminated to 50 ohm load.

(2) Output power, spurs, and harmonics can vary based on board layout and components.

(3) For lower VCO frequencies, the N divider minimum value can limit the phase-detector frequency.

(4) The PLL noise contribution is measured using a clean reference and a wide loop bandwidth and is composed into flicker and flat

components. PLL_flat = PLL_FOM + 20 × log(Fvco/Fpd) + 10 × log(Fpd / 1Hz). PLL_flicker (offset) = PLL_flicker_Norm + 20 × log(Fvco

/ 1GHz) – 10 × log(offset / 10kHz). Once these two components are found, the total PLL noise can be calculated as PLL_Noise = 10 ×

log(10 ^{PLL_Flat / 10}+ 10 ^{PLL_flicker / 10}

)

9

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Electrical Characteristics (continued)

3.15 V ≤ V_CC≤ 3.45 V, –40°C ≤ T_A≤ +85°C. Typical values are at V_CC= 3.3 V, 25°C (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VCO CHARACTERISTICS

10 kHz

100 kHz

1 MHz

–80

–107

–128

–148

–157

–79

VCO1

f_VCO= 8 GHz

10 MHz

90 MHz

10 kHz

100 kHz

1 MHz

–105

–127

–147

–157

–77

VCO2

f_VCO= 9.2 GHz

10 MHz

90 MHz

10 kHz

100 kHz

1 MHz

–104

–126

–147

–157

–76

VCO3

f_VCO= 10.3 GHz

10 MHz

90 MHz

10 kHz

100 kHz

1 MHz

–103

–125

–145

–158

–74

VCO4

f_VCO= 11.3 GHz

PN_VCO

VCO phase noise

dBc/Hz

10 MHz

90 MHz

10 kHz

100 kHz

1 MHz

–100

–123

–144

–157

–73

VCO5

f_VCO= 12.5 GHz

10 MHz

90 MHz

10 kHz

100 kHz

1 MHz

–100

–122

–143

–155

–73

VCO6

f_VCO= 13.3 GHz

10 MHz

90 MHz

10 kHz

100 kHz

1 MHz

–99

VCO7

f_VCO= 14.5 GHz

–121

–143

–152

50

10 MHz

90 MHz

No assist

Partial assist

Close frequency

Full assist

Switch across the entire

frequency band

35

t_VCOCAL

VCO calibration speed

µs

f_OSC= 200 MHz, f_PD

=

20

100 MHz⁽⁵⁾

5

(5) See Application and Implementation for more details on the different VCO calibration modes.

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Electrical Characteristics (continued)

3.15 V ≤ V_CC≤ 3.45 V, –40°C ≤ T_A≤ +85°C. Typical values are at V_CC= 3.3 V, 25°C (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

92

MAX

UNIT

8 GHz

9.2 GHz

10.3 GHz

11.3 GHz

12.5 GHz

13.3 GHz

14.5 GHz

91

115

121

195

190

213

K_VCO

VCO gain

MHz/V

Allowable temperature drift

when VCO is not recalibrated

|ΔT_CL

|

RAMP_EN = 0 or RAMP_MANUAL= 1

125

°C

H2

H3

VCO second harmonic

VCO third haromonic

f_VCO= 8 GHz, divider disabled

–20

–50

dBc

SYNC PIN AND PHASE ALIGNMENT

Category 3

0

100

f_OSCinSY Maximum usable OSCin with

MHz

NC

sync pin (Figure 27)

Categories1 and 2

1400

DIGITAL INTERFACE

Applies to SLK, SDI, CSB, CE, RampDir, RampClk, MUXout, SYNC (CMOS Mode), SysRefReq (CMOS Mode)

V_IH

V_IL

I_IH

High-level input voltage

Low-level input voltage

High-level input current

Low-level input current

High-level output voltage

Low-level output voltage

1.4

0

Vcc

0.4

25

V

–25

µA

V

I_IL

–25

25

V_OH

V_OL

Load current = –10 mA

Load current = 10 mA

V_CC– 0.4

MUXout pin

0.4

V

6.6 Timing Requirements

(3.15 V ≤ V_CC≤ 3.45 V, –40°C ≤ T_A≤ +85°C, except as specified. Nominal values are at V_CC= 3.3 V, T_A= 25°C)

MIN

NOM

MAX

UNIT

SYNC, SYSRefReq, RampClk, and RampDIR Pins

SYNC pin

2.5

2

Setup time for pin relative to

OSCin rising edge

t_SETUP

ns

SysRefReq pin

SYNC pin

Hold time for SYNC pin

relative to OSCin rising edge

t_HOLD

SysRefReq pin

2

DIGITAL INTERFACE WRITE SPECIFICATIONS

f_SPIWrite

t_CE

SPI write speed

t_CWL+ t_CWH> 13.333 ns

75

MHz

ns

Clock to enable low time

Data to clock setup time

Clock to data hold time

Clock pulse width high

Clock pulse width low

Enable to clock setup time

Enable pulse width high

5

2

5

2

t_DCS

ns

t_CDH

ns

t_CWH

t_CWL

t_ECS

See Figure 1

ns

t_EWH

ns

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Timing Requirements (continued)

(3.15 V ≤ V_CC≤ 3.45 V, –40°C ≤ T_A≤ +85°C, except as specified. Nominal values are at V_CC= 3.3 V, T_A= 25°C)

MIN

NOM

MAX

UNIT

DIGITAL INTERFACE READBACK SPECIFICATIONS

f_SPIReadback

SPI readback speed

50

MHz

ns

t_CE

Clock to enable low time

Data to clock setup time

Clock to data hold time

10

2

t_DCS

t_CDH

ns

2

ns

Clock falling edge to

t_CR

available readback data wait See Figure 2

time.

0

10

ns

t_CWH

t_CWL

t_ECS

t_EWH

Clock pulse width high

Clock pulse width low

Enable to clock setup time

Enable pulse width high

10

ns

SCK

t_CWL

t_CWH

t_CDH

SDI

R/W

A6

A5 ~ A1

A0

D15

D14 ~ D2

D1

D0

t_DCS

t_CE

t_EWH

t_ECS

CSB

Figure 1. Serial Data Input Timing Diagram

There are several other considerations for writing on the SPI:

•

The R/W bit must be set to 0.

The data on SDI pin is clocked into a shift register on each rising edge on the SCK pin.

The CSB must be held low for data to be clocked. Device will ignore clock pulses if CSB is held high.

When SCK and SDI lines are shared between devices, TI recommends to hold the CSB line high on the

device that is not to be clocked.

•

Note that t_CEis only a valid spec if CPOL (Clock Polarity) = 0 and CPHA (Clock Phase) = 0 is used for SPI

protocol. For SPI mode (CPOL = 1 and CPHA = 1), the minimum distance required between the last rising

edge of clock and the rising edge of CSB is t_CE+ clock_period/2.

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SCK

t_CWL

t_CWH

t_CDH

SDI

R/W

A6

A5 ~ A1

A0

t_DCS

t_CR

MUXout

D15

D14 ~ D2

D1

D0

t_ECS

t_CE

t_EWH

CSB

Figure 2. Serial Data Readback Timing Diagram

There are several other considerations for SPI readback:

•

The R/W bit must be set to 1.

The MUXout pin will always be low for the address portion of the transaction.

The data on MUXout is clocked out at t_CRafter the falling edge of SCK. In other words, the readback data will

be available at the MUXout pin t_CRafter the clock falling edge.

•

The data portion of the transition on the SDI line is always ignored.

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6.7 Typical Characteristics

-30

-40

1: 100 Hz -84.0 dBc/Hz 6: 10 MHz -141.8 dBc/Hz

2: 1 kHz -94.5 dBc/Hz 7: 40 MHz -150.2 dBc/Hz

3: 10 kHz -104.8 dBc/Hz 8: 95 MHz -148.6 dBc/Hz

4: 100 kHz -107.5 dBc/Hz 9: 100 MHz -147.6 dBc/Hz

5: 1 MHz -114.7 dBc/Hz

1: 100 Hz -85.5 dBc/Hz 6: 10 MHz -143.2 dBc/Hz

2: 1 kHz -95.6 dBc/Hz 7: 40 MHz -151.5 dBc/Hz

3: 10 kHz -105.6 dBc/Hz 8: 95 MHz -153.8 dBc/Hz

4: 100 kHz -108.7 dBc/Hz 9: 100 MHz -153.8 dBc/Hz

5: 1 MHz -117.3 dBc/Hz

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

-160

-170

-180

-190

-100

-110

-120

-130

-140

-150

-160

-170

-180

-190

15.0 GHz

-4.1 dBm

13.0 GHz

0.1 dBm

1*10^2

1*10^3

1*10^4

1*10^5

1*10^6

1*10^7

1*10^8

1*10^2

1*10^3

1*10^4

1*10^5

1*10^6

1*10^7

1*10^8

Offset (Hz)

D002

D003

f_OSC= 100 MHz

f_PD= 200 MHz

Jitter = 55.8 fs (100 Hz - 100 MHz)

f_OSC= 100 MHz

f_PD= 200 MHz

Jitter = 52.6 fs (100 Hz - 100 MHz)

Figure 3. Closed-Loop Phase Noise at 15 GHz

Figure 4. Closed-Loop Phase Noise at 13 GHz

-30

-40

-30

-40

1: 100 Hz -87.1 dBc/Hz 6: 10 MHz -145.6 dBc/Hz

2: 1 kHz -97.2 dBc/Hz 7: 40 MHz -154.5 dBc/Hz

3: 10 kHz -107.2 dBc/Hz 8: 95 MHz -158.8 dBc/Hz

4: 100 kHz -109.4 dBc/Hz 9: 100 MHz -159.1 dBc/Hz

5: 1 MHz -121.8 dBc/Hz

1: 100 Hz -88.3 dBc/Hz 6: 10 MHz -147.4 dBc/Hz

2: 1 kHz

-98.5 dBc/Hz 7: 40 MHz -154.7 dBc/Hz

-50

3: 10 kHz -108.9 dBc/Hz 8: 95 MHz -155.2 dBc/Hz

4: 100 kHz -111.4 dBc/Hz 9: 100 MHz -155.0 dBc/Hz

5: 1 MHz -123.1 dBc/Hz

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

-160

-170

-180

-190

-100

-110

-120

-130

-140

-150

-160

-170

-180

-190

11.0 GHz

-0.3 dBm

1*10^4

9.0 GHz

1.6 dBm

1*10^2

1*10^3

1*10^4

1*10^5

1*10^6

1*10^7

1*10^8

1*10^2

1*10^3

1*10^5

1*10^6

1*10^7

1*10^8

Offset (Hz)

D004

D005

f_OSC= 100 MHz

f_PD= 200 MHz

Jitter = 46.8 fs (100 Hz - 100 MHz)

f_OSC= 100 MHz

f_PD= 200 MHz

Jitter = 46.9 fs (100 Hz - 100 MHz)

Figure 5. Closed-Loop Phase Noise at 11 GHz

Figure 6. Closed-Loop Phase Noise at 9 GHz

-30

-40

-30

-40

1: 100 Hz -89.6 dBc/Hz 6: 10 MHz -148.3 dBc/Hz

1: 100 Hz -90.1 dBc/Hz 6: 10 MHz -149.3 dBc/Hz

2: 1 kHz -100.4 dBc/Hz 7: 40 MHz -154.8 dBc/Hz

3: 10 kHz -110.6 dBc/Hz 8: 95 MHz -155.1 dBc/Hz

4: 100 kHz -113.7 dBc/Hz 9: 100 MHz -148.5 dBc/Hz

5: 1 MHz -125.1 dBc/Hz

2: 1 kHz

-99.8 dBc/Hz

7: 40 MHz -155.2 dBc/Hz

-50

3: 10 kHz -110.1 dBc/Hz 8: 95 MHz -157.1 dBc/Hz

4: 100 kHz -113.4 dBc/Hz 9: 100 MHz -148.2 dBc/Hz

5: 1 MHz -123.1 dBc/Hz

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

-160

-170

-180

-190

-100

-110

-120

-130

-140

-150

-160

-170

-180

-190

8.0 GHz

5.0 dBm

7.5 GHz

5.3 dBm

1*10^4

1*10^2

1*10^3

1*10^4

1*10^5

1*10^6

1*10^7

1*10^8

1*10^2

1*10^3

1*10^5

1*10^6

1*10^7

1*10^8

Offset (Hz)

D001

D011

f_OSC= 100 MHz

f_PD= 200 MHz

Jitter = 46.87 fs (100 Hz - 100 MHz)

f_OSC= 100 MHz

f_PD= 200 MHz

Jitter = 44.1 fs (100 Hz - 100 MHz)

Figure 7. Closed-Loop Phase Noise at 8 GHz

Figure 8. Closed-Loop Phase Noise at 7.5 GHz

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Typical Characteristics (continued)

-30

12.16

12.14

12.12

12.1

1: 100 Hz -96.7 dBc/Hz 6: 10 MHz -149.5 dBc/Hz

-40

-50

1: -95.988 ns 12.0006 GHz 2: 2 ms 12.1255 GHz

2: 1 kHz -106.8 dBc/Hz 7: 40 MHz -150.9 dBc/Hz

3: 10 kHz -117.0 dBc/Hz 8: 95 MHz -151.1 dBc/Hz

4: 100 kHz -119.7 dBc/Hz 9: 100 MHz -127.8 dBc/Hz

5: 1 MHz -130.6 dBc/Hz

-60

-70

-80

-90

12.08

12.06

12.04

12.02

12

-100

-110

-120

-130

-140

-150

-160

-170

-180

-190

11.98

11.96

3.5 GHz

1.3 dBm

1*10^2

1*10^3

1*10^4

1*10^5

1*10^6

1*10^7

1*10^8

-500 -400 -300 -200 -100

0

100 200 300 400 500

Offset (Hz)

D012

Time (ms)

D010

f_OSC= 100 MHz

f_PD= 200 MHz

f_VCO= 14 GHz

f_OUT= 14 GHz / 4 = 3.5 GHz

Jitter = 49.4 fs (100 Hz - 100 MHz)

Figure 10. VCO Ramping 12-GHz to 12.125-GHz Calibration

Free

Figure 9. Closed-Loop Phase Noise at 3.5 GHz

15

14.5

14

8.5

8

13.5

13

12.5

12

11.5

11

7.5

7

6.5

6

10.5

10

9.5

9

8.5

8

7.5

7

5.5

1: -2.1 ms 3.7177 GHz

2: 2.9 ms 7.5832 GHz

3: 3.7 ms 7.5845 GHz

4: 17.7 ms 6.9996 GHz

5: 31.5 ms 6.9991 GHz

5

4.5

4

3.5

0

1

2

3

4

5

6

7

8

9

10

-10

-5

0

5

10

15

20

25

30

35

40

Time (ms)

D013

D008

The glitches in the plot are due to the inability of the measurement

equipment to track the VCO while calibrating.

CalTime = 33.6 µs = 5.8 µs (Core) + 14 µs (Fcal) + 13.8 µs

(Ampcal)

f_OSC= 200 MHz, f_PD= 100 MHz, f_VCO= 7.5 - 14 GHz, CHDIV = 2

Figure 11. VCO Ramping 7.5-GHz to 15-GHz Triangle Wave

With VCO Calibration

Figure 12. VCO Unassisted Calibration

-80

8.5

8

Flicker (PLL 1/f =-129.2 dBc/Hz)

Flat (FOM = -236.2 dBc/Hz)

-84

Modeled Phase Noise

Measurement

-88

7.5

7

-92

-96

-100

-104

-108

-112

-116

-120

6.5

6

5.5

1: -200 ns 3.4745 GHz

2: 400 ns 7.4476 GHz

3: 1.1 ms 7.4437 GHz

4: 10.2 ms 7.0531 GHz

5: 25 ms 7.0382 GHz

5

4.5

4

3.5

-10

100

1000

10000

100000

D014

-5

0

5

10

15

20

25

30

35

40

Offset (Hz)

Time (ms)

D009

f_VCO= 12 GHz

f_PD= 100 MHz

CalTime = 25.2 µs = 1.3 µs (Core) + 9.1 µs (Fcal) +14.8 µs

(Ampcal)

f_OSC= 200 MHz, f_PD= 100 MHz, f_VCO= 7.5 GHz - 14 GHz, CHDIV

= 2

Figure 13. VCO Calibration With Partial Assist

Figure 14. Calculation of PLL Noise Metrics

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Typical Characteristics (continued)

-80

-88

-80

Fpd=100 MHz

Fpd=200 MHz

Fpd=400 MHz

Ta=25

Ta=-40

Ta=85

-88

-96

-104

-112

-120

-128

-136

-144

-152

-160

-104

-112

-120

-128

-136

-144

-152

-160

10000

100000

1000000

Offset (Hz)

1E+72E+7 5E+71E+8

D016

100

1000

10000

100000 1000000

Offset (Hz)

1E+7 5E+7

D015

f_VCO= 8 GHz, Narrow Loop Bandwidth (<100 Hz)

f_OSC= 200 MHz

f_VCO= 14.8 GHz

Figure 16. VCO Phase Noise Over Temperature

Figure 15. PLL Phase Noise Variation vs. f_PD

2

1.6

1.2

0.8

0.4

0

14

Ta=25

Ta=-40

Ta=85

Resistor Pull-up

Inductor Pull-Up

13

12

11

10

9

8

7

6

-0.4

-0.8

-1.2

-1.6

-2

5

4

3

2

1

0

10000

100000

1000000

Offset (Hz)

1E+72E+7 5E+71E+8

D017

3

4

5

6

7

8

9

10 11 12 13 14 15

Output Frequency (GHz)

D018

Single-Ended Output

OUTx_PWR = 50

Figure 17. CHANGE in 8-GHz VCO Phase Noise Over

Temperature

Figure 18. Output Power Across Frequency

0

-1

-2

-3

-4

-5

-6

-7

-8

-9

14

Ta=-40

Ta=25

Ta=85

13

12

11

10

9

8

7

6

5

4

3

2

1

RF_out = 8 GHz

0

-10

3

4

5

6

7

8

9

10 11 12 13 14 15

0

5

10 15 20 25 30 35 40 45 50 55 60 65

OUTA_PWR

Frequency (GHz)

D019

D030

Single-ended output with resistor pullup and OUTx_PWR = 50.

Note that Near 13.3 to 14.3 GHz, output power can be impacted at

hot temperature. See the Application Information section for more

information.

Resistor pullup

Normalized to maximum output power.

Figure 20. Output Power Normalized To Maximum Across

OUTA_PWR With Resistor Pullup

Figure 19. Output Power vs Temperature

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Typical Characteristics (continued)

-145

-147.5

-150

-152.5

-155

-157.5

-160

-162.5

-165

-167.5

-170

-172.5

-175

0.02

0.1

1

10

Output Frequency (GHz)

D020

This noise adds to the scaled VCO Noise when the channel divider is used.

Figure 21. Additive VCO Divider Noise Floor

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7 Detailed Description

7.1 Overview

The LMX2594 is a high-performance, wideband frequency synthesizer with integrated VCO and output divider.

The VCO operates from 7.5 GHz to 15 GHz, and this can be combined with the output divider to produce any

frequency in the range of 10 MHz to 15 GHz. Within the input path, there are two dividers and a multiplier for

flexible frequency planning. The multiplier also allows the reduction of spurs by moving the frequencies away

from the integer boundary.

The PLL is fractional-N PLL with a programmable delta-sigma modulator up to 4^thorder. The fractional

denominator is a programmable 32-bit long, which can easily provide fine frequency steps below 1-Hz resolution,

or be used to do exact fractions like 1/3, 7/1000, and many others. The phase frequency detector goes up to 300

MHz in fractional mode or 400 MHz in integer mode, although minimum N-divider values must also be taken into

account.

For applications where deterministic or adjustable phase is desired, the SYNC pin can be used to get the phase

relationship between the OSCin and RFout pins deterministic. When this is done, the phase can be adjusted in

very fine steps of the VCO period divided by the fractional denominator.

The ultra-fast VCO calibration is designed for applications where the frequency must be swept or abruptly

changed. The frequency can be manually programmed, or the device can be set up to do ramps and chirps.

The JESD204B support includes using the RFoutB output to create a differential SYSREF output that can be

either a single pulse or a series of pulses that occur at a programmable distance away from the rising edges of

the output signal.

The LMX2594 device requires only a single 3.3-V power supply. The internal power supplies are provided by

integrated LDOs, eliminating the need for high-performance external LDOs.

The digital logic for the SPI interface and is compatible with voltage levels from 1.8 V to 3.3 V.

Table 1 shows the range of several of the dividers, multipliers, and fractional settings.

Table 1. Range of Dividers, Multipliers, and Fractional Settings

PARAMETER

MIN

MAX

COMMENTS

Outputs enabled

0

2

The low noise doubler can be used to increase the

phase detector frequency to improve phase noise and

avoid spurs. This is in reference to the OSC_2X bit.

OSCin doubler

0 (1X)

1 (2X)

Only use the Pre-R divider if the multiplier is used and

the input frequency is too high for the multiplier.

Pre-R divider

Multiplier

1 (bypass)

3

128

7

This is in reference to the MULT word.

The maximum input frequency for the Post-R divider is

250 MHz. Use the Pre-R divider if necessary.

Post-R divider

1 (bypass)

255

The minimum divide depends on modulator order and

VCO frequency. See N-Divider and Fractional Circuitry

for more details.

N divider

≥ 28

524287

The fractional denominator is programmable and can

assume any value between 1 and 2³²–1; it is not a

fixed denominator.

Fractional numerator/

denominator

1 (Integer mode)

0

2³²– 1 = 4294967295

Fractional order

(MASH_ORDER)

Order 0 is integer mode and the order can be

programmed

4

This is the series of several dividers. Also, be aware

that above 10 GHz, the maximum allowable channel

divider value is 6.

Channel divider

1 (bypass)

10 MHz

768

This is implied by the minimum VCO frequency divided

by the maximum channel divider value.

Output frequency

15 GHz

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7.2 Functional Block Diagram

Loop Filter

CPout

Phase

Detector

OSCinP

Vtune

Input

signal

OSCin

Douber

Pre-R

Divider

Post-R

Divider

Multiplier

Charge

Pump

RFoutAP

ϕ

MUX

Vcc

OSCinM

RFoutAM

RFoutBM

Channel

Divider

Sigma-Delta

Modulator

CSB

SCK

SDI

Serial Interface

Control

RFoutBP

N Divider

SYSREF

MUXout

7.3 Feature Description

7.3.1 Reference Oscillator Input

The OSCin pins are used as a frequency reference input to the device. The input is high impedance and requires

AC-coupling caps at the pin. A CMOS clock or XO can drive the single-ended OSCin pins. Differential clock input

is also supported, making it easier to interface with high-performance system clock devices such as TI’s LMK

series clock devices. As the OSCin signal is used as a clock for the VCO calibration, a proper reference signal

must be applied at the OSCin pin at the time of programming FCAL_EN.

7.3.2 Reference Path

The reference path consists of an OSCin doubler (OSC_2X), Pre-R divider, multiplier (MULT) and a Post-R

divider.

OSCin

Douber

Pre-R

Divider

Post-R

Divider

OSCin

Multiplier

Phase Frequency Detector

Figure 22. Reference Path Diagram

The OSCin doubler (OSC_2X) can double up low OSCin frequencies. Pre-R (PLL_R_PRE) and Post-R (PLL_R)

dividers both divide frequency down while the multiplier (MULT) multiplies frequency up. The purposes of adding

a multiplier is to reduce integer boundary spurs or to increase the phase detector frequency. Use Equation 1 to

calculate the phase detector frequency, f_PD

:

f_PD= f_OSC× OSC_2X × MULT / (PLL_R_PRE × PLL_R)

(1)

•

In the OSCin doubler or input multiplier is used, the OSCin signal should have a 50% duty cycle as both the

rising and falling edges are used.

If neither the OSCin doubler nor the input multiplier are used, only rising edges of the OSCin signal are used

and duty cycle is not critical.

The input multiplier and OSCin doubler should not both be used at the same time.

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Feature Description (continued)

7.3.2.1 OSCin Doubler (OSC_2X)

The OSCin doubler allows one to double the input reference frequency up to 400 MHz. This doubler adds

minimal noise and is useful for raising the phase detector frequency for better phase noise and also to avoid

spurs. When the phase-detector frequency is increased, the flat portion of the PLL phase noise improves.

-80

Doubler Disabled, Fpd=100 MHz

Doubler Enabled, Fpd=200 MHz

-84

-88

-92

-96

-100

-104

-108

-112

-116

-120

-124

-128

-132

-136

-140

1x10²

2x10²

5x10²

1x10³

2x10³

5x10³

1x10⁴

2x10⁴

5x10⁴

1x10⁵

2x10⁵

5x10⁵

1x10⁶

Offset (Hz)

tc_O

Figure 23. Benefit of Using the OSC_2X Doubler at 14 GHz

7.3.2.2 Pre-R Divider (PLL_R_PRE)

The Pre-R divider is useful for reducing the input frequency so that the programmable multiplier (MULT) can be

used to help meet the maximum 250-MHz input frequency limitation to the PLL-R divider. Otherwise, it does not

have to be used.

7.3.2.3 Programmable Multiplier (MULT)

The MULT is useful for shifting the phase-detector frequency to avoid integer boundary spurs. The multiplier

allows a multiplication of 3, 4, 5, 6, or 7. Be aware that unlike the doubler, the programmable multiplier degrades

the PLL figure of merit. This only would matter, however, for a clean reference and if the loop bandwidth was

wide.

7.3.2.4 Post-R Divider (PLL_R)

The Post-R divider can be used to further divide down the frequency to the phase detector frequency. When it is

used (PLL_R > 1), the input frequency to this divider is limited to 250 MHz.

7.3.2.5 State Machine Clock

The state machine clock is a divided down version of the OSCin signal that is used internally in the device. This

divide value is 1, 2, 4, or 8, and is determined by CAL_CLK_DIV programming word (described in the

Programming section). This state machine clock impacts various features like the lock detect delay, VCO

calibration, and ramping. The state machine clock is calculated as f_smclk= f_OSC/ 2^CAL_CLK_DIV

.

7.3.3 PLL Phase Detector and Charge Pump

The phase detector compares the outputs of the Post-R divider and N-divider, and generates a correction current

corresponding to the phase error until the two signals are aligned in-phase. This charge-pump current is software

programmable to many different levels, allowing modification of the closed-loop bandwidth of the PLL. See the

Application Information section for more information.

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Feature Description (continued)

7.3.4 N-Divider and Fractional Circuitry

The N-divider includes fractional compensation and can achieve any fractional denominator from 1 to (2³²– 1).

The integer portion of N is the whole part of the N-divider value, and the fractional portion, N_frac= NUM / DEN, is

the remaining fraction. In general, the total N-divider value is determined by N + NUM / DEN. The N, NUM and

DEN are software programmable. The higher the denominator, the finer the resolution step of the output. For

example, even when using f_PD= 200 MHz, the output can increment in steps of 200 MHz / (2³²– 1) = 0.047 Hz.

Equation 2 shows the relationship between the phase detector and VCO frequencies. Note that in SYNC mode,

there is an extra divider that is not shown in Equation 2.

NUM

DEN

≈

’

f_VCO= f_pdì N +

∆

÷

◊

«

(2)

The sigma-delta modulator that controls this fractional division is also programmable from integer mode to fourth

order. To make the fractional spurs consistent, the modulator is reset any time that the R0 register is

programmed.

The N-divider has minimum value restrictions based on the modulator order and VCO frequency. Furthermore,

the PFD_DLY_SEL bit must be programmed in accordance to the Table 2.

Table 2. Minimum N-Divider Restrictions

MASH_ORDER

f_VCO(MHz)

≤ 12500

> 12500

≤ 10000

10000-12500

>12250

MINIMUM N

PFD_DLY_SEL

0

28

32

28

32

36

32

36

40

44

48

1

2

1

2

3

2

3

4

5

6

1

2

3

4

≤ 10000

>10000

≤ 10000

>10000

≤ 10000

>10000

7.3.5 MUXout Pin

The MUXout pin can be used to readback programmable states of the device or for lock detect.

Table 3. MUXout Pin Configurations

MUXOUT_SEL

FUNCTION

Readback

0

1

Lock Detect

7.3.5.1 Lock Detect

The MUXout pin can be configured for lock detect done in by reading back the rb_LD_VTUNE field or using the

pin as shown in the Table 4.

Table 4. Configuring the MUXout Pin for Lock Detect

FIELD

PROGRAMMING

DESCRIPTION

0 = VCO Calibration Status

1 = Indirect Vtune

LD_TYPE

LD_DLY

OUT_MUTE

Select Lock Detect Type.

0 to 65535

Only valid for Vtune lock detect. This is a delay in state machine cycles.

Turns off outputs when lock detect is low.

0 = Disabled

1 = Enabled

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VCO calibration status lock detect works by indicating a low signal on the MUXout pin whenever the VCO is

calibrating or the LD_DLY counter is running. The delay from the LD_DLY is added to the true VCO calibration

time (t_VCOCAL), so it can be used to account for the analog lock time of the PLL.

Indirect Vtune lock detect is based on internally generated voltage that is related to (but not the same as) the

Vtune voltage of the charge pump. It indicates a high signal on MUXout pin or reads back state 2 of

rb_LD_VTUNE when the device is locked.

7.3.5.2 Readback

The MUXout pin can be configured to read back useful information from the device. Common uses for readback

are:

1. Read back registers to ensure that they have been programmed to the correct value.

2. Read back the lock detect status to determine if the PLL is in lock.

3. Read back VCO calibration information so that it can be used to improve the lock time.

4. Read back information to help troubleshoot.

7.3.6 VCO (Voltage-Controlled Oscillator)

The LMX2594 includes a fully integrated VCO. The VCO takes the voltage from the loop filter and converts this

into a frequency. The VCO frequency is related to the other frequencies is shown in Equation 3:

f_VCO= f_PD× N divider

(3)

7.3.6.1 VCO Calibration

To reduce the VCO tuning gain and therefore improve the VCO phase-noise performance, the VCO frequency

range is divided into several different frequency bands. The entire range, 7.5 to 15 GHz, covers an octave that

allows the divider to take care of frequencies below the lower bound. This creates the need for frequency

calibration to determine the correct frequency band given a desired output frequency. The frequency calibration

routine is activated any time that the R0 register is programmed with the FCAL_EN = 1. It is important that a

valid OSCin signal must present before VCO calibration begins.

The VCO also has an internal amplitude calibration algorithm to optimize the phase noise which is also activated

any time the R0 register is programmed.

The optimum internal settings for this are temperature dependent. If the temperature is allowed to drift too much

without being recalibrated, some minor phase noise degradation could result. The maximum allowable drift for

continuous lock, ΔT_CL, is stated in the electrical specifications. For this device, a number of 125°C means the

device never loses lock if the device is operated under the Recommended Operating Conditions.

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The LMX2594 allows the user to assist the VCO calibration. In general, there are three kinds of assistance, as

shown in Table 5:

Table 5. Assisting the VCO Calibration Speed

ASSISTANCE LEVEL

DESCRIPTION

PROGRAMMABLE SETTINGS

User does nothing to improve VCO calibration speed, but the user-specified

VCO_SEL, VCO_DACISET_STRT and VCO_CAPCTRL_STRT values do

affect the starting point of VCO calibration. For oscillation to start up

properly and for VCO to calibrate correctly, TI recommends setting

VCO_SEL = 7, VCO_DACISET_STRT = 300 and VCO_CAPCTRL_STRT =

183 for all frequencies except 11.9 GHz ~ 12.1 GHz. For frequencies within

11.9 ~ 12.1 GHz, user must use VCO_SEL = 4 for proper VCO calibration.

QUICK_RECAL_EN=0

VCO_SEL_FORCE=0

VCO_DACISET_FORCE=0

VCO_CAPCTRL_FORCE=0

No assist

QUICK_RECAL_EN=0

VCO_SEL_FORCE=0

VCO_DACISET_FORCE=0

VCO_CAPCTRL_FORCE=0

Upon every frequency change, before the FCAL_EN bit is checked, the

user provides the initial starting point for the VCO core (VCO_SEL), band

(VCO_CAPCTRL_STRT), and amplitude (VCO_DACISET_STRT) based on

Table 6.

Partial assist

QUICK_RECAL_EN=1

VCO_SEL_FORCE=0

VCO_DACISET_FORCE=0

VCO_CAPCTRL_FORCE=0

Upon initialization of the device, user enables QUICK_RECAL_EN bit.

Close Frequency Assist The VCO uses the current VCO_CAPCTRL and VCO_DACISET_STRT

settings as the initial starting point.

The user forces the VCO core (VCO_SEL), amplitude settings

(VCO_DACISET), and frequency band (VCO_CAPCTRL) and manually

sets the value. If the two frequency points are no more than 5MHz apart

QUICK_RECAL_EN=0

VCO_SEL_FORCE=1

Full assist

and on the same VCO core, the user can set the VCO amplitude and

capcode for any frequency between those two points using linear

interpolation.

VCO_DACISET_FORCE=1

VCO_CAPCTRL_FORCE=1

To do the partial assist for the VCO calibration, follow this procedure:

1. Determine the VCO Core

Find a VCO Core that includes the desired VCO frequency. If at the boundary of two cores, choose one

based on phase noise or performance.

2. Calculate the VCO CapCode as follows:

VCO_CAPCTRL_STRT = round (C_CoreMin– (C_CoreMin– C_CoreMax) × (f_VCO– f_CoreMin) / (f_CoreMax– f_CoreMin))

3. Get the VCO amplitude setting from Table 6.

VCO_DACISET_STRT = round (A_CoreMin+ (A_CoreMax– A_CoreMin) × (f_VCO– f_CoreMin)/(f_CoreMax– f_CoreMin))

Table 6. VCO Core Ranges

VCO CORE

VCO1

f_CoreMin

7500

f_CoreMax

8600

C_CoreMin

164

C_CoreMax

A_CoreMin

299

A_CoreMax

240

12

16

19

0

VCO2

8600

9800

165

356

247

VCO3

9800

10800

12000

12900

13900

15000

158

324

224

VCO4

10800

12000

12900

13900

140

383

244

VCO5

183

36

6

205

146

VCO6

155

242

163

VCO7

175

19

323

244

SPACE

NOTE

In the range of 11900 MHz to 12100 MHz, VCO assistance cannot be used, and the

settings must be: VCO_SEL 4, VCO_DACISET_STRT 300, and

=

VCO_CAPCTRL_STRT = 1. Outside this range, in the partial assist for the VCO

calibration, the VCO calibration runs. This means that if the settings are incorrect, the

VCO still locks with the correct settings. The only consequence is that the calibration time

might be a little longer. The closer the calibration settings are to the true final settings, the

faster the VCO calibration will be.

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7.3.6.2 Determining the VCO Gain

The VCO gain varies between the seven cores and is the lowest at the lowest end of the band and highest at the

highest end of each band. For a more accurate estimation, use Table 7:

Table 7. VCO Gain

CORE

VCO1

VCO2

VCO3

VCO4

VCO5

VCO6

VCO7

f1

f2

Kvco1

73

Kvco2

114

121

132

141

215

218

239

7500

8600

9800

61

9800

10800

12000

12900

13900

15000

98

10800

12000

12900

13900

106

170

172

182

Based on Table 7, Equation 4 can estimate the VCO gain for an arbitrary VCO frequency of f_VCO

:

Kvco = Kvco1 + (Kvco2 – Kvco1) × (f_VCO– f1) / (f2 – f1)

(4)

7.3.7 Channel Divider

To go below the VCO lower bound of 7.5 GHz, the channel divider can be used. The channel divider consists of

four segments, and the total division value is equal to the multiplication of them. Therefore, not all values are

valid.

MUX

RFoutA

Divide by

2 or 3

Divide by

2,4,6,8

Divide by

2,4,6,8,16

1/2

MUX

VCO

MUX

RFoutB

Figure 24. Channel Divider

When the channel divider is used, there are limitations on the values. Table 8 shows how these values are

implemented and which segments are used.

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Table 8. Channel Divider Segments

EQUIVALENT

DIVISION

VALUE

FREQUENCY

LIMITATION

OutMin (MHz)

OutMax (MHz)

CHDIV[4:0]

SEG0

SEG1

SEG2

SEG3

2

4

3750

1875

7500

3750

0

1

2

1

2

1

None

6

1250

2500

2

3

1

8

937.5

1437.5

958.333

718.75

479.167

359.375

239.583

179.6875

159.722

119.792

89.844

59.896

44.922

29.948

22.461

14.974

n/a

3

2

1

12

625

4

2

3

2

1

16

468.75

312.5

5

2

4

1

24

6

2

6

1

32

234.375

156.25

117.1875

104.167

78.125

58.594

39.0625

29.297

19.531

14.648

9.766

7

2

8

1

48

8

2

3

8

1

64

9

2

8

2

72

f_VCO≤ 11.5 GHz

10

11

12

13

14

15

16

17

18-31

2

3

6

2

96

2

3

8

2

128

192

256

384

512

768

Invalid

2

8

4

2

8

6

2

8

2

3

8

2

8

16

n/a

2

3

8

n/a

The channel divider is powered up whenever an output (OUTx_MUX) is selected to the channel divider or

SysRef, regardless of whether it is powered down or not. When an output is not used, TI recommends selecting

the VCO output to ensure that the channel divider is not unnecessarily powered up.

Table 9. Channel Divider

OUTA MUX

Channel Divider

X

OUTB MUX

CHANNEL DIVIDER

Powered up

X

Channel Divider or SYSREF

Powered up

All Other Cases

Powered down

7.3.8 Output Buffer

The RF output buffer type is open collector and requires an external pullup to Vcc. This component may be a 50-

Ω resistor to target 50-Ω output impedance match, or an inductor for higher output power at the expense of the

output impedance being far from 50 Ω. If inductor is used, it is recommended to follow with resistive pad for

better impedance matching. The current to the output buffer increases for states 0 to 31 and then again from

states 48 to 63. States 32 to 47 are redundant and mimic states 16 to 31. If using a resistor, limit the

OUTx_PWR setting to 50. Higher settings may actually reduce power due to the voltage drop across the resistor.

Table 10. OUTx_PWR Recommendations for Resistor Pullup

RECOMMENDATION

f_OUT

COMMENTS

LOWEST NOISE

FLOOR

HIGHEST POWER

OUTx_PWR = 50

OUTx_PWR = 15

OUTx_PWR = 31

10 MHz ≤ f_OUT< 13.3 GHz

13.3 GHz ≤ f_OUT≤ 14.3 GHz

14.3 GHz < f_OUT≤ 15 GHz

OUTx_PWR = 50

OUTx_PWR = 15

OUTx_PWR = 20

-

TI recommends to set OUTx_PWR ≤ 15 to avoid

the power drop at hot temperature.

-

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7.3.9 Power-Down Modes

The LMX2594 can be powered up and down using the CE pin or the POWERDOWN bit. When the device comes

out of the powered down state, either by resuming the POWERDOWN bit to zero or by pulling back CE pin

HIGH, register R0 must be programmed with FCAL_EN high again to re-calibrate the device.

7.3.10 Phase Synchronization

7.3.10.1 General Concept

The SYNC pin allows one to synchronize the LMX2594 such that the delay from the rising edge of the OSCin

signal to the output signal is deterministic. Initially, the devices are locked to the input, but are not synchronized.

The user sends a synchronization pulse that is reclocked to the next rising edge of the OSCin pulse. After a

given time, t₁, the phase relationship from OSCin to f_OUTwill be deterministic. This time is dominated by the sum

of the VCO calibration time, the analog setting time of the PLL loop, and the MASH_RST_CNT if used in

fractional mode.

...

Device 1

SYNC

...

Device 2

...

f_OSC

t₂

t₁

Figure 25. Devices Are Now Synchronized to OSCin Signal

When the SYNC feature is enabled, part of the channel divide may be included in the feedback path. This will be

referred to as IncludedDivide

Table 11. IncludedDivide With VCO_PHASE_SYNC = 1

OUTx_MUX

CHANNEL DIVIDER

Don't Care

INCLUDEDDIVIDE

1

OUTA_MUX = OUTB_MUX = 1 ("VCO")

Divisible by 3, but NOT 24 or 192

All other values

SEG0 × SEG1 = 6

SEG0 × SEG1 = 4

All Other Valid Conditions

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External loop filter

RFoutA

RFoutB

MUX

Pre-R

Divider

R

OSCin

Doubler

X M

Divider

Charge

Pump

SEG0

f

SEG2

SEG1

SEG3

N Divider

Figure 26. Phase SYNC Diagram

7.3.10.2 Categories of Applications for SYNC

The requirements for SYNC depend on certain setup conditions. In cases that the SYNC is not timing critical, it

can be done through software by toggling the VCO_PHASE_SYNC bit from 0 to 1. When it is timing critical, then

it must be done through the pin and the setup and hold times for the OSCin pin are critical. Figure 27 gives the

different categories.

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Start

NO

CHDIV<512

This means the Channel divider

after the VCO is less than 512

CHDIV <512

?

CHDIV = 1,2,4,6

This means the channel divider after the

VCO is either bypassed,2,4, or 6. In this

case, SYNC mode will put it in the loop.

M = 1

M is the product of any input

path multiplication due to the

OSC_2X bit and MULT word.

If neither of these are used,

M=1.

Category 4

Device can NOT be reliably

used in SYNC mode

NO

M = 1

?

CHDIV = 1,2,4,6

?

NO

f_OUT%(M‡ f_OSC)=0

f_OUT% (M‡ f_OSC)= 0

f_OUT% f_OSC= 0

Category 3

ñ SYNC Required

ñ SYNC Timing Critical

ñ Limitations on f_OSC

M is the product of any

input multiplication. This

requirement is testing if

the output frequency is a

multiple of the highest

frequency in the input

path.

This means that the output

frequency (f_OUT) is an integer

multiple of the input frequency

NO

f_OUT% f_OSC= 0

?

(f_OSC

)

CHDIV = 1,2,4,6

This means the channel

divider after the VCO is

either bypassed,2,4, or 6. In

this case, SYNC mode will

put it in the loop.

Category 2

ñ SYNC Required

ñ SYNC Timing NOT critical

ñ No limitations on f_OSC

NO

CHDIV = 1,2,4, 6

?

Integer Mode

This is asking if the device

is in integer mode, which

would mean the fractional

numerator is zero.

YES

NO

Integer Mode

?

Category 1

NO

ñ SYNC Mode Required

ñ No Software/Pin SYNC Pulse

required

CHDIV=1?

Category 1

ñ SYNC Mode Not required at all

ñ No limitations on f_OSC

Figure 27. Determining the SYNC Category

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7.3.10.3 Procedure for Using SYNC

This procedure must be used to put the device in SYNC mode.

1. Use the flowchart to determine the SYNC category.

2. Make determinations for OSCin and using SYNC based on the category.

1. If Category 4, SYNC cannot be performed in this setup.

2. If category 3, ensure that the maximum f_OSCfrequency for SYNC is not violated and there are hardware

accommodations to use the SYNC pin.

3. Determine the value of IncludedDivide:

1. If OUTA_MUX is not channel divider and OUTB_MUX is not channel divider or SysRef, then

IncludedDivide = 1.

2. Otherwise, IncludedDivide = 2 × SEG1. In the case that the channel divider is 2, then IncludedDivide=4.

4. If not done already, divide the N-divider and fractional values by IncludedDivide to account for the

IncludedDivide.

5. Program the device with the VCO_PHASE_SYNC = 1. Note that this does not count as applying a SYNC to

device (for category 2).

6. Apply the SYNC, if required:

1. If category 2, VCO_PHASE_SYNC can be toggled from 0 to 1. Alternatively, a rising edge can be sent to

the SYNC pin and the timing of this is not critical.

2. If category 3, the SYNC pin must be used, and the timing must be away from the rising edge of the

OSCin signal. Toggling the SYNC pin runs VCO calibration when FCAL_EN = 1. If FCAL_EN = 0 then

SYNC pin does not function.

7.3.10.4 SYNC Input Pin

The SYNC input pin can be driven either in CMOS or LVDS mode. However, if not using SYNC mode

(VCO_PHASE_SYNC = 0), then the INPIN_IGNORE bit must be set to one, otherwise it causes issues with lock

detect. If the pin is desired for to be used and VCO_PHASE_SYNC = 1, then set INPIN_IGNORE = 0. LVDS or

CMOS mode may be used. LVDS works to 250 mVPP, but is not ensured in production.

7.3.11 Phase Adjust

The MASH_SEED word can use the sigma-delta modulator to shift output signal phase with respect to the input

reference. If a SYNC pulse is sent (software or pin) or the MASH is reset with MASH_RST_N, then this phase

shift is from the initial phase of zero. If the MASH_SEED word is written to, then this phase is added. Use

Equation 5 to calculate the phase shift.

Phase shift in degrees = 360 × ( MASH_SEED / PLL_DEN) × ( IncludedDivide / CHDIV )

(5)

Example:

Mash seed = 1

Denominator = 12

Channel divider = 16

Phase shift (VCO_PHASE_SYNC = 0) = 360 × (1/12) × (1/16) = 1.875 degrees

Phase Shift (VCO_PHASE_SYNC = 1) = 360 × (1/12) × (4/16) = 7.5 degrees

There are several considerations with phase shift with MASH_SEED:

•

Phase shift can be done with a FRAC_NUM = 0, but MASH_ORDER must be greater than zero. For

MASH_ORDER = 1, the phase shifting only occurs when MASH_SEED is a multiple of PLL_DEN.

•

For the phase adjust, the condition PLL_DEN > PLL_NUM + MASH_SEED must be satisfied.

When MASH_SEED and Phase SYNC are used together with IncludedDivide > 1, additional constraints may

be necessary to produce a monotonic relationship between MASH_SEED and the phase shift, especially

when the VCO frequency is below 10 GHz. These constraints are application specific, but some general

guidelines are to reduce modulator order and increase the N divider. One possible guideline is for PLL_N ≥

45 (2nd order modulator), PLL_N ≥ 49 (3rd Order modulator), PLL_N ≥ 54 (4th Order Modulator).

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7.3.12 Fine Adjustments for Phase Adjust and Phase SYNC

Phase SYNC refers to the process of getting the same phase relationship for every power-up cycle and each

time assuming that a given programming procedure is followed. However, there are some adjustments that can

be made to get the most accurate results. As for the consistency of the phase SYNC, the only source of variation

could be if the VCO calibration chooses a different VCO core and capacitor, which can introduce a bimodal

distribution with about 10 ps of variation. If this 10 ps is not desirable, then it can be eliminated by reading back

the VCO core, capcode, and DACISET values and forcing these values to ensure the same calibration settings

every time. The delay through the device varies from part to part and can be on the order of 60 ps. This part to

part variation can be calibrated out with the MASH_SEED. The variation in delay through the device also

changes on the order of +2.5 ps/°C, but devices on the same board likely have similar temperatures, so this will

somewhat track. In summary, the device can be made to have consistent delay through the part and there are

means to adjust out any remaining errors with the MASH_SEED. This tends only to be an issue at higher output

frequencies when the period is shorter.

7.3.13 Ramping Function

The LMX2594 supports the ability to make ramping waveforms using manual mode or automatic mode. In

manual mode, the user defines a step and uses the RampClk and RampDir pins to create the ramp. In automatic

mode, the user sets up the ramp with up to two linear segments in advance and the device automatically creates

this ramp. Table 12 fields apply in both automatic mode and manual pin mode.

Table 12. Ramping Field Descriptions

FIELD

PROGRAMMING

GENERAL COMMANDS

DESCRIPTION

0 = Disabled

1 = Enabled

RAMP_EN

RAMP_EN must be 1 for any ramping functions to work.

In automatic ramping mode, the ramping is automatic and the

clock is based on the phase detector. In manual pin ramping

mode, the clock is based on rising edges on the RampClk

pin.

0 = Automatic ramping mode

1 = Manual pin ramping mode

RAMP_MANUAL

This is the amount the fractional numerator is increased for

each phase detector cycle in the ramp.

RAMPx_INC

RAMPx_DLY

0 to 2³⁰– 1

0 to 65535

This is the length of the ramp in phase detector cycles.

DEALING WITH VCO CALIBRATION

Whenever the fractional numerator changes this much (either

positive or negative) because the VCO was last calibrated,

the VCO is forced to recalibrate.

RAMP_THRESH

0 to ± 2³³– 1

0 = Disabled

1 = Enabled

When enabled, the VCO is forced to recalibrate at the

beginning each ramp.

RAMP_TRIG_CAL

In ramping mode, the denominator must be fixed to this

PLL_DEN

LD_DLY

4294967295

0

forced value of 2³²– 1. However, the effective denominator in

ramping mode is 2²⁴

.

This must be zero to avoid interfering with calibration.

RAMP LIMITS

2’s complement of the total value of the ramp low and high

limits can never go beyond. If this value is exceeded, then the

frequency is limited.

RAMP_LIMIT_LOW

RAMP_LIMIT_HIGH

0 to ± 2³³– 1

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Table 13. General Restrictions for Ramping

RULE

RESTRICTION

EXPLANATION

Minimum Phase Detector Frequency when Ramping

The phase detector frequency cannot be less than the state machine clock

frequency, which is calculated from expression on the left-hand side of the

inequality. This is satisfied provided there is no division in the input path.

However, if the PLL R-divider is used, it is necessary to adjust CAL_CLK_DIV

to adjust the state machine clock frequency. This also implies a maximum R

f_OSC/2^CAL_CLK_DIV

≤ f_PD

125 MHz

Phase Detector

Frequency

divide of 8 this is the maximum value of 2^CAL_CLK_DIV

.

≤

Maximum Phase Detector Frequency

TI recommends to set the phase-detector frequency ≤ 125 MHz because, if

the phase detector frequency is too high, it can lead to distortion in the ramp.

Higher phase-detector frequency may be possible, but this distortion is

application specific.

7.3.13.1 Manual Pin Ramping

Manual pin ramping is enabled by setting RAMP_EN = 1 and RAMP_MANUAL = 1. The rising edges are applied

to the RampClk pin are reclocked to the phase detector frequency. The RampDir pin controls the size of the

change. If a rising edge is seen on the RampClk pin while the VCO is calibrating, then this rising edge is ignored.

The frequency for the RampClk must be limited to a frequency of 250 kHz or less, and the rising edge of the

RampDir signal must be targeted away from the rising edges of the RampCLK pin.

Table 14. RAMP_INC

RampDir PIN

Low

STEP SIZE

Add RAMP0_INC

Add RAMP1_INC

High

7.3.13.1.1 Manual Pin Ramping Example

In this ramping example, assume that we want to use the pins for UP/Down control of the ramp for 10-MHz steps

and the phase detector is 100 MHz.

Table 15. Step Ramping Example

FIELD

PROGRAMMING

1 = Enabled

DESCRIPTION

RAMP_EN

RAMP_MANUAL

1 = Manual pin ramping mode

(10 MHz )/ (100 MHz) × 16777216 = 1677722

2’s complement = 1677722

RAMP0_INC

1677722

(–10 MHz )/ (100 MHz) × 16777216 = –1677722

2’s complement = 2³⁰– 1677722 = 1072064102

RAMP1_INC

1072064102

1

RAMP_TRIG_CAL

Recalibrate at every clock cycle

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time

Figure 28. Step Ramping Example

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7.3.13.2 Automatic Ramping

Automatic ramping is enabled when RAMP_EN = 1 and RAMP_MANUAL = 0. The action of programming FCAL

= 1 starts the ramping. In this mode, there are two ramps that one can use to set the length and frequency

change. In addition to this, there are ramp limits that can be used to create more complicated waveforms.

Automatic ramping can really be divided into two classes depending on if the VCO must calibrate in the middle of

the ramping waveform or not. If the VCO can go the entire range without calibrating, this is calibration-free

ramping, which is shown in Typical Characteristics. Note that this range is less at hot temperatures and for lower

frequency VCOs. This range is not ensured, so margin must be built into the design.

For waveforms that are NOT calibration free, the slew rate of the ramp must be kept less than 250 kHz/µs. Also,

for all automatic ramping waveforms, be aware that there is a very small phase disturbance as the VCO crosses

over the integer boundary, so one might consider using the input multiplier to avoid these or timing the VCO

calibrations at integer boundaries.

Table 16. Automatic Ramping Field Descriptions

FIELD

PROGRAMMING

DESCRIPTION

Normally, the ramp clock is equal to the phase detector frequency.

When this feature is enabled, it reduces the ramp clock by a factor of

2.

0 = One clock cycle

RAMP_DLY

1 = Two clock cycles

0 to 65535

RAMP0_LEN

RAMP1_LEN

This is the length of the ramp in clock cycles. Note that the VCO

calibration time is added to this time.

RAMP0_INC

RAMP1_INC

0 to 2³⁰– 1

2’s complement of the value for the ramp increment.

Defines which ramp comes after the current ramp.

RAMP0_NEXT

RAMP1_NEXT

0 = RAMP0

1 = RAMP1

0 = Timeout counter

1 = Trigger A

2 = Trigger B

RAMP0_NEXT_TRIG

RAMP1_NEXT_TRIG

Determines what triggers the action of the next ramp occurrence.

3 = Reserved

0 = Disabled

1 = RampClk rising edge

2 = RampDir rising edge

4 = Always triggered

9 = RampClk falling edge

10 = RampDir falling edge

All other States = invalid

RAMP_TRIG_A

RAMP_TRIG_B

This field defines the ramp trigger.

RAMP0_RST

RAMP1_RST

0 = Disabled

1 = Enabled

Enabling this bit causes the ramp to reset to the original value when

the ramping started. This is useful for roundoff errors.

This is the number the ramping pattern repeats and only applies for a

terminating ramping pattern.

RAMP_BURST_COUNT

0 to 8191

0 = Ramp Transition

1 = Trigger A

2 = Trigger B

RAMP_BURST_TRIG

This defines what causes the RAMP_COUNT to increment.

3 = Reserved

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7.3.13.2.1 Automatic Ramping Example (Triangle Wave)

Suppose user wants to generate a sawtooth ramp that goes from 8 to 10 GHz in 2 ms (including calibration

breaks) with a phase-detector frequency of 50 MHz. Divide this into segments of 50 MHz where the VCO ramps

for 25 µs, then calibrates for 25 µs, for a total of 50 µs. There would therefore be 40 such segments which span

over a 2-GHz range and would take 2 ms, including calibration time.

Table 17. Sawtooth Ramping Example

FIELD

PROGRAMMING

1 = Enabled

DESCRIPTION

RAMP_EN

0 = Automatic ramping

mode

RAMP_MANUAL

RAMP_TRIG_CAL

RAMP_THRESH

0 = Disabled

16777216 (= 50-MHz

ramp_thresh)

50 MHz / 50 MHz × 2²⁴= 16777216

RAMP_DLY

RAMPx_LEN

RAMP0_INC

0 = 1 clock cycle

50000

1000 µs × 50 MHz = 50000

(2000 MHz) / (50 MHz) × 2²⁴/ 50000 = 13422

13422

(–2000 MHz) / (50 MHz) × 2²⁴/ 50000 = –13422

RAMP1_INC

1073728402

2’s complement = 2³⁰– 13422 = 1073728402

RAMP0_NEXT

RAMP1_NEXT

1 = RAMP1

0 = RAMP0

RAMPx_NEXT_TRIG

RAMP_TRIG_x

0 = Timeout counter

0 = Disabled

1 = Enabled

0 = Disabled

0

RAMP0_RST

Not necessary, but good practice to reset.

Do not reset this, or ramp does not work.

RAMP1_RST

RAMP_BURST_COUNT

RAMP_BURST_TRIG

0 = Ramp Transition

NOTE

To calculate ramp_scale_count and ramp_dly_cnt, remember that the desired calibration

time is 25 µs.

10

GHz

8 GHz

2 ms

time

4 ms

Figure 29. Triangle Waveform Example

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7.3.14 SYSREF

The LMX2594 can generate a SYSREF output signal that is synchronized to f_OUTwith a programmable delay.

This output can be a single pulse, series of pulses, or a continuous stream of pulses. To use the SYSREF

capability, the PLL must first be placed in SYNC mode with VCO_PHASE_SYNC = 1.

f_OUT

RFoutA

MUX

Rest of Channel

Divider

f_VCO

IncludedDivide

N Divider

To Phase

Detector

Divider

(SYSREF_DIV_PRE)

Divider

(SYSREF_DIV)

1/2

f_SYSREF

Delay Circuit

RFoutB

Re-clocking

Circuit

SysRefReq Pin

Figure 30. SYSREF Setup

As Figure 30 shows, the SYSREF feature uses IncludedDivide and SYSREF_DIV_PRE divider to generate

f_INTERPOLATOR. This frequency is used for reclocking of the rising and falling edges at the SysRefReq pin. In

master mode, the f_INTERPOLATORis further divided by 2 × SYSREF_DIV to generate finite series or continuous

stream of pulses.

Table 18. SYSREF Setup

PARAMETER

f_VCO

MIN

7.5

TYP

MAX

15

UNIT

GHz

f_INTERPOLATOR

IncludedDivide

SYSREF_DIV_PRE

SYSREF_DIV

0.8

1.5

4 or 6

1, 2, or 4

4,6,8, ... , 4098

f_INTERPOLATOR= f_VCO/ (IncludedDivide ×

SYSREF_DIV_PRE)

f_INTERPOLATOR

f_SYSREF

Delay step size

f_SYSREF= f_INTERPOLATOR/ (2 × SYSREF_DIV)

9

ps

Pulses for pulsed mode (SYSREF_PULSE_CNT)

0

15

n/a

The delay can be programmed using the JESD_DAC1_CTRL, JESD_DAC2_CTRL, JESD_DAC3_CTRL, and

JESD_DAC4_CTRL words. By concatenating these words into a larger word called "SYSREFPHASESHIFT", the

relative delay can be found. The sum of these words should always be 63.

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Table 19. SysRef Delay

SYSREFPHASESHIFT

DELAY

JESD_DAC1

JESD_DAC2

JESD_DAC3

JESD_DAC4

0

...

Minimum

36

27

0

36

0

63

1

37

62

...

99

0

63

62

0

1

100

...

161

162

163

225

226

247

> 247

0

1

62

0

63

1

0

62

63

0

62

1

0

Maximum

Invalid

41

22

Invalid

7.3.14.1 Programmable Fields

Table 20 has the programmable fields for the SYSREF functionality.

Table 20. SYSREF Programming Fields

FIELD

PROGRAMMING

DEFAULT

DESCRIPTION

Enables the SYSREF mode. SYSREF_EN

should be 1 if and only if OUTB_MUX = 2

(SysRef).

0: Disabled

1: Enabled

SYSREF_EN

0

1: DIV1

2: DIV2

4: DIV4

SYSREF_DIV_PRE

SYSREF_REPEAT

The output of this divider is f_INTERPOLATOR.

Other states: invalid

In master mode, the device creates a series

of SYSREF pulses. In repeater mode,

SYSREF pulses are generated with the

SysRefReq pin.

0: Master mode

1: Repeater mode

0

Continuous mode continuously makes

SYSREF pulses, where pulsed mode makes

a series of SYSREF_PULSE_CNT pulses.

0: Continuous mode

1: Pulsed mode

SYSREF_PULSE

0

4

In the case of using pulsed mode, this is the

number of pulses. Setting this to zero is an

allowable, but not practical state.

SYSREF_PULSE_CNT

0 to 15

0: Divide by 4

1: Divide by 6

2: Divide by 8

...

This is one of the dividers between the VCO

and SysRef output used in master mode.

SYSREF_DIV

0

2047: Divide by 4098

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7.3.14.2 Input and Output Pin Formats

7.3.14.2.1 Input Format for SYNC and SysRefReq Pins

These pins are single-ended, but a differential signal can be converted to drive them. In the LVDS mode, if the

INPIN_FMT is set to LVDS mode, then the bias level can be adjusted with INPIN_LVL and the hysteresis can be

adjusted with INPIN_HYST.

V_MIN

SYNC / SysRefReq

LMX2594

V_MAX

Figure 31. Driving SYNC/SYSREF With Differential Signal

7.3.14.2.2 SYSREF Output Format

The SYSREF output comes in differential format through RFoutB. This will have a minimum voltage of about 2.3

V and a maximum of 3.3 V. If DC coupling cannot be used, there are two strategies for AC coupling.

3.3 V

SysRefOutP

Data

Converter

SysRefOutN

LMX2594

3.3 V

Figure 32. SYSREF Output

1. Send a series of pulses to establish a DC-bias level across the AC-coupling capacitor.

2. Establish a bias voltage at the data converter that is below the threshold voltage by using a resistive divider.

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7.3.14.3 Examples

The SysRef can be used in a repeater mode (SYSREF_REPEAT = 1), which just echos the SysRefReq pin, after

being reclocked to the f_INTERPOLATORfrequency and then f_OUT(from RFoutA).

RFoutAM

OSCinM

OSCinP

RFoutAP

RFoutBP

RFoutBM

SysRefReq

t₂

t₁

t₂

f

t₁

f

Figure 33. SYSREF Out In Repeater Mode

In master mode (SYSREF_REPEAT = 0), rising and falling edges at the SysRefReq pin are first reclocked to the

f_OSC, then f_INTERPOLATOR, and finally to f_OUT. A programmable number of pulses is generated with a frequency

equal to f_VCO

/ (2 × IncludedDivide × SYSREF_DIV_PRE × SYSREF_DIV). In continuous mode

(SYSREF_PULSE = 0), the SysRefReq pin is held high to generate a continuous stream of pulses. In pulse

mode (SYSREF_PULSE = 1), a finite number of pulses determined by SYSREF_PULSE_CNT is sent for each

rising edge of the SysRefReq pin.

RFoutAM

OSCinM

OSCinP

RFoutAP

RFoutBP

RFoutBM

SysRefReq

f

Figure 34. Figure 1. SYSREF Out In Pulsed/Continuous Mode

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7.3.14.4 SYSREF Procedure

To use SYSREF, do the these steps:

1. Put the device in SYNC mode using the procedure already outlined.

2. Figure out IncludedDivide the same way it is done for SYNC mode.

3. Calculate the SYSREF_DIV_PRE value such that the interpolator frequency (f_INTERPOLATOR) is in the range of

800 to 1500 MHz. f_INTERPOLATOR= f_VCO/IncludedDivide/SYSREF_DIV_PRE. Make this frequency a multiple of

f_OSCif possible.

4. If using continuous mode (SYSREF_PULSE = 0), ensure the SysRefReq pin is high.

5. If using pulse mode (SYSREF_PULSE = 1), set up the pulse count as desired. Pulses are created by

toggling the SysRefReq pin.

6. Adjust the delay between the RFoutA and RFoutB signal using the JESD_DACx_CTL fields.

7.3.15 SysRefReq Pin

The SysRefReq pin can be used in CMOS all the time, or LVDS mode is also optional if SYSREF_REPEAT = 1.

LVDS mode cannot be used in master mode.

7.4 Device Functional Modes

Although there are a vast number of ways to configure this device, only one is really functional.

Table 21. Device Functional Modes

MODE

DESCRIPTION

SOFTWARE SETTINGS

Registers are held in their reset state. This device does have a

power on reset, but it is good practice to also do a software reset if

RESET

there is any possibility of noise on the programming lines, especially RESET = 1, POWERDOWN = 0

if there is sharing with other devices. Also realize that there are

registers not disclosed in the data sheet that are reset as well.

POWERDOWN = 1

POWERDOWN

Normal operating mode

SYNC mode

Device is powered down.

or CE Pin = Low

This is used with at least one output on as a frequency synthesizer.

This is used where part of the channel divider is in the feedback path

VCO_PHASE_SYNC = 1

to ensure deterministic phase.

VCO_PHASE_SYNC =1,

In this mode, RFoutB is used to generate pulses for SYSREF.

SYSREF_EN = 1

SYSREF mode

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7.5 Programming

The LMX2594 is programmed using 24-bit shift registers. The shift register consists of a R/W bit (MSB), followed

by a 7-bit address field and a 16-bit data field. For the R/W bit, 0 is for write, and 1 is for read. The address field

ADDRESS[6:0] is used to decode the internal register address. The remaining 16 bits form the data field

DATA[15:0]. While CSB is low, serial data is clocked into the shift register upon the rising edge of clock (data is

programmed MSB first). When CSB goes high, data is transferred from the data field into the selected register

bank. See Figure 1 for timing details.

7.5.1 Recommended Initial Power-Up Sequence

For the most reliable programming, TI recommends this procedure::

1. Apply power to device.

2. Program RESET = 1 to reset registers.

3. Program RESET = 0 to remove reset.

4. Program registers as shown in the register map in REVERSE order from highest to lowest.

5. Wait 10 ms.

6. Program register R0 one additional time with FCAL_EN = 1 to ensure that the VCO calibration runs from a

stable state.

7.5.2 Recommended Sequence for Changing Frequencies

The recommended sequence for changing frequencies is as follows:

1. Change the N-divider value.

2. Program the PLL numerator and denominator.

3. Program FCAL_EN (R0[3]) = 1.

7.5.3 General Programming Requirements

Follow these requirements when programming the device:

1. For register bits that do not have field names in Table 23, it is necessary to program these values just as

shown in the register map.

2. Not all registers need to be programmed. Refer to Table 22 for details.

3. Power-on-reset register values may not be optimal, so it is always necessary to program all of the required

registers after powering on the device. Note that the 'Reset' column in register descriptions is the power-on-

reset value.

Table 22. Programming Requirement

Registers

Function

Comment

R107 – R112

Readback

These registers are for readback only and do not need to be programmed.

If ramping function is not used (RAMP_EN = 0), then these registers do not need to be

programmed.

R79 – R106

R0 – R78

Ramping

General

These registers need to be programmed for all scenarios.

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7.6.1 General Registers R0, R1, & R7

Figure 35. Registers Excluding Address

Addre

ss

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

VCO_

PHAS

E_SY

NC_E

N

MUX

POW

ERDO

WN

RAMP

_EN

OUT_ FCAL_HPFD_ FCAL_LPFD_

FCAL OUT_ RESE

_EN LD_S

EL

R0

1

0

1

MUTE

ADJ

T

R1

R7

0

1

0

1

0

1

0

1

0

CAL_CLK_DIV

1

OUT_

FORC

E

0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 24. Field Descriptions

Location Field

Type

Reset

Description

R0[15]

R0[14]

R0[9]

RAMP_EN

R/W

0

0: Disable frequency ramping mode

1: Enable frequency ramping mode

VCO_PHASE_SYNC

OUT_MUTE

R/W

0

0: Disable phase SYNC mode

1: Enable phase SYNC mode

Mute the outputs when the VCO is calibrating.

0: Disabled. If disabled, also be sure to enable OUT_FORCE

1: Enabled. If enabled, also be sure to disable OUT_FORCE

R0[8:7]

FCAL_HPFD_ADJ

R/W

Set this field in accordance to the phase-detector frequency for

optimal VCO calibration.

0: f_PD≤ 100 MHz

1: 100 MHz < f_PD≤ 150 MHz

2: 150 MHz < f_PD≤ 200 MHz

3: f_PD>200 MHz

R0[6:5]

FCAL_LPFD_ADJ

R/W

0

Set this field in accordance to the phase detector frequency for

optimal VCO calibration.

0: f_PD≥ 10 MHz

1: 10 MHz > f_PD≥ 5 MHz

2: 5 MHz > f_PD≥ 2.5 MHz

3: f_PD< 2.5 MHz

R0[3]

R0[2]

FCAL_EN

R/W

0

Enable the VCO frequency calibration. Also note that the action

of programming this bit to a 1 activates the VCO calibration

MUXOUT_LD_SEL

Selects the state of the function of the MUXout pin

0: Readback

1: Lock detect

R0[1]

RESET

R/W

0

Resets and holds all state machines and registers to default

value.

0: Normal operation

1: Reset

R0[0]

POWERDOWN

CAL_CLK_DIV

R/W

0

3

Powers down entire device

0: Normal operation

1: Powered down

R1[2:0]

Sets divider for VCO calibration state machine clock based on

input frequency.

0: Divide by 1. Use for f_OSC≤ 200 MHz

1: Divide by 2. Use for f_OSC≤ 400 MHz

2: Divide by 4. Use for f_OSC≤ 800 MHz

3: Divide by 8. All f_OSC

If user is not concerned with lock time, it is recommended to set

this value to 3. By slowing down the VCO calibration, the best

and most repeatable VCO phase noise can be attained

R7[14]

OUT_FORCE

R/W

0

Works with OUT_MUTE in disabling outputs when VCO

calibrating.

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7.6.2 Input Path Registers

Figure 36. Registers Excluding Address

D15

D14

D13

D12

D11

D10

D9

1

D8

D7

D6

0

D5

0

D4

0

D3

D2

D1

D0

OSC_

2X

R9

0

1

0

1

0

R10

R11

R12

0

1

0

1

0

1

MULT

1

0

1

0

PLL_R

PLL_R_PRE

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 25. Field Descriptions

Location Field

Type

Reset

Description

R9[12]

OSC_2X

R/W

0

Low=noise OSCin frequency doubler.

0: Disabled

1: Enabled

R10[11:7] MULT

R/W

1

Programmable input frequency multiplier

0,2,,8-31: Reserved

1: Byapss

3: 3X

...

7: 7X

R11[11:4] PLL_R

R/W

1

Programmable input path divider after the programmable input

frequency multiplier.

R12[11:0] PLL_R_PRE

Programmable input path divider before the programmable input

frequency multiplier.

7.6.3 Charge Pump Registers (R13, R14)

Figure 37. Registers Excluding Address

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

R14

0

1

0

CPG

0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 26. Field Descriptions

Location Field

Type

Reset

Description

R14[6:4] CPG

R/W

7

Effective charge-pump current. This is the sum of up and down

currents.

0: 0 mA

1: 6 mA

2: Reserved

3: 12 mA

4: 3 mA

5: 9 mA

6: Reserved

7: 15 mA

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7.6.4 VCO Calibration Registers

Figure 38. Registers Excluding Address

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

R4

R8

ACAL_CMP_DLY

0

1

0

1

VCO_

DACI

SET_

FORC

E

VCO_

CAPC

0

1

0

TRL_

FORC

E

0

R16

R17

R19

0

1

0

1

0

1

VCO_DACISET

VCO_DACISET_STRT

VCO_CAPCTRL

1

0

VCO_

SEL_

FORC

E

R20

1

VCO_SEL

0

1

0

1

0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 27. Field Descriptions

Location Field

Type

Reset

Description

R4[15:8] ACAL_CMP_DELAY

R/W

10

VCO amplitude calibration delay. Lowering this value can speed

up VCO calibration, but lowering it too much may degrade VCO

phase noise. The minimum allowable value for this field is 10

and this allows the VCO to calibrate to the correct frequency for

all scenarios. To yield the best and most repeatable VCO phase

noise, this relationship should be met: ACAL_CMP_DLY >

Fsmclk / 10 MHz, where Fsmclk = Fosc / 2^CAL_CLK_DIVand Fosc

is the input reference frequency. If calibration time is of concern,

then it is recommended to set this register to ≥ 25.

R8[14]

R8[11]

VCO_DACISET_FORCE

VCO_CAPCTRL_FORCE

R/W

0

This forces the VCO_DACISET value

This forces the VCO_CAPCTRL value

0

R16[8:0] VCO_DACISET

128

This sets the final amplitude for the VCO calibration in the case

that amplitude calibration is forced.

R17[8:0] VCO_DACISET_STRT

R/W

250

This sets the initial starting point for the VCO amplitude

calibration.

R19[7:0] VCO_CAPCTRL

R20[13:11] VCO_SEL

R/W

183

7

This sets the final VCO band when VCO_CAPCTRL is forced.

This sets VCO start core for calibration and the VCO when it is

forced.

0: Not Used

1: VCO1

2: VCO2

3: VCO3

4: VCO4

5: VCO5

6: VCO6

7: VCO7

R20[10] VCO_SEL_FORCE

R/W

0

This forces the VCO to use the core specified by VCO_SEL. It is

intended mainly for diagnostic purposes.

0: Disabled (recommended)

1: Enabled

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7.6.5 N Divider, MASH, and Output Registers

Figure 39. Registers Excluding Address

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

R34

R36

0

PLL_N[18:16]

PLL_N

MASH

_SEE

D

R37

0

PFD_DLY_SEL

0

1

0

_EN

R38

R39

R40

R41

R42

R43

PLL_DEN[31:16]

PLL_DEN[15:0]

[31:16]

[15:0]

PLL_NUM[31:16]

PLL_NUM[15:0]

MASH

_RES

ET_N

OUTB OUTA

R44

0

OUTA_PWR

0

1

0

MASH_ORDER

_PD

R45

R46

1

0

1

0

OUTA_MUX

OUT_ISET

0

1

OUTB_PWR

0

1

OUTB_MUX

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 28. Field Descriptions

Location Field

Type

Reset

Description

R34[2:0] PLL_N

R36[15:0]

R/W

100

The PLL_N divider value is in the feedback path and divides the

VCO frequency.

R37[15] MASH_SEED_EN

R/W

0

2

Enabling this bit allows the to be applied to shift the phase at the

output or optimize spurs.

R37[13:8] PFD_DLY_SEL

The PFD_DLY_SEL must be adjusted in accordance to the N-

divider value. This is with the functional description for the N-

divider.

R38[15:0] PLL_DEN

R39[15:0]

R/W

42949672 The fractional denominator.

95

R40[15:0] MASH_SEED

R41[15:0]

0

The initial state of the MASH engine first accumulator. Can be

used to shift phase or optimize fractional spurs. Every time the

field is programmed, it ADDS this MASH seed to the existing

one. To reset it, use the MASH_RESET_N bit.

R42[15:0] PLL_NUM

R43[15:0]

R/W

0

The fractional numerator

R44[13:8] OUTA_PWR

31

1

Adjusts output power. Higher numbers give more output power

to a point, depending on the pullup component used.

R44[7]

R44[6]

R44[5]

OUTB_PD

Powers down output B

0: Output B active

1: Output B powered down

OUTA_PD

R/W

0

1

0

Powers down output A

0: Output A Active

1: Output A powered down

MASH_RESET_N

Resets MASH circuitry to an initial state

0: MASH held in reset. All fractions are ignored

1: Fractional mode enabled. MASH is NOT held in reset.

R44[2:0] MASH_ORDER

Sets the MASH order

0: Integer mode

1: First order modulator

2: Second order modulator

3: Third order modulator

4: Fourth order modulator

5-7: Reserved

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Table 28. Field Descriptions (continued)

Location Field

Type

Reset

Description

R45[12:11] OUTA_MUX

R/W

1

Selects what signal goes to RFoutA

0: Channel divider

1: VCO

2: Reserved

3: High impedance

R45[10:9] OUT_ISET

R/W

0

Setting to a lower value allows slightly higher output power at

higher frequencies at the expense of higher current

consumption.

0: Maximum output power boost

...

3: No output power boost

R45[5:0] OUTB_PWR

R46[1:0] OUTB_MUX

R/W

31

1

Output power setting for RFoutB.

Selects what signal goes to RFoutB

0: Channel divider

1: VCO

2: SysRef (also ensure SYSREF_EN=1)

3: High impedance

7.6.6 SYNC and SysRefReq Input Pin Register

Figure 40. Registers Excluding Address

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

INPIN INPIN

_IGN _HYS

R58

INPIN_LVL

INPIN_FMT

0

1

ORE

T

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 29. Field Descriptions

Location Field

Type

Reset

Description

R58[15] INPIN_IGNORE

R/W

1

Ignore SYNC and SysRefReq Pins

0: Pins are used. Only valid for VCO_PHASE_SYNC = 1

1: Pin is ignored

R58[14] INPIN_HYST

R58[13:12] INPIN_LVL

R/W

0

High Hysteresis for LVDS mode

0: Disabled

1: Enabled

Sets bias level for LVDS mode. In LVDS mode, a voltage divider

can be inserted to reduce susceptibility to common-mode noise

of an LVDS line because the input is single-ended. With a

reasonable setup, TI recommends using INPIN_LVL = 1 (Vin) to

use the entire signal swing of an LVDS line.

0: Vin/4

1: Vin

2: Vin/2

3: Invalid

R58[11:9] INPIN_FMT

R/W

0

0: SYNC = SysRefReq = CMOS

1: SYNC = LVDS, SysRefReq=CMOS

2: SYNC = CMOS, SysRefReq = LVDS

3: SYNC = SysRefReq = LVDS

4: Invalid

5: Invalid

6: Invalid

7: Invalid

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7.6.7 Lock Detect Registers

Figure 41. Registers Excluding Address

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

LD_T

YPE

R59

R60

0

LD_DLY

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 30. Field Descriptions

Location Field

Type

Reset

Description

R59[0]

LD_TYPE

R/W

1

Lock detect type

0: VCO calibration status

1: VCO calibration status and Indirect Vtune

R60[15:0] LD_DLY

R/W

1000

Lock Detect Delay. This is the delay added to the lock detect

after the VCO calibration is successful and before the lock

detect is asserted high. The delay added is in phase-detector

cycles. If set to 0, the lock detect immediately becomes high

after the VCO calibration is successful.

7.6.8 MASH_RESET

Figure 42. Registers Excluding Address

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

R69

R70

MASH_RST_COUNT[31:16]

MASH_RST_COUNT[15:0]

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 31. Field Descriptions

Location Field

Type

Reset

Description

R69[15:0] MASH_RST_COUNT

R70[15:0]

R/W

50000

If the designer does not use this device in fractional mode with

VCO_PHASE_SYNC = 1, then this field can be set to 0. In

phase-sync mode with fractions, this bit is used so that there is a

delay for the VCO divider after the MASH is reset. This delay

must be set to greater than the lock time of the PLL. It does

impact the latency time of the SYNC feature.

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7.6.9 SysREF Registers

Figure 43. Registers Excluding Address

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SYSR

EF_R

EPEA

T

SYSR SYSR

EF_P EF_E

R71

0

SYSREF_DIV_PRE

0

1

ULSE

N

R72

R73

R74

0

SYSREF_DIV

JESD_DAC2_CTRL

JESD_DAC4_CTRL

JESD_DAC1_CTRL

JESD_DAC3_CTRL

SYSREF_PULSE_CNT

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 32. Field Descriptions

Location Field

Type

Reset

Description

R71[7:5] SYSREF_DIV_PRE

R/W

4

Pre-divider for SYSREF

1: Divide by 1

2: Divide by 2

4: Divide by 4

All other states: invalid

R71[4]

SYSREF_PULSE

R/W

0

Enable pulser mode in master mode

0: Disabled

1: Enabled

R71[3]

R71[2]

SYSREF_EN

R/W

0

Enable SYSREF

SYSREF_REPEAT

Enable repeater mode

0: Master mode

1: Repeater mode

R72[10:0] SYSREF_DIV

R/W

0

Divider for the SYSREF

0: Divide by 4

1: Divide by 6

2: Divide by 8

...

2047: Divide by 4098

R73[5:0] JESD_DAC1_CTRL

R73[11:6] JESD_DAC2_CTRL

R74[5:0] JESD_DAC3_CTRL

R74[11:6] JESD_DAC4_CTRL

R74[15:12] SYSREF_PULSE_CNT

R/W

63

0

These are the adjustments for the delay for the SYSREF. Two of

these must be zero and the other two values must sum to 63.

0

Number of pulses in pulse mode in master mode

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7.6.10 CHANNEL Divider Registers

Figure 44. Registers Excluding Address

Reg

15

0

14

13

0

12

0

11

0

10

0

9

1

8

1

7

1

6

1

5

1

4

0

3

1

2

1

0

R31

R75

CHDIV

_DIV2

0

1

CHDIV

0

Table 33. Field Descriptions

Location Field

Type

Reset

Description

R31[14] SEG1_EN

R/W

0

Enable driver buffer for CHDIV > 2

0: Disabled (only valid for CHDIV = 2)

1: Enabled (use for CHDIV > 2)

R75[10:6] CHDIV

R/W

0

VCO divider value

0: 2

1: 4

2: 6

3: 8

4: 12

5: 16

6: 24

7: 32

8: 48

9: 64

10: 72

11: 96

12: 128

13: 192

14: 256

15: 384

16: 512

17: 768

18-31: Reserved

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7.6.11 Ramping and Calibration Fields

Figure 45. Registers Excluding Address

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

RAMP

_THR

ESH[3

2]

QUIC

K_RE

CAL_

EN

R78

0

VCO_CAPCTRL_STRT

1

R79

R80

RAMP_THRESH[31:16]

RAMP_THRESH[15:0]

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 34. Field Descriptions

Location Field

Type

Reset

Description

R78[11] RAMP_THRESH

R79[15:0]

R80[15:0]

R/W

0

This sets how much the ramp can change the VCO frequency

before calibrating. If this frequency is chosen to be Δf, then it is

calculated as follows:

RAMP_THRESH = (Δf / f_PD) × 16777216

R78[9]

QUICK_RECAL_EN

R/W

0

Causes the initial VCO_CORE, VCO_CAPCTRL, and

VCO_DACISET to be based on the last value. Useful if the

frequency change is small, as is often the case for ramping.

0: Disabled

1: Enabled

R78[8:1] VCO_CAPCTRL_STRT

This sets the initial value for VCO_CAPCTRL if not overridden

by other settings. Smaller values yield a higher frequency band

within a VCO core. Valid number range is 0 to 183.

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7.6.12 Ramping Registers

These registers are only relevant for ramping functions and are enabled if and only if RAMP_EN (R0[15]) = 1.

7.6.12.1 Ramp Limits

Figure 46. Registers Excluding Address

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

RAMP

_LIMI

T_HIG

H[32]

R81

0

R82

R83

RAMP_LIMIT_HIGH[31:16]

RAMP_LIMIT_HIGH[15:0]

RAMP

_LIMI

T_LO

W[32]

R84

0

R85

R86

RAMP_LIMIT_LOW[31:16]

RAMP_LIMIT_LOW[15:0]

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 35. Field Descriptions

Location Field

Type

Reset

Description

R81[0]

R82[15:0]

R83[15:0]

RAMP_LIMIT_HIGH

R/W

0

This sets a maximum frequency that the ramp can not exceed

so that the VCO does not get set beyond a valid frequency

range. Suppose f_HIGHis this frequency and f_VCOis the starting

VCO frequency then:

For f_HIGH≥ f_VCO

:

RAMP_LIMIT_HIGH = (f_HIGH– f_VCO)/f_PD× 16777216

For f_HIGH< f_VCOthis is not a valid condition to choose.

R84[0]

R85[15:0]

R86[15:0]

RAMP_LIMIT_LOW

R/W

0

This sets a minimum frequency that the ramp can not exceed so

that the VCO does not get set beyond a valid frequency range.

Suppose f_LOWis this frequency and f_VCOis the starting VCO

frequency then:

For f_LOW≤ f_VCO

:

RAMP_LIMIT_LOW = 2³³– 16777216 x (f_VCO– f_LOW) / f_PD

For f_LOW> f_VCO, this is not a valid condition to choose.

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7.6.12.2 Ramping Triggers, Burst Mode, and RAMP0_RST

Figure 47. Registers Excluding Address

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

RAMP

_BUR

ST_E

N

R96

R97

RAMP_BURST_COUNT

0

RAMP

0_RS

T

RAMP_BURS

T_TRIG

0

1

RAMP_TRIGB

RAMP_TRIGA

0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 36. Field Descriptions

Location Field

Type

Reset

Description

R96[15] RAMP_BURST_EN

R/W

0

Enables burst ramping mode. In this mode, a

RAMP_BURST_COUNT ramps are sent out when RAMP_EN is

set from 0 to 1.

0: Disabled

1: Enabled

RAMP96[1 RAMP_BURST_COUNT

4:2]

R/W

0

Sets how many ramps are run in burst ramping mode.

R97[15] RAMP0_RST

Resets RAMP0 at start of ramp to eliminate round-off errors.

Must only be used in automatic ramping mode.

0: Disabled

1: Enabled

R97[6:3] RAMP_TRIGA

R/W

0

Multipurpose Trigger A definition:

0: Disabled

1: RampClk pin rising edge

2: RampDir pin rising edge

4: Always triggered

9: RampClk pin falling edge

10: RampDir pin falling edge

All other states: reserved

R97[10:7] RAMP_TRIGB

Multipurpose trigger B definition:

0: Disabled

1: RampClk pin Rising Edge

2: RampDir pin Rising Edge

4: Always Triggered

9: RampClk pin Falling Edge

10: RampDir pin Falling Edge

All other states: Reserved

R97[1:0] RAMP_BURST_TRIG

Ramp burst trigger definition that triggers the next ramp in the

count. Note that RAMP_EN starts the count, not this word.

0: Ramp Transition

1: Trigger A

2: Trigger B

3: Reserved

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7.6.12.3 Ramping Configuration

Figure 48. Registers Excluding Address

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

RAMP

0_DL

Y

R98

RAMP0_INC[29:16]

0

R99

RAMP0_INC[15:0]

RAMP0_LEN

R100

RAMP

RAMP RAMP

0

_NEX

T

RAMP0_

NEXT_TRIG

R101

0

1

0

_DLY _RST

R102

R103

R104

RAMP1_INC[29:16]

RAMP1_INC[15:0]

RAMP1_LEN

RAMP

_MAN

UAL

1

_NEX

T

RAMP1_

NEXT_TRIG

R105

RAMP_DLY_CNT

0

RAMP

_TRIG

_CAL

RAMP_SCALE_COUN

T

R106

0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 37. Field Descriptions

Location Field

Type

Reset

Description

R98[15:2] RAMP0_INC

R99[15:0]

R/W

0

2's complement of the amount the RAMP0 is incremented in

phase detector cycles.

R98[0]

RAMP0_DLY

R/W

0

Enabling this bit uses two clocks instead of one to clock the

ramp. Effectively doubling the length.

0: Normal ramp length

1: Double ramp length

R100[15:0] RAMP0_LEN

R101[6] RAMP1_DLY

R/W

0

Length of RAMP0 in phase detector cycles

Enabling this bit uses two clocks instead of one to clock the

ramp. Effectively doubling the length.

0: Normal ramp length

1: Double ramp length

R101[5] RAMP1_RST

R/W

0

Resets RAMP1 to eliminate rounding errors. Must be used in

automatic ramping mode.

0: Disabled

1: Enabled

R101[4] RAMP0_NEXT

R/W

0

Defines what ramp comes after RAMP0

0: RAMP0

1: RAMP1

R101[1:0] RAMP0_NEXT_TRIG

Defines what triggers the next ramp

0: RAMP0_LEN timeout counter

1: Trigger A

2: Trigger B

3: Reserved

R102[13:0] RAMP1_INC

R103[15:0]

R/W

0

2's complement of the amount the RAMP1 is incremented in

phase detector cycles.

R104[15:0] RAMP1_LEN

R/W

0

Length of RAMP1 in phase detector cycles

R105[15:6] RAMP_DLY_CNT

This is the number of state machine clock cycles for the VCO

calibration in automatic mode. If the VCO calibration is less, then

it is this time. If it is more, then the time is the VCO calibration

time.

R105[5] RAMP_MANUAL

R/W

0

Enables manual ramping mode, or otherwise automatic mode

0: Automatic ramping mode

1: Manual ramping mode

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Table 37. Field Descriptions (continued)

Location Field

Type

Reset

Description

R105[4] RAMP1_NEXT

R/W

0

Determines what ramp comes after RAMP1:

0: RAMP0

1: RAMP1

R105[1:0] RAMP1_NEXT_TRIG

R/W

0

Defines what triggers the next ramp

0: RAMP1_LEN timeout counter

1: Trigger A

2: Trigger B

3: Reserved

R106[4] RAMP_TRIG_CAL

R/W

0

7

Enabling this bit forces the VCO to calibrate after the ramp.

Multiplies RAMP_DLY count by 2^{RAMP_SCALE_COUNT}

R106[2:0] RAMP_SCALE_COUNT

7.6.13 Readback Registers

Figure 49. Registers Excluding Address

D15

D14

D13

D12

D11

D10

rb_LD_

VTUNE

D9

D8

0

D7

D6

D5

D4

D3

D2

D1

D0

R110

0

rb_VCO_SEL

0

R111

R112

0

rb_VCO_CAPCTRL

rb_VCO_DACISET

0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 38. Field Descriptions

Location Field

Type

Reset

Description

R110[10:9] rb_LD_VTUNE

R

0

Readback of Vtune lock detect

0: Unlocked (Vtune low)

1: Invalid State

2: Locked

3: Unlocked (Vtune High)

R110[7:5] rb_VCO_SEL

R

0

Reads back the actual VCO that the calibration has selected.

0: Invalid

1: VCO1

...

7: VCO7

R111[7:0] rb_VCO_CAPCTRL

R112[8:0] rb_VCO_DACISET

R

183

170

Reads back the actual CAPCTRL capcode value the VCO

calibration has chosen.

Reads back the actual amplitude (DACISET) value that the VCO

calibration has chosen.

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 OSCin Configuration

The OSCin supports single-ended or differential clocks. There must be a AC-coupling capacitor in series before

the device pin. The OSCin inputs are high-impedance CMOS with internal bias voltage. TI recommends putting

termination shunt resistors to terminate the differential traces (if there are 50-Ω characteristic traces, place 50-Ω

resistors). The OSCin and OSCin* side should be matched in layout. A series AC-coupling capacitors should

immediately follow OSCin pins in the board layout, then the shunt termination resistors to ground should be

placed after.

Input clock definitions are shown in Figure 50:

V_OSCin

CMOS

Sine wave

Differential

Figure 50. Input Clock Definitions

8.1.2 OSCin Slew Rate

The slew rate of the OSCin signal can impact the spurs and phase noise of the LMX2594 if it is too low. In

general, a high slew rate and a lower amplitude signal, such as LVDS, can give best performance.

8.1.3 RF Output Buffer Power Control

The OUTA_PWR and OUTB_PWR registers can be used to control the output power of the output buffers. The

setting for optimal power may depend on the pullup component, but is typically around 50. The higher the setting,

the higher the current consumption of the output buffer.

8.1.4 RF Output Buffer Pullup

The choice of output buffer components is very important and can have a profound impact on the output power.

Table 39 shows how to treat each pin. If using a single-ended output, a pullup is required, and the user can put a

50-Ω resistor after the capacitor.

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Application Information (continued)

Table 39. Different Methods for Pullup on Outputs

PULLUP STYLE

DIAGRAM

COMMENTS

+v_cc

Potentially higher output power,

but output impedance is far from

50 Ω. Consider also using with a

resistive pad.

L

Inductor

C

RFoutAP

+v_cc

R

Resistor

More consistent matching

C

RFoutAP

Table 40. Output Pullup Configuration

COMPONENT

Inductor

VALUE

Varies with frequency

50 Ω

PART NUMBER

Resistor

Vishay FC0402E50R0BST1

ATC 520L103KT16T

ATC 504L50R0FTNCFT

Capacitor

Varies with frequency

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8.2.1 Design Requirements

The design of the loop filter is complex and is typically done with software. The PLLATINUM™ Sim software is

an excellent resource for doing this and the design is shown in the Figure 52. For those interested in the

equations involved, the PLL Performance, Simulation, and Design Handbook listed in the end of this document

goes into great detail as to the theory and design of PLL loop filters.

Figure 52. PLLATINUM™ Sim Design Screen

8.2.2 Detailed Design Procedure

The integration of phase noise over a certain bandwidth (jitter) is an performance specification that translates to

signal-to-noise ratio. Phase noise inside the loop bandwidth is dominated by the PLL, while the phase noise

outside the loop bandwidth is dominated by the VCO. Generally, jitter is lowest if the loop bandwidth is designed

to the point where the two intersect. A higher phase margin loop filter design has less peaking at the loop

bandwidth and thus lower jitter. The tradeoff with this is that longer lock times and spurs must be considered in

design as well.

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8.2.3 Application Curve

Figure 53. Typical Jitter

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9 Power Supply Recommendations

If fractional spurs are a large concern, using a ferrite bead to each of these power supply pins can reduce spurs

to a small degree. This device has integrated LDOs, which improves the resistance to power supply noise.

However, the pullup components on the RFoutA and RFoutB pins on the outputs have a direct connection to the

power supply, take extra care to ensure that the voltage is clean for these pins. Figure 54 is a typical application

example.

This device can be powered by an external DC-DC buck converter, such as the TPS62150. Note that although

Rtps, Rtps1, and Rtps2 are 0 Ω in the schematic, they could be potentially replaced with a larger resistor value or

inductor value for better power supply filtering.

Figure 54. Using the TPS62150 as a Power Supply

For DC bias levels, refer to .

Table 41. Bias Levels of Pins

(1)

Pin Number

Pin Name

VBIASVCO

VBIASVCO2

VREFVCO2

VBIASVARAC

VREFVCO

Bias Level

3

1.3

0.7

2.9

1.7

2.9

2.1

27

29

33

36

38

VREGVCO

(1) The bias level is measured after following Recommended Initial Power-Up Sequence.

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10 Layout

10.1 Layout Guidelines

In general, the layout guidelines are similar to most other PLL devices. Here are some specific guidelines.

•

GND pins may be routed on the package back to the DAP.

The OSCin pins are internally biased and must be AC-coupled.

If not used, RampClk, RampDir, and SysRefReq can be grounded to the DAP.

For the Vtune pin, try to place a loop filter capacitor as close as possible to the pin. This may mean

separating the capacitor from the rest of the loop filter.

•

For the outputs, keep the pullup component as close as possible to the pin and use the same component on

each side of the differential pair.

If a single-ended output is needed, the other side must have the same loading and pullup. However, the

routing for the used side can be optimized by routing the complementary side through a via to the other side

of the board. On this side, use the same pullup and make the load look equivalent to the side that is used.

•

Ensure that DAP on device is well-grounded with many vias, preferably copper filled.

Have a thermal pad that is as large as the LMX2594 exposed pad. Add vias to the thermal pad to maximize

thermal performance.

•

Use a low loss dielectric material, such as Rogers 4003, for optimal output power.

See instructions for the LMX2594EVM (LMX2594 EVM Instructions, 15 GHz Wideband Low Noise PLL With

Integrated VCO) for more details on layout.

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10.2 Layout Example

Figure 55. LMX2594 PCB Layout

66

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11 器件和文档支持

11.1 器件支持

11.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类

产品或服务单独或与任何 TI 产品或服务一起的表示或认可。

11.1.2 开发支持

德州仪器 (TI) 在 www.ti.com.cn 提供了多种辅助开发的软件工具。其中包括：

•

EVM 软件，用于了解如何对器件和 EVM 板进行编程。

EVM 板说明，用于了解典型测量数据、详细测量条件以及完整设计的信息。

PLLatinum Sim 程序，用于设计回路滤波器以及对相位噪声和杂散进行仿真。

11.2 文档支持

11.2.1 相关文档

请参阅如下相关文档：

•

《AN-1879 分数 N 频率合成》(SNAA062)

《PLL 性能、仿真和设计手册》(SNAA106)

LMX2594 EVM 说明 - 带集成 VCO 的 15GHz 宽带低噪声 PLL (SNAU210)

11.3 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.4 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.5 商标

PLLATINUM, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

11.6 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

11.7 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

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12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

68

GENERIC PACKAGE VIEW

RHA 40

6 x 6, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4225870/A

www.ti.com

PACKAGE OUTLINE

RHA0040H

VQFN - 1 mm max height

S

C

A

L

E

2

.

2

0

PLASTIC QUAD FLATPACK - NO LEAD

6.1

5.9

B

0.5

0.3

A

0.3

0.2

DETAIL

OPTIONAL TERMINAL

TYPICAL

PIN 1 INDEX AREA

6.1

5.9

(0.1)

SIDE WALL DETAIL

OPTIONAL METAL THICKNESS

C

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

(0.2) TYP

2X 4.5

EXPOSED

THERMAL PAD

11

20

36X 0.5

10

21

SEE SIDE WALL

DETAIL

2X

41

SYMM

4.5

4.5 0.1

SEE TERMINAL

DETAIL

1

30

0.3

0.2

40X

40

31

PIN 1 ID

(OPTIONAL)

0.1

0.05

C A B

SYMM

0.5

0.3

40X

4219055/B 08/22/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RHA0040H

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

4.5)

SYMM

40

31

40X (0.6)

1

30

40X (0.25)

4X

(1.27)

(

0.2) TYP

VIA

(0.73)

(5.8)

TYP

4X

41

SYMM

(1.46)

36X (0.5)

10

21

(R0.05)

TYP

11

(0.73) TYP

4X (1.46)

20

4X (1.27)

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:12X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219055/B 08/22/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RHA0040H

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(1.46) TYP

9X ( 1.26)

(R0.05) TYP

40

31

40X (0.6)

1

30

40X (0.25)

41

(1.46)

TYP

SYMM

(5.8)

36X (0.5)

10

21

METAL

TYP

11

20

SYMM

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 41:

70% PRINTED SOLDER COVERAGE BY AREA

SCALE:15X

4219055/B 08/22/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

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这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LMX2594
厂家：	TEXAS INSTRUMENTS
描述：	具有相位同步功能且支持 JESD204B 的 15GHz 宽带 PLLatinum™ 射频合成器射频
文件：	总77页 (文件大小：2189K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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