LMX5453_技术文档

LMX5453

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SNOSAU2D –FEBRUARY 2006–REVISED JANUARY 2014

®

LMX5453 Micro-Module Integrated Bluetooth 2.0 Baseband Controller and Radio

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1

FEATURES

•

Fractional-N Sigma/Delta modulator

Operating voltage range 2.5–3.6V

I/O voltage range 1.6–3.6V

2

The LMX5453 is a drop in replacement for the

LMX5452. The LMX5453 has new features

added:

60-pad micro-module BGA package (6.1 mm ×

9.1 mm × 1.2 mm)

•

eSCO

eSCO over USB HCI transport

Enhanced scatternet

Interlaced scan

APPLICATIONS

•

Mobile Handsets

USB Dongles

Flushing

Stereo Headsets

Audio PCM slave mode support

Generic PCM configuration

Personal Digital Assistants

Personal Computers

Automotive Telematics

Compliant with the Bluetooth 2.0 Core

Specification

•

Better than -80 dBm input sensitivity

Class 2 operation

DESCRIPTION

The LMX5453 is a highly integrated Bluetooth 2.0

compliant solution. The integrated baseband

controller and 2.4 GHz radio combine to form a

complete, small form-factor (6.1 mm × 9.1 mm × 1.2

mm) Bluetooth node.

Low power consumption:

Accepts external clock or crystal input:

–

Clocking option 12/13 MHz with PLL bypass

mode for power reduction

–

10-20 MHz external clock or crystal network

The on-chip memory, ROM, and Patch RAM provide

lowest cost and minimize design risk with the

flexibility of firmware upgrades.

Secondary 32.768 kHz oscillator for low-

power modes

The firmware supplied in the on-chip ROM supports a

complete Bluetooth Link Manager and HCI with

communication through a UART or USB interface.

This firmware features point-to-point and point-to-

multipoint link management, supporting data rates up

to 723 kbps.

–

Advanced power management features

•

High integration:

–

Implemented in 0.18 μm CMOS technology

RF includes on-chip antenna filter and

switch

•

On-chip firmware with complete HCI

The radio employs an integrated antenna filter and

switch to minimize the number of external

components.

Embedded ROM (200K) and Patch RAM (16.6K)

memory

The radio has a heterodyne receiver architecture with

a low intermediate frequency (IF), which enables the

IF filters to be integrated on-chip. The transmitter

uses direct IQ-modulation with Gaussian-filtered bit-

stream data, a voltage-controlled oscillator (VCO)

buffer, and a power amplifier.

•

Up to 7 Asynchronous Connection Less (ACL)

links

Support for two simultaneous voice or

Extended Synchronous Connection Oriented

(eSCO) and Synchronous Connection Oriented

(SCO) and links.

The LMX5453 module is lead free and RoHS

(Restriction of Hazardous Substances) compliant. For

more information on those quality standards, please

visit our green compliance website at **

http://www.national.com/quality/green/

•

Enhanced scatternet

Interlaced scan

Flushing

Audio PCM slave mode support

Generic PCM configuration

•

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

Bluetooth is a registered trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

LMX5453

SNOSAU2D –FEBRUARY 2006–REVISED JANUARY 2014

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Functional Block Diagram

USB_D-

USB_D+

VCC_USB

GND_USB

USB

Clock

Oscillator/

Crystal

Generator

including

PLL

Link

Manager

HCI

Transport

TXD

RXD

RTS#

CTS#

UART

JTAG

SCL

SDA

Access

bus

Baseboard

Controller

&RPSDFW5,6&

Antenna

Radio

Processor

MDODI

MWCS#

MSK

MDIDO

SPI

SCLK

SFS

SFS1

STD

SRD

Combined

System and

Patch RAM

Voltage

Regulator

CVSD

Codecs

Audio

Port

ROM

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

INTERFACES

•

Full-duplex UART supporting transfer rates up to 921.6 kbps including baud rate detection for HCI

Full speed (12 Mbps) USB 2.0 for HCI

ACCESS.bus and SPI/Microwire for interfacing with external non-volatile memory

Advanced Audio Interface (AAI) for interfacing with external 8-kHz PCM codec

Up to 3 GPIO port pins (OP4/PG4, PG6, PG7) controllable by HCI commands

JTAG based serial on-chip debug interface

Single Rx/Tx-pad radio interface

2

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CONNECTION DIAGRAM

1

2

3

4

5

6

7

8

9

10

A

B

C

D

E

F

VCC_USB

RTS#

USB_D+

GND_USB

CTS#

USB_D-

RXD

RDY#

TCK

TMS

TDI

XOSCEN

PG6

VDD_IF

TE

VDD_RF

TST1/DIV2#

GND_RF

ANT

B_RESET_RA# RESET_BB# RESET_RA#

GND_RF

TST4

OP6/SCL/MSK

MDODI

TXD

VCC_IO

VCC_CORE

ENV1#

TST2

TST3

TST5

PG7

OP3/MWCS# OP7/SDA/MDIDO TDO

OP4/PG4

VDD_IOR

VCC_PLL

GND_IF

X1_CKI

X1_CKO

TST6

VCC

GND

STD

SRD

VCC_IOP

OP5/SFS1

X2_CKO

X2_CKI

VDD_X1

VCO_OUT

GND_VCO

VCO_IN

GND_RF

VDD_VCO

SCLK

SFS

Figure 1. X-ray - Top View

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SIGNAL DESCRIPTIONS

Table 1. Signal Descriptions

Pad Name

X1_CKO

Pad Location

Type

Default Layout

Description

F7

E7

F5

E5

B8

B6

B7

C6

O

I

Crystal 10-20 MHz

X1_CKI

Crystal or External Clock 10-20 MHz

32.768 kHz Crystal Oscillator

X2_CKI

I

GND (if not used)

NC (if not used)

X2_CKO

O

I

32.768 kHz Crystal Oscillator

RESET_RA#

B_RESET_RA#

RESET_BB#

ENV1

Radio Reset Input (active low)

O

I

Buffered Radio Reset Output (active low)

Baseband Controller Reset (active low)

NC

ENV1: Environment Select used for manufacturing

test only

I

TE

A9

GND

Test Enable - Used for manufacturing test only

TST1/DIV2#

B10

NC

TST1: Test Mode. Leave not connected to permit use

with VTune automatic tuning algorithm.

DIV2#: No longer supported

I

TST2

TST3

TST4

TST5

TST6

C7

C8

C9

D8

D9

I

GND

Test Mode, Connect to GND

GND

VCO_OUT

Test Input, Connect to VCO_OUT through a zero-

ohm resistor to permit use with VTune automatic

tuning algorithm

I

USB_D-

USB_D+

A3

A2

D1

C1

I

USB Data (negative)

USB Data (positive)

(1)

MDODI

I/O

SPI Master Data Out/Slave Data In

OP6/SCL/MSK

See Table 20

OP6: Pin checked during the start-up sequence for

configuration option

OP6: I

SCL/MSK:

I/O

SCL: ACCESS.Bus Clock

MSK: SPI Shift

OP7/SDA/MDIDO

D4

OP7: I

SDA/MDID

O:

OP7: Pin checked during the start-up sequence for

configuration option

SDA: ACCESS.Bus Serial Data

I/O

MDIDO: SPI Master Data In/Slave Data Out

OP3/MWCS#

OP4/PG4

D3

D6

F4

See Table 20 and Table 21 OP3: Pin checked during the start-up sequence for

configuration option

I

MWCS#: SPI Slave Select Input (active low)

See Table 20 and Table 21 OP4: Pin checked during the start-up sequence for

OP4: I

PG4: I/O

configuration option

PG4: GPIO

OP5/SFS1

See Table 20 and Table 21 OP5: Pin checked during the start-up sequence for

configuration option

I/O

SFS1: Audio PCM Interface - Frame Synchronization

for second codec

SCLK

SFS

F1

F2

F3

E3

A6

I/O

I

Audio PCM Interface Clock

Audio PCM Interface Frame Synchronization

Audio PCM Interface Receive Data Input

Audio PCM Interface Transmit Data Output

SRD

STD

O

XOSCEN

Clock Request. Toggles with X2 (LP0) crystal

enable/disable

O

PG6

PG7

A7

D2

See NVS Table 21

GPIO - Default setup USB status indication

GPIO - Default setup TL (Transport Layer) traffic

LED indication

(1) Must use 1k ohm pull up

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Table 1. Signal Descriptions (continued)

Pad Name

Pad Location

Type

Default Layout

Description

Host Serial Port Clear To Send (active low)

Host Serial Port Receive Data

Host Serial Port Request To Send (active low)

Host Serial Port Transmit Data

JTAG Ready Output (active low)

JTAG Test Clock Input

(2)

CTS#

RXD

C2

B3

I

GND (if not used)

(3)

RTS#

TXD

B1

O

I

NC (if not used)

C3

RDY#

A4

NC

TCK

B4

I

TDI

B5

I

JTAG Test Data Input

TDO

D5

O

I

JTAG Test Data Output

TMS

A5

JTAG Test Mode Select Input

Charge Pump Output, connect to loop filter

VCO Tuning Input, feedback from loop filter

RF Antenna, 50-ohm nominal impedance

1.8V Core Logic Power Supply Output

1.8V Voltage Regulator Output

Power Supply Crystal Oscillator

Power Supply VCO

VCO_OUT

VCO_IN

ANT

F8

O

I

F9

D10

F6

O

I

VCC_PLL

VCC_CORE

VDD_X1

VDD_VCO

VDD_RF

VDD_IOR

VDD_IF

VCC_USB

VCC_IOP

VCC_IO

VCC

C5

E8

F10

A10

E6

I

Power Supply RF

I

Power Supply I/O Radio/BB

Power Supply IF

A8

I

A1

I

Power Supply USB Transceiver

Power Supply Audio Interface

Power Supply I/O

E4

I

C4

I

E1

I

Voltage Regulator Input

GND_VCO

GND_USB

GND_RF

GND_IF

GND

E9

Ground

B2

Ground

B9, C10, E10

D7

Ground

E2

Ground

(2) Connect to GND if CTS is not used

(3) Treat as No Connect if RTS is not used. Pad required for mechanical stability

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Electrical Specifications

Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended

Operating Conditions indicate conditions for which the device is intended to be functional, but do not guarantee

specific performance limits. This device is ESD sensitive. Handling and assembly of this device should be

performed at ESD-free workstations. All pads are rated 2 kV. This device operates between -40 and +85°C.

Absolute Maximum Ratings

Parameter

Min

–0.2

Max

Units

VCC

Power Supply Voltage

4.0

V

V_I

Voltage on any pad with GND = 0V

Supply Voltage Radio

–0.2

0.2

VCC + 0.2

3.3

VDD_RF

VDD_IF

VDD_X1

VDD_VCO

P_INRF

V_ANT

RF Input Power

0

1.95

+150

225

dBm

V

Applied Voltage to ANT pad

Storage Temperature Range

Lead Temperature ⁽¹⁾(solder 4 sec)

Lead Temperature NOPB ⁽¹⁾⁽²⁾(solder 40 sec)

ESD - Human Body Model

ESD - Machine Model

T_S

–65

°C

V

T_L

T_LNOPB

ESD_HBM

ESD_MM

ESD_CDM

260

2000

200

V

ESD - Charged Device Model

1000

V

(1) Reference IPC/JEDEC J-STD-020C spec.

(2) NOPB = No Pb (No Lead)

Recommended Operating Conditions

Parameter

Min

Typ

2.75

Max

Units

V

VCC

Module Power Supply Voltage

2.5

3.6

T_R

Module Power Supply Rise Time

10

+85

3.6

µS

°C

V

T_A

Ambient Opoerating Temperature Range Fully Functional Bluetooth Node

Supply Voltage Digital I/O

–40

1.6

+25

3.3

VCC_IO

VCC_USB

VCC_PLL

VDD_RF

VDD_IF

VDD_X1

VDD_VCO

VDD_IOR

VCC_IOP

Supply Voltage USB

2.97

3.63

V

Internally connected to VCC_Core

Supply Voltage Radio

2.5

2.75

3.0

V

Supply Voltage Radio I/O

1.6

2.75 VDD_RF

V

Supply Voltage PCM Interface

3.3

1.8

5

3.6

2.0

VCC_CORE Supply Voltage Output

V

VCC_CORE Supply Voltage Output Max Load

MAX

mA

VCC_CORE_SWhen used as supply input (VCC grounded)

1.6

1.8

V

HORT

6

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Power Supply Requirements⁽¹⁾⁽²⁾

Parameter

Min

Typ

Max

Units

mA

µA

I_RXDM5

I_TXDM5

I_RXDH5

I_TXDH5

I_RXHV1

I_TXHV1

I_CC-RX

I_CC-TX

During Receive DM5

26

27

26

27

12

During Transmit DM5

During Receive DH5

During Transmit DH5

During Receive HV1

During Transmit HV1

Receive Power Supply Current (Receive in Continuous Mode)

Transmit Power Supply Current (Transmit in Continuous Mode)

Power-down Current (Standby, XO off)

Active Mode - Page/Inquiry Scan Enabled

Sniff Mode - Sniff Interval 1.28 sec.

65

I_CC-PWDN

I_ACTIVE

I_SNIFF

34

6

mA

5

(1) Power supply requirements are based on Class 2 output power.

(2) VCC = 2.75V, T_A= +25°C

DC Characteristics

Parameter

Condition

Min

Max

Units

VCC_IO +

0.2

VCC_IO +

0.2

0.7 x

VCC_IO

2.0

1.6V ≤ VCC_IO ≤ 3.0

3.0V ≤ VCC_IO ≤ 3.6

V_IH

Logical 1 Input Voltage High (except oscillator I/O)

Logical 1 Input Voltage Low (except oscillator I/O)

V

0.25 x

VCC_IO

0.8

1.6V ≤ VCC_IO ≤ 3.0

3.0V ≤ VCC_IO ≤ 3.6

-0.2

V_IL

V

V_OH= 2.4V, VCC_IO =

3.0V

(1)

I_OH

Logical 1 Output Current

Logical 0 Output Current

-10

10

mA

V_OL= 0.4V, VCC_IO =

3.0V

I_OL

(1) Maximum current is 50mA per VCC_IO/GND pair.

USB Transceiver

Parameter

Condition

Min

2.97

Typ

Max

Units

V

VCC_USB

V_DI

USB Power Supply Voltage

Differential Input Sensitivity

Differential Common Mode Range

Siungle Ended Received Threshold

Output Low Voltage

3.3

3.63

+0.2

2.5

(D+) - (D-)

-0.2

0.8

V

V_CM

V

V_SE

2.0

V

V_OL

R_L= 1.5k, to 3.6V

0V < V_IN< 3.3V

0.3

V

V_OH

Output High Voltage

2.8

-10

V

I_OZ

TRI-STATE Data Line Leakage

Transceiver Capacitance

+10

20

µA

pF

C_TRN

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RF Characteristics

Parameter

Condition

Min

Typ⁽¹⁾

–80

0

Max

–76

Units

dBm

2.402 GHz

2.441 GHz

2.480 GHz

RX_sense

PinRF

Receive Sensitivity

BER < 0.001

Maximum Input Level

–10

–38

F₁= + 3 MHz,

F₂= + 6 MHz,

P_inRF = –64 dBm

-36

Intermodulation

Performance

(2) (3)

IMP

,

RSSI Dynamic Range at

LNA Input

–72

–52

–8

dBm

RSSI

Z_RFIN

Input Impedance of RF Port

(RF_inout)

32

Ω

(3)

Single input impedance F_in= 2.5 GHz

(3)

Return Loss

dB

P_inRF = -10 dBm,

30 MHz < F_CWI< 2 GHz,

BER < 0.001

–10

–27

–10

dBm

P_inRF = -27 dBm,

2000 MHz < F_CWI< 2399 MHz,

BER < 0.001

dBm

Out of Band Blocking

Performance

OOB^{(2) (3)}

,

P_inRF = -27 dBm,

2498 MHz < F_CWI< 3000 MHz,

BER < 0.001

P_inRF = -10 dBm,

3000 MHz < F_CWI< 12.75 GHz,

BER < 0.001

(1) Typical operating conditions are at 2.75V operating voltage and 25°C ambient temperature.

(2) The f₀= –64 dBm Bluetooth modulated signal, f₁= -39 dbm sine wave, f₂= -39 dBm Bluetooth modulated signal, f₀= 2f₁- f₂, and |f₂- f₁|

= n × 1 MHz, where n is 3, 4, or 5. For the typical case, n = 3.

(3) Not tested in production.

Transmitter Characteristics

Parameter

Condition

Min

Typ⁽¹⁾

Max

–30

Units

PA 2nd Harmonic

Suppression

Maximum gain setting: f₀= 2402 MHz, P_out

4804 MHz

=

dBm

d₍₂₎

P_OUT2 x f_o

RF Output Impedance/Input

Impedance of RF Port

(RF_inout)

47

Ω

Z_RFOUTθ

P_out@ 2.5 GHz

(1) Typical operating conditions are at 2.75V operating voltage and 25°C ambient temperature.

(2) Out-of-Band spurs only exist at 2nd and 3rd harmonics of the CW frequency for each channel.

Synthesizer Characteristics

Parameter

Condition

Min

Typ

Max

2480

Units

MHz

µs

f_VCO

VCO Frequency Range

Lock Time

2402

t_LOCK

f₀± 20 kHz

120

Initial Carrier

Frequency Tolerance

–75

0

75

kHz

Δf₀offset⁽¹⁾

During preamble

DH1 data packet

DH3 data packet

DH5 data packet

–25

–40

–20

0

25

40

kHz

Initial Carrier

Frequency Drift

Δf₀drift⁽¹⁾

20 kHz/50

µs

Drift Rate

t_D-Tx

Transmitter Delay Time From Tx data to antenna

4

µs

(1) Frequency accuracy is dependent on crystal oscillator chosen. The crystal must have a cumulative accuracy of <20 ppm to meet

Bluetooth specifications.

8

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Crystal Requirements

The LMX5453 provides an on-chip driver that may be used with an external crystal and capacitors to form an

oscillator. Figure 2 shows the recommended crystal circuit. Table 5 specifies the system clock requirements.

The RF local oscillator and internal digital clocks for the LMX5453 are derived from the reference clock at the

CLK+ input. This reference may come from either an external clock signal or the oscillator using the on-chip

driver.

When the on-chip driver is used, the board- and design dependent capacitance must be considered in tuning the

crystal circuit. Equations that provide a close approximation of the crystal tuning capacitance are used as a

starting point, but the optimal values will vary with the capacitive properties of the circuit board. As a result, fine

tuning of the crystal circuit must be performed experimentally, by testing different values of load capacitance.

Many different crystals can be used with the LMX5453. A key requirement from the Bluetooth specification is a

cumulative accuracy of <20 ppm. Additionally, ESR (Equivalent Series Resistance) must be carefully considered.

The LMX5453 can support a maximum ESR of 230Ω, but it is recommended to stay <100Ω for best performance

over voltage and temperature. See Figure 3 for ESR as part of the crystal circuit for more information. The ESR

of the crystal also has an impact on the start-up time of the crystal oscillator circuit. See ** Section 15.0 and

Table 18 for system start-up timing.

Crystal

The crystal appears inductive near its resonant frequency. It forms a resonant circuit with its load capacitors. The

resonant frequency may be trimmed with the crystal load capacitance.

Load Capacitance

For resonance at the correct frequency, the crystal should be loaded with its specified load capacitance. Load

capacitance is a parameter specified by the crystal vendor, typically expressed in pF. The crystal circuit shown in

Figure 3 is composed of:

•

C1 (motional capacitance)

R1 (motional resistance)

L1 (motional inductance)

C0 (static or shunt capacitance)

The LMX5453 provides some of the load with internal capacitors C_intand XOC_TUNE. The remainder must come

from the external capacitors labeled Ct1 and Ct2 shown in Figure 2. For best noise performance, Ct1 and Ct2

should have the same the value.

The value of XOC_TUNEcan be programmed in register 2. There are 7 bits of tuning for XOC_TUNE. The default

value is 0028h, which results in an additional 2.6 pF internal capacitance. This register can be used in production

testing for additional tuning, if necessary. See Table 19 for the range of XOC_TUNEvalues.

The crystal load capacitance (C_L) is calculated as:

C_L C_intꢀ XOC_TUNEꢀ Ct1/ /Ct2

(1)

The C_Labove does not include the crystal internal self capacitance C₀as shown in Figure 3, so the total

capacitance is:

C_total C_Lꢀ C₀

(2)

Based on the crystal specification and equation:

C_L C_intꢀ XOC_TUNEꢀ Ct1/ /Ct2

(3)

(4)

C_L 8 pF ꢀ 2.6 pF ꢀ 6 pF 16.6 pF

16.6 pF is very close to the TEW crystal requirement of 16 pF load capacitance. With the internal shunt

capacitance C_total

:

C_total 16.6 pF ꢀ 5 pF 21.6 pF

(5)

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LMX5453

CLK+

CLK-

C

int

XOC

TUNE

Ct2

Ct1

Crystal

Figure 2. Recommended Crystal Circuit

R1

C1

L1

C0

Figure 3. Crystal Equivalent Circuit

Crystal Pullability

Pullability is another important crystal parameter, which is the change in frequency of a crystal with units of

ppm/pF, either from the natural resonant frequency to a load resonant frequency, or from one load resonant

frequency to another. The frequency can be pulled in a parallel resonant circuit by changing the value of load

capacitance. A decrease in load capacitance causes an increase in frequency, and an increase in load

capacitance causes a decrease in frequency.

Frequency Tuning

Frequency tuning is performed by adjusting the crystal load capacitance with external capacitors. It is a Bluetooth

requirement that the frequency is always within 20 ppm. The crystal/oscillator must have cumulative accuracy

specifications of 15 ppm to provide margin for frequency drift with aging and temperature.

TEW Crystal

The LMX5453 has been tested with the TEW TAS-4025A crystal (see Table 3). Because the internal capacitance

of the crystal circuit is 8 pF and the load capacitance is 16 pF, 12 pF is a good starting point for both Ct1 and

Ct2. The 2480 MHz RF frequency offset is then tested. Figure 5 shows the RF frequency offset test results.

Figure 5 shows the results are -20 kHz off the center frequency, which is –1 ppm. The pullability of the crystal is

2 ppm/pF, so the load capacitance must be decreased by about 1.0 pF. By changing Ct1 or Ct2 to 10 pF, the

total load capacitance is decreased by 1.0 pF. Figure 6 shows the frequency offset test results. The frequency

offset is now zero with Ct1 = 10 pF and Ct2 = 10 pF.

See Table 3 for crystal tuning values used on the Phoenix Development Board with the TEW crystal.

Table 2. TEW TAS-4025A

Specification

Package

Value

4.0 × 2.5 × 0.65 mm - 4 pads

13.000 MHz

Frequency

Mode

Fundamental

Stability

<15ppm @ –40 to +85°C

16 pF

CL Load Capacitance

ESR

80Ω max

CO Shunt Capacitance

5 pF

10

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Table 2. TEW TAS-4025A (continued)

Specification

Drive Level

Value

50 ± 10uV

Pullability

2 ppm/pF (minimum)

–40 to +85°C

Storage Temperature

Table 3. TEW on Phoenix Board

Specification

Value

10 pF

Ct1

Ct2

TCXO (Temperature Compensated Crystal Oscillator)

The LMX5453 also can operate with an external TCXO (Temperature Compensated Crystal Oscillator). The

TCXO signal is directly connected to the CLK+.

1. Input Impedance

The LMX5453 CLK+ pin has in input impedance of 2pF capacitance in parallel with >400kΩ resistance

Optional 32 KHZ Oscillator

A second oscillator is provided (see Figure 4) that is tuned to provide optimum performance and low-power

consumption while operating with a 32.768 kHz crystal. An external crystal clock network is required between the

32kHz_CLKI clock input (pad B13) and the 32kHz_CLKO clock output (pad C13) signals. The oscillator is built in

a Pierce configuration and uses two external capacitors. Figure 4 provides the oscillator’s specifications.

In case the 32Khz is placed optionally, it is recommended to remove C2 and replace C1 with a zero ohm

resistor.

32kHz_CLKI

32.768 kHz

32kHz_CLKO

C2

C1

GND

Figure 4. 32.768 kHz Oscillator

Table 4. 32.768 kHz Oscillator Specifications

Symbol

V_DD

Parameter

Supply Voltage

Condition

Min

1.62

Typ

1.8

Max

1.98

Unit

V

I_DDACT

Supply Current (Active)

2

32.768

1.8

µA

Nominal Output

Frequency

f

kHz

V_PPOSC

Oscillating Amplitude

Duty Cycle

V

40

60

%

Table 5. System Clock Requirements

Symbol

Parameter

External Reference Clock Frequency⁽¹⁾

Frequency Tolerance (over full operating temperature and aging)

Digital Crystal Tuning Load Range

Min

Typ

13

15

8

Max

Unit

MHz

ppm

pF

C_REF

C_TOL

10

20

–20

XOC_TUNE

C_OSC

Crystal Oscillator

10

13

20

MHz

(1) Frequencies supported: 10.00, 10.368, 12.00, 12.60, 12.80, 13.00, 13.824, 14.40, 15.36, 16.00, 16.20, 16.80, 19.20, 19.44, 19.68, and

19.80 MHz

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Table 5. System Clock Requirements (continued)

Symbol

C_ESR

Parameter

Crystal Serial Resistance

Min

Typ

Max

230

Unit

Ω

C_REF-PS

C_int

External Reference Clock Power Swing (peak to peak)

Internal Load Capacitance

Aging

100

200

400

mV

8

pF

C_AGE

1

ppm/year

Figure 5. Frequency Offset with 12 pF//12 pF Capacitors

Figure 6. Frequency Offset with 10 pF//10 pF Capacitors

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Table 6. Register 2: XOCTUNE Tuning Load Range

Binary Value

Hex Value

Value

Units

pF

000 0000

010 1000

111 1111

00

28⁽¹⁾

7F

0

2.6

8

pF

(1) Default value for RF initialization register 2.

Figure 7. ESR vs. Load Capacitance for the Crystal

Antenna Matching and Front-End Filtering

Figure 8 shows the recommended component layout to be used between RF output and antenna input. Allows

for versatility in the design such that the match to the antenna maybe improved and/or the blocking margin

increased by addition of a LC filter. Refer to antenna application note for further details.

LC filter

To Antenna

PI Match

Figure 8. Front End Layout

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Loop Filter Design

Since the LMX5453 has an external loop filter that determines the performance of the device to a great extent, it

is important that it is designed correctly. Texas Instruments will provide the starting component values but the

end customer may have to make adjustments to optimize the performance. Please refer to Loop Filter application

note and also Texas Instrument’s Webench design tool for detailed information.

Component Calculations

The following parameters are required for component value calculation of a third order passive loop filter.

symbol?

F_c

Phase Margin: Phase of the open loop transfer function

Loop Bandwidth

F_comp

Comparison Frequency: Phase detector frequency

VCO gain: Sensitivity of the VCO to control volts

Charge Pump gain: Magnitude of the alternating current during lock

Mean RF output frequency

KVOC

K symbol?

F_OUT

T31

Ratio of the poles T3 to T1 in a 3rd order filter

Gamma optimization parameter

symbol?

The third order loop filter being defined has the topology shown in Figure 10.

R3

CP

VCO

R2

C1

C3

C2

GND

Figure 9. Third Order Loop Filter

§

¨

©

·

¸

¹

J

I tan^ꢀ1

ꢀ tan^ꢀ1(Z T1) ꢀ tan^ꢀ1(Z T1 T31)

C

Z_CT1T1ꢁ T31

(6)

(7)

Calculate the poles and zeros. Use exact method to solve for T1 using numerical methods.

J

T3 T31u T1

T2

Z_C(T1ꢀ T3)

2

KIK_vco

1ꢀ Z_C T2²

A0

2

Z_CN

(1ꢀ Z_C T1 )(1ꢀ Z_C T3²)

(8)

(9)

Calculate the loop filter coefficients,

A1 A0(T1ꢀ T3) A2 A0 T1T3

§

¨

©

·

A2

T2²

T2 A0 ꢀ T2 A1

§

·

C1

1ꢁ 1ꢁ

¨

¸

¹

¨

©

¸

¹

A2

(10)

Summary:

Symbol

Description

Units

None

rad/s

S

η

N counter value

Loop Bandwidth

Loop filter pole

T1

14

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Symbol

T2

Description

Units

Loop filter zero

Total capacitance

S

T3

A0

nF

A1

First order loop filter coefficient

nFs

nFs2

A2

Second order loop filter coefficients

Components can then be calculated from loop filter coefficients

1T2²C1 ꢀ T2 A1C1ꢁ A2 A0

2

C3

C2 A0 ꢁ C1ꢁ C3

T2²C1ꢁ A2

(11)

(12)

T2

C2

400

F_C

A2

R2

LT

R3

C1C3 T2

(1ꢀ log₁₀'F) where 'F

Frequency ꢀ tolerance

Frequency ꢀ jump

(13)

Some typical values for the LMX5453 are:

Symbol

Description

13

Units

MHz

PI rad

kHz

Comparison Frequency

Phase Margin

Loop bandwidth

T3 or T1 ratio

Gamma

48

100

40

%

1.0

VCO gain

120

0.6

MHz per V

mA

Charge pump gain

Fout

2441

MHz

Which give the following component values:

Symbol

C1

Description

0.17

Units

nF

C2

2.38

C3

0.04

R2

R3

1737

7025

ohms

Phase Noise and Lock-Time Calculations

Phase noise has three sources, the VCO, crystal oscillator and the rest of the PLL consisting of the phase

detector, dividers, charge pump and loop filter. Assuming the VCO and crystal are very low noise, it is possible to

put down approximate equations that govern the phase noise of the PLL.

Phase noise (in-band) = PN1Hz + 20Log[N] + 10Log [F_comp

]

Where PH1Hz is the PLL normalized noise floor in 1 Hz resolution bandwidth.

Further out from the carrier, the phase noise will be affected by the loop filter roll-off and hence its bandwidth.

As a rule-of-thumb; Δ Phase noise = 40Log [Δ F_c]

Where Fc is the relative change in loop BW expressed as a fraction.

For example if the loop bandwidth is reduced from 100kHz to 50kHz or by one half, then the change in phase

noise will be -12dB. Loop BW in reality should be selected to meet the lower limit of the modulation deviation,

this will yield the best possible phase noise.

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Even further out from the carrier, the phase noise will be mainly dominated by the VCO noise assuming the

crystal is relatively clean.

Lock-time is dependent on three factors, the loop bandwidth, the maximum frequency jump that the PLL must

make and the final tolerance to which the frequency must settle. As a rule-of-thumb it is given by:

400

F_C

Frequency ꢀ tolerance

Frequency ꢀ jump

LT

(1ꢀ log₁₀'F)

where 'F

(14)

These equations are approximations of the ones used by Webench to calculate phase noise and lock-time.

Practical Optimisation

In an example where frequency drift and drift rate can be improved though loop filter tweaks, consider the results

taken below. The drift rate is 26.1 kHz per 50us and the maximum drift is 25 kHz for DH1 packets, both of which

are exceeding or touching the Bluetooth pass limits. These measurements are taken with component values

shown above.

Table 7. TRM/CA/09/C (Carrier Drift)

Hopping On - Low Channel

DH1

26, 1 kHz

25 kHz

–1 kHz

10

DH3

N/A

DH5

–30,5 kHz

36 kHz

12 kHz

10

Drift Rate / 50us

Max Drift

Average Drift

Packets Tested

Packets Failed

Overall Result

2

10

Failed

Results below were taken on the same board with three loop filter values changed. C2 and R2 have been

increased in value and C1 has been reduced. The drift rate has improved by 13 kHz per 50 μs and the maximum

drift has improved by 10 kHz.

Table 8. TRM/CA/09/C (Carrier Drift)

Hopping On - Low Channel

DH1

–13,6 kHz

15 kHz

3 kHz

10

DH3

N/A

DH5

15,6 kHz

21 kHz

1 kHz

10

Drift Rate / 50us

Max Drift

Average Drift

Packets Tested

Packets Failed

Overall Result

0

Passed

The effect of changing these three components is to reduce the loop bandwidth which reduces the phase noise.

The reduction in this noise level corresponds directly to the reduction of noise in the payload area where drift is

measured. This noise reduction comes at the expense of locktime which can be increased to 120 μs without

suffering any ill effects, however if we continue to reduce the loop BW further the lock-time will increase such that

the PLL does not have time to lock before data transmission and the drift will again increase. Before the lock-

time goes out of spec, the modulation index will start to fall since it is being cut by the reducing loop BW.

Therefore a compromise has to be found between lock-time, phase noise and modulation, which yields best

performance.

Note// The values shown on the LMX5453 datasheet are the best case optimized values that have been shown

to produce the best overall results and are recommended as a starting point for all designs.

Another example of how the loop filter values can affect frequency drift rate, these results below show the DUT

with maximum drift on mid and high channels failing. Adjusting the loop bandwidth as shown provides the

improvement required to pass qualification.

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Table 9. Original results:

Hopping OFF - Low Channel

DH1

–15.00 kHz

–19 kHz

–11 kHz

10

DH3

DH5

Limits

Drift Rate / 50us

Maximum Drift

Average Drift

Packets Tested

Packets Failed

Result

–28.10 kHz

–37 kHz

–32 kHz

10

–19.10 kHz

–20 kHz

–10 kHz

10

+/– 20 kHz

DH1: +/– 25 kHz

DH3: +/– 40 kHz

DH5: +/– 40 kHz

0

1

0

Pass

Fail

Pass

Hopping OFF - Med Channel

DH1

–18.60 kHz

–29 kHz

–19 kHz

10

DH3

16.30 kHz

–44 kHz

–37 kHz

10

DH5

–18.00 kHz

–28 kHz

–19 kHz

10

Limits

Drift Rate / 50us

Maximum Drift

Average Drift

Packets Tested

Packets Failed

Result

+/– 20 kHz

DH1: +/– 25 kHz

DH3: +/– 40 kHz

DH5: +/– 40 kHz

2

0

Fail

Pass

Hopping OFF - High Channel

DH1

DH3

16.80 kHz

–61 kHz

–48 kHz

10

DH5

–17.70 kHz

–38 kHz

–29 kHz

10

Limits

Drift Rate / 50us

Maximum Drift

Average Drift

Packets Tested

Packets Failed

Result

–16.30 kHz

–36 kHz

–31 kHz

10

+/– 20 kHz

DH1: +/– 25 kHz

DH3: +/– 40 kHz

DH5: +/– 40 kHz

10

8

0

Fail

Pass

Table 10. New Results:

Hopping OFF - Low Channel

DH1

–12.00 kHz

–15 kHz

–6 kHz

10

DH3

–15.10 kHz

–35 kHz

–25 kHz

10

DH5

18.80 kHz

–19 kHz

–9 kHz

10

Limits

Drift Rate / 50us

Maximum Drift

Average Drift

Packets Tested

Packets Failed

Result

+/– 20 kHz

DH1: +/– 25 kHz

DH3: +/– 40 kHz

DH5: +/– 40 kHz

0

Pass

Hopping OFF - Med Channel

DH1

–14.20 kHz

–16 kHz

–11 kHz

10

DH3

–16.10 kHz

–34 kHz

–27 kHz

10

DH5

17.20 kHz

–22 kHz

–9 kHz

10

Limits

Drift Rate / 50us

Maximum Drift

Average Drift

Packets Tested

Packets Failed

Result

+/– 20 kHz

DH1: +/– 25 kHz

DH3: +/– 40 kHz

DH5: +/– 40 kHz

0

Pass

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Hopping OFF - High Channel

DH1

DH3

–17.40 kHz

–29 kHz

–25 kHz

10

DH5

–16.50 kHz

–25 kHz

–16 kHz

10

Limits

Drift Rate / 50us

Maximum Drift

Average Drift

Packets Tested

Packets Failed

Result

–12.70 kHz

–23 kHz

–12 kHz

10

+/– 20 kHz

DH1: +/– 25 kHz

DH3: +/– 40 kHz

DH5: +/– 40 kHz

0

Pass

Reference Starting Values

Recommended starting values for the LMX5453 as also stated in the reference design towards the end of this

datasheet are a as shown in Table 11. These values have been optimized through testing to yield the best

results from the design. However minor changes to the layout could mean the values need re-optimization.

Table 11. Loop Filter Values

Device

C1

C2

C3

R2

R3

LMX5453

220 pF

2200 pF

39 pF

4.7k

10k

Functional Blocks

Baseband Processor And Link Management Processor

Baseband and lower link control functions are implemented using a combination of a CompactRISC 16-bit

processor and the Bluetooth Lower Link Controller (LLC). These processors operate from integrated ROM

memory and RAM. They execute on-board firmware implementing all Bluetooth functions.

Bluetooth Lower Link Controller

The integrated Bluetooth Lower Link Controller complies with the Bluetooth Specification version 2.0 and

implements the following functions:

•

Faster connection

Interlaced Scanning

Adaptive frequency hopping (AFH)

Enhanced Error detection

Support for 1-, 3-, and 5-slot packet types

79 channel hop-frequency generation circuitry

Fast frequency hopping at 1600 hops per second

Power management control

Access code correlation and slot timing recovery

Memory

The LMX5453 provides 16K of combined system and Patch RAM memory that can be used for data and/or code

upgrades of the ROM-based firmware. Due to the flexible startup used for the LMX5453, operating parameters

like the Bluetooth Device Address (BD_ADDR) are defined during boot time. This allows reading the parameters

from an external EEPROM or programming them directly over HCI.

External Memory Interfaces

Because the LMX5453 is a ROM-based device with no onchip non-volatile storage, the operation parameters will

be lost after a power cycle or hardware reset. To avoid reinitializing operation parameters, patches, or user data,

the LMX5453 offers two options for connecting with an external EEPROM:

•

Microwire/SPI

ACCESS.bus (I²C compatible)

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The interface is selected during start-up, based on states sampled from the option pins. See Table 20 for the

option pin descriptions.

Microwire/SPI Interface

If the configuration selected by the option pins uses a Microwire/SPI interface, the LMX5453 activates that

interface and attempts to read the EEPROM. The external memory must be compatible with the features listed in

Table 12.

The largest size EEPROM supported is limited by the addressing format of the selected EEPROM. The device

must have a page size equal to N x 32 bytes.

The LMX5453 firmware requires that the EEPROM supports page write. The clock must be high when idle.

Table 12. M95640-S EEPROM 8K × 8

Parameter

Supplier

Value

ST Microelectronics

Supply Voltage⁽¹⁾

1.8 - 3.6 V

Interface

SPI compatible (positive clock SPI modes)

8K x 8 (64 Kbits)

Memory Size

Clock Rate⁽¹⁾

Access

2 MHz

Byte and page write (up to 32 bytes)

(1) Parameter range reduced to requirements of Texas Instruments' reference design.

ACCESS.bus Interface

If the configuration selected by the option pins uses an ACCESS.bus or I2C-compatible interface, the LMX5453

activates that interface and attempts to read the EEPROM. The external memory must be compatible with the

features listed in Table 13.

The largest size EEPROM supported is limited by the addressing format of the selected EEPROM. The device

must have a page size equal to N x 32 bytes. The device uses a 16-bit address format. The device address must

be 000.

Table 13. 24C64 EEPROM 8K × 8

Parameter

Supplier

Value

Atmel

Supply Voltage⁽¹⁾

2.7 - 5.5 V

Interface

2-wire serial interface

8K x 8 (64 Kbits)

100 kHz

Memory Size

Clock Rate⁽¹⁾

Access

32-byte page-write mode

(1) Parameter range reduced to requirements of Texas Instruments' reference design.

Host Controller Interface Port

UART Interface

The LMX5453 provides one Universal Asynchronous Receiver Transmitter (UART). It supports 8-bit data with or

without parity, and with one or two stop bits. The UART can operate at standard baud rates from 300 baud up to

a maximum of 921.6 kbaud. DMA transfers are supported to allow for fast processor-independent receive and

transmit operation. The UART implements flow-control signals (RTS# and CTS#) for hardware handshaking.

The reference clock and UART baud rate are configured during start-up by sampling option pins OP3, OP4, and

OP5. If the auto baud rate detect option is selected, the firmware checks an area in non-volatile storage (NVS)

for a valid UART baud rate stored during a previous session. If no value was saved, the LMX5453 will switch to

auto baud rate detection and wait for an incoming reference signal.

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The UART can detect a BREAK signal, which forces the LMX5453 to reset. This is useful when the only

connection between the LMX5453 and the host system is the HCI port.

The UART offers wake-up from low-power modes through its Multi-Input Wake-Up module (MIWU). When the

LMX5453 is in a low-power mode, RTS# and CTS# can function as Host_WakeUp and Bluetooth_WakeUp,

respectively. Table 14 represents the operational modes supported by the LMX5453 firmware for implementing

the HCI transport port with the UART.

Table 14. UART Operation Modes

Modes

Range

Default at Power-Up

With Auto Baud Detect

Configured by option

pins, NVS parameter,

or auto baud rate

detection

Baud Rate

0.3 to 921.6 kbaud

Flow Control

Parity

RTS#/CTS# or None

RTS#/CTS#

Odd, Even, or None

None

Stop Bits

Data Bits

1 or 2

8

1

8

1

8

USB Interface

The LMX5453 USB node controller features enhanced DMA support with many automatic data handling features.

It is certifiable to USB specification version 2.0. The USB interface is the standard 12 Mbit/s. An internal PLL

provides the necessary 48 MHz clock.

The USB node controller integrates the required USB transceiver, a Serial Interface Engine (SIE) and USB

endpoint FIFOs. Seven endpoint pipelines are supported: one for the mandatory control endpoint and six to

support interrupt, bulk, and isochronous endpoints. Each endpoint pipeline has a dedicated FIFO (8 bytes for the

control endpoint, and 64 bytes for the other endpoints).

Audio Port

Advanced Audio Interface

The Advanced Audio Interface (AAI) is an advanced version of the Synchronous Serial Interface (SSI) that

provides a full-duplex communications port to a variety of industry-standard 13/14/15/16-bit linear or 8-bit log

PCM codecs, DSPs, and other serial audio devices.

The interface supports up to two codecs or interfaces. The firmware selects the desired audio path and interface

configuration using a parameter in RAM (imported from nonvolatile storage or programmed during boot-up). The

audio path options include 16-bit two’s complement linear audio through the HCI transport, the Motorola

MC145483 codec, and the OKI MSM7717 codec through the AAI, or No Audio. See NVS Table 21.

If an external codec or DSP is used, the LMX5453 audio interface generates the necessary bit and frame clock

for driving the interface.

Table 15 summarizes the audio path selection and the configuration of the audio interface at the specific modes.

The LMX5453 supports two simultaneous SCO links.

Table 15. Audio Path configuration

AAI Frame Sync

Pulse Length

Audio setting

Interface

Freq

Format

AAI Bit Clock

480 KHz

AAI Frame Clock

8 KHz

Advanced audio

interface

8-bit log PCM (a-law

only)

OKI MSM7717

14 Bits

(1)

ANY

Motorola

Advanced audio

interface

13-bit linear

480 KHz

8 KHz

13 Bits

MC145483⁽²⁾

(1) For supported frequencies see Table 5

(2) Due to internal clock divider limitations the optimum of 512KHz, 8KHz can not be reached. The values are set to the best possible

values. The clock mismatch does not result in any discernible loss in audio quality.

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Table 15. Audio Path configuration (continued)

AAI Frame Sync

Pulse Length

Audio setting

Interface

Freq

Format

AAI Bit Clock

520 KHz

AAI Frame Clock

Advanced audio

interface

8-bit log PCM (a-law

only)

OKI MSM7717

8 KHz

--

14 Bits

13 Bits

14 Bits

13 Bits

8/16 Bits

--

13MHz

Motorola

Advanced audio

interface

13-bit linear

520 KHz

MC145483⁽³⁾

Winbond

W681310

Advanced audio

interface

8 bit log PCM A-law

and u-law

13MHz

ANY⁽¹⁾

520 KHz

Winbond

W681360

Advanced audio

interface

13-bit linear

8/16 bits

520 KHz

Advanced audio

interface

PCM slave⁽⁴⁾

128 - 1024 KHz

--

Audio over

HCI

16-Bit Two’s

Complement Linear

HCI Transport

(3) Due to internal clock divider limitations the optimum of 512KHz, 8KHz can not be reached. The values are set to the best possible

values. The clock mismatch does not result in any discernible loss in audio quality.

(4) In PCM slave mode, parameters are stored in NVS. Bit clock and frame clock must be generated by the host interface.

PCM slave configuration example: PCM slave uses the slot 0, 1 slot per frame, 16 bit linear mode, long frame

sync, normal frame sync. In this case, 0x03E0 should be stored in NVS. See ** “LMX5453 Software User’s

Guide” for more details.

Auxiliary Ports

RESET#

There are two reset inputs: RESET_RA# for the radio and RESET_BB# for the baseband. Both are active low.

There is also a reset output, B_RESET_RA# (Buffered Radio Reset), which is also active low. This output follows

input RESET_RA#. When RESET_RA# is released, going high, B_RESET_RA# stays low until the clock has

started.

See ** Section 15.0 for details and Section 16.0 for schematics.

General Purpose I/O Ports

The LMX5453 provides 3 GPIO ports which either can be used as indication and configuration pins or can be

used for general-purpose functionality. The states which select these options are sampled during the start-up

sequence.

In a general-purpose configuration, the pins are controlled by hardware-specific HCI commands. These

commands provide the ability to set the direction of the pin, drive the pin high or low, and enable a weak pull-up

on the pin.

In the alternate-function configuration, the pins have predefined indication functions. See Table 16 for a

description of the alternate-function configuration.

Table 16. Alternate GPIO Pin Configuration

OP4/PG4

PG6

Description

Operation mode pin to configure transport layer settings during boot-up

USB status indication

PG7

TL (Transport Layer) traffic indication

System Power-Up

To power-up the LMX5453 the following sequence must be performed:

1. Apply VCC_IO and VCC to the LMX5453.

2. The RESET_RA# should be driven high.

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3. Then RESET_BB# should be driven high at a recommended time of 1ms after the LMX5453 voltage rails are

high. The LMX5453 is properly reset. (See Figure 10).

all VCC and VDD lines

t

PTORRA

RESET_RA#

t

PTORBB

RESET_BB#

X1_CKO

LMX5453

Initialization

LMX5453

Oscillator

Start-Up

LMX5453 in Normal Mode

LMX5453 in

Power-Up Mode

Figure 10. LMX5453 Power-On Reset Timing

Table 17. LMX5453 Power to Reset Timing

Symbol

t_PTORRA

t_PTORBB

Parameter

Condition

Min

Typ

Max

Units

µs

Power to Reset

Reset to Reset

VCC and VCC_IO at operating voltage level to valid reset <500⁽¹⁾

VCC and VCC_IO at operating voltage level to valid reset

1⁽²⁾

ms

(1) Rise time on power must switch on fast, rise time <500 µs

(2) Recommended value.

Table 18. ESR vs. Start-Up Time

ESR (Ω)

10

Typical⁽¹⁾⁽²⁾

Units

ms

12

13

16

24

30

25

ms

40

ms

50

ms

80

ms

(1) Frequency, loading caps, and ESR all must be considered for determining the start-up time.

(2) For reference only, must be tested on each system to accurately determine the start-up time.

Start-Up Sequence

During start-up, the LMX5453 samples the option inputs OP3 to OP7 for configuration, external clock source,

HCI transport layer, and available non-volatile storage EEPROM interface. The start-up options are described in

Table 20.

Options Register

The states sampled from the OP inputs listed in Table 20 are latched in this register at the end of reset. The

Options register can be read by the LMX5453 firmware at any time.

All pads are inputs with weak on-chip pull-up/down resistors during reset. The resistors are disconnected at the

end of RESET_BB#.

1 = Pull-up resistor connected in application

0 = Pull-down resistor connected in application

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x = Don’t care

Start-Up With External EEPROM

To read information from an external EEPROM, the OP inputs have to be strapped according to Table 20.

The start-up sequence performs these operations:

1. From the Options register bits OP6 and OP7, the firmware checks whether a serial EEPROM is available to

use (ACCESS.bus or Microwire/SPI).

2. If a serial EEPROM is available, the permanent parameter block, patch block, and non-volatile storage (NVS)

are initialized from it.

3. From the Options register bits OP3, OP4, and OP5, the firmware checks for clocking information and

transport layer settings. If the NVS information are not sufficient, the firmware will send the Await Initialization

event on the TL and wait for additional information (see ** Section 15.1.3)

4. The firmware compensates the UART for new BBCLK information from the NVS.

5. The firmware starts up the Bluetooth core.

Start-Up Without External EEPROM

The following sequence will take place if OP6 and OP7 have selected No external memory, as described in

Table 20.

The start-up sequence performs these operations:

1. From the Options registers OP6 and OP7, the firmware checks if an EEPROM is available to use.

2. From the Options register OP3, OP4 and OP5, the firmware checks the clocking mode and transport layer

settings.

3. The firmware sends the Await Initialization event on the transport layer and waits for NVS configuration

commands. The configuration is finalized by sending the Enter Bluetooth Mode command.

4. The firmware compensates the UART for new BBCLK information from the NVS.

5. The firmware starts up the Bluetooth core.

Table 19. Start-Up Sequence Options⁽¹⁾

Package Pad

Description

OP3

OP4

OP5

OP6

OP7

ENV1#

PD = Internal pull-

down during reset

PU = Internal pull-up

during reset

PD

PU

x

Open (0)

1

Open (0)

Open (1) BBCLK

No serial memory

TBD

Microwire serial

memory

x

Open (0)

1

Open (1) BBCLK

ACCESS.bus serial

memory

x

1

T_SCLK

T_RFDATA

T_RFCE

0 BBCLK/US BCLK Test mode

(1) I/O pull-up/down resistor connected in application.

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Table 20. Fixed Frequencies

Osc Freq

(MHz)

PLL (48

MHz)

BBLCK (MHz)

OP3

OP4

OP5

Description

12

13

12

13

10-20⁽¹⁾

Off

On

0

1

0

1

0

HCI UART transport

layer with baud rate

detection

10-20

HCI UART transport

layer 115.2 kbaud

13

Off

1

0

12

13

12

13

10-20⁽¹⁾

On

0

1

0

1

HCI USB transport

layer

10-20

HCI UART transport

layer 921.6 kbaud

13

Off

1

(1) See Table 5 for supported frequencies.

Configuring the LMX5453 Through the Transport Layer

As described in Section 15.0, the LMX5453 checks the Options register during start-up to determine whether an

external EEPROM is available. If the EEPROM information is incomplete or no EEPROM is installed, the

LMX5453 will boot into the initialization mode. The mode is confirmed by the Await Initialization event.

The following information is needed to enter Bluetooth mode:

•

Bluetooth Device Address (BD_ADDR)

External clock source (only if 10–20 MHz has been selected)

UART baud rate (only needed if auto baud rate detection has been selected)

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Reset

OP6/7

EEPROM available?

yes

no

Read BD_Addr

CLK, UART speed.

Apply Patches

OP3/4/5

Transport Layer

and Clock?

USB

UART

Clock and baudrate

properly defined by

the NVS?

Clock and baudrate

properly defined by

the OP pins?

no

Clock properly defined

by OP pins or NVS?

yes

ERROR

undefined clock

AutoBaudrate

Detection

Send HCI command to

set temporary values

for Clock and Baudrate

no

BD_Addr available

in NVS?

Send HCI command

to set BD_Addr

yes

Send HCI command

to Enter BT Mode

Bluetooth Mode

Figure 11. Flow Chart for the Start-Up Sequence

In general, the following procedure will initialize the LMX5453:

1. Wait for the Await initialization event. The event will only appear if the transport layer speed is set or after

successful baud rate detection.

2. Send Set Clock and Baudrate command for temporary clock frequency and UART configuration.

3. Send Write BD_Addr to configure local Bluetooth device address.

4. Send Enter Bluetooth Mode. The LMX5453 will use the configured clock frequency and UART baud rate to

start the HCI transport layer interface.

Note: These clock and baud rate settings are only valid until the next power-on or hardware reset.

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Auto Baud Rate Detection

The LMX5453 supports an auto baud rate detection in case the external clock is different from 12, 13 MHz or the

range 10-20 MHz or the baud rate is different from 115.2 or 921.6 kbaud.

The baud rate detection is based on the measurement of a single character. The following issues need to be

considered:

•

The flow control pin CTS# must be low, otherwise the host is held in flow stop mode.

The auto baud rate detector measures the length of the 0x01 character from the positive edge of bit 0 to the

positive edge of the stop bit.

•

Therefore, the very first received character must always be 0x01.

The host can restrict itself to send only a 0x01 character or it can send an HCI command.

If an HCI command is used for baud rate detection, the second received character must be 0x00.

The host must flush the TX buffer within 50–100 milliseconds, depending on the clock frequency of the host

controller.

•

After 50–100 milliseconds, the UART is about to be initialized. Then, the host should receive an Await

Initialization event or a Command Status event.

CTS#

RX

0x01

0x00

ꢀꢁ±ꢂꢁꢁꢃPVꢃGHOD\

Figure 12. Auto Baud Rate Detection

Using an External EEPROM for Nonvolatile Storage

The LMX5453 offers two interfaces for connecting to external EEPROM used for non-volatile storage (NVS). The

interface is selected by the states sampled from the option inputs during the start-up sequence. See Table 20 for

the available options.

The external memory is used to store mandatory parameters such as the Bluetooth device address (BD_ADDR)

as well as many optional parameters such as link keys or user data.

The firmware uses fixed addresses to reference the parameters, which allows the EEPROM to be

preprogrammed with default parameters in manufacturing. See Table 21 for the organization of the NVS

parameter map.

If the EEPROM is empty, during the first start-up the LMX5453 will behave as though no memory is connected.

(see ** Section 15.1.3). During the start-up sequence, parameters can be written directly to the EEPROM so that

they can be used during subsequent sessions. Patches supplied over the transport layer will be stored

automatically into the EEPROM.

Table 21. Non Volatile Storage Map

Address

Name

Description

Bluetooth Device Address

LAP(lsb), LAP, UAP, NAP, NAP (msb)

00-05⁽¹⁾

BD_ADDR

0x00: One motorola MC145483 codec

0x01: Two motorola MC145483 codecs

0x02: One OKI MSM7717 codec

0x03: Two OKI MSM7717 codecs

06

Audio Path Selection

Baudrate

0x04: Generic PCM Slave. For this setting the generic slave configuration and the

generic slave frame clock prescaler must also be set to correct values in the NVS.

0x05 0xFE: No audio path

0xFF: HCI used for SCO transfer

07-0A

(1) Parameters located at these addresses are requested by the Bluetooth Core for proper operation.

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Table 21. Non Volatile Storage Map (continued)

Address

Name

Description

0B

0C-0D

0E-0F

10

Frame settings⁽²⁾

USB Vid

USB PID

USB Self powered

USB max power

Frequency⁽³⁾

11

12-15

Core parameters

16-BD⁽¹⁾

BE⁽¹⁾

BF-1B6⁽¹⁾

1B7⁽¹⁾

1B8⁽¹⁾

1B9-1C8⁽¹⁾

Link Keys

Local Name Length

Local Device Name

Link Key Type

Unit Key Present

Unit Key

Internal use, 24 bytes per key

Length of Local Device Name

Friendly bluetooth name of the bluetooth device

Debugging info

Internal use only.

Reserved

1C9-1D7

1D8-1E9

Assert Information

Runtime Information

1EA

Options

Bit 0: Reserved

Bit 1: Low power operation

0: Disable low power operation

1: Enable low power operation

Bit 2: Traffic LED Indication

0: Enable traffic LED indication on PG7

1: Disable traffic LED indication on PG7

Bit 3: USB status

0: Enable USB status on PG6

1: Disable USB status on PG6

Bit 4: TLKAS (Transport Layer Keep Alive during Scans)

0: Normal TL power off

1: Only power off TL if page/inquiry scans disabled Bit4 has no effect on USB TL.

The USB TL will always use halt in order to comply with USB power constraints.

This option does not affect the protocol for TL power management, only the

internal operation of the firmware. TLKAS == 0 requires a stable clock when

exiting from HALT mode.ormal TL power off

Bit 5-7: Unused

1EB

1EC

1ED

1EE

Vtune_Desired_Threshold

Vtune_on

Internal use only.

Vtune_enable

AclAndScoBufferMode

0: 8 339 byte ACL buffers, 2 SCO buffers

1: 8 ACL 339 bytes, 1 eSCO/SCO

2: 4 339 byte ACL, 2 eSCO/SCO

0xFF: specifies same set-up as 1.

(2) This parameter can only be used with a pre-programming external EEPROM.

(3) The frequency parameter is only needed when the firmware starts up in a mode with unknown crystal frequency (10- 20MHz). FSEL

pins are used to determine if the crystal frequency is unknown. Reference Table 5 for supported frequencies.

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Table 21. Non Volatile Storage Map (continued)

Address

Name

Description

1F1-1F2

Generic PCM slave config

This 16-bit value (LSB first) is used to store the PCM format configuration for the

PCM generic slave. The Fcprs value must also be set in order to use the generic

PCM slave.

Attention: Some values are not mapped directly to the parameter values, because

we want 0xFF to select the default behavior.

Bit 0-1: Slot selection:

11: use slot 0

00: use slot 1

01: use slot 2

10: use slot 3

Bit 2-3: Number of slots per frame:

11: 1 slot

00: 2 slots

01: 3 slots

10: 4 slots

Bit 4-6: PCM data format:

000: 8 bit A-law

001: 8 bit u-law

010: 13 bit linear

011: 14 bit linear

100: 15 bit linear

101: 16 bit linear

110: 16 bit linear

111: 16 bit linear

Bit 7: Frame sync length:

0: short frame sync

1: long frame sync

Bit 8: Data word length:

0: 8-bit data word length

1: 16-bit data word length

Bit 9: Frame sync polarity:

0: use normal frame sync

1: use inverted frame sync

Bit 10-15: Unused, set to 1

1F3

Generic PCM slave Fcprs

Frame clock prescaler for generic PCM slave. The ratio between the bit clock and

the frame clock must be written into this register for the generic PCM slave to

operate correctly.

BIT0-6: Fcprs

This value is an unsigned integer indicating the prescaler. The following equation

must be true: bit_clock/(Fcprs + 1) = frame_clock.

Example: bit clock = 480000, frame sync rate = 8000, Fcprs must be set to 59

since 480000/(59 + 1) = 8000

BIT7: Unused, set to 1

Production Parameters

1F0⁽⁴⁾

XOC_TUNE

RfReg4

1F4-1F7

1F8-1FB

1FC-1FF

RfReg15

Unused

Reserved for RF development

Internal use only.

200-2FF

RF Development

Patch code

Patch Code Area

300-1CFF

Space for Patch code, activated during startup

Application Data

1D00-2000

1D00-4000

1D00-8000

User Data

Available space if 8K EEPROM is used

Available space if 16K EEPROM is used

Available space if 32K EEPROM is used

(4) Reference Section 11.0 "Crystal Requirements" on page 12 for details on crystal tuning.

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Low-Power Operation

The LMX5453 provides low-power modes which cover the main usage scenarios in a Bluetooth environment.

Each of the low-power modes is optimized for minimal power consumption in that particular scenario. The

modular structure of the LMX5453 allows the firmware to power down unused modules or to switch to a low-

speed clock. Because the LMX5453 firmware supports these modes transparently, no power-control mechanisms

need to be implemented by application code to use these modes.

To reduce power consumption, the LMX5453 can disable the UART transport layer, which switches off the UART

module and enables a wake-up mechanism triggered by the UART interface.

Power Modes

The LMX5453 has six operating power modes, which are selected by the activity level of the HCI transport layer

and the Bluetooth baseband processor. Mode switching is triggered by a change in the baseband processor

activity or by enabling/disabling the UART transport layer.

The baseband processor activity depends on application requirements and is defined by standard Bluetooth

operations such as inquiry/page scanning and link establishment.

A remote device establishing or disconnecting a link may also indirectly change the baseband processor activity

and therefore the power mode.

The HCI transport layer is enabled on device power-up by default. To disable the transport layer, the vendor-

specific HCI command HCI_DISABLE_TL is used. Therefore, only the host side of the HCI can disable the

transport layer. Reenabling the transport layer is controlled by the hardware wake-up signalling. This can be

performed from either the host or the LMX5453 side of the interface. See Section 15.5 for detailed information.

Note: The HCI_Disable_TL command is only supported with the UART transport layer. The Main clock can

disabled for PM0. The Main clock itself may be 12, 13, or 10-20 MHz. The PLL will always be enabled if the

transport layer is USB or if the transport layer is UART but the Main clock is not 12 or 13 MHz. Also, in PM2, the

Main and System clocks will be disabled by Host Controller when not needed by the Lower Link Controller.

Table 22. LMX5453 Power Modes

Power Mode

UART Mode

Baseband Activity

Description

PM0

Disabled Wake-Up Trigger Enabled

None

Standby mode.

Transport layer ready to receive commands,

no baseband processor activity.

PM1

PM2

Enabled

None

LMX5453 discoverable/connectable for other

devices. UART disabled. Wake-up trigger

enabled to wake-up host on incoming

connection.

Disabled Wake-Up Trigger Enabled

Scanning

LMX5453 discoverable/connectable for other

devices. UART enabled.

PM3

PM4

PM5

Enabled

Disabled Wake-Up Trigger Enabled

Enabled

Scanning

Active Link

LMX5453 handling at least one link. UART

disabled. Wake-up trigger enabled to wake-

up host on incoming data or connections.

Standard active mode. LMX5453 handling at

least one link.

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The LMX5453 switches between power modes in response to certain changes in activity. Because any of the

parameters can be changed dynamically, there is no limitation on which mode can be reached from another.

Figure 13 shows an overview of the power modes and the transitions between modes.

Bluetooth Baseband

Page/Inquiry Scanning

Active Link(s)

Disabled

Disconnect

HCI Disabled

PM0

PM2

PM4

Incoming

Connection

HCI

Disable

HCI

Enable

HCI

Disable

HCI

Enable

HCI

Disabl

HCI

Enable

Scan Disable

Disconnect

Connection

HCI Enabled

PM1

PM3

PM5

Scan Enable

Connection

Figure 13. LMX5453 Power Modes

Controlling the UART

Hardware Wake-Up Function

In certain usage scenarios, the host may switch off the transport layer of the LMX5453 to reduce power

consumption. Then, both devices are able to shut down their UART interfaces. In this mode, the firmware will

configure the UART interface to enable a hardware wake-up trigger.

The hardware interface between the host and the UART interface on the LMX5453 is shown in Figure 14.

Host

LMX5453

RTS

CTS

TX

RTS

CTS

TX

RX

Figure 14. UART Null Modem Connections

Disabling the UART

The host can disable the UART transport layer by sending the Disable Transport Layer command. In response,

the LMX5453 will empty its buffers, send the confirmation event, and disable its UART interface. Then, the UART

interface will be reconfigured to wake-up the LMX5453 when a rising edge occurs on the CTS# input.

When the HCI transport layer is disabled, both the host and the LMX5453 will drive RTS=0, because they will be

in a Not Ready to Receive mode. The hardware wake-up signal is then defined as a falling edge on the CTS

input i.e. a device wakes up the other device by asserting its own Ready to Receive output (i.e. Setting RTS

active).

If the LMX5453 redefines the CTS input from flow-control input to wake-up input when the UART has shifted out

the last byte of the HCI_COMMAND_COMPLETE (for HCI_DISABLE_TL) event and the host redefines its RTS

output when it has received the last byte of the HCI_COMMAND_COMPLETE event there will be a short period

of time during which the signalling is ambiguous. To avoid this, delays are introduced as illustrated in Figure 15.

LMX5453 To Host Wake-Up and UART Enable

Because the transport layer can be disabled in any situation, the LMX5453 must first verify that the transport

layer is enabled before sending data to the host. Possible scenarios in which the LMX5453 must wake up the

host include incoming data or incoming link indicators. If the UART is not enabled, the LMX5453 assumes that it

must wake up the host by asserting RTS#. To respond to this assertion, the host must monitor its CTS# input.

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When CTS# is asserted, the host must wake up its UART interface and confirm the UART status by sending the

HCI_RTX_WAKEUP_COMPLETE event. This event should not be sent until the HCI transport layer is ready for

transferring data. When the host receives the HCI_RTX_WAKEUP_COMPLETE debug event, both sides know

that the HCI transport layer is enabled.

Host

Controller

Host

RTS+CTS used for flow-control

HCI_DISABLE_TL

After last Tx byte:

Set RTS Inactive

RTS is now used for power-control

After last Rx byte:

Set RTS Inactive

L

DHC

RTS is now used for power-control

CTS is now used for power-control

From now setting RTS will

wake-up the Host

DH

From now setting RTS will

wake-up the Host Controler

L is the time period in which the RTS/CTS signalling is

ambiguous.

To make the mechanism work, the following relations

must be true:

DHC is the time period the LMX5453 must delay redefin-

ing CTS to Wake-Up input.

Lmax L Lmin

DHC Lmax

DH is the time period the Hostmust wait before attempt-

ing to send a Wake-Up signal to the LMX5453 by setting

RTS active.

DH DHC - Lmin

Figure 15. Disabling the UART Transport Layer

The LMX5453 should now send the pending HCI events that triggered the wake-up. See Figure 16 for the

complete process.

Host

LMX5453

HCI_Disable TL

HCI_Command_Complete

HCI TL Disabled

Air Activity

Set RTS Active

HW Wakeup

HW Wakeup Ack.

Set RTS Active

HCI Wakeup Complete

HCI TL Enabled

Figure 16. LMX5453 Wake-Up to Host

Host to LMX5453 Wake-Up and UART Enable

If the host needs to send data or commands to the LMX5453 while the UART transport layer is disabled, it must

first assume that the LMX5453 is sleeping and wake it up by asserting its RTS signal.

When the LMX5453 detects the wake-up signal, it enables the UART and acknowledges the wake-up signal by

asserting its RTS signal. Additionally, the wake up will be confirmed by a confirmation event. When the host has

received this HCI_WAKEUP_COMPLETE event, the LMX5453 is ready to receive commands. The host may now

send the pending HCI events that triggered the wakeup. See Figure 17 for the complete process.

Note: Even though the LMX5453 sets RTS active (indicating Ready to Receive mode), the host must not send

any HCI commands to the LMX5453 before receiving the HCI_WAKEUP_COMPLETE event.

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Host

LMX5453

HCI_Disable TL

HCI_Command_Complete

HCI TL Disabled

Host Activity

HW Wakeup

Set RTS Active

HCI Wakeup Complete

Set RTS Active

HCI TL Enabled

Figure 17. Host Wake-Up to LMX5453

Applications Information

USB Dongle Reference Schematic

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Soldering

The LMX5453 bumps are composed of a solder alloy and reflow (melt and reform) during the Surface Mount

Assembly (SMA) process. In order to ensure reflow of all solder bumps and maximum solder joint reliability while

minimizing damage to the package, recommended reflow profiles should be used. Table 23, Table 24, and

Figure 18 provide the soldering details required to properly solder the LMX5453 to standard PCBs. The

illustration serves only as a guide and Texas Instruments is not liable if a selected profile does not work.

Table 23. Soldering Details

Parameter

Value

PCB Land Pad Diameter

PCB Solder Mask Opening

PCB Finish

13 mil

19 mil

Defined by customer or manufacturing facility

17 mil

Stencil Aperture

Stencil Thickness

5 mil

Solder Paste Used

Flux Cleaning Process

Defined by customer or manufacturing facility

(1)(2)

Table 24. Classification Reflow Profiles

Profile Feature

NOPB Assembly

Average Ramp-Up Rate (TsMAX to Tp)

Preheat:

150°C

200°C

60–180 seconds

Temperature Min (Ts_MIN

Temperature Max (Ts_MAX

Time (ts_MINto ts_MAX

)

Time maintained above:

Temperature (T_L)

Time (t_L)

217°C

60–150 seconds

Peak/Classification Temperature (Tp)

Time within 5°C of actual Peak Temperature (tp)

Ramp-Down Rate

260 + 0°C

20–40 seconds

6°C/second maximum

8 minutes maximum

See Figure 18

Time 25°C to Peak Temperature

Reflow Profiles

(1) See ** IPC/JEDEC J-STD-020C, July 2004.

(2) All temperatures refer to the top side of the package, measured on the package body surface.

Figure 18. Typical Reflow Profiles

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REVISION HISTORY

Changes from Revision C (June 2013) to Revision D

Page

•

Added data to Recommended Operating Conditions because data was missing from old National version ...................... 6

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MECHANICAL DATA

NZB0060A

SLF60A (Rev A)

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型号：	LMX5453
厂家：	TEXAS INSTRUMENTS
描述：	LMX5453 Micro-Module Integrated BluetoothÂ®2.0 Baseband Controller and Radio
文件：	总37页 (文件大小：2335K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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