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LMX8410L

ZHCSHV3A –MARCH 2018–REVISED NOVEMBER 2018

带集成式合成器的 LMX8410L 高性能混合器

1 特性

3 说明

1

•

宽带射频输入：4 至 10GHz

LMX8410L 是一款具有集成 LO 和 IF 放大器的高性能

宽带（射频输入为 4 至 10GHz）I/Q 解调器。在 IIP3

为 28dBm 而 NF 为 15dB（频率均为 5GHz）的情况

下，该器件可提供出色的动态范围，适用于高性能应

用中使用 DP83869。该器件可提供 2.7GHz 的大型复

杂带宽，适用于高数据速率应用。

大型中频带宽：直流至 1350MHz

输入 IP3：5GHz 射频输入时为 28dBm

噪声系数：5GHz 射频输入时为 15dB

高电压转换增益：5GHz 射频输入时为 11dB

集成宽带射频输入平衡-非平衡变压器

自动离线直流失调电压校正为 ±2mV

可编程 IMRR 校准

LMX8410L 提供自动直流失调电压校正算法，可将失

调电压降至 ±2mV 以下。使用 SPI 接口可以精确控制 I

和 Q 通道的增益和相位，从而实现高镜像抑制。

针对多个器件的同步功能

高性能集成 LO 合成器：5GHz 载波条件下具有

56.5dBc 的 DSB 集成噪声

LMX8410L 具有高度集成度，可提供高性能，同时还

能节省布板空间并降低复杂性。它集成了宽带射频输入

平衡-非平衡变压器，因此无需外部平衡-非平衡变压

器。它集成了高性能 PLL 和 VCO，因此无需外部 LO

和 LO 驱动器。该器件还集成了一个 IF 放大器和几个

低噪声 LDO，进一步简化了电路板。

•

外部 LO 模式：可旁路绕开集成 LO 合成器；支持

外部 LO 注入

•

集成低噪声 LDO

7mm × 7mm 48 引脚 QFN 封装

2 应用

LMX8410L 集成了一个极低噪声的合成器，PLL FOM

为 –236dBc/Hz，在 5GHz 载波条件下提供高达

56.5dBc 的 DSB 集成噪声。LO 允许跨多个器件进行

相位同步。高性能合成器输出可用于驱动另一级或数据

转换器。对于共享外部 LO 的应用，可以旁路掉集成

的 LO。

•

测试和测量设备

无线基础设施

相控阵雷达

微波回程

卫星通信

软件定义无线电

器件信息⁽¹⁾

器件型号

LMX8410L

封装

VQFN (48)

封装尺寸（标称值）

7.00mm × 7.00mm

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

简化方框图

IF I Output

SYNC

OSCin

Synthesizer

IQ LO

generator

RF input

LO output

External LO input

MUX

IF Q Output

SPI

Interface

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNAS730

LMX8410L

ZHCSHV3A –MARCH 2018–REVISED NOVEMBER 2018

www.ti.com.cn

7.5 Programming........................................................... 29

7.6 Register Map........................................................... 30

Application and Implementation ........................ 53

8.1 Application Information............................................ 53

8.2 Typical Application ................................................. 53

Power Supply Recommendations...................... 56

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 6

6.1 Absolute Maximum Ratings ...................................... 6

6.2 ESD Ratings.............................................................. 6

6.3 Recommended Operating Conditions....................... 6

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics........................................... 7

6.6 Timing Requirements.............................................. 12

6.7 Typical Characteristics............................................ 14

Detailed Description ............................................ 22

7.1 Overview ................................................................. 22

7.2 Functional Block Diagram ....................................... 22

7.3 Feature Description................................................. 23

7.4 Device Functional Modes........................................ 28

8

9

10 Layout................................................................... 56

10.1 Layout Guidelines ................................................. 56

10.2 Layout Examples................................................... 57

11 器件和文档支持 ..................................................... 61

11.1 文档支持................................................................ 61

11.2 接收文档更新通知 ................................................. 61

11.3 社区资源................................................................ 61

11.4 商标....................................................................... 61

11.5 静电放电警告......................................................... 61

11.6 术语表 ................................................................... 61

12 机械、封装和可订购信息....................................... 61

7

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Original (March 2018) to Revision A

Page

•

首次发布生产数据产品说明书 ................................................................................................................................................ 1

Changed many numbers in electrical specifications table. .................................................................................................... 6

已添加 typical performance characteristics section. ............................................................................................................ 14

已更改 and added significant details in detailed descriptions sections. Added sections, changed several portions of

the register map.................................................................................................................................................................... 22

2

LMX8410L

www.ti.com.cn

ZHCSHV3A –MARCH 2018–REVISED NOVEMBER 2018

5 Pin Configuration and Functions

RGZ Package

48-Pin QFN

Top View

48

47

46

45

44

43

42

41

40

39

38

37

CE

VBIAS_VCO2

VBIAS_VCO1

GND

VCM_IN

VCC_IFI

NC

1

2

36

35

34

33

32

31

30

29

28

27

26

25

3

VCC_RF

GND

4

5

SYNC

GND

RF

6

49

VCC_DIG

GND

7

8

OSCINP

OSCINM

VCC_RF

NC

9

VREG_OSCIN

MUXOUT

VCC_IFQ

CSB

10

11

12

DAP

15

VCC_CP

SDI

13

14

16

17

18

19

20

21

22

23

24

Pin Functions

NAME

I/O

DESCRIPTION

NAME

1

CE

Input

Chip Enable input. Active HIGH powers on the device. 1.8V to 3.3V logic.

VCO bias. Requires connecting 10-µF capacitor to VCO ground. Place close to pin. If using

external LO, this pin should either be floated or configured the same way as internal LO mode.

2

3

VBIAS_VCO2

Bypass

VCO bias. Requires connecting 10-µF capacitor to VCO ground. Place close to pin. If using

external LO, this pin should either be floated or configured the same way as internal LO mode.

VBIAS_VCO1

Bypass

4

5

6

7

GND

SYNC

Ground

Input

VCO ground. VBIAS pin capacitors must bypass to this point.

Trigger pin for synchronizing multiple devices. If using external LO, tie this pin to GND.

Digital ground. VCC_DIG bypass capacitors must bypass to this point.

Digital supply. TI recommends connecting 0.1-µF capacitor to digital ground.

GND

Ground

Supply

VCC_DIG

Reference input clock (+). High input impedance. Requires connecting series capacitor (0.1 µF

recommended). If using external LO, tie this pin to GND.

8

9

OSCINP

OSCINM

Input

Reference input clock (–). High input impedance. Requires connecting series capacitor (0.1 µF

recommended). If using external LO, tie this pin to GND.

Internal LDO output. Requires connecting 1-µF capacitor to digital ground. Place close to pin. If

using external LO, this pin should either be floated or configured the same way as internal LO

mode.

10

VREG_OSCIN

Bypass

3

LMX8410L

ZHCSHV3A –MARCH 2018–REVISED NOVEMBER 2018

www.ti.com.cn

Pin Functions (continued)

I/O

DESCRIPTION

NAME

11

MUXOUT

Output

Supply

Readback or lock detect output. Pin mode configured by internal register settings.

Charge pump supply. TI recommends connecting 0.1 µF and 100 pF to charge pump ground.

Place close to pin. This pin must be connected to VCC, even if using external LO.

12

13

VCC_CP

CP

Charge pump output. TI recommends connecting C1 of loop filter close to pin. If using external

LO, this pin should either be floated or configured the same way as internal LO mode.

Output

14

15

GND

Ground

Charge pump ground. VCC_CP bypass capacitors must bypass to this point.

MASH engine ground. VCC_MASH bypass capacitors must bypass to this point.

MASH engine supply. TI recommends connecting 0.1 µF and 100 pF to MASH engine ground.

Place close to pin. This pin must be connected to VCC, even if using external LO.

16

VCC_MASH

Supply

Internal LO differential output (–) or external LO differential input (–). In differential output mode,

requires connecting 50-Ω resistor pullup to V_CCas close as possible to pin. In differential input

mode, remove the pull up resistors or inductors. The input should be capacitively coupled with

internal biasing. See LO Interface for more information.

17

LO_M

Input/Output

Internal LO differential output (+) or external LO differential input (+). In differential output mode,

requires connecting 50-Ω resistor pullup to V_CCas close as possible to pin. In differential input

mode, remove the pull up resistors or inductors. The input should be capacitively coupled with

internal biasing. See LO Interface for more information.

18

LO_P

Input/Output

LO buffer supply. TI recommends connecting 0.1 µF and 100 pF to VCO ground. This pin must

be connected to VCC, even if using external LO.

19

20

21

VCC_BUF

GND

Supply

Ground

Output

IF amplifier Q-channel ground. Q-channel VCC5 bypass capacitors must bypass to this point.

IF amplifier Q-channel differential output (–). TI recommends connecting series 50-Ω resistor

close to pin.

IF_QM

IF amplifier Q-channel differential output (+). TI recommends connecting series 50-Ω resistor

close to pin.

22

23

IF_QP

Output

Supply

IF amplifier Q-channel 5-V supply. TI recommends connecting 0.1 µF and 100 pF to IF amplifier

Q-channel ground. Place close to pin.

VCC5_IFQ

24

25

26

27

28

29

32

31

32

33

34

35

SCK

SDI

Input

SPI clock signal. High impedance CMOS input. 1.8-V to 3.3-V logic.

SPI data signal. High impedance CMOS input. 1.8-V to 3.3-V logic.

SPI chip select signal. High impedance CMOS input. 1.8-V to 3.3-V logic.

IF mixer Q-channel supply. TI recommends connecting 0.1 µF and 100 pF to digital ground.

No connect. Pin is not internally connected and may be floated or shorted to other nodes.

RF Q-channel supply. TI recommends connecting 0.1 µF and 100 pF to digital ground.

RF input path ground.

CSB

Input

VCC_IFQ

NC

Supply

N/A

VCC_RFQ

GND

Supply

Ground

Input

RF

RF input. Single-ended. Must be AC coupled.

GND

Ground

Supply

Ground

Supply

RF input path ground.

VCC_RFI

GND

RF I-channel supply. TI recommends connecting 0.1 µF and 100 pF to digital ground.

Should be connected IF ground.

VCC_IFI

IF mixer I-channel supply. TI recommends connecting 0.1 µF and 100 pF to digital ground.

Common-mode voltage input. When the VCM_CONFIG register is set to external (0xF), the

voltage on this pin sets the common-mode voltage of the IF amplifiers.

36

37

38

VCM_IN

NC

Input

Ground

Supply

Connect this pin to IF ground.

IF amplifier I-channel 5-V supply. TI recommends connecting 0.1 µF and 100 pF to IF amplifier I-

channel ground. Place close to pin.

VCC5_IFI

IF amplifier I-channel differential output (+). TI recommends connecting series 50-Ω resistor close

to pin.

39

IF_IP

Output

IF amplifier I-channel differential output (–). TI recommends connecting series 50-Ω resistor close

to pin.

40

41

42

43

IF_IM

GND

Output

Ground

Bypass

Ground

IF amplifier I-channel ground. I-channel VCC5 bypass capacitors should bypass to this point.

VCO varactor bias. Requires connecting 10µF capacitor to VCO ground. If using external LO, this

pin should either be floated or configured the same way as internal LO mode.

VBIAS_VARAC

GND

VCO ground. Varactor bias bypass capacitor should bypass to this point.

4

LMX8410L

www.ti.com.cn

ZHCSHV3A –MARCH 2018–REVISED NOVEMBER 2018

Pin Functions (continued)

I/O

DESCRIPTION

NAME

VCO tuning voltage input. If using internal LO, connect the output of the loop filter to this point. If

using external LO, tie this pin to GND.

44

VTUNE

Input

Bypass

Supply

VCO LDO output node. Requires connecting 10-µF capacitor to VCO ground. Place close to pin.

This capacitor must be present even if used in external LO mode.

45

46

VREG_VCO

VCC_VCO

VCO supply. TI recommends connecting 0.1-µF and 100-pF capacitors to VCO ground. This pin

must be connected to VCC, even if using external LO.

VCO LDO reference node. Requires connecting 1-µF capacitor to VCO ground. If using external

LO, this pin should either be floated or configured the same way as internal LO mode.

47

48

49

VREF_VCO

GND

Bypass

Ground

VCO ground. VCO LDO, LDO reference, and supply bypass capacitors must bypass to this point.

Die attach pad. Internally connected to ground. TI recommends shorting ground pins to this pad

on the same plane, if possible.

PAD

5

LMX8410L

ZHCSHV3A –MARCH 2018–REVISED NOVEMBER 2018

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

3.6

5.3

5

UNIT

V

V_CC

V_CC5

P_D

Power supply voltage, 3.3-V rail

Power supply voltage, 5-V rail

Power dissipation

V

W

T_J

Junction temperature

–40

–65

150

°C

T_stg

Storage temperature

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per

ANSI/ESDA/JEDEC JS-001, all pins

2500

V_(ESD)

Electrostatic discharge

V

Charged device model (CDM), per JEDEC

specificationJESD22-C101, all pins

500

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

3.15

4.75

–40

NOM

3.3

5

MAX

UNIT

V

V_CC

V_CC5

T_A

Power supply voltage, 3.3V rail

Power supply voltage, 5V rail

Ambient temperature

3.45

5.25

85

V

25

°C

T_J

Junction temperature

125

6.4 Thermal Information

LMX8410L

THERMAL METRIC^{(1) (2)}

RGZ (VQFN)

UNIT

48 PINS

21.9

9.4

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

5.6

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.1

Ψ_JB

5.6

R_θJC(bot)

0.4

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2) Thermal model based on JEDEC standard coupon, 50.8 mm × 50.8 mm × 1.6 mm, six-layer Cu, 0.5 oz top layer, 2 oz else. 6 × 6

thermal vias in DAP, 0.2 mm diameter.

6

LMX8410L

www.ti.com.cn

ZHCSHV3A –MARCH 2018–REVISED NOVEMBER 2018

6.5 Electrical Characteristics

Measurements are done at 25 degree C. Parameters are measured at IF = 65MHz with high side injection, unless otherwise

noted. Measurements are done with external VCM = 1.7V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

POWER SUPPLY

V_CC

Power supply voltage, 3.3-V rail

Power supply current, 3.3-V rail

Power supply voltage, 5-V rail

3.15

3.3

650

330

5

3.45

V

Internal LO

I_CC

mA

External LO

V_CC5

I_CC5

4.75

5.25

V

Power supply current both channels I

and Q, 5-V rail

130

mA

FREQUENCY RANGES

F_RF

F_LO

RF port frequency range

4000

10000

MHz

LO port frequency range

IF port frequency range (3dB

bandwidth)

F_IF

DC

1350

MHz

DYNAMIC PERFORMANCE

RF = 4 GHz

RF = 5 GHz

RF = 6 GHz

RF = 7 GHz

RF = 8 GHz

RF = 9 GHz

RF = 10 GHz

RF = 4 GHz

RF = 5 GHz

RF = 6 GHz

RF = 7 GHz

RF = 8 GHz

RF = 9 GHz

RF = 10 GHz

RF = 4 GHz

RF = 5 GHz

RF = 6 GHz

RF = 7 GHz

RF = 8 GHz

RF = 9 GHz

RF = 10 GHz

RF = 4 GHz

RF = 5 GHz

RF = 6 GHz

RF = 7 GHz

RF = 8 GHz

RF = 9 GHz

RF = 10 GHz

15

16

17

18

19

11

10.5

9.5

9

NF

Noise figure

dB

G

Voltage gain⁽¹⁾

dB

8

7

28

26.5

27

26.5

27

48

46

44

45

44

42

IIP3

Input intercept point, 3rd order⁽²⁾

dBm

Input intercept point, 2nd order

(uncalibrated)

IIP2

dBm

(1) For measurements that require RF input, RF input power is -10dBm unless otherwise specified.

(2) For two-tone measurements, tone separation is 17MHz.

7

LMX8410L

ZHCSHV3A –MARCH 2018–REVISED NOVEMBER 2018

www.ti.com.cn

Electrical Characteristics (continued)

Measurements are done at 25 degree C. Parameters are measured at IF = 65MHz with high side injection, unless otherwise

noted. Measurements are done with external VCM = 1.7V.

PARAMETER

TEST CONDITIONS

RF = 4 GHz

MIN

TYP

-58

-54

-52

-50

-48

-75

12

MAX

UNIT

RF = 5 GHz

RF = 6 GHz

SP_2x2

2×2 spur [RF input power at –10 dBm] RF = 7 GHz

dBc

RF = 8 GHz

RF = 9 GHz

RF = 10 GHz

RF = 4 GHz

RF = 5 GHz

RF = 6 GHz

SP_3x3

3×3 spur [RF input power at –10 dBm] RF = 7 GHz

dBc

dBm

dB

RF = 8 GHz

RF = 9 GHz

RF = 10 GHz

RF = 4 GHz

RF = 5 GHz

RF = 6 GHz

12

O_P1dB

Output 1-dB compression point

Image rejection ratio [calibrated]

RF to IF isolation

RF = 7 GHz

RF = 8 GHz

RF = 9 GHz

RF = 10 GHz

RF = 4 GHz

RF = 5 GHz

RF = 6 GHz

RF = 7 GHz

RF = 8 GHz

RF = 9 GHz

RF = 10 GHz

RF = 4 GHz

RF = 5 GHz

RF = 6 GHz

RF = 7 GHz

RF = 8 GHz

RF = 9 GHz

RF = 10 GHz

LO = 4 GHz

LO = 5 GHz

LO = 6 GHz

LO = 7 GHz

LO = 8 GHz

LO = 9 GHz

LO = 10 GHz

12

43

44

IRR

44

43

42

36

40

ISO_RFxIF

40

dB

40

-35

LEAK_RFxIF

LO to IF leakage

dBm

8

LMX8410L

www.ti.com.cn

ZHCSHV3A –MARCH 2018–REVISED NOVEMBER 2018

Electrical Characteristics (continued)

Measurements are done at 25 degree C. Parameters are measured at IF = 65MHz with high side injection, unless otherwise

noted. Measurements are done with external VCM = 1.7V.

PARAMETER

TEST CONDITIONS

LO = 4 GHz

MIN

TYP

-60

-52

-50

-45

–40

MAX

UNIT

LO = 5 GHz

LO = 6 GHz

LO = 7 GHz

LO = 8 GHz

LO = 9 GHz

LO = 10 GHz

LEAK_LOxRF

LO to RF leakage (internal Lo mode)

dBm

PERFORMANCE TUNING

G_{IQ_CAL}

I/Q gain calibration range

IMRR_GCAL register full range

IMRR_PCAL register full range

±0.5

0.05

±20

dB

G_{IQ_STEP}

PH_{IQ_CAL}

I/Q gain calibration step size

I/Q phase calibration range

Deg

Step size can be made reduced

to 0.25 deg in fine accuracy

mode

PH_{IQ_STEP}

I/Q phase calibration step size

calibrated differential DC offset

0.45

+/- 2

Deg

mV

V_DCOC

PORTS

RF = 4 GHz

RF = 5 GHz

RF = 6 GHz

RF = 7 GHz

RF = 8 GHz

RF = 9 GHz

RF = 10 GHz

RF = 4 GHz

RF = 5 GHz

RF = 6 GHz

RF = 7 GHz

RF = 8 GHz

RF = 9 GHz

RF = 10 GHz

8 GHz RF_IN

<7 GHz RFout

<10 GHz RFout

8

19

21

16

10

9

dB

S11_RF

RF return loss

dB

9

dB

15

20

17

18

17

12

6

dB

LO return loss (differential

measurement)

S11_LO

dB

P_{LO_IN}

External LO input power

dBm

VPP

2

P_{LO_OUT}

External LO output power⁽³⁾

-1

2

V_{IF_RANGE}

V_CM

IF output voltage swing (differential)

IF common mode voltage, internal or

external source

1.2

1.7

2

5

V

Pin_RF

RF input power

dBm

LO SYNTHESIZER INPUT SIGNAL PATH

OSC_2X = 0

5

1400

200

2

Reference oscillator port frequency

range

F_OSCIN

V_OSCIN

F_MULT

MHz

Vpp

OSC_2X = 1

AC-coupled required⁽⁴⁾

Reference input voltage

0.2

30

Input range

70

Multiplier frequency (when multiplier

enabled)

MHz

Output range

180

250

(3) Output power, spurs, and harmonics can vary based on board layout and components.

(4) For lower VCO frequencies, the N divider minimum value can limit the phase detector frequency.

9

LMX8410L

ZHCSHV3A –MARCH 2018–REVISED NOVEMBER 2018

www.ti.com.cn

Electrical Characteristics (continued)

Measurements are done at 25 degree C. Parameters are measured at IF = 65MHz with high side injection, unless otherwise

noted. Measurements are done with external VCM = 1.7V.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LO SYNTHESIZER PHASE DETECTOR AND CHARGE PUMP

Integer Mode (FRAC_ORDER =

0)

0.125

400

300

240

Fractional Mode (FRAC_ORDER

= 1,2,3)

F_PD

Phase detector frequency

5

MHz

nA

Fractional Mode (FRAC_ORDER

= 4)

Charge pump leakage current

CPG = 0

CPG = 4

CPG = 1

CPG = 5

CPG = 3

CPG = 7

15

3

6

I_CPOUT

Effective charge pump current (sum of

up and down currents)

9

mA

12

15

PN_1/F

Normalized PLL flicker noise

–129

–236

dBc/Hz

F_PD= 100 MHz, F_VCO= 12

GHz⁽⁵⁾

PN_FLAT

Normalized PLL thermal noise floor

(5) The PLL noise contribution is measured using a clean reference and a wide loop bandwidth and is composed into flicker and flat

components. PLL_FLAT= PLL_FOM+ 20log(F_VCO/ F_PD) + 10log(F_PD/ 1Hz). PLL_FLICKER(offset) = PLL_{FLICKER_NORM}+ 20log(F_VCO/ 1GHz) -

10log(offset frequency / 10kHz). Once these two components are found, the total PLL noise can be calculated as PLL_NOISE

=

10log(10^{PLLFLAT / 10}+ 10^{PLLFLICKER / 10}).

10

LMX8410L

www.ti.com.cn

ZHCSHV3A –MARCH 2018–REVISED NOVEMBER 2018

Electrical Characteristics (continued)

Measurements are done at 25 degree C. Parameters are measured at IF = 65MHz with high side injection, unless otherwise

noted. Measurements are done with external VCM = 1.7V.

PARAMETER

LO SYNTHESIZER VCO

TEST CONDITIONS

MIN

TYP

MAX

UNIT

8 GHz VCO, 10 kHz offset

–80

–107

–128

–148

–157

–79

8 GHz VCO, 100 kHz offset

8 GHz VCO, 1 MHz offset

8 GHz VCO, 10 MHz offset

8 GHz VCO, 90 MHz offset

9.2 GHz VCO, 10 kHz offset

9.2 GHz VCO, 100 kHz offset

9.2 GHz VCO, 1 MHz offset

9.2 GHz VCO, 10 MHz offset

9.2 GHz VCO, 90 MHz offset

10.3 GHz VCO, 10 kHz offset

10.3 GHz VCO, 100 kHz offset

10.3 GHz VCO, 1 MHz offset

10.3 GHz VCO, 10 MHz offset

10.3 GHz VCO, 90 MHz offset

11.3 GHz VCO, 10 kHz offset

11.3 GHz VCO, 100 kHz offset

11.3 GHz VCO, 1 MHz offset

11.3 GHz VCO, 10 MHz offset

11.3 GHz VCO, 90 MHz offset

12.5 GHz VCO, 10 kHz offset

12.5 GHz VCO, 100 kHz offset

12.5 GHz VCO, 1 MHz offset

12.5 GHz VCO, 10 MHz offset

12.5 GHz VCO, 90 MHz offset

13.3 GHz VCO, 10 kHz offset

13.3 GHz VCO, 100 kHz offset

13.3 GHz VCO, 1 MHz offset

13.3 GHz VCO, 10 MHz offset

13.3 GHz VCO, 90 MHz offset

14.5 GHz VCO, 10 kHz offset

14.5 GHz VCO, 100 kHz offset

14.5 GHz VCO, 1 MHz offset

14.5 GHz VCO, 10 MHz offset

14.5 GHz VCO, 90 MHz offset

–105

–127

–147

–157

–77

–104

–126

–147

–157

–76

–103

–125

–145

–158

–74

PNvco

Open loop VCO phase noise

dBc/Hz

–100

–123

–144

–157

–73

–100

–122

–143

–155

–73

–99

–121

–143

–152

50

VCO calibration speed, switch across No assist

the entire frequency band, F_OSC= 200

t_{VCO_CAL}

µs

MHz, F_PD= 100 MHz⁽⁶⁾

Close frequency

20

(6) See Application and Implementation for more details on the different VCO calibration modes.

11

LMX8410L

ZHCSHV3A –MARCH 2018–REVISED NOVEMBER 2018

www.ti.com.cn

Electrical Characteristics (continued)

Measurements are done at 25 degree C. Parameters are measured at IF = 65MHz with high side injection, unless otherwise

noted. Measurements are done with external VCM = 1.7V.

PARAMETER

TEST CONDITIONS

8 GHz

MIN

TYP

89

MAX

UNIT

9.2 GHz

93

10.3 GHz

11.3 GHz

12.5 GHz

13.3 GHz

14.5 GHz

110

124

189

182

205

K_VCO

VCO gain

MHz/V

Allowable temperature drift when VCO

is not re-calibrated

|ΔT_CL

|

125

°C

H2

H3

VCO second harmonic

VCO third harmonic

FVCO = 8 GHz, divider disabled

-30

-40

dBc

SYNC PIN AND PHASE ALIGNMENT

Category 3 (int LO mode)

Category 1 or 2

0

100

Maximum usable OSCIN frequency

F_{OSCIN_SYNC}

MHz

with SYNC pin

DIGITAL INTERFACE (SCK, SDI, CSB, MUXOUT, SYNC, CE)

1400

V_IH

V_IL

I_IH

High level input voltage

Low level input voltage

High level input current

Low level input current

1.4

0

VCC

0.4

50

V

-50

µA

I_IL

50

VCC –

0.55

V_OH

V_OL

High level output voltage

High level output current

I_L= –5 mA

I_L= 5 mA

V

0.55

6.6 Timing Requirements

MIN

NOM

MAX

UNIT

SYNC

t_SETUP

Setup time for pin relative to OSCIN rising edge

Hold time for pin relative to OSCIN rising edge

2.5

2

ns

t_HOLD

DIGITAL WRITE INTERFACE⁽¹⁾

F_{SPI_WRITE}SPI write speed

50

MHz

ns

t_ES

Clock to enable low time

Data to clock setup time

Data to clock hold time

Clock pulse width high

Clock pulse width low

Enable to clock setup time

Enable pulse width high

5

2

t_CS

ns

t_CH

2

ns

t_CWH

t_CWL

t_CES

t_EWH

5

ns

10

ns

DIGITAL READBACK INTERFACE⁽²⁾

F_{SPI_READ}SPI readback speed

50

10

MHz

ns

t_ES

Clock to enable low time

Clock to data wait time

Clock pulse width high

Clock pulse width low

Enable to clock setup time

10

t_CS

ns

t_CWH

t_CWL

t_CES

10

ns

(1) See Figure 1

(2) See Figure 2

12

LMX8410L

www.ti.com.cn

ZHCSHV3A –MARCH 2018–REVISED NOVEMBER 2018

Timing Requirements (continued)

MIN

NOM

MAX

UNIT

t_EWH

Enable pulse width high

10

ns

MSB

LSB

D0

SDI

R/W

A5

A0

D15

D14

SCK

CSB

t

CWH

CS

t_ES

t

CH

CES

t

CWL

t

EWH

图 1. Serial Data Input Timing Diagram

There are several other considerations for writing on the SPI:

•

The R/W bit must be set to 0.

The signal on the SDI pin is clocked into a shift register on each rising edge of the SCK pin.

The CSB must be held low for data to be clocked. Device ignores clock pulses if CSB is held high.

The CSB transition from high to low must occur when SCK is low.

When SCK and SDI lines are shared between devices, TI recommends holding the CSB line high on any

devices besides the intended programming target.

LSB

MUXout

SDI

RB15

RB14

RB0

MSB

R/W

A6

A5

A0

SCK

CSB

t

CS

CWH

t_ES

t

CES

t

CWL

t

EWH

图 2. Serial Data Readback Timing Diagram

There are several other considerations for SPI readback:

•

The R/W bit must be set to 1.

The MUXOUT pin is always for the address portion of the transaction.

The address on the SDI pin is clocked into a shift register on each rising edge of the SCK pin.

The data portion of the transaction on the SDI line is always ignored.

The data on the MUXOUT pin should be considered valid on each rising edge of the SCK pin, provided all

timing requirements are met.

•

All CSB considerations for SPI writing also apply to SPI readback.

13

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ZHCSHV3A –MARCH 2018–REVISED NOVEMBER 2018

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6.7 Typical Characteristics

12

10

8

10

8

6

4

Temperature = -40

Temperature = 25

Temperature = -40

Temperature = 25

Temperature = 85

2

4000

6000

8000

10000

12000

4000

6000

8000

10000

12000

LO Frequency (MHz)

D001

D002

图 3. Voltage Gain Across LO Frequency for Internal LO

图 4. Voltage Gain Across LO frequency for External LO

Mode

14

12

10

8

12

10

8

6

4

2

LO Frequency = 4000 MHz

LO Frequency = 8000 MHz

LO Frequency = 12000 MHz

LO Frequency = 4000 MHz

LO Frequency = 8000 MHz

LO Frequency = 12000 MHz

0

-2

-2000 -1500 -1000 -500

0

500 1000 1500 2000

-2000 -1500 -1000 -500

0

500 1000 1500 2000

IF Frequency

D003

D004

图 5. Voltage Gain Across IF Frequency for Internal LO

图 6. Voltage Gain Across IF Frequency for External LO

Mode

40

Temperature = -40

Temperature = 25

Temperature = 85

Temperature = -40

Temperature = 25

Temperature = 85

38

36

34

32

30

28

26

24

22

20

38

36

34

32

30

28

26

24

22

20

4000

6000

8000

10000

12000

4000

6000

8000

10000

12000

LO Frequency (MHz)

D005

D006

图 7. IIP3 Across LO Frequency for Internal LO Mode

图 8. IIP3 Across LO Frequency for External LO Mode

14

LMX8410L

www.ti.com.cn

ZHCSHV3A –MARCH 2018–REVISED NOVEMBER 2018

Typical Characteristics (接下页)

40

35

30

25

20

15

40

35

30

25

20

15

10

5

10

LO Frequency = 4000 MHz

LO Frequency = 8000 MHz

LO Frequency = 12000 MHz

LO Frequency = 4000 MHz

LO Frequency = 8000 MHz

LO Frequency = 12000 MHz

5

0

-1500

-1000

-500

0

500

1000

1500

-1500

-1000

-500

0

500

1000

1500

IF Frequency (MHz)

D007

D008

图 9. IIP3 Across IF Frequency for Internal LO Mode

图 10. IIP3 Across IF Frequency for External LO Mode

80

70

60

50

40

30

20

10

0

80

70

60

50

40

30

20

10

0

Temperature = -40

Temperature = 25

Temperature = 85

Temperature = -40

Temperature = 25

Temperature = 85

4000

6000

8000

10000

12000

4000

6000

8000

10000

12000

LO Frequency (MHz)

D009

D010

图 11. IIP2: F1-F2 Across LO Frequency for Internal LO

图 12. IIP2: F1-F2 Across LO Frequency for External LO

Mode

80

90

80

70

60

50

40

30

20

10

70

60

50

40

30

20

10

LO Frequency = 4000MHz

LO Frequency = 8000 MHz

LO Frequency = 12000MHz

LO Frequency = 4000MHz

LO Frequency = 8000 MHz

LO Frequency = 12000MHz

0

-1500

-1000

-500

0

500

1000

1500

-1500

-1000

-500

0

500

1000

1500

IF Frequency (MHz)

D011

D012

图 13. IIP2: F1-F2 Across IF Frequency for Internal LO Mode

图 14. IIP2: F1-F2 Across IF Frequency for External LO Mode

15

LMX8410L

ZHCSHV3A –MARCH 2018–REVISED NOVEMBER 2018

www.ti.com.cn

Typical Characteristics (接下页)

80

70

60

50

40

30

80

70

60

50

40

30

20

10

0

20

Temperature = -40

Temperature = 25

Temperature = 85

Temperature = -40

Temperature = 25

Temperature = 85

10

0

4000

6000

8000

10000

12000

4000

6000

8000

10000

12000

LO Frequency (MHz)

D013

D014

图 15. IIP2: F1+F2 Across LO Frequency for Internal LO

图 16. IIP2: F1+F2 Across LO Frequency for External LO

Mode

70

60

50

40

30

60

50

40

30

20

10

20

LO Frequency = 4000MHz

LO Frequency = 8000 MHz

LO Frequency = 12000MHz

LO Frequency = 4000MHz

LO Frequency = 8000 MHz

10

LO Frequency = 12000MHz

0

-1500

-1000

-500

0

500

1000

1500

-1500

-1000

-500

0

500

1000

1500

IF Frequency (MHz)

D015

D016

图 17. IIP2: F1+F2 Across IF Frequency for Internal LO Mode

图 18. IIP2: F1+F2 Across IF Frequency for External LO

Mode

24

22

20

18

16

27

Temperature = -40

Temperature = 25

Temperature = 85

25

23

21

19

17

15

13

11

Temperature = -40

Temperature = 25

Temperature = 85

14

12

4000

6000

8000

10000

12000

4000

6000

8000

10000

12000

LO Frequency (MHz)

D017

D018

图 19. Noise Figure Across LO Frequency for Internal LO

图 20. Noise Figure Across LO Frequency for External LO

Mode

16

LMX8410L

www.ti.com.cn

ZHCSHV3A –MARCH 2018–REVISED NOVEMBER 2018

Typical Characteristics (接下页)

24

22

20

18

16

14

12

10

22

20

18

16

LO Frequency = 4000 MHz

LO Frequency = 6000 MHz

LO Frequency = 8000 MHz

LO Frequency = 10000 MHz

LO Frequency = 12000 MHz

14

12

10

LO Frequency = 6000 MHz

LO Frequency = 8000 MHz

LO Frequency = 10000 MHz

LO Frequency = 12000 MHz

0

200

400

600

800 1000 1200 1400 1600

0

200

400

600

800 1000 1200 1400 1600

IF Frequency (MHz)

D019

D020

图 21. Noise Figure Across IF Frequency for Internal LO

图 22. Noise Figure Across IF Frequency for External LO

Mode

-80

Temperature = -40

Temperature = 25

Temperature = -40

Temperature = 25

-82

Temperature = 85

-84

Temperature = 85

-84

-86

-88

-90

-92

-94

-96

-98

-86

-88

-90

-92

-94

-96

-98

-100

4000

-100

4000

6000

8000

10000

12000

6000

8000

10000

12000

LO Frequency (MHz)

D022

D024

图 23. Uncalibrated IQ Phase Difference for Internal LO

图 24. Uncalibrated IQ Phase Difference for External LO

Mode

0.5

Temperature = -40

Temperature = 25

Temperature = 85

Temperature = -40

Temperature = 25

Temperature = 85

0.4

0.3

0.2

0.1

0

0.4

0.3

0.2

0.1

0

-0.1

-0.2

-0.3

-0.4

-0.5

-0.1

-0.2

-0.3

-0.4

-0.5

4000

6000

8000

10000

12000

4000

6000

8000

10000

12000

LO Frequency (MHz)

D025

D026

图 25. Uncalibrated IQ Gain Imbalance for Internal LO Mode

图 26. Uncalibrated IQ Gain Imbalance for External LO Mode

17

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ZHCSHV3A –MARCH 2018–REVISED NOVEMBER 2018

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Typical Characteristics (接下页)

0

-10

-20

-30

-40

-50

-60

-70

-80

Uncalibrated IMRR

Calibrated IMRR

Uncalibrated IMRR

Calibrated IMRR

-10

-20

-30

-40

-50

-60

-70

-80

4000

6000

8000

10000

12000

4000

6000

8000

10000

12000

LO Frequency (MHz)

D027

D028

图 27. IMRR for Internal LO Mode: Calibrated and

图 28. IMRR for External LO Mode: Calibrated and

Uncalibrated

15

10

5

30

20

LO Frequency = 4000 MHz

LO Frequency = 8000 MHz

LO Frequency = 12000 MHz

LO Frequency = 4000 MHz

LO Frequency = 8000 MHz

LO Frequency = 12000 MHz

10

0

-5

-10

-20

-30

-10

-15

-63 -54 -45 -36 -27 -18 -9

0

9

18 27 36 45 54 63

-63 -54 -45 -36 -27 -18 -9

0

9

18 27 36 45 54 63

code

D040

D041

Minus sign on x-axis means polarity is set to '1'.

图 30. IMRR Phase Calibration: Extended Range Mode

图 29. IMRR Phase Calibration: Fine Accuracy Mode

1.25

0

Temperature = -40

Temperature = 25

Temperature = 85

1

0.75

0.5

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

0.25

0

-0.25

-0.5

-0.75

-1

IMRR_GCAL_ICH

IMRR_GCAL_QCH

-1.25

0

51

102

153

204

255

4000

6000

8000

10000

12000

Code

LO Frequency (MHz)

D045

D029

图 31. IMRR Gain Calibration

图 32. 2x2 Spur for Internal LO Mode

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ZHCSHV3A –MARCH 2018–REVISED NOVEMBER 2018

Typical Characteristics (接下页)

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

Temperature = -40

Temperature = 25

Temperature = 85

Temperature = -40

Temperature = 25

Temperature = 85

4000

6000

8000

10000

12000

4000

6000

8000

10000

12000

LO Frequency (MHz)

D030

D032

D034

D031

图 33. 2x2 Spur for External LO Mode

图 34. 3x3 Spur for Internal LO Mode

0

80

70

60

50

40

30

20

10

0

Temperature = -40

Temperature = 25

Temperature = 85

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

Temperature = -40

Temperature = 25

Temperature = 85

4000

6000

8000

10000

12000

4000

6000

8000

10000

12000

LO Frequency (MHz)

D033

图 35. 3x3 Spur for External LO Mode

图 36. RF to IF Isolation

0

-10

-20

-30

-40

-50

-60

0

-10

-20

-30

-40

-50

-60

-70

-80

Temperature = -40

Temperature = 25

Temperature = 85

Temperature = -40

Temperature = 25

Temperature = 85

4000

6000

8000

10000

12000

4000

6000

8000

10000

12000

LO Frequency (MHz)

D035

图 37. LO to IF Leakage Level

图 38. LO to RF Leakage Level: Internal LO Mode

19

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Typical Characteristics (接下页)

0

20

19

18

17

16

15

14

13

12

11

10

Temperature = -40

Temperature = 25

Temperature = 85

-10

-20

-30

-40

-50

-60

-70

-80

External 6dBm LO

Internal LO

4000

6000

8000

10000

12000

3900

4400

4900

5400

5900

6400

LO Frequency (MHz)

D036

D037

1. The LO frequency is capped at 6600MHz because IP1dB

exceeds +10dBm when LO frequency goes beyond 6600MHz;

The device can be damaged when input power is more than

+10dBm.

图 40. OP1dB Across LO Frequency

图 39. LO to RF Leakage Level: External LO Mode

25

24

23

22

21

20

19

18

17

16

15

0

NF Measured; Temperature = -40

NF Calculated; Temperature = -40

NF Measured; Temperature = 25

NF Calculated; Temperature = 25

NF Measured; temperature = 85

NF Calculated; Temperature = 85

-5

-10

-15

-20

-25

-25 -22.5 -20 -17.5 -15 -12.5 -10 -7.5 -5 -2.5

Jammer Power (dBm)

0

4000

6000

8000

LO Frequency

10000

12000

D039

D042

1. Jammer frequency = 8.8GHz, LO = 7.8GHz, IF = 100MHz.

2. Internal LO phase noise values used for calculation at -40, 25,

and 85 degrees

separately.

C are –155, –154.5 and –154 dBc/Hz,

图 42. RF Port S11

图 41. Noise Figure with Jammer

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www.ti.com.cn

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Typical Characteristics (接下页)

-5

6

4

Ta=25

Ta=-40

Ta=85

-10

-15

-20

-25

-30

-35

2

0

-2

-4

-6

-8

-10

-12

-14

0

2000

4000

6000

8000 10000 12000 14000

0

2000 4000 6000 8000 10000 12000 14000 16000

Frequency (MHz)

Output Frequency (MHz)

D043

D044

1. Board losses and mismatch are not subtracted out. True output

power may be higher. This plot shows single-ended LO output

power only. Differential output power can be higher.

图 44. LO Output Power

图 43. LO Port Mixed Modes S11

Measurements are done at 25 degree C unless temperature is specified in the plots.

For measurements across LO frequency, IF = 65MHz, and LO injection type is high side injection. For measurements

across IF frequency, high side injection is applied

For all measurements that require RF input, RF input power = -10 dBm unless otherwise specified.

For two-tone measurements, the separation between two tones is 17MHz.

For all measurements, internal 1.7V VCM is applied.

For all external LO mode measurements, LO power = +6 dBm.

IF baluns used for measurements are: ADT2-18+ from Mini-Circuits™.

LO balun used for measurements is: BIB-100G from PPM-Test™.

RF combiner used for measurements of IP2, IP3 and NF with jammer is: 4426-2 from Narda-MITEQ™.

All path losses are calibrated out.

21

LMX8410L

ZHCSHV3A –MARCH 2018–REVISED NOVEMBER 2018

www.ti.com.cn

7 Detailed Description

7.1 Overview

The LMX8410L is a high-performance I/Q demodulator with an RF input range of 4 to 10 GHz and an IF output

range of DC to 1350 MHz. This device integrates many components to allow high system performance as well as

simplified design. There is an integrated synthesizer that generates wide-band frequencies at very low phase

noise, with signal carefully conditioned for driving the mixer LO port. The RF input is single ended, enabled by an

integrated wide-band RF balun at the front end. The two mixers on each I/Q channel are highly linear with

optimized filtering and interfacing with components on each port. The IF amplifier is a high gain and high linearity

component, saving users from matching discrete amplifiers and being restricted by common mode voltages

typically encountered when interfacing mixers and ADC’s. In addition to high linearity and low noise performance,

the LMX8410L comes equipped with many features to further optimize certain parameters. The automatic DC

offset calibration is run by an internal automatic algorithm which will sense and tune the DC offset between the N

and P sides of the differential signal of each IF amplifier, thus ensuring optimal performance when directly DC

coupled to the ADC. The I/Q calibration knob allows tuning blocks within the mixer and IF amplifier to balance

both the gain and the phase of the I/Q output signals, thus giving the user capability to adjust and achieve high

image rejection. The internal synthesizer also has a feature of synchronization, which allows multiple LMX8410L

designed in parallel to have synchronized LO signal phase.

7.2 Functional Block Diagram

VCC_

MASH

VCC_DIG VCC_CP

12

VCC_BUF VCC_IFQ VCC_RFQ VCC_RFI

19 27 29 33

VCC_IFI VCC_VCO

VCC5_IFQ VCC5_IFI

23 38

7

16

35

46

VBIAS_VCO2

2

39

40

8

IF_IP

I-CH DCOC

MIXDAC

IFA

I-CHANNEL

I-CH DCOC

AMPDAC

VCM_IN

3

VBIAS_VCO1

VREG_OSCIN

IF_IM

IMRR GAIN

CAL I-CH

INTEGRATED SYNTHESIZER

10

42

45

47

INTEGRATED

LDO/VCO

BYPASSING

OSCINP

OSCINM

CP

POST-R

÷

PRE-R

MULT

÷

OSC_2X

VBIAS_VARAC

VREG_VCO

9

PHASE

DETECTOR

I/Q GENERATION

CHARGE

PUMP

13

IMRR

PHASE

CAL

SYNC

I

N ÷

SYNC

I-CH

VREF_VCO

LOGEN ÷2

CHDIV

VCO

44

36

VTUNE

Q

I

I/Q

SEL

RF

31

5

LNA

VCM_IN

LOGEN

POLYPHASE

SYNC

CE

IMRR

PHASE

CAL

Q

LO OUT SEL

LO I/O SEL

I/Q

SEL

Q-CH

1

SCK

SDI

24

25

26

11

18

17

21

22

LO_P

LO_M

SPI

INTERFACE

IMRR GAIN

CAL Q-CH

CONTROL

REGISTERS

CSB

IF_QM

IF_QP

Q-CH DCOC

MIXDAC

IFA

Q-CHANNEL

Q-CH DCOC

AMPDAC

VCM_IN

MUXOUT

4

6

14

GND

15

GND

20

GND

30

GND

32

41

GND

43

48

49

34

37

GND

PAD

N/C

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LMX8410L

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ZHCSHV3A –MARCH 2018–REVISED NOVEMBER 2018

7.3 Feature Description

7.3.1 Device Configurations and Feature Description

7.3.1.1 RF, LO and IF Interfaces

7.3.1.1.1 RF Interface

LMX8410 RF input stage provides a wideband input matching in complete RF frequency range. The RF interface

requires an external DC block capacitor.

RF

C

50 W

图 45. RF Interface

7.3.1.1.2 LO Interface

LO interface for LMX8410 serves dual functionality:

1. Drive the VCO or channel divider output to pin LO_M and LO_P.

2. Inject external LO signal in external LO mode where on-chip synthesizer needs to be bypassed.

7.3.1.1.2.1 LO Interface as Output Port

When LO interface operates as output port, it drives either VCO or Channel Divider output to the port. The device

provides open collector output. Therefore, a pair of off-chip load resistors or inductors are needed in order to

have LO output power.

C

LO_P

+3.3 V

LO_M

C

图 46. LO Port Operating In Output Mode Requires Load Resistors Or Inductors

7.3.1.1.2.2 LO Interface as Input Port

When LO interface operates as input port, the pull-up resistors or inductors must be removed. Device pins must

be AC coupled with DC block. LO pins offer wideband differential 100 Ohm termination to enable port matching.

The value of termination can be set to 100Ohm, 200Ohm or high impedance through register

EXTLO_INT_MATCH_RES (R123<1:0>). It is recommended to keep the termination setting to 100 ohm during

external LO injection and to high impedance mode while LO is brought out from the device.

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Feature Description (接下页)

LO_P

C

R

LO_M

图 47. LO Port Operating In Input Mode

7.3.1.1.3 Baseband Interface

LMX8410 has a low impedance output driver capable of driving the resistive as well as capacitive loads.

Therefore, a pair of 50 ohm off-chip resistors can be placed in both IF_P and IF_M paths to provide 100Ohm

differential matching if IF port matching is required.

IF_P

50 W

IF_M

图 48. IF Interface Requires External Resistors for 100Ohm Differential Matching

7.3.1.2 Device Configurations Overview

Follow below steps to configure the device successfully.

7.3.1.2.1 Initialize the Device

After the device is powered on, follow below setups in sequence.

1. Set R127 = 0x0003

2. Set R6 = 0x0100

3. Set R127 = 0x0000

4. Load device configuration bits.

7.3.1.2.2 Configure LO Modes

Refer to 表 5 to set up correct LO modes. After LO mode is configured, In case of internal LO mode, lock the

integrated synthesizer and jump to Perform DCOC (DC Offset Correction). In case of external LO mode, go to

Set Up External LO Clock.

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Feature Description (接下页)

7.3.1.2.3 Set Up External LO Clock

Follow below steps to set up external LO clock:

1. Set external LO divider. Refer to State Machine Clock

2. Provide external LO signal on the pin.

3. Enable the divider by setting EXTLO_CLK_DIV_EN (R81<7:6>) to 3. This step should be done only after

valid external LO signal is driven on the pin.

4. Select SM clock source towards external LO driven SM clock by setting SM_CLK_SEL (R81<0>) = 1.

5. Wait for 100 usec before performing DCOC.

7.3.1.2.4 Perform DCOC (DC Offset Correction)

Perform DCOC for both I and Q channels. Refer to DCOC (DC Offset Correction) for detailed instructions.

7.3.1.2.5 Turn Off SM Clock

Turn off SM clock after DCOC to remove coupling spurs from clock signals.

1. In internal LO mode, set SM_CLK_EN (R2<10>) to 0.

2. In external LO mode, set EXTLO_CLK_DIV_EN (R81<7:6>) to 0.

7.3.1.2.6 Perform IMRR (Image Rejection Ratio) Calibration

Refer to Image Rejection Calibration for detailed instructions.

7.3.1.3 State Machine Clock

The State machine clock can be derived, through a MUX, from division of OSCin frequency in internal LO mode

or from division of external LO frequency in external LO mode. The upper bound for State machine clock is

200MHz while lower bound is 1MHz/10MHZ in internal/external LO modes. In external LO mode, two sets of

dividers need to be programmed to set the right SM clock frequency. DIV_A is an 8-state divider which drives

DIV_B. Input frequency to DIV_B must be kept less than 1.4GHz. Recommended SM_CLK frequency is

100MHz.

2^CAL_CLK_DIV

f_OSCin

MUX

f_SMCLK

DIV_A

DIV_B

f_LO

图 49. Block Diagram of SM Clock

7.3.1.3.1 Set Divider Values For Internal LO Mode

The value of divider in internal LO mode is 2^(value of CAL_CLK_DIV).

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Feature Description (接下页)

7.3.1.3.2 Set Divider Values For External LO Mode

The divider for external LO mode is EXTLO_DIV (R82<5:0>), where R82<5:3> sets DIV_A and R82<2:0> sets

DIV_B. The value of DIV_A should be set according to 表 1. The value of DIV_B is 2^(value of R82<2:0>).

表 1. DIV_A Encoding

EXTLO_DIV (R82<5:3>)

Division Value

000

001

010

011

100

101

110

111

/1

/2

/16

/4

/16

/8

7.3.1.4 DCOC (DC Offset Correction)

The DC offset of IF output can be automatically corrected by checking EN_DCOC_ICH_LUT and

EN_DCOC_QCH_LUT

8b DAC in each mixer

for offset fine tuning

8b DAC in each IFA

for offset coarse tuning

IF output (I Channel)

ADC CH1

Synthesizer

OSCin

IQ LO

generator

LO output

RF input

VCM from

RF ADC

MUX

External LO input

ADC CH2

IF output (Q Channel)

8b DAC in each mixer

for offset fine tuning

8b DAC in each IFA

for offset coarse tuning

GND

图 50. DC Offset Correction Diagram

7.3.1.4.1 RF Input Power Restriction During DCOC

For best accuracy, power at the RF input of the LMX8410 should be kept below -50dBm during DCOC

calibration. Additional isolation (~15dB) can be obtained by turning of LNA_PD and LNA_BIAS_OFF.

7.3.1.4.2 Set Up DCOC Clock Divider

DCOC state machine clock can operate from 0.5MHz to 2MHz, preferably set to 1MHz. Calculation of clock

frequency: DCOC clock Frequency = (SM_CLK frequency)/(2*DCOC_CLK_DIV value). Refer to State Machine

Clock for SM_CLK setup. It is recommended to set and reset DCOC_FSM_RESET (R126<8>) every time the LO

frequency is changed.

7.3.1.5 Image Rejection Calibration

LMX8410 provides registers to vary the gain and phase of the I and Q channel individually to improve image

rejection.

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IF output (I Channel)

Synthesizer

OSCin

IQ LO

generator

LO output

M

U

X

External LO input

IF output (Q Channel)

图 51. Image Reject Calibration Example

7.3.1.5.1 Phase Calibration

Phase magnitude can be tuned using IMRR_PHCAL (R95<14:9>), polarity of phase calibration can be set by

IMRR_PHCAL_POL (R95<15>). If Q channel leads I by > 90 deg. Set polarity to ‘0’, otherwise set it to ‘1’.

Typical step size of magnitude tuning is 0.2 deg for fine accuracy mode and 0.45 deg for extended range mode.

The fine accuracy mode and extended range mode can be set by IMRR_PHCAL_EXTEND (R126<15>). Refer to

图 29 and 图 30 for details of the two modes.

7.3.1.5.2 Gain Calibration

The voltage magnitude of

I and Q channel can be tuned by IMRR_GCAL_ICH (R94<7:0>) and

IMRR_GCAL_QCH (R94<15:8>). The recommended code range is 128 to 255. In this code range, gain tuning

range is 0.5dB. Extended code range is 0 to 127. In this range, step size is higher and gain tuning range is 1dB.

Refer to 图 31 for details of the two code ranges. Re-calibration may be needed with temperature drift.

7.3.1.6 IF Amplifier Common Mode Configurations

IF amplifier common mode voltage can be set by VCM_CONFIG (R83<12:9>). Additional setups are needed

depending on VCM magnitude. Refer to 表 2 for more details. For best common mode voltage accuracy, supply

external VCM and choose "External" in VCM_CONFIG.

表 2. IF Amplifier Common Mode Configurations

IFA common mode(V)

IFA_PULLUP_EN (R79<6>)

IFA_PULLUP (R83<15:13>)

IFA_CONFIG (R88<1:0>)

1.2

1

0

7

3

1

0

3

1.3

1.4

1.5

>= 1.6

7.3.1.7 Synchronization Mode (Internal LO Mode Only)

7.3.1.7.1 Synchronization of the LO_OUT Output to the Fosc Input

The LO_OUT pin can be synchronized to the Fosc input in exactly the same way that the LMX2594 can. For

cases where the output frequency is not a multiple of the input frequency, the SYNC pin an be used.

7.3.1.7.2 Synchronization of I/Q Outputs to Fosc Inputs Using Internal LO

When the internal LO is used, IF outputs of two devices can be synchronized to the Fosc input if and only if the

VCO frequency is a multiple of the Fosc frequency and there is no multiplication in the input path (OSC_2X = 0

and MULT=1). The device is inherently in SYNC all the time in this condition so therefore there is no need to use

the SYNC pin or to toggle the SYNC_PHASE_PLL bit.

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7.4 Device Functional Modes

The LMX8410L can be programmed for two functional modes: internal LO mode (using the integrated

synthesizer) or external LO mode (bypassing the integrated synthesizer). In internal LO mode, when 4GHz <=

LO frequency <=7.5 GHz, use divide-by-2 (Div 2) mode; when 7.5 GHz <= LO frequency <= 10 GHz, use

polyphase filter mode (Poly). Refer to 表 3 to set up registers correctly. Under special circumstances where

integrated synthesizer fails to lock at 7.5 ~ 7.7GHz, refer to VCO Range Uncertainty for 7.5 to 7.7 GHz for more

instructions.

表 3. Internal LO Mode and External LO Mode Register Configurations

FIELD NAME

PLL_PD

ADDRESS

R0[0]

INTERNAL LO/DIV2 INTERNAL LO/Poly

EXTERNAL LO

0

1

0

1

LO_OUT_PD

R44[7]

SIGCHAIN_PD

R79[0]

0

LO_PATH_EN

R79[14:12]

R80[5:0]

R81[0]

0

7

LO_MUX

9

10

0

34

1

SM_CLK_SEL

0

EXTLO_CLK_DRV_EN

LO_DRVR_MODE

EXTLO_CLK_DIV_EN

LO_POLY_MODE1

LO_POLY_MODE2

EXTLO_INT_MATCH_RES

R81[2:1]

R81[5:4]

R81[7:6]

R81[11:8]

R103[13:10]

R123[1:0]

0

3

1

0

3

0

3

0

15

0

11

0

3

7.4.1 Internal LO Mode

When using internal LO mode, the integrated synthesizer is activated to generate the desired LO frequency. The

OSCINP and OSCINM pins are used to provide a reference frequency to the PLL and are required to generate

the internal state machine clock. The CP pin generates the phase detector output for use with an external loop

filter. The filtered phase detector output is fed into the VTUNE pin to control the internal VCO, generating

frequencies between 7.5 GHz and 15 GHz. The VCO output is divided down to close the loop into the phase

detector. The VCO output may be fed directly into the I/Q generation circuitry.

The I/Q generation circuitry has two paths: a divide-by-2 path, and a polyphase filter path. Depending on the

frequency of the LO, the I/Q generation circuitry used will differ. The divide-by-2 path requires the VCO frequency

to be double that of the LO frequency. When the LO frequency is between 4 GHz and 7.5 GHz, the VCO can be

programmed to between 8 GHz and 15 GHz, and the VCO output can be fed into the divide-by-2 path. When the

LO frequency is greater than 7.5 GHz, the VCO can be programmed to between 7.5 GHz and 15 GHz, and the

VCO output can be fed into the polyphase filter path.

In Internal LO mode, the LO pins may be used as outputs (refer to LO Interface as Output Port) for three

separate signals internal to the device:

1. The VCO output may be fed directly to the LO pins.

2. The VCO may be divided by any possible combination using the channel divider, and the divided output may

be fed to the LO pins. Refer to the datasheet of LMX2594 for more details.

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7.4.1.1 VCO Range Uncertainty for 7.5 to 7.7 GHz

Although the majority of devices have a VCO range of 7.5 to 15 GHz, this is NOT ensured. In reality, the VCO is

tested for sure to cover 7.7 to 15 GHz. In the range of 7.5 to 7.7 GHz and 15 to 15.4 GHz, the VCO will cover at

least enough frequency to cover a factor of two in frequency. What this means if using the internal mixer is that if

one wants a LO frequency of 7.6 GHz, then first try this using the poly mode and VCO frequency of 7.6 GHz.

However, if the VCO can not do 7.6 GHz, then one has to try DIV2 Mode with the VCO at 15.2 GHz.

表 4. VCO Ensured Frequency

Parameter

Symbol

f_VCOMin

f_VCOMax

Ensured Condition

f_VCOMin <= 7.7 GHz

Minimum VCO Frequency

Maximum VCO Frequency

f_VCOMax >= Max{ 15 GHz , 2 × f _VCOMin }

7.4.2 External LO Mode

When using External LO mode, the integrated synthesizer may be powered down and bypassed. The internal

state machine clock is derived by dividing down the LO input. Since the frequency range of the LO circuit is

bounded below the operational frequency of the divide-by-2 path, I/Q generation must be done using the

polyphase filter path.

In External LO mode, some pins must be configured differently than in Internal LO mode. Even when the

synthesizer circuitry is bypassed, VCC should be applied to all power pins (though bypass capacitors are no

longer required). 表 5 contains a summary of the External LO requirements.

表 5. External LO Pin Configuration

PIN NO.

NAME

I/O

EXTERNAL LO REQUIREMENTS

Floating (no connection) or same

configuration with internal LO mode

2

VBIAS_VCO2

Bypass

Floating (no connection) or same

configuration with internal LO mode

3

VBIAS_VCO1

Bypass

5

8

9

SYNC

Input

input

Grounded

OSCINP

OSCINM

Floating (no connection) or same

configuration with internal LO mode

10

13

17

18

VREG_OSCIN

CP

Bypass

Output

Input

Floating (no connection) or same

configuration with internal LO mode

Matching network recommended. No pull-up

LO_M

(1)

resisters / inductors.

Matching network recommended. No pull-up

LO_P

Input

(1)

resisters / inductors.

Floating (no connection) or same

configuration with internal LO mode

42

44

47

VBIAS_VARAC

VTUNE

Bypass

Input

Grounded

Floating (no connection) or same

configuration with internal LO mode

VREF_VCO

Bypass

(1) Refer to LO Interface as Input Port for LO interfacing.

7.5 Programming

7.5.1 General Comments Regarding Programming

This device is programmed using 24-bit shift registers. The shift register consists of a R/W bit (MSB), followed by

a 7-bit address field and a 16-bit data field. For the R/W bit, 0 is for write, and 1 is for read. The address field

ADDRESS[6:0] is used to decode the internal register address. The remaining 16 bits form the data field

DATA[15:0]. While CSB is low, serial data is clocked into the shift register upon the rising edge of clock (data is

programmed MSB first). When CSB goes

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Programming (接下页)

7.5.2 Recommended Initial Power Up Sequence

For the most reliable programming, TI recommends this procedure: 1. 2. Program RESET = 1 to reset registers.

3. Program RESET = 0 to remove reset. 4. Program registers as shown in the register map in REVERSE order

from highest to lowest. 5. Program register R0 one additional time with FCAL_EN = 1 to ensure that the VCO

calibration runs from a stable state.

1. Apply power to device.

2. Program Register R127 to value 0x7F0003

3. Program Register R6 to value 0x060100

4. Program registers R127 to R0 in REVERSE Order

5. If using internal LO, wait 10 ms and then Program register R0 again

7.5.3 Recommended and Power on Reset Bit Values

There a few points of clarification for power on reset values and recommended values.

1. Whenever power is cycled on the chip, the registers are reset to their power on reset (not necessarily

recommended) state.

2. In the main register map, there are several registers with only 1's and 0's and no defined words. DO NOT

ASSUME that these registers do not need to be programmed. In many cases, these 1's and 0's are different

than the power on reset values.

3. In the register description, the word 'RESET" is used, but what is really meant is "Recommended" State

7.6 Register Map

This device has 128 registers from R0 to R127. They must be programmed in REVERSE order. Note that there

are several registers that have no description, but they still need to be programmed as the power on reset value

is not always the correct value. The complete listing for all registers, including those not described in this

datasheet are available on the Registers tab on the TI TICSPro software.

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Table 7 lists the memory-mapped registers for the Device registers. All register offset addresses not listed in

Table 7 should be considered as reserved locations and the register contents should not be modified.

Table 7. Device Registers

Address

0x0

Acronym

R0

Register Name

Section

Go

0x1

R1

0x2

R2

0x9

R9

0xA

R10

R11

R14

R36

R37

R38

R39

R40

R41

R42

R43

R44

R46

R58

R59

R69

R70

R75

R78

R79

R80

R81

R82

R83

R84

R88

R94

R95

R103

R110

R111

R112

R121

R123

R126

0xB

0xE

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2E

0x3A

0x3B

0x45

0x46

0x4B

0x4E

0x4F

0x50

0x51

0x52

0x53

0x54

0x58

0x5E

0x5F

0x67

0x6E

0x6F

0x70

0x79

0x7B

0x7E

Complex bit access types are encoded to fit into small table cells. Table 8 shows the codes that are used for

access types in this section.

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Table 8. Device Access Type Codes

Access Type

Read Type

R

Code

Description

R

Read

Write Type

W

Write

Reset or Default Value

-n

Value after reset or the default

value

7.6.1 R0 Register (Address = 0x0) [reset = X]

R0 is shown in Figure 52 and described in Table 9.

Return to Summary Table.

Figure 52. R0 Register

7

6

5

4

3

2

1

0

FCAL_HPFD_A

DJ

RESERVED

FCAL_EN

MUXOUT_SEL

RESET_PLL

PLL_PD

R/W-0x0

R-0x0

R/W-0x1

R/W-0x0

Table 9. R0 Register Field Descriptions

Bit

Field

Type

Reset

Description

14

SYNC_PHASE_PLL

R/W

X

Puts PLL in SYNC mode so that the channel divider can be

synchronized

13-10

9

RESERVED

OUT_MUTE

R

X

R/W

Output buffer automute.

0x0 = Disabled

0x1 = Mutes output buffer during FCAL and when PLL not locked

VCO calibration adjust for higher phase detector frequencies

0x0 = Fpd < 100 MHz

8-7

FCAL_HPFD_ADJ

R/W

0x0

0x1 = Fpd 100 - 150 MHz

0x2 = Fpd 150 - 200 MHz

0x3 = Fpd > 200 MHz

6-4

3

RESERVED

FCAL_EN

R

0x0

0x1

R/W

Enables frequency calibration. When this bit is high, the VCO

frequency calibration will be triggered whenever the R0 register is

written to.

2

MUXOUT_SEL

R/W

0x1

Selects to route readback serial data output or lock detect output at

the MUXout pin

0x0 = Readback

0x1 = Lock Detect

1

0

RESET_PLL

PLL_PD

R/W

0x0

Reset registers to default values. This bit is self-clearing.

0x0 = No Reset

0x1 = Trigger Reset

PLL power down.

0x0 = Powerd Up

0x1 = Powered Down

7.6.2 R1 Register (Address = 0x1) [reset = 0x3]

R1 is shown in Figure 53 and described in Table 10.

Return to Summary Table.

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Figure 53. R1 Register

7

6

5

4

3

2

1

0

RESERVED

R-0x0

CAL_CLK_DIV

R/W-0x3

Table 10. R1 Register Field Descriptions

Bit

Field

Type

R

Reset

0x0

Description

7-3

2-0

RESERVED

CAL_CLK_DIV

R/W

0x3

Divides down for state machine clock [SM clock =

Fosc/2^CAL_CLK_DIV]. Maximum state machine clock frequency is

200MHz. For fastest calibration speed, choose value which will make

state machine clock closest to 200 MHz.

7.6.3 R2 Register (Address = 0x2) [reset = X]

R2 is shown in Figure 54 and described in Table 11.

Return to Summary Table.

Figure 54. R2 Register

7

6

5

4

3

2

1

0

RESERVED

R-0x0

Table 11. R2 Register Field Descriptions

Bit

Field

Type

R/W

R

Reset

X

Description

10

SM_CLK_EN

RESERVED

Enables state machine clock

9-0

0x0

7.6.4 R9 Register (Address = 0x9) [reset = X]

R9 is shown in Figure 55 and described in Table 12.

Return to Summary Table.

Figure 55. R9 Register

7

6

5

4

3

2

1

0

RESERVED

R-0x0

Table 12. R9 Register Field Descriptions

Bit

Field

Type

Reset

Description

12

OSC_2X

R/W

X

Enables the frequency doubler after the input reference signal.

0x0 = Bypass

0x1 = Enable doubler

11-0

RESERVED

R

0x0

7.6.5 R10 Register (Address = 0xA) [reset = 0x80]

R10 is shown in Figure 56 and described in Table 13.

Return to Summary Table.

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Figure 56. R10 Register

7

6

5

4

3

2

1

0

MULT

R/W-0x1

RESERVED

R-0x0

Table 13. R10 Register Field Descriptions

Bit

Field

Type

Reset

Description

11-7

MULT

R/W

0x1

Input signal multiplier. When not in bypass, input range is 40-70MHz,

output range is 180-250MHz. 1,3,4,5,6, and 7 are the only valid

values.

0x1 = Bypass

0x3 = x3

0x4 = x4

0x5 = x5

0x6 = x6

6-0

RESERVED

R

0x0

7.6.6 R11 Register (Address = 0xB) [reset = 0x10]

R11 is shown in Figure 57 and described in Table 14.

Return to Summary Table.

Figure 57. R11 Register

7

6

5

4

3

2

1

0

PLL_R

RESERVED

R-0x0

R/W-0x1

Table 14. R11 Register Field Descriptions

Bit

Field

Type

R/W

R

Reset

0x1

Description

PLL R dividerthat is after the input mulitplier.

11-4

3-0

PLL_R

RESERVED

0x0

7.6.7 R14 Register (Address = 0xE) [reset = 0x70]

R14 is shown in Figure 58 and described in Table 15.

Return to Summary Table.

Figure 58. R14 Register

7

6

5

4

3

2

1

0

RESERVED

R-0x0

CPG

RESERVED

R-0x0

R/W-0x7

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Table 15. R14 Register Field Descriptions

Bit

7

Field

Type

R

Reset

0x0

Description

RESERVED

CPG

6-4

R/W

0x7

Charge pump gain

0x0 = 0 mA

0x1 = 6 mA

0x2 = 6 mA

0x3 = 12 mA

0x4 = 3 mA

0x5 = 9 mA

0x6 = 9 mA

0x7 = 15 mA

3-0

RESERVED

R

0x0

7.6.8 R36 Register (Address = 0x24) [reset = 0x64]

R36 is shown in Figure 59 and described in Table 16.

Return to Summary Table.

Figure 59. R36 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PLL_N

R/W-0x64

Table 16. R36 Register Field Descriptions

Bit

15-0

Field

PLL_N

Type

Reset

Description

R/W

0x64

Integer part of N divider

7.6.9 R37 Register (Address = 0x25) [reset = 0x200]

R37 is shown in Figure 60 and described in Table 17.

Return to Summary Table.

Figure 60. R37 Register

15

7

14

6

13

5

12

4

11

PFD_DLY_SEL

R/W-0x2

10

9

1

8

0

RESERVED

R-0x0

3

2

RESERVED

R-0x0

Table 17. R37 Register Field Descriptions

Bit

Field

Type

R

Reset

0x0

Description

15-14

13-8

RESERVED

PFD_DLY_SEL

R/W

0x2

Sets the appropriate delay adjustment for the phase detector based

on PLL_N, MASH_ORDER, and phase detector frequency.

7-0

RESERVED

R

0x0

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7.6.10 R38 Register (Address = 0x26) [reset = 0x0]

R38 is shown in Figure 61 and described in Table 18.

Return to Summary Table.

Figure 61. R38 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PLL_DEN_31:16

R/W-0x0

Table 18. R38 Register Field Descriptions

Bit

15-0

Field

PLL_DEN_31:16

Type

Reset

Description

Denominator of N divider fraction (MSB)

R/W

0x0

7.6.11 R39 Register (Address = 0x27) [reset = 0x2710]

R39 is shown in Figure 62 and described in Table 19.

Return to Summary Table.

Figure 62. R39 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PLL_DEN

R/W-0x2710

Table 19. R39 Register Field Descriptions

Bit

15-0

Field

PLL_DEN

Type

Reset

Description

Denominator of N divider fraction (LSB)

R/W

0x2710

7.6.12 R40 Register (Address = 0x28) [reset = 0x0]

R40 is shown in Figure 63 and described in Table 20.

Return to Summary Table.

Figure 63. R40 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MASH_SEED_31:16

R/W-0x0

Table 20. R40 Register Field Descriptions

Bit

15-0

Field

MASH_SEED_31:16

Type

Reset

Description

R/W

0x0

MSB bit of MASH_SEED

7.6.13 R41 Register (Address = 0x29) [reset = 0x0]

R41 is shown in Figure 64 and described in Table 21.

Return to Summary Table.

Figure 64. R41 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MASH_SEED

R/W-0x0

41

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Table 21. R41 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-0

MASH_SEED

R/W

0x0

The MASH_SEED can be used for optimizing fractional mode (see

simulation tool) and also phase adjustment feature. Phase

adjustment writing to this register will trigger a phase shift (in

degrees) = 360 x [MASH_SEED] x [PLL_N_PRE] / [N-divider

denominator] / [Channel divider]. MASH_SEED must be less than N-

divider denominator For example, for MASH_SEED = 100,

PLL_N_PRE=2, PLL_DEN = 200, CHDIV=3, Phase Shift = 360 * 100

* 2 / 200 / 3 = 120 degrees

7.6.14 R42 Register (Address = 0x2A) [reset = 0x0]

R42 is shown in Figure 65 and described in Table 22.

Return to Summary Table.

Figure 65. R42 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PLL_NUM_31:16

R/W-0x0

Table 22. R42 Register Field Descriptions

Bit

15-0

Field

PLL_NUM_31:16

Type

Reset

Description

Numerator of N divider fraction (MSB)

R/W

0x0

7.6.15 R43 Register (Address = 0x2B) [reset = 0x0]

R43 is shown in Figure 66 and described in Table 23.

Return to Summary Table.

Figure 66. R43 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PLL_NUM

R/W-0x0

Table 23. R43 Register Field Descriptions

Bit

15-0

Field

PLL_NUM

Type

Reset

Description

Numerator of N divider fraction (LSB)

R/W

0x0

7.6.16 R44 Register (Address = 0x2C) [reset = 0xA2]

R44 is shown in Figure 67 and described in Table 24.

Return to Summary Table.

Figure 67. R44 Register

15

14

13

12

11

10

2

9

1

8

0

RESERVED

R-0x0

7

6

5

4

3

LO_OUT_PD

RESERVED

MASH_RESET

_N

RESERVED

R-0x0

MASH_ORDER

R/W-0x1

R-0x0

R/W-0x1

R/W-0x2

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Table 24. R44 Register Field Descriptions

Bit

15-8

7

Field

Type

R

Reset

0x0

Description

RESERVED

LO_OUT_PD

R/W

0x1

Disable output buffer of output A

0x0 = Enable

0x1 = Disable (disable if not using output B)

6

5

RESERVED

R

0x0

0x1

MASH_RESET_N

R/W

MASH enable. Should be set to 1 in fractional mode. To reset the

MASH toggle from 0 to 1.

4-3

2-0

RESERVED

R

0x0

0x2

MASH_ORDER

R/W

Fractional-N divider sigma-delta MASH engine order. This sets the

algorithm used in fractional-N mode generation and has impact on

fractional spurs. Refer to the datasheet for more information.

Recommended values are as follows, but other values may also

work.

7.6.17 R46 Register (Address = 0x2E) [reset = 0x1]

R46 is shown in Figure 68 and described in Table 25.

Return to Summary Table.

Figure 68. R46 Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

RESERVED

R-0x0

4

3

RESERVED

R-0x0

LO_OUT_MUX

R/W-0x1

Table 25. R46 Register Field Descriptions

Bit

Field

Type

R

Reset

0x0

Description

15-2

1-0

RESERVED

LO_OUT_MUX

R/W

0x1

Selects signal to route to output B

0x0 = Selects the output from channel divider MUX

0x1 = Selects output from VCO

7.6.18 R58 Register (Address = 0x3A) [reset = 0x8000]

R58 is shown in Figure 69 and described in Table 26.

Return to Summary Table.

Figure 69. R58 Register

15

14

6

13

5

12

11

10

2

9

1

8

0

SYNC_PIN_IG

NORE

RESERVED

R/W-0x1

7

R-0x0

3

4

RESERVED

R-0x0

43

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Table 26. R58 Register Field Descriptions

Bit

Field

Type

Reset

Description

15

SYNC_PIN_IGNORE

R/W

0x1

Enable this bit when NOT using SYNC mode as the SYNC pin

interferes with lock detect in this case. When PLL_PHASE_SYNC=1,

this bit may be disabled with no issues with lock detect.

14-0

RESERVED

R

0x0

7.6.19 R59 Register (Address = 0x3B) [reset = 0x1]

R59 is shown in Figure 70 and described in Table 27.

Return to Summary Table.

Figure 70. R59 Register

15

7

14

6

13

5

12

11

10

2

9

1

8

RESERVED

R-0x0

4

3

0

RESERVED

R-0x0

LD_TYPE

R/W-0x1

Table 27. R59 Register Field Descriptions

Bit

Field

Type

R

Reset

0x0

Description

15-1

0

RESERVED

LD_TYPE

R/W

0x1

Lock detect type. VCOCal lock detect is high except when the VCO

is calibrating and also during a timeout count right after calibration

set LD_DLY. Vtune and VCOCal lock detect is high whenever

VCOCal lock detect would be high and the VCO tuning voltage is

within an acceptable range.

0x0 = VCOCal

0x1 = Vtune and VCOCal.

7.6.20 R69 Register (Address = 0x45) [reset = 0x0]

R69 is shown in Figure 71 and described in Table 28.

Return to Summary Table.

Figure 71. R69 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MASH_RST_COUNT_31:16

R/W-0x0

Table 28. R69 Register Field Descriptions

Bit

15-0

Field

Type

Reset

Description

MASH_RST_COUNT_31: R/W

16

0x0

MSB of MASH_RST_COUNT

7.6.21 R70 Register (Address = 0x46) [reset = 0xC350]

R70 is shown in Figure 72 and described in Table 29.

Return to Summary Table.

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Figure 72. R70 Register

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

MASH_RST_COUNT

R/W-0xC350

Table 29. R70 Register Field Descriptions

Bit

15-0

Field

MASH_RST_COUNT

Type

Reset

Description

R/W

0xC350

When using a fractional N value with PLL_PHASE_SYNC=1, this is

used to set a delay to allow the SYNC to work properly. In general, it

should be set to a count equal to 4X the analog settling time of the

PLL. (LSB)

7.6.22 R75 Register (Address = 0x4B) [reset = 0x0]

R75 is shown in Figure 73 and described in Table 30.

Return to Summary Table.

Figure 73. R75 Register

15

7

14

6

13

12

11

10

2

9

8

0

RESERVED

R-0x0

CHDIV

R/W-0x0

5

4

3

1

CHDIV

RESERVED

R-0x0

R/W-0x0

Table 30. R75 Register Field Descriptions

Bit

Field

Type

R

Reset

0x0

Description

15-11

10-6

5-0

RESERVED

CHDIV

R/W

R

0x0

Channel divider that divides the VCO frequency.

RESERVED

0x0

7.6.23 R78 Register (Address = 0x4E) [reset = 0x0]

R78 is shown in Figure 74 and described in Table 31.

Return to Summary Table.

Figure 74. R78 Register

15

7

14

6

13

5

12

11

10

2

9

8

RESERVED

R-0x0

VCO_CALSTA

RT_CLOSE

RESERVED

R/W-0x0

1

R-0x0

0

4

3

RESERVED

R-0x0

Table 31. R78 Register Field Descriptions

Bit

Field

RESERVED

Type

Reset

0x0

Description

15-10

9

R

VCO_CALSTART_CLOS R/W

E

0x0

Uses current values for VCO core, frequency band, and amplitude

as the starting point for the next VCO calibration. Enable this if the

VCO frequency change is close, on the order of 50 MHz or less.

8-0

RESERVED

R

0x0

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7.6.24 R79 Register (Address = 0x4F) [reset = 0x7000]

R79 is shown in Figure 75 and described in Table 32.

Return to Summary Table.

Figure 75. R79 Register

15

14

13

12

11

10

9

1

8

0

RESERVED

R-0x0

LO_PATH_EN

R/W-0x7

RESERVED

R-0x0

7

6

5

4

3

2

RESERVED

IFA_PULLUP_

EN

RESERVED

LNA_PD

SIGPATH_RST SIGCHAIN_PD

R-0x0

R/W-0x0

R-0x0

R/W-0x0

R/W-0x0 R/W-0x0

Table 32. R79 Register Field Descriptions

Bit

15

Field

Type

R

Reset

0x0

Description

RESERVED

14-12

11-7

6

LO_PATH_EN

RESERVED

R/W

R

0x7

Enables various parts of the Poly and DIV2 Path

0x0

IFA_PULLUP_EN

R/W

0x0

Enable the pull up resistor at the input of the IFA. Needed when the

output comoon mode is <1.4V

5-3

2

RESERVED

LNA_PD

R

0x0

R/W

LNA power down

1

SIGPATH_RST

SIGCHAIN_PD

Master reset for the signal chain

Master power down for the signal chain.

0

7.6.25 R80 Register (Address = 0x50) [reset = 0xA]

R80 is shown in Figure 76 and described in Table 33.

Return to Summary Table.

Figure 76. R80 Register

15

7

14

6

13

5

12

11

10

9

8

RESERVED

R-0x0

SYNC_PHASE SYNC_DRV2_ SYNC_DRV1_

RESERVED

_MIXLO

R/W-0x0

EN

R/W-0x0

R-0x0

0

4

3

2

1

RESERVED

R-0x0

LO_MUX

R/W-0xA

Table 33. R80 Register Field Descriptions

Bit

Field

Type

R

Reset

0x0

Description

15-12

11

RESERVED

SYNC_PHASE_MIXLO

SYNC_DRV2_EN

R/W

0x0

Sync bit to close the loop from Mixer LO back to synthesizer

10

0x0

Enables the SYNC 2nd stage driver from the LO output path. It

should be enabled in SYNC mode.

0x0 = Disabled

0x1 = Enabled

9

SYNC_DRV1_EN

RESERVED

R/W

R

0x0

Enables the SYNC first stage driver from the LO output path. It

should be enabled in SYNC mode.

0x0 = Disabled

0x1 = Enabled

8-6

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Table 33. R80 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

5-0

LO_MUX

R/W

0xA

Sets up various MUXs and Drivers

0x9 = Internal LO DIV2 Mode

0x10 = Internal LO Poly 48 External LO

7.6.26 R81 Register (Address = 0x51) [reset = 0x0]

R81 is shown in Figure 77 and described in Table 34.

Return to Summary Table.

Figure 77. R81 Register

15

14

13

12

11

10

9

8

RESERVED

R-0x0

LO_POLY_MODE1

R/W-0x0

7

6

5

4

3

2

1

0

EXTLO_CLK_DIV_EN

R/W-0x0

LO_DRVR_MODE

R/W-0x0

RESERVED

R-0x0

EXTLO_CLK_DRV_EN

R/W-0x0

SM_CLK_SEL

R/W-0x0

Table 34. R81 Register Field Descriptions

Bit

Field

Type

R

Reset

0x0

Description

15-12

11-8

RESERVED

LO_POLY_MODE1

R/W

0x0

Sets up parameters for the poly path

0x0 = Internal LO Poly

0x15 = External LO

0x19 = Internal LO DIV2

Selects driver for SMCLK

0x0 = Internal LO

7-6

5-4

EXTLO_CLK_DIV_EN

R/W

0x0

0x1 = Reserved

0x2 = Reserved

0x3 = External LO

LO_DRVR_MODE

Sets up drivers for LO quadrature path

0x0 = Internal LO Poly

0x1 = Internal LO DIV2

0x2 = Reserved

0x3 = External LO

3

2-1

0

RESERVED

R

0x0

EXTLO_CLK_DRV_EN

SM_CLK_SEL

R/W

Enables drivers for state machine clock.

Selects the state machine clock source for the signal path

0x0 = Internal LO

0x1 = External LO

7.6.27 R82 Register (Address = 0x52) [reset = 0x23]

R82 is shown in Figure 78 and described in Table 35.

Return to Summary Table.

Figure 78. R82 Register

15

14

13

12

11

10

2

9

1

8

0

RESERVED

R-0x0

7

6

5

4

3

47

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RESERVED

R-0x0

EXTLO_DIV

R/W-0x23

Table 35. R82 Register Field Descriptions

Bit

15-6

5-0

Field

Type

R

Reset

0x0

Description

RESERVED

EXTLO_DIV

R/W

0x23

Sets total divide value for the state machine clock when using an

exeternal LO. This total divide is the product of two divides, DIVA

and DIVB.

0x0 = 1

0x1 = 2

0x2 = 16

0x3 = 8

0x4 = 16

0x5 = 16

0x6 = 64

0x7 = 8

7.6.28 R83 Register (Address = 0x53) [reset = 0x2000]

R83 is shown in Figure 79 and described in Table 36.

Return to Summary Table.

Figure 79. R83 Register

15

7

14

13

5

12

4

11

10

2

9

1

8

IFA_PULLUP

R/W-0x1

VCM_CONFIG

R/W-0x0

RESERVED

R-0x0

6

3

0

RESERVED

R-0x0

Table 36. R83 Register Field Descriptions

Bit

Field

Type

Reset

Description

15-13

IFA_PULLUP

R/W

0x1

IFA virtual node pull up resistor to set the biasing of the IFA input

stage correct when the output common mode is <1.4V. Should be

used in conjunction with the corresponding EN bit in first register.

0x2 = Invalid

0x4 = Invalid

0x5 = Invalid

0x6 = Invalid

12-9

VCM_CONFIG

RESERVED

R/W

0x0

Output Common mode (VOCM) configuration for IFA. Only one bit to

be set as high at a time. Only valid states are 0,3,5,9.

0x0 = 1.7

0x3 = 2V

0x5 = External

0x9 = 1.4V

8-0

R

7.6.29 R84 Register (Address = 0x54) [reset = 0x1900]

R84 is shown in Figure 80 and described in Table 37.

Return to Summary Table.

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Figure 80. R84 Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

DCOC_CLK_DIV

R/W-0x64

4

3

DCOC_CLK_DIV

RESERVED

R-0x0

EN_DCOC_QC EN_DCOC_IC

H_LUT

R/W-0x64

R/W-0x0

Table 37. R84 Register Field Descriptions

Bit

15-6

5-2

1

Field

Type

R/W

R

Reset

0x64

0x0

Description

DCOC_CLK_DIV

RESERVED

DCOC clock division controlled

EN_DCOC_QCH_LUT

R/W

0x0

Enable offset calibration for Q channel. Write 1 to trigger calibration.

To re-trigger, clear this bit and then write 1 again.

0

EN_DCOC_ICH_LUT

R/W

0x0

Enable offset calibration for I channel. Write 1 to trigger calibration.

To re-trigger, clear this bit and then write 1 again.

7.6.30 R88 Register (Address = 0x58) [reset = 0x0]

R88 is shown in Figure 81 and described in Table 38.

Return to Summary Table.

Figure 81. R88 Register

15

14

13

5

12

4

11

10

2

9

1

8

0

RESERVED

R-0x0

rb_DCOC_CAL

R-0x0

RESERVED

R-0x0

7

6

3

RESERVED

R-0x0

Table 38. R88 Register Field Descriptions

Bit

15

14

Field

Type

R

Reset

0x0

Description

RESERVED

rb_DCOC_CAL

R

0x0

Status bit. Indicates whether I channel DC offset calibration is done.

0x0 = Neither Channel Done 1 I Channel Done

0x2 = Q Channel Done

0x3 = Both Channels Done

13-0

RESERVED

R

0x0

7.6.31 R94 Register (Address = 0x5E) [reset = 0x8080]

R94 is shown in Figure 82 and described in Table 39.

Return to Summary Table.

Figure 82. R94 Register

15

7

14

6

13

5

12

11

10

2

9

1

8

0

IMRR_GCAL_QCH

R/W-0x80

4

3

IMRR_GCAL_ICH

R/W-0x80

49

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Table 39. R94 Register Field Descriptions

Bit

15-8

7-0

Field

Type

R/W

Reset

0x80

Description

IMRR_GCAL_QCH

IMRR_GCAL_ICH

IMRR gain ontrol for the Q channel.

IMRR gain control for the I channel.

7.6.32 R95 Register (Address = 0x5F) [reset = X]

R95 is shown in Figure 83 and described in Table 40.

Return to Summary Table.

Figure 83. R95 Register

7

6

5

4

3

2

1

0

RESERVED

R-0x0

Table 40. R95 Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

IMRR Phase polarity control using the phase interpolar.

15

IMRR_PHCAL_POL

IMRR_PHCAL

X

14-9

IMRR Phase control using the phase interpolar. Preferred method of

the IMRR phase correction.

8

LODRV_IMRR_PHCAL_P R/W

OLCTRL

X

IMRR Phase polarity control using the slew control driver.

7-0

RESERVED

R

0x0

7.6.33 R103 Register (Address = 0x67) [reset = X]

R103 is shown in Figure 84 and described in Table 41.

Return to Summary Table.

Figure 84. R103 Register

7

6

5

4

3

2

1

0

RESERVED

R-0x0

Table 41. R103 Register Field Descriptions

Bit

Field

Type

R/W

R

Reset

X

Description

Selects configurations between Poly and DIV2 Mode

13-10

9-0

LO_POLY_MODE2

RESERVED

0x0

7.6.34 R110 Register (Address = 0x6E) [reset = X]

R110 is shown in Figure 85 and described in Table 42.

Return to Summary Table.

Figure 85. R110 Register

7

6

5

4

3

2

1

0

rb_VCO_SEL

R-0x0

RESERVED

R-0x0

50

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ZHCSHV3A –MARCH 2018–REVISED NOVEMBER 2018

Table 42. R110 Register Field Descriptions

Bit

Field

Type

Reset

Description

10-9

rb_LD_VTUNE

R

X

Readback word for the PLL lock status

0x0 = Unlock (Fvco Low)

0x1 = Invalid

0x2 = PLL Locked

0x3 = Unlock (Fvco High)

8

RESERVED

R

X

7-5

rb_VCO_SEL

0x0

Reads back the VCO core selected.

0x0 = Invalid

0x1 = VCO1

0x2 = VCO2

0x3 = VCO3

0x4 = VCO4

0x5 = VCO5

0x6 = VCO6

0x7 = VCO7

4-0

RESERVED

R

0x0

7.6.35 R111 Register (Address = 0x6F) [reset = 0x0]

R111 is shown in Figure 86 and described in Table 43.

Return to Summary Table.

Figure 86. R111 Register

7

6

5

4

3

2

1

0

rb_VCO_CAPCTRL

R-0x0

Table 43. R111 Register Field Descriptions

Bit

7-0

Field

rb_VCO_CAPCTRL

Type

Reset

Description

R

0x0

Readback word for the actual value of VCO_CAPCTRL chosen by

the VCO frequency calibration.

7.6.36 R112 Register (Address = 0x70) [reset = 0x0]

R112 is shown in Figure 87 and described in Table 44.

Return to Summary Table.

Figure 87. R112 Register

7

6

5

4

3

2

1

0

rb_VCO_DACISET

R-0x0

Table 44. R112 Register Field Descriptions

Bit

8-0

Field

rb_VCO_DACISET

Type

Reset

Description

R

0x0

Readback word for the actual value of VCO_DACISET chosen by

the VCO amplitude calibration.

51

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7.6.37 R121 Register (Address = 0x79) [reset = 0x0]

R121 is shown in Figure 88 and described in Table 45.

Return to Summary Table.

Figure 88. R121 Register

7

6

5

4

3

2

1

0

RESERVED

R-0x0

BIAS_LNA_CUR_CONFIG_2

R/W-0x0

RESERVED

R-0x0

Table 45. R121 Register Field Descriptions

Bit

7

Field

Type

Reset

0x0

Description

RESERVED

R

6-5

BIAS_LNA_CUR_CONFI R/W

G_2

0x0

4-0

RESERVED

R

0x0

7.6.38 R123 Register (Address = 0x7B) [reset = 0x3]

R123 is shown in Figure 89 and described in Table 46.

Return to Summary Table.

Figure 89. R123 Register

7

6

5

4

3

2

1

0

RESERVED

R-0x0

EXTLO_INT_MATCH_RES

R/W-0x3

Table 46. R123 Register Field Descriptions

Bit

Field

RESERVED

Type

Reset

0x0

Description

7-2

1-0

R

EXTLO_INT_MATCH_RE R/W

S

0x3

Control internal resistor termination at EXTLO input pin

0x0 = No termination

0x1 = 200 Ohms differential termination

0x2 = Same as 1

0x3 = 100 Ohms differential termination

7.6.39 R126 Register (Address = 0x7E) [reset = X]

R126 is shown in Figure 90 and described in Table 47.

Return to Summary Table.

Figure 90. R126 Register

7

6

5

4

3

2

1

0

RESERVED

R-0x0

Table 47. R126 Register Field Descriptions

Bit

Field

Type

R/W

R

Reset

X

Description

15

14-9

8

IMRR_PHCAL_EXTEND

RESERVED

Increase the range of the IMRR phase interpolator DAC by 2x

Reset DC offset

X

DCOC_FSM_RST

RESERVED

R/W

R

X

7-0

0x0

52

LMX8410L

www.ti.com.cn

ZHCSHV3A –MARCH 2018–REVISED NOVEMBER 2018

8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

Typical Application shows a typical usage of the LMX8410L with internal synthesizer and shows the basic

components needed for the operation of the device. There is also guidance on how to design the loop external

loop filter which is part of the LMX8410L synthesizer. The PLLatinum Sim is a tool that allows users to enter the

information regarding the input reference and target LO frequency they need and simulate the expected phase

noise and performance parameters for the synthesizer.

8.2 Typical Application

图 91. Typical Application Schematic

8.2.1 Design Requirements

The design of the loop filter is complex and is typically done with software. The PLLatinum Sim software is an

excellent resource for doing this and the design is shown in the following figure. For those interested in the

equations involved, the PLL Performance, Simulation, and Design Handbook listed in the end of this document

goes into great detail as to theory and design of PLL loop filters. PLLatinum Sim does not model the mixers and

LNAs in this device, but it can be used for the PLL. To use this tool, it can be modeled as the LMX2594 PLL.

53

LMX8410L

ZHCSHV3A –MARCH 2018–REVISED NOVEMBER 2018

www.ti.com.cn

Typical Application (接下页)

8.2.2 Detailed Design Procedure

The integration of phase noise over a certain bandwidth (jitter) is an performance specification that translates to

signal-to-noise ratio. Phase noise inside the loop bandwidth is dominated by the PLL, while the phase noise

outside the loop bandwidth is dominated by the VCO. Generally, jitter is lowest if loop bandwidth is designed to

the point where the two intersect. A higher phase margin loop filter design has less peaking at the loop

bandwidth and thus lower jitter. The tradeoff with this is that longer lock times and spurs must be considered in

design as well.

As for software programming, it is highly recommended to use the TICSPro software. In addition to simplifying

the process, it also gives the user recommended programming default values for the undisclosed registers not

mentioned in the datasheet.

图 92. PLLatinum Sim Design Example

54

LMX8410L

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ZHCSHV3A –MARCH 2018–REVISED NOVEMBER 2018

Typical Application (接下页)

8.2.3 Application Curve

-60

-70

7.5 GHz

1.1 dBm

1: 1 kHz

-90.8 dBc/Hz

2: 10 kHz -104.0 dBc/Hz

3: 100 kHz -111.0 dBc/Hz

4: 1 MHz -125.2 dBc/Hz

5: 10 MHz -148.6 dBc/Hz

6: 20 MHz -152.2 dBc/Hz

7: 100 MHz -155.0 dBc/Hz

-80

-90

-100

-110

-120

-130

-140

-150

-160

1 kHz

10 kHz

100 kHz

1 MHz

10 MHz

100 MHz

Offset (Hz)

ta_C

图 93. Direct VCO Noise

55

LMX8410L

ZHCSHV3A –MARCH 2018–REVISED NOVEMBER 2018

www.ti.com.cn

9 Power Supply Recommendations

1. Design 5-V supply to be capable of greater than 200 mA.

2. Design 3.3-V supply to be capable of greater than 800 mA.

3. Supply to channel I and Q sides must be well matched and isolated from one another. Recommend using

ferrite beads in series to the pin. The I and Q supplies are for IF amplifier (at pin 38 and 23), for RF input (at

pin 33 and 29), and for IF path circuitry (at pin 35 and 27).

4. Pins 7 and 16 are supplies for digital circuitry, and they can have extra isolation in this path (TI recommends

using ferrite bead in series to the pin).

5. Pins 12, 19, and 46 are supplies for the internal synthesizer; designer must take care not to have noise

sources that can couple to it nearby.

6. Typically use 0.1-µF capacitors near the pins. Add extra capacitance values at specific frequencies if known

interfering frequencies in system. See Pin Configuration and Functions for more recommendations on

component value recommendations.

10 Layout

10.1 Layout Guidelines

Generally, there are two major focuses of layout guidelines: high frequency signals and power routing.

10.1.1 High Frequency Trace Routing

•

Design all traces for matched impedance. The single-ended RF trace must be controlled for 50-Ω impedance,

while the differential OSCIN, LO, and IF traces must be controlled for 100-Ω differential impedance.

•

Run an uninterrupted ground plane beneath all impedance-controlled traces. No other currents should flow

directly under the controlled impedance traces.

•

Keep high-frequency traces as short as possible to minimize losses, or potential for cross-coupling.

Controlled impedance can be challenging in materials not designed for RF applications. For example,

standard FR-4 has a wide range of acceptable dielectric constants in practice. Although the constants seen in

boards from the same panel or material lot code may match very well, this does not ensure that the constants

match between different lots or different dielectric manufacturers. Furthermore, FR-4 has a high loss tangent

compared to many other materials, which can result in much greater attenuation of high frequency signals

across the same distances. TI recommends the use of materials designed specifically for high-frequency use,

such as RO4350B or RO4003C from Rogers Corporation.

•

The RF pin is surrounded on three sides by ground pins to assist in the creation of a coplanar waveguide

structure. Design the coplanar waveguide to minimize current flow on the ground traces around the pins.

•

The IF outputs are low impedance, and require resistors to set the output impedance.

The LO pins are capacitively coupled as inputs, with internal 50-Ω termination. Use 50-Ω pullup resistors to

VCC_BUF to bias these pins as inputs, if driven through external capacitors. The LO pins require 50-Ω pullup

resistors to VCC_BUF as outputs.

•

The LO pins are located very close to the Q-channel IF pins, and the LO buffer supply is located between

these two ports. Placing a bypass capacitor as close as possible to the LO buffer is recommended for proper

operation, but this presents a potential problem: vias to VCC and GND must be routed between the

differential pairs. Because the high frequency currents in the bypass capacitor and the LO buffer circuit tend

to follow the loop with the lowest inductance, and since the VCC via interrupts the path from capacitor ground

to IC ground on the plane layer immediately below the top, ground currents tend to travel around this via, in

the path of the LO and IF coupling to the plane layer. To maintain the signal integrity of both the LO and IF

differential traces, no other currents should be flowing immediately below them on the plane layer. Therefore,

the LO bypass capacitor ground via must not connect to the plane layer immediately below the capacitor. TI

recommends connecting through the subsequent layer. See the Layout Example section on how this is done.

56

LMX8410L

www.ti.com.cn

ZHCSHV3A –MARCH 2018–REVISED NOVEMBER 2018

Layout Guidelines (接下页)

10.1.2 Power Trace Routing

•

Regardless of whether the part is used in internal or external LO mode, all synthesizer VCC and GND pins

must be connected properly. If VCC and GND pins are not connected on the synthesizer, the internal power-

up procedure may not execute properly. Noise may also be coupled into the mixer from the synthesizer

circuitry if power and ground are not properly connected.

•

Place bypass capacitors, whenever possible, to minimize the inductance of the current loop formed by the

capacitor and the IC. Placing the bypass capacitors on the same surface as the IC allows one terminal to be

connected closely to the IC, minimizing this loop. The ground connection can also be made low-inductance by

placing a ground via to a plane layer immediately below. Placing capacitors on the opposite surface

substantially limits the effective frequencies they can bypass, since the current must travel through two vias.

The loop area formed by placing a capacitor on the opposite surface is almost always larger than the loop

area formed by placing a capacitor on the same surface.

•

Consider the path that ground currents will take. For optimal performance, supply and bypass capacitor

currents must not flow underneath high-frequency traces.

Use as many ground vias as possible to connect the IC pad to the ground plane. This is required for optimal

thermal performance.

Connect ground pins back to the pad. Aside from routing convenience, the inductance through the bond wires

tends to be very high, and the inductance through the ground pad tends to be very low.

Avoid connecting different VCC pins in such a way that the current paths overlap. Overlapping current paths

can inject common-mode noise into the supply pins, degrading performance.

10.2 Layout Examples

图 94. Top Layer

57

LMX8410L

ZHCSHV3A –MARCH 2018–REVISED NOVEMBER 2018

www.ti.com.cn

Layout Examples (接下页)

图 95. Ground Layer 1

图 96. Mid Layer 1

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LMX8410L

www.ti.com.cn

ZHCSHV3A –MARCH 2018–REVISED NOVEMBER 2018

Layout Examples (接下页)

图 97. Mid Layer 2

图 98. Mid Layer 3

59

LMX8410L

ZHCSHV3A –MARCH 2018–REVISED NOVEMBER 2018

www.ti.com.cn

Layout Examples (接下页)

图 99. Bottom Layer

60

LMX8410L

www.ti.com.cn

ZHCSHV3A –MARCH 2018–REVISED NOVEMBER 2018

11 器件和文档支持

11.1 文档支持

11.1.1 相关文档

请参阅如下相关文档：

《LMX8410LEVM 用户指南》

11.2 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

11.4 商标

E2E is a trademark of Texas Instruments.

Narda-MITEQ is a trademark of L3 Narda-MITEQ.

Mini-Circuits is a trademark of Mini-Circuits.

PPM-Test is a trademark of Pulse Power & Measurement Ltd..

All other trademarks are the property of their respective owners.

11.5 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.6 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。

61

GENERIC PACKAGE VIEW

RGZ 48

7 x 7, 0.5 mm pitch

VQFN - 1 mm max height

PLASTIC QUADFLAT PACK- NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224671/A

www.ti.com

PACKAGE OUTLINE

RGZ0048D

VQFN - 1 mm max height

S

C

A

L

E

1

.

9

0

PLASTIC QUAD FLATPACK - NO LEAD

7.1

6.9

A

B

0.5

0.3

PIN 1 INDEX AREA

7.1

6.9

0.30

0.18

DETAIL

OPTIONAL TERMINAL

TYPICAL

1.0

0.8

C

SEATING PLANE

0.08 C

0.05

0.00

5.6 0.1

2X 5.5

(0.2) TYP

13

24

44X 0.5

12

25

EXPOSED

THERMAL PAD

2X

49

SYMM

5.5

SEE TERMINAL

DETAIL

1

36

0.30

48X

0.18

37

48

PIN 1 ID

(OPTIONAL)

SYMM

0.1

C A B

0.5

0.3

48X

0.05

4219046/B 11/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RGZ0048D

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

5.6)

SYMM

48

37

48X (0.6)

1

36

48X (0.24)

6X

(1.22)

44X (0.5)

SYMM

10X

(1.33)

49

(6.8)

(R0.05)

TYP

(

0.2) TYP

VIA

25

12

13

24

10X (1.33)

6X (1.22)

(6.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:12X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219046/B 11/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RGZ0048D

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(0.665 TYP)

(1.33) TYP

16X ( 1.13)

37

48

48X (0.6)

49

36

1

48X (0.24)

44X (0.5)

(1.33)

TYP

(0.665)

TYP

SYMM

(6.8)

(R0.05) TYP

25

12

METAL

TYP

13

24

SYMM

(6.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 49

66% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:15X

4219046/B 11/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

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本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	LMX8410RGZR
厂家：	TEXAS INSTRUMENTS
描述：	带集成式合成器的高性能混合器 \| RGZ \| 48 \| -40 to 85
文件：	总70页 (文件大小：2814K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LMX8410RGZR [TI]

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