LP3981IMM-3.3 [TI]
LP3981 Micropower, 300mA Ultra Low-Dropout CMOS Voltage Regulator; LP3981微功耗, 300毫安超低压差CMOS电压稳压器型号: | LP3981IMM-3.3 |
厂家: | TEXAS INSTRUMENTS |
描述: | LP3981 Micropower, 300mA Ultra Low-Dropout CMOS Voltage Regulator |
文件: | 总21页 (文件大小:1065K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LP3981
www.ti.com
SNVS159G –OCTOBER 2001–REVISED MAY 2013
LP3981 Micropower, 300mA Ultra Low-Dropout CMOS Voltage Regulator
Check for Samples: LP3981
1
FEATURES
APPLICATIONS
2
•
•
Small, Space Saving VSSOP-8
•
•
•
•
•
CDMA Cellular Handsets
Low Thermal Resistance in WSON-6 Package
Gives Excellent Power Capability
Wideband CDMA Cellular Handsets
GSM Cellular Handsets
•
•
Logic Controlled Enable
Portable Information Appliances
Tiny 3.3V ± 5% to 2.5V, 300mA Converter
Stable with Ceramic and High Quality
Tantalum Capacitors
•
•
Fast Turn-On
DESCRIPTION
The LP3981's performance is optimized for battery
powered systems to deliver ultra low noise, extremely
low dropout voltage and low quiescent current.
Regulator ground current increases only slightly in
dropout, further prolonging the battery life.
Thermal Shutdown and Short-Circuit Current
Limit
KEY SPECIFICATIONS
•
•
•
•
•
2.5 to 6.0V Input Range
300mA Output
Power supply rejection is better than 60 dB at low
frequencies. This high power supply rejection is
maintained down to lower input voltage levels
common to battery operated circuits.
60dB PSRR at 1kHz
≤1μA Quiescent Current when Shut Down
Fast Turn-On Time: 120 μs (Typ.) with CBYPASS
= 0.01uF
The device is ideal for mobile phone and similar
battery powered wireless applications. It provides up
to 300 mA, from a 2.5V to 6V input, consuming less
than 1µA in disable mode.
•
•
•
132mV Typ Dropout with 300mA Load
35μVrms Output Noise over 10Hz to 100kHz
The LP3981 is available in VSSOP-8 package. For
LP3981 in WSON-6 package, contact TI sales offices.
Performance is specified for −40°C to +125°C
temperature range. The device available in the
following output voltages; 2.5V, 2.7V, 2.8V, 2.83V,
3.0V, 3.03V and 3.3V as standard. Other output
options can be made available, please contact your
local TI sales office.
−40 to +125°C Junction Temperature Range for
Operation
•
2.5V, 2.7V, 2.8V, 2.83V, 3.0V, 3.03V, and 3.3V
Outputs Standard
Typical Application Circuit
Note: Pin Numbers in parenthesis indicate WSON-6 package.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2013, Texas Instruments Incorporated
LP3981
SNVS159G –OCTOBER 2001–REVISED MAY 2013
www.ti.com
Block Diagram
PIN DESCRIPTIONS
Name
VEN
VSSOP-8
WSON-6
Function
Enable Input Logic, Enable High.
Common Ground. Connect to PAD.
Output Voltage of the LDO.
7
5
1
2
6
4
6
4
1
2
5
3
GND
VOUT
VIN
Input Voltage of the LDO.
Bypass
VOUT-SENSE
Optional bypass capacitor for noise reduction.
Output. Voltage Sense Pin. Should be connected to
VOUT for proper operation.
N.C.
3, 8
GND
PAD
Common Ground. Connect to pin 4.
Connection Diagrams
1
2
3
6
5
4
V
V
OUT
EN
Device
Code
Bypass
GND
V
IN
V
OUT-SENSE
GND
Figure 1. Top View
VSSOP-8 Package
See Package Number DGK
Figure 2. Top View
WSON-6 Package
See Package Number NGC0006D
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WSON-6
SNVS159G –OCTOBER 2001–REVISED MAY 2013
ORDERING INFORMATION(1)(2)
LP3981 Supplied as
1000 Units
LP3981 Supplied as
Output Voltage
Grade
4500 Units
Package Marking
Tape and Reel
Tape and Reel
2.5V
LP3981ILD-2.5
LP3981ILD-2.7
LP3981ILD-2.8
LP3981ILD-2.83
LP3981ILD-3.0
LP3981ILD-3.03
LP3981ILD-3.3
LP3981ILDX-2.5
LP3981ILDX-2.7
LP3981ILDX-2.8
LP3981ILDX-2.83
LP3981ILDX-3.0
LP3981ILDX-3.03
LP3981ILDX-3.3
LO1UB
LO1VB
LO1ZB
L01SB
L017B
LO1YB
LO1XB
2.7V
2.8V
2.83V
STD
3.0V
3.03V
3.3V
VSSOP-8 Package
LP3981 Supplied as
1000 Units
LP3981 Supplied as
3500 Units
Output Voltage
Grade
Package Marking
Tape and Reel
Tape and Reel
2.5V
2.7V
2.8V
2.83V
3.0V
3.03V
3.3V
LP3981IMM-2.5
LP3981IMM-2.7
LP3981IMM-2.8
LP3981IMM-2.83
LP3981IMM-3.0
LP3981IMM-3.03
LP3981IMM-3.3
LP3981IMMX-2.5
LP3981IMMX-2.7
LP3981IMMX-2.8
LP3981IMMX-2.83
LP3981IMMX-3.0
LP3981IMMX-3.03
LP3981IMMX-3.3
LFKB
LFLB
LFTB
LDUB
LF3B
LFPB
LFNB
STD
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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SNVS159G –OCTOBER 2001–REVISED MAY 2013
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Absolute Maximum Ratings(1)(2)(3)
VIN, VEN
−0.3 to 6.5V
−0.3 to VIN + 0.3, Max 6.5V
150°C
VOUT, VOUT-SENSE
Junction Temperature
Storage Temperature
Lead Temp.
−65°C to +150°C
Pad Temp.
(4)
Power Dissipation
θJA (VSSOP-8)
θJA (WSON-6)
210°C/W
50°C/W
Maximum Power Dissipation at 25°C
VSSOP-8
WSON-6
595mW
2.5W
ESD Rating(5)
Human Body Model
Machine Model
2kV
200V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to the potential at the GND pin.
(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(4) The figures given for Absolute Maximum Power dissipation for the device are calculated using the following
equations:
where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θ JA is the
junction-to-ambient thermal resistance. E.g. for the WSON package θ JA=50°C/W, TJ(MAX)=150°C and using TA=25°C the maximum
power dissipation is found to be 2.5W. The derating factor (−1/θJA) = −20mW/°C, thus below 25°C the power dissipation figure can be
increased by 20 mW per degree, and similarity decreased by this factor for temperatures above 25°C
(5) The human body model is 100pF discharged through 1.5kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged
directly into each pin.
Operating Ratings(1)(2)
VIN
2.7 to 6V
0 to VIN
VEN
Junction Temperature
−40°C to +125°C
(3)
Maximum Power Dissipation
VSSOP-8
476mW
2.0W
WSON-6
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to the potential at the GND pin.
(3) As for the Maximum Power dissipation, the maximum power in operation is dependant on the ambient temperature. This can be
calculated in the same way using TJ=125°C, giving 2W as the maximum power dissipation for the WSON package in operation. The
same derating factor applies.
4
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SNVS159G –OCTOBER 2001–REVISED MAY 2013
Electrical Characteristics
Unless otherwise specified: VEN = 1.2V, VIN = VOUT + 0.5V, CIN = 2.2 µF, CBP = 0.033 µF, IOUT = 1mA, COUT = 2.2 µF. Typical
values and imits appearing in standard typeface are for TJ = 25°C. Limits appearing in boldface type apply over the entire
junction temperature range for operation, −40°C to +125°C.(1)(2)
Limit
Symbol
Parameter
Conditions
Typ
Units
Min
Max
Output Voltage
Tolerance
−2
−3
2
3
% of
VOUT(nom)
VIN = VOUT + 0.5V to 6.0V, TA < +85°C
VIN = VOUT + 0.5V to 6.0V, TJ ≤125°C
IOUT = 1 mA to 300 mA
0.005
−0.1
−0.2
0.1
0.2
%/V
%/V
ΔVOUT
Line Regulation Error
Load Regulation Error
0.0003
50
0.005
%/mA
(3)
VIN = VOUT(nom) + 1V,
f = 1 kHz,
IOUT = 50 mA (Figure 4)
(4)
PSRR
IQ
Power Supply Rejection Ratio
Quiescent Current
dB
VIN = VOUT(nom) + 1V,
f = 10 kHz,
IOUT = 50 mA (Figure 4)
55
VEN = 1.2V, IOUT = 1 mA
70
120
210
VEN = 1.2V, IOUT = 1 to 300 mA,
VOUT = 2.5V(5)
170
µA
VEN = 0.4V
0.003
0.5
1.5
5
IOUT = 1 mA
IOUT = 200 mA
IOUT = 300 mA
(6)
Dropout Voltage
88
133
200
mV
132
600
ISC
en
Short Circuit Current Limit
Output Noise Voltage
Output Grounded
(Steady State)
mA
BW = 10 Hz to 100 kHz,
CBP = 0.033µF
35
µVrms
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
Peak Output Current
160
20
°C
°C
TSD
IOUT(PK)
IEN
V
OUT ≥ VOUT (nom) - 5%
455
300
Maximum Input Current at VEN
Logic Low Input threshold
Logic High Input threshold
VEN = 0 and VIN
VIN = 2.7 to 6.0V
VIN = 2.7 to 6.0V
CBYPASS = 0.033 µF
0.001
µA
V
VIL
0.4
VIH
1.4
V
(4) (7)
TON
Turn-On Time
240
350
µs
(1) Min and Max Limits are specified by design, test, or statistical analysis. Typical (Typ.) numbers are not verified, but do represent the
most likely norm.
(2) The target output voltage, which is labeled VOUT(nom), is the desired voltage option.
(3) An increase in the load current results in a slight decrease in the output voltage and vice versa.
(4) Specified by design. Not production tested.
(5) For VOUT > 2.5C, Increase IQ(MAX) by 2.5µA for every 0.1V increase in VOUT(NOM).i.e. IQ(MAX) = 210 + ((VOUT(NOM) - 2.5) * 25)µA
(6) Dropout voltage is the input-to-output voltage difference at which the output voltage is 100mV below its nominal value. This specification
does not apply for input voltages below 2.5V.
(7) Turn-on time is time measured between the enable input just exceeding VIH and the output voltage just reaching 95% of its nominal
value.
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SNVS159G –OCTOBER 2001–REVISED MAY 2013
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Units
Electrical Characteristics Output Capacitor, Recommended Specification
Limit
Symbol
Parameter
Conditions
Typ
Min
2.2
Max
COUT
Output Capacitor
Capacitance
ESR
22
500
µF
5
mΩ
Figure 3. Line Transient Response Input Perturbation
Figure 4. PSRR Input Perturbation
6
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SNVS159G –OCTOBER 2001–REVISED MAY 2013
Typical Performance Characteristics
Unless otherwise specified, CIN = COUT = 2.2 µF Ceramic, CBP = 0.033 µF, VIN = VOUT + 0.5V, TA = 25°C, Enable pin is tied to
VIN.
Output Voltage
Dropout Voltage
vs.
vs.
Temperature (VOUT = 2.83V)
Temperature (VOUT = 2.85V)
Ground Current
vs.
Load Current (VOUT = 2.85V)
Output Short Circuit Current
Output Short Circuit Current
Ripple Rejection (VIN = VOUT + 1V)
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Typical Performance Characteristics (continued)
Unless otherwise specified, CIN = COUT = 2.2 µF Ceramic, CBP = 0.033 µF, VIN = VOUT + 0.5V, TA = 25°C, Enable pin is tied to
VIN.
Ripple Rejection (VIN = VOUT + 1V)
Ripple Rejection (VIN = VOUT + 1V)
Load Transient Response (VIN = 3.5V)
Load Transient Response (VIN = 3.5V)
Line Transient Response
(VIN = VOUT + 1V to VOUT + 1.6V)
Line Transient Response
(VIN = VOUT + 1V to VOUT + 1.6V)
8
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SNVS159G –OCTOBER 2001–REVISED MAY 2013
Typical Performance Characteristics (continued)
Unless otherwise specified, CIN = COUT = 2.2 µF Ceramic, CBP = 0.033 µF, VIN = VOUT + 0.5V, TA = 25°C, Enable pin is tied to
VIN.
Line Transient Response
(VIN = VOUT + 1V to VOUT + 1.6V)
Line Transient Response
(VIN = VOUT + 1V to VOUT + 1.6V)
Enable Response (TON
)
Enable Response (TON)
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SNVS159G –OCTOBER 2001–REVISED MAY 2013
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APPLICATION HINTS
POWER DISSIPATION AND DEVICE OPERATION
The permissible power dissipation for any package is a measure of the capability of the device to pass heat from
the power source, the junctions of the IC, to the ultimate heat sink, the ambient environment. Thus, the power
dissipation is dependant on the ambient temperature and the thermal resistance across the various interfaces
between the die and ambient air.
As stated in the notes for Absolute Maximum Ratings and Operating Ratings, the allowable power dissipation for
the device in a given package can be calculated using the equation:
(1)
With a θJA = 50°C/W, the device in the WSON package returns a value of 2.0W with a maximum junction
temperature of 125°C and an ambient temperature of 25°C. The device in a VSSOP package returns a figure of
0.476W, ( θJA = 210°C/W).
The actual power dissipation across the device can be represented by the following equation:
PD = (VIN − VOUT) x IOUT
(2)
This establishes the relationship between the power dissipation allowed due to thermal considerations, the
voltage drop across the device, and the continuous current capability of the device. The device can deliver
300mA but care must be taken when choosing the continuous current output for the device under the operating
load conditions.
EXTERNAL CAPACITORS
Like any low-dropout regulator, the LP3981 requires external capacitors for regulator stability. The LP3981 is
specifically designed for portable applications requiring minimum board space and smallest components. These
capacitors must be correctly selected for good performance.
INPUT CAPACITOR
An input capacitance of ≊ 2.2µF is required between the LP3981 input pin and ground (the amount of the
capacitance may be increased without limit).
This capacitor must be located a distance of not more than 1cm from the input pin and returned to a clean
analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.
Important: Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a low-
impedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input,
it must be specified by the manufacturer to have a surge current rating sufficient for the application.
There are no requirements for the ESR on the input capacitor, but tolerance and temperature coefficient must be
considered when selecting the capacitor to ensure the capacitance will be ≊ 2.2µF over the entire operating
temperature range.
OUTPUT CAPACITOR
The LP3981 is designed specifically to work with very small ceramic output capacitors. A ceramic capacitor
(dielectric types Z5U, Y5V or X7R) in 2.2 to 22 µF range with 5mΩ to 500mΩ ESR range is suitable in the
LP3981 application circuit.
It may also be possible to use tantalum or film capacitors at the output, but these are not as attractive for
reasons of size and cost (see CAPACITOR CHARACTERISTICS).
The output capacitor must meet the requirement for minimum amount of capacitance and also have an ESR
(Equivalent Series Resistance) value which is within a stable range (5 mΩ to 500 mΩ).
NO-LOAD STABILITY
The LP3981 will remain stable and in regulation with no external load. This is specially important in CMOS RAM
keep-alive applications.
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SNVS159G –OCTOBER 2001–REVISED MAY 2013
NOISE BYPASS CAPACITOR
Connecting a 0.033µF capacitor between the CBP pin and ground significantly reduces noise on the regulator
output. This cap is connected directly to a high impedance node in the bad gap reference circuit. Any significant
loading on this node will cause a change on the regulated output voltage. For this reason, DC leakage current
through this pin must be kept as low as possible for best output voltage accuracy.
The types of capacitors best suited for the noise bypass capacitor are ceramic and film. Hight-quality ceramic
capacitors with either NPO or COG dielectric typically have very low leakage. Polypropolene and polycarbonate
film capacitors are available in small surface-mount packages and typically have extremely low leakage current.
Unlike many other LDO's, addition of a noise reduction capacitor does not effect the transient response of the
device.
CAPACITOR CHARACTERISTICS
The LP3981 is designed to work with ceramic capacitors on the output to take advantage of the benefits they
offer: for capacitance values in the range of 1µF to 4.7µF range, ceramic capacitors are the smallest, least
expensive and have the lowest ESR values (which makes them best for eliminating high frequency noise). The
ESR of a typical 1µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR
requirement for stability by the LP3981.
The ceramic capacitor's capacitance can vary with temperature. Most large value ceramic capacitors (≊ 2.2µF)
are manufactured with Z5U or Y5V temperature characteristics, which results in the capacitance dropping by
more than 50% as the temperature goes from 25°C to 85°C.
A better choice for temperature coefficient in a ceramic capacitor is X7R, which holds the capacitance within
±15%.
Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more
expensive when comparing equivalent capacitance and voltage ratings in the 1µF to 4.7µF range.
Another important consideration is that tantalum capacitors have higher ESR values than equivalent size
ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the
stable range, it would have to be larger in capacitance (which means bigger and more costly ) than a ceramic
capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about
2:1 as the temperature goes from 25°C down to −40°C, so some guard band must be allowed.
ON/OFF INPUT OPERATION
The LP3981 is turned off by pulling the VEN pin low, and turned on by pulling it high. If this feature is not used,
the VEN pin should be tied to VIN to keep the regulator output on at all time. To assure proper operation, the
signal source used to drive the VEN input must be able to swing above and below the specified turn-on/off voltage
thresholds listed in the Electrical Characteristics section under VIL and VIH.
FAST ON-TIME
The LP3981 utilizes a speed up circuitry to ramp up the internal VREF voltage to its final value to achieve a fast
output turn on time.
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SNVS159G –OCTOBER 2001–REVISED MAY 2013
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REVISION HISTORY
Changes from Revision F (May 2013) to Revision G
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 11
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PACKAGE OPTION ADDENDUM
www.ti.com
12-Nov-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
1000
1000
(1)
(2)
(6)
(3)
(4/5)
LP3981ILD-2.5
NRND
ACTIVE
WSON
WSON
NGC
6
6
TBD
Call TI
CU SN
Call TI
-40 to 125
-40 to 125
LO1UB
LP3981ILD-2.5/NOPB
NGC
Green (RoHS
& no Sb/Br)
Level-3-260C-168 HR
LO1UB
L01ZB
L017B
LO1XB
LO1UB
LO1VB
L01ZB
LO1SB
LO1YB
LP3981ILD-2.8/NOPB
LP3981ILD-3.0/NOPB
LP3981ILD-3.3/NOPB
LP3981ILDX-2.5/NOPB
LP3981ILDX-2.7/NOPB
LP3981ILDX-2.8/NOPB
LP3981ILDX-2.83/NOPB
LP3981ILDX-3.03/NOPB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
NGC
NGC
NGC
NGC
NGC
NGC
NGC
NGC
6
6
6
6
6
6
6
6
1000
1000
1000
4500
4500
4500
4500
4500
Green (RoHS
& no Sb/Br)
CU SN
CU SN | Call TI
CU SN
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Green (RoHS
& no Sb/Br)
CU SN
Green (RoHS
& no Sb/Br)
CU SN
Green (RoHS
& no Sb/Br)
CU SN
Green (RoHS
& no Sb/Br)
CU SN
Green (RoHS
& no Sb/Br)
CU SN
LP3981IMM-2.5
NRND
VSSOP
VSSOP
DGK
DGK
8
8
1000
1000
TBD
Call TI
CU SN
Call TI
-40 to 125
-40 to 125
LFKB
LFKB
LP3981IMM-2.5/NOPB
ACTIVE
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
LP3981IMM-2.7/NOPB
LP3981IMM-2.8/NOPB
LP3981IMM-3.0/NOPB
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
VSSOP
DGK
DGK
DGK
8
8
8
1000
1000
1000
Green (RoHS
& no Sb/Br)
CU SN
CU SN
CU SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
LFLB
LFTB
LF3B
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
LP3981IMM-3.03
NRND
VSSOP
VSSOP
DGK
DGK
8
8
1000
1000
TBD
Call TI
CU SN
Call TI
-40 to 125
-40 to 125
LFPB
LFPB
LP3981IMM-3.03/NOPB
ACTIVE
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
LP3981IMM-3.3
NRND
VSSOP
VSSOP
DGK
DGK
8
8
1000
1000
TBD
Call TI
CU SN
Call TI
-40 to 125
-40 to 125
LFNB
LFNB
LP3981IMM-3.3/NOPB
ACTIVE
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Nov-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
LP3981IMMX-2.5/NOPB
LP3981IMMX-3.3/NOPB
ACTIVE
VSSOP
VSSOP
DGK
8
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
LFKB
LFNB
ACTIVE
DGK
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
12-Nov-2013
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP3981ILD-2.5
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
NGC
NGC
NGC
NGC
NGC
NGC
NGC
NGC
NGC
NGC
DGK
DGK
DGK
DGK
DGK
DGK
DGK
DGK
6
6
6
6
6
6
6
6
6
6
8
8
8
8
8
8
8
8
1000
1000
1000
1000
1000
4500
4500
4500
4500
4500
1000
1000
1000
1000
1000
1000
1000
1000
178.0
178.0
178.0
178.0
178.0
330.0
330.0
330.0
330.0
330.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
12.4
4.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
5.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.4
3.4
3.4
3.4
3.4
3.4
3.4
3.4
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
LP3981ILD-2.5/NOPB
LP3981ILD-2.8/NOPB
LP3981ILD-3.0/NOPB
LP3981ILD-3.3/NOPB
LP3981ILDX-2.5/NOPB
LP3981ILDX-2.7/NOPB
LP3981ILDX-2.8/NOPB
LP3981ILDX-2.83/NOPB WSON
LP3981ILDX-3.03/NOPB WSON
LP3981IMM-2.5
VSSOP
LP3981IMM-2.5/NOPB VSSOP
LP3981IMM-2.7/NOPB VSSOP
LP3981IMM-2.8/NOPB VSSOP
LP3981IMM-3.0/NOPB VSSOP
LP3981IMM-3.03
LP3981IMM-3.03/NOPB VSSOP
LP3981IMM-3.3 VSSOP
VSSOP
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2013
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP3981IMM-3.3/NOPB VSSOP
LP3981IMMX-2.5/NOPB VSSOP
LP3981IMMX-3.3/NOPB VSSOP
DGK
DGK
DGK
8
8
8
1000
3500
3500
178.0
330.0
330.0
12.4
12.4
12.4
5.3
5.3
5.3
3.4
3.4
3.4
1.4
1.4
1.4
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP3981ILD-2.5
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
VSSOP
VSSOP
VSSOP
VSSOP
NGC
NGC
NGC
NGC
NGC
NGC
NGC
NGC
NGC
NGC
DGK
DGK
DGK
DGK
6
6
6
6
6
6
6
6
6
6
8
8
8
8
1000
1000
1000
1000
1000
4500
4500
4500
4500
4500
1000
1000
1000
1000
210.0
213.0
213.0
213.0
213.0
367.0
367.0
367.0
367.0
367.0
210.0
210.0
210.0
210.0
185.0
191.0
191.0
191.0
191.0
367.0
367.0
367.0
367.0
367.0
185.0
185.0
185.0
185.0
35.0
55.0
55.0
55.0
55.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
LP3981ILD-2.5/NOPB
LP3981ILD-2.8/NOPB
LP3981ILD-3.0/NOPB
LP3981ILD-3.3/NOPB
LP3981ILDX-2.5/NOPB
LP3981ILDX-2.7/NOPB
LP3981ILDX-2.8/NOPB
LP3981ILDX-2.83/NOPB
LP3981ILDX-3.03/NOPB
LP3981IMM-2.5
LP3981IMM-2.5/NOPB
LP3981IMM-2.7/NOPB
LP3981IMM-2.8/NOPB
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2013
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LP3981IMM-3.0/NOPB
LP3981IMM-3.03
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
VSSOP
DGK
DGK
DGK
DGK
DGK
DGK
DGK
8
8
8
8
8
8
8
1000
1000
1000
1000
1000
3500
3500
210.0
210.0
210.0
210.0
210.0
367.0
367.0
185.0
185.0
185.0
185.0
185.0
367.0
367.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
LP3981IMM-3.03/NOPB
LP3981IMM-3.3
LP3981IMM-3.3/NOPB
LP3981IMMX-2.5/NOPB
LP3981IMMX-3.3/NOPB
Pack Materials-Page 3
MECHANICAL DATA
NGC0006D
LDC06D (Rev B)
www.ti.com
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