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LP8731-Q1

SNVSA28 –DECEMBER 2014

LP8731-Q1 Dual High-Current Step-Down DC-DC And Dual Linear Regulators

with I²C Interface

1 Features

3 Description

The LP8731-Q1 is a multi-function, programmable

Power Management Unit (PMU), optimized for low

power FPGAs, microprocessors, and DSPs. This

device integrates two highly efficient 1.2-A step-down

DC-DC converters with dynamic voltage management

(DVM), two 300-mA linear regulators, and a 400-kHz

I²C-compatible interface to allow a host controller

access to the internal control registers of the LP8731-

Q1. The LP8731-Q1 device additionally features

programmable power-on sequencing.

1

•

Two LDOs for Powering Internal Processor

Functions and I/Os

•

High-Speed Serial Interface for Independent

Control of Device Functions and Settings

•

Precision Internal Reference

Thermal Overload Protection

Current Overload Protection

Software Programmable Regulators

External Power-On-Reset Function for Buck1 and

Buck2 (Power Good with Delay Function)

Device Information⁽¹⁾

PART NUMBER

PACKAGE

BODY SIZE (MAX)

•

Undervoltage Lockout (UVLO)

LP8731-Q1

DSBGA (25)

2.52 mm x 2.52 mm

LP8731-Q1 is an Automotive-Grade Product:

AECQ-100 Grade-1 Qualified

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

•

Step-Down DC/DC Converter (2xBuck)

space

–

Programmable V_OUTfrom:

–

Buck1 : 0.8875 V – 1.675 V at 1.2 A

Buck2 : 0.8875 V – 1.675 V at 1.2 A

–

Up to 96% Efficiency

Simplified Schematic

PWM Switching Frequency of 2.1 MHz

±2% Output Voltage Accuracy

Automatic Soft Start

LDO1

EN_T

I/O Voltage

Domain

VINLDO12

VDD

100k

1 PF

ENLDO1

ENLDO2

nPOR

VIN1

•

Linear Regulators (2xLDO)

ENSW1

ENSW2

LDO1

SDA

SCL

Advanced

Power

Controller

10 PF

–

Programmable V_OUTof 0.8 V to 3.3 V

±3% Output Voltage Accuracy

300-mA Output Current

2.2 PH

SW1

FB1

10 PF

0.47 PF

VINLDO1

VINLDO2

LDO2

GND_SW1

Buck1

LDO1

Core ADAS

Domain

Block

1 PF

LP8731

VIN2

30-mV (Typical) Dropout

10 PF

2.2 PH

0.47 PF

SW2

FB2

2 Applications

Buck2

LDO2

Peripheral

ADAS

Blocks

SDA

SCL

10 PF

•

Configurable Output PMU for ADAS (Advanced

Driver Assistance Systems)

GND_SW2

AVDD

GND_L

GND_C

Application

System or SoC

1 PF

•

FPGA, DSP Core Power

Applications Processors

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LP8731-Q1

SNVSA28 –DECEMBER 2014

www.ti.com

Table of Contents

8.2 Functional Block Diagram ....................................... 11

8.3 Features Description............................................... 12

8.4 Device Functional Modes........................................ 19

8.5 Programming........................................................... 20

8.6 LP8731-Q1 Register Maps ..................................... 22

Application and Implementation ........................ 37

9.1 Application Information............................................ 37

9.2 Typical Application .................................................. 37

1

2

3

4

5

6

7

Features.................................................................. 1

Applications ........................................................... 1

Description ............................................................. 1

Revision History..................................................... 2

Device Comparison Tables................................... 3

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

7.1 Absolute Maximum Ratings ...................................... 5

7.2 ESD Ratings ............................................................ 5

7.3 Recommended Operating Conditions (Bucks).......... 5

7.4 Thermal Information.................................................. 5

7.5 General Electrical Characteristics............................. 6

7.6 Low Dropout Regulators, LDO1 And LDO2.............. 6

7.7 Buck Converters SW1, SW2..................................... 7

7.8 I/O Electrical Characteristics..................................... 7

7.9 Power-On Reset Threshold/Function (POR) ............ 7

7.10 I²C-Compatible Interface Timing............................. 8

7.11 Typical Characteristics............................................ 9

Detailed Description ............................................ 11

8.1 Overview ................................................................. 11

9

10 Power Supply Recommendations ..................... 43

10.1 Analog Power Signal Routing ............................... 43

11 Layout................................................................... 44

11.1 Layout Guidelines ................................................. 44

11.2 Layout Example .................................................... 44

12 Device and Documentation Support ................. 45

12.1 Device Support...................................................... 45

12.2 Documentation Support ........................................ 45

12.3 Trademarks........................................................... 45

12.4 Electrostatic Discharge Caution............................ 45

12.5 Glossary................................................................ 45

8

13 Mechanical, Packaging, and Orderable

Information ........................................................... 45

4 Revision History

DATE

REVISION

NOTES

December 2014

*

Initial release.

2

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5 Device Comparison Tables

Table 1. Factory Default Programming⁽¹⁾

ORDER NUMBER

BUCK1

1.0625 V

nPOR

BUCK2

1.0625 V

UVLO

LDO1

LDO2

DEFAULT I²C ADDRESS

LP8731QYZRRQ1

2.8 V

3.3 V

59

Start/shutdown sequence

Buck1 (1.5 ms) → Buck2 (2 ms) → LDO1 (3 ms) → LDO2 (6 ms)

50 µs

Disabled

(1) All numbers are typical.

Table 2. Power Block Operation

POWER BLOCK OPERATION

POWER BLOCK INPUT

NOTE

ENABLED

VIN+⁽¹⁾

DISABLED

VIN+

VINLDO12

AVDD

Always powered

VIN+

VIN1

VIN+

VIN+ or 0 V

≤ VIN+

VIN2

VIN+

VINLDO 1

VINLDO 2

≤ VIN+

If enabled, min V_INis 2.45 V

≤ VIN+

(1) VIN+ is the largest potential voltage on the device.

6 Pin Configuration and Functions

DSBGA (YZR) Package

25 Pins

Top View

VIN

LDO12

VIN

LDO2

GND_S

SW1

5

VIN1

W1

VIN

LDO12

EN_S

W1

4

EN_T

nPOR

SDA

FB1

AVDD

FB2

LDO2

EN_

LDO2

EN_

LDO1

GND_C

3

EN_

SW2

SCL

LDO1

2

1

VIN

LDO1

GND_

SW2

GND_

L

SW2

D

VIN2

E

A

B

C

Pin Functions

I/O

TYPE

DESCRIPTION

NUMBER

NAME

VINLDO1

LDO1

A1

A2

A3

A4

A5

I

O

I

PWR

D

VINLDO1 power in from either DC source or battery to input pin to LDO1.

LDO1 Output

ENLDO2

LDO2

LDO2 enable pin, a logic HIGH enables the LDO2

LDO2 Output

O

I

PWR

VINLDO2

VINLDO2 power in from either DC source or battery to input pin to LDO2.

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Pin Functions (continued)

I/O

TYPE

DESCRIPTION

NUMBER

B1

NAME

GND_L

SCL

G

I

G

LDO ground

I²C Clock

B2

D

B3

ENLDO1

VINLDO12

GND_SW2

SDA

I

LDO1 enable pin, a logic HIGH enables the LDO1

Analog power for internal functions (VREF, BIAS, I²C, Logic)

Buck2 NMOS Power ground

B4, B5

C1

I

PWR

G

I/O

O

C2

D

I²C Data (bidirectional)

C3

nPOR

D

nPOR power-on reset pin for both Buck1 and Buck2. Open drain logic output

100K pull-up resistor. nPOR is pulled to ground when the voltages on these

supplies are not good. See Flexible Power-On Reset (for example, Power

Good with Delay) section for more info.

C4

EN_T

I

D

Enable for preset power-on sequence. (See Flexible Power-On Reset (for

example, Power Good with Delay).)

C5

D1

D2

D3

D4

D5

E1

E2

E3

E4

E5

GND_SW1

SW2

G

O

I

G

PWR

D

Buck1 NMOS power ground

Buck2 switcher output pin

ENSW2

GND_C

ENSW1

SW1

Enable pin for Buck2 switcher, a logic HIGH enables Buck2

Non-switching core ground pin

G

I

G

D

Enable pin for Buck1 switcher, a logic HIGH enables Buck1

Buck1 switcher output pin

O

I

PWR

A

VIN2

VIN2 power in from either DC source or Battery to Buck2

Buck2 input feedback pin

FB2

I

AVDD

FB1

I

PWR

A

Analog Power for Buck converters

I

Buck1 input feedback pin

VIN1

I

PWR

VIN1 power in from either DC source or Battery to Buck1

A: Analog Pin; D: Digital Pin; G: Ground Pin; PWR: Power Pin; I: Input Pin; O: Output Pin; I/O: Input/Output Pin

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

6

UNIT

V_IN, SDA, SCL

−0.3

V

GND to GND SLUG

±0.3

Power dissipation (P_{D_MAX}

Junction temperature (T_J-MAX

Maximum lead temperature (soldering)

Storage temperature (T_stg

)

Internally limited

)

150

260

150

°C

)

–65

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE

±2000

±750

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

V_(ESD)

Electrostatic discharge

V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions (Bucks)

over operating free-air temperature range (unless otherwise noted)

MIN

2.8

0

MAX

UNIT

V_IN

5.5

(V_IN+ 0.3)

125

V

V_EN

Junction temperature (T_J)

Ambient temperature (T_A)

–40

°C

125

7.4 Thermal Information

LP8731-Q1

THERMAL METRIC⁽¹⁾

DSBGA (YZR)

UNIT

°C/W

25 PINS

58.7

0.3

R_θJA

Junction-to-ambient thermal resistance

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

8

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.6

ψ_JB

8

R_θJC(bot)

n/a

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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7.5 General Electrical Characteristics

Unless otherwise noted, V_IN= 3.6 V. Typical values and limits apply for T_J= 25°C.⁽¹⁾

PARAMETER

TEST CONDITIONS

MIN

TYP

3

MAX UNIT

I_Q

VINLDO12 shutdown current

Power-on reset threshold

Thermal shutdown threshold

Thermal shutdown hysteresis

V_IN= 3.6 V

V_DDFalling Edge⁽²⁾

µA

V

V_POR

T_SD

T_SDH

1.9

160

20

°C

V

Rising

Falling

2.9

2.7

UVLO

Undervoltage lockout

(1) All voltages are with respect to the potential at the GND pin.

(2) VPOR is voltage at which the EPROM resets. This is different from the UVLO on VINLDO12, which is the voltage at which the

regulators shut off; and is also different from the nPOR function, which signals if the regulators are in a specified range.

7.6 Low Dropout Regulators, LDO1 And LDO2

Unless otherwise noted, V_IN= 3.6 V, C_IN= 1 µF, C_OUT= 0.47 µF. Typical values and limits apply for T_J= 25°C.^(1)(2)(3)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_IN

Operational voltage range

Output voltage accuracy (default

V_OUT)

VINLDO1 and VINLDO2 PMOS pins⁽⁴⁾

2.45⁽⁵⁾

5.5⁽⁵⁾

V

V_OUT

Accuracy

Load current = 1 mA

−3%⁽⁵⁾

3%⁽⁵⁾

0.2⁽⁵⁾

V_IN= (V_OUT+ 0.3 V) to 5 V⁽⁶⁾

Load current = 1 mA

Line regulation

%/V

ΔV_OUT

V_IN= 3.6 V,

Load current = 1 mA to I_MAX

Load regulation

0.011⁽⁵⁾

%/mA

mA

I_SC

Short circuit current limit

LDO1 to LDO2, V_OUT= 0 V

Load current = 50 mA at V_OUT= 2.8 V⁽⁷⁾

Load current = 250 mA at V_OUT= 2.8 V

ƒ = 10 kHz, Load current = I_MAX

10 Hz < F < 100 KHz

500

30

50⁽⁵⁾

200⁽⁵⁾

V_IN– V_OUT

Dropout voltage

mV

150

45

PSRR

Power supply ripple rejection

Supply output noise

Quiescent current “on”

Quiescent current “off”

Turn-on time

dB

µVrms

µA

θn

280

40

I_OUT= 0 mA

(8)(9)

I_Q

I_OUT= I_MAX

EN is de-asserted⁽¹⁰⁾

60

µA

0.03

300

0.47

1

µA

T_ON

Start-up from shutdown

Capacitance for stability 0°C ≤ T_J≤ 125°C

−40°C ≤ T_J≤ 125°C

µs

0.33

0.68

5

µF

C_OUT

Output capacitance

µF

ESR

500

mΩ

(1) All voltages are with respect to the potential at the GND pin.

(2) Minimum and Maximum limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the

most likely norm.

(3) C_IN, C_OUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

(4) Pins A1 and/or A5 can operate from V_INmin of 1.74 to a V_INmax of 5.5 V. This rating is only for the series pass PMOS power FET. It

allows the system design to use a lower voltage rating if the input voltage comes from a buck output. However, if V_INis required to

operate at a higher voltage than other device supply pins, it is necessary to wire the VINLDO12 pins (B4 an B5) and VINLDO1 and

VINLDO2 pins (A1 and/or A5) together to that higher voltage so that the LDO core supply has sufficient head-room to operate the gate

of the PMOS.

(5) Limits apply over the entire operating junction temperature range for operation, –40°C to 125°C.

(6) V_INminimum for line regulation values is 1.8 V.

(7) Dropout voltage is the voltage difference between the input and the output at which the output voltage drops to 100 mV below its

nominal value.

(8) Quiescent current is defined here as the difference in current between the input voltage source and the load at V_OUT

.

(9) The I_Qcan be defined as the standing current of the LP8731-Q1 when the I²C bus is activated and all other power blocks have been

disabled via the I²C bus, or it can be defined as the I²C bus active, and the other power blocks are active under no load condition.

These two values can be used by the system designer when the LP8731-Q1 is powered using a battery.

(10) The I_Qexhibits a higher current draw when the EN pin is de-asserted because the I²C buffer pins draw an additional 2 µA.

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7.7 Buck Converters SW1, SW2

Unless otherwise noted, V_IN= 3.6 V, C_IN= 10 µF, C_OUT= 10 µF, L_OUT= 2.2 µH ceramic. Typical values and limits apply for T_J

= 25°C.^(1)(2)(3)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_FB

Feedback voltage

−3%⁽⁴⁾

3%⁽⁴⁾

2.8 V < V_IN< 5.5 V

I_OUT= 10 mA

Line regulation

Load regulation

0.089%

/V

100 mA < I_O< I_MAX

0.0013%

/mA

V_OUT

V_IN= 3.3 V, V_OUTfrom 0.8875 V to

1.1625 V

Output accuracy⁽⁵⁾

–2%⁽⁴⁾

2%⁽⁴⁾

Load from 0 mA to 600 mA

Eff

Efficiency

Load current = 250 mA

EN is de-asserted

90%

0.01

2.1

1.7

2

I_SHDN

f_OSC

Shutdown supply current

Internal oscillator frequency

Buck1 peak switching current limit

Buck2 peak switching current limit

Quiescent current “on”

Pin-pin resistance PFET

Pin-pin resistance NFET

Turn-on time

µA

1.7⁽⁴⁾

MHz

I_PEAK

A

(6)

I_Q

No load PWM Mode

mA

mΩ

µs

R_DSON(P)

R_DSON(N)

T_ON

200

180

500

Start-up from shutdown

Capacitance for stability

C_IN

Input capacitance

10

µF

C_O

Output capacitance

µF

(1) All voltages are with respect to the potential at the GND pin.

(2) Minimum and Maximum limits are ensured by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the

most likely norm.

(3) C_IN, C_OUT: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

(4) Limits apply over the entire operating junction temperature range for operation, –40°C to 125°C

(5) Based on closed loop, bench test data with LP8731YZREVM.

(6) The I_Qcan be defined as the standing current of the LP8731-Q1 when the I²C bus is active and all other power blocks have been

disabled via the I²C bus, or it can be defined as the I²C bus active, and the other power blocks are active under no load condition.

These two values can be used by the system designer when the LP8731-Q1 is powered using a battery.

7.8 I/O Electrical Characteristics

PARAMETER

Input low level

Input high level

TEST CONDITIONS

MIN

TYP

MAX

0.4⁽¹⁾

UNIT

V_IL

V_IH

V

1.2⁽¹⁾

(1) This specification is ensured by design.

7.9 Power-On Reset Threshold/Function (POR)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

nPOR

nPOR = Power-on reset for Buck1 and

Buck2

Default

50

µs

nPOR

threshold

Percentage of target voltage Buck1 or

Buck2

V_BUCK1AND V_BUCK2rising

V_BUCK1OR V_BUCK2falling

Load = I_OL= 0.2 mA

94%

85%

0.23

V_OL

Output level low

0.5⁽¹⁾

V

(1) This specification is ensured by design.

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7.10 I²C-Compatible Interface Timing

Unless otherwise noted, V_IN= 3.6 V. Nominal values and limits apply for T_J= 25°C.⁽¹⁾

MIN

NOM

MAX

UNIT

kHz

µs

ƒ_CLK

Clock frequency

400

t_BF

Bus-free time between start and stop

Hold time repeated start condition

CLK low period

See⁽¹⁾

1.3

0.6

1.3

0.6

0

t_HOLD

t_CLKLP

t_CLKHP

t_SU

µs

CLK high period

µs

Setup time repeated start condition

Data hold time

µs

t_DATAHLD

t_DATASU

T_SU

µs

Data setup time

100

0.6

ns

Setup time for start condition

Maximum pulse width of spikes that

µs

T_TRANS

must be suppressed by the input filter See⁽¹⁾

of both DATA & CLK signals

50

ns

(1) This specification is ensured by design.

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7.11 Typical Characteristics

T_A= 25°C unless otherwise noted

2.00

1.50

1.00

0.50

0.00

-0.50

-1.00

-1.50

-2.00

2.00

1.50

1.00

0.50

0.00

-0.50

-1.00

-1.50

-2.00

-50 -35 -20 -5 10 25 40 55 70 85 100

TEMPERATURE (°C)

V_IN= 3.6 V

V_OUT= 3.3 V

100-mA load

V_IN= 3.6 V

V_OUT= 2.6 V

100-mA load

Figure 2. Output Voltage Change vs. Temperature (LDO2)

Figure 1. Output Voltage Change vs. Temperature (LDO1)

LDO-1

(50 mV/DIV)

LDO-1

(50 mV/DIV)

Iout

(100 mA/DIV)

Time (500 µs/DIV)

V_OUT= 3.6 V

V_OUT= 1.8 V

I_LOAD= 0 to 300 mA

Tr = Tf = 1 µs

V_OUT= 3.6 V

V_OUT= 1.8 V

I_LOAD= 0 to 300 mA

Tr = Tf = 4 µs

Figure 3. Load Transient 1-µs Edge Rate

Figure 4. Load Transient 4-µs Edge Rate

Vin Step

(500 mV/DIV)

Vout LDO

(10 mV/DIV)

Time (100 µs/DIV)

Time (1 ms/DIV)

V_IN= 3.6 V to 4.2 V

V_OUT= 1.8 V

I_LOAD= 300 mA

Tr = Tf = 20 µs

V_IN= 3.6 V to 4.2 V

V_OUT= 1.8 V

I_OUT= 1 mA

Tr = Tf = 30 µs

Figure 5. Line Transient 300-mA, 4-µs Edge Rate

Figure 6. Line Transient 1-mA, 30-µs Edge Rate

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Typical Characteristics (continued)

T_A= 25°C unless otherwise noted

Vin Step

(500 mV/DIV)

Buck-2

(100 mV/DIV)

Vout LDO

(20 mV/DIV)

Iout

(400 mA/DIV)

Time (50 µs/DIV)

I_OUT= 200 mA to 1.2 A PWM

V_INStep

I_OUT= 300 mA

Tr = Tf = 30 µs

Figure 7. Buck Load Transient PWM Mode

Figure 8. Buck Line Transient PWM

Vin Step

(500 mV/DIV)

Vout LDO

(20 mV/DIV)

Time (50 µs/DIV)

V_INStep

I_OUT= 1.2 A

Tr = Tf = 10 µs

V_INStep

I_OUT= 1.2 A

Tr = Tf = 30 µs

Figure 9. Buck Line Transient PWM

Figure 10. Buck Line Transient PWM

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8 Detailed Description

8.1 Overview

The LP8731-Q1 supplies the various power needs of the application by means of two Linear Low Drop

Regulators (LDO1 and LDO2) and two Buck converters (SW1 and SW2). Table 3 lists the output characteristics

of the various regulators.

Table 3. Supply Specification

OUTPUT

SUPPLY

LOAD

I_MAX

V_OUTRANGE (V)

RESOLUTION (mV)

MAXIMUM OUTPUT CURRENT (mA)

LDO1

LDO2

SW1

analog

digital

0.8 to 3.3

100

300

0.8875 to 1.675

12.5

1200

SW2

8.2 Functional Block Diagram

VBATT +

C_VDD

4.7PF

1PF

PF

10

1PF

10 PF

ULVO

V_INOK

LSW1 2.2PH

1.25V

OSC

VBUCK1

SW1

VFB1

C_BUCK1

10PF

BUCK1

AVDD

ENLDO1

2.2PH

LSW1

ENLDO2

ENSW 1

1.25V

VBUCK2

Power

ON-OFF

Logic

SW2

VFB2

BUCK2

C_BUCK2

10PF

AVDD

ENSW 2

EN_T

VINLDO1

Thermal

Shutdown

2.8V

LDO1

C_LDO1

0.47PF

RESET

I²C

VINLDO12

VINLDO2

2

I C_SCL

BIAS

1.8V

LDO2

2

I C_SDA

LDO2

C_LDO2

0.47PF

RDY1

RDY2

VDD

R_PULLUP

Logic Control

and Registers

nPOR

100k

Power On

Reset

GND_SW1

GND_SW2

GND_C

GND_L

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8.3 Features Description

8.3.1 Linear Low Dropout Regulators (LDOs)

LDO1 and LDO2 are identical linear regulators targeting analog loads characterized by low noise requirements.

LDO1 and LDO2 are enabled through the ENLDO pin or through the corresponding LDO1 or LDO2 control

register. The output voltages of both LDOs are register programmable. The default output voltages are factory

programmed during Final Test, which can be tailored to the specific needs of the system designer.

VLDO

VIN

LDO

Register

controlled

+

-

ENLDO

Vref

GND

Figure 11. LDO Functional Block Diagram

8.3.2 No-Load Stability

The LDOs remain stable and in regulation with no external load. This is an important consideration in some

circuits, for example, CMOS RAM keep-alive applications.

8.3.3 LDO1 and LDO2 Control Registers

LDO1 and LDO2 can be configured by means of the LDO1 and LDO2 control registers. The output voltage is

programmable in steps of 100 mV from 1 V to 3.5 V by programming bits D4 to D0 in the LDO Control registers.

Both LDO1 and LDO2 are enabled by applying a logic 1 to the ENLDO1 and ENLDO2 pin. Enable/disable control

is also provided through enable bit of the LDO1 and LDO2 control registers. The value of the enable LDO bit in

the register is logic 1 by default. The output voltage can be altered while the LDO is enabled.

8.3.4 SW1, SW2: Synchronous Step-Down Magnetic DC-DC Converters

8.3.4.1 Functional Description

The LP8731-Q1 incorporates two high-efficiency synchronous switching buck regulators, SW1 and SW2, that

deliver a constant voltage from a single Li-Ion battery to the portable system processors. Using a voltage mode

architecture with synchronous rectification, both bucks have the ability to deliver up to 1200 mA, depending on

the input voltage and output voltage (voltage head room), and the inductor chosen (maximum current capability).

Both SW1 and SW2 can operate up to a 100% duty cycle (PMOS switch always on) for low dropout control of

the output voltage. In this way the output voltage is controlled down to the lowest possible input voltage.

Additional features include soft-start, undervoltage lockout, current overload protection, and thermal overload

protection.

8.3.4.2 Circuit Operation

A buck converter contains a control block, a switching PFET connected between input and output, a synchronous

rectifying NFET connected between the output and ground (BUCKGND pin) and a feedback path. During the first

portion of each switching cycle, the control block turns on the internal PFET switch. This allows current to flow

from the input through the inductor to the output filter capacitor and load. The inductor limits the current to a

ramp with a slope of

V_IN- V_OUT

L

(1)

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Features Description (continued)

by storing energy in a magnetic field. During the second portion of each cycle, the control block turns the PFET

switch off, blocking current flow from the input, and then turns the NFET synchronous rectifier on. The inductor

draws current from ground through the NFET to the output filter capacitor and load, which ramps the inductor

current down with a slope of

-V_OUT

L

(2)

The output filter stores charge when the inductor current is high, and releases it when low, smoothing the voltage

across the load.

8.3.4.3 PWM Operation

During PWM operation the converter operates as a voltage-mode controller with input voltage feed forward. This

allows the converter to achieve excellent load and line regulation. The DC gain of the power stage is proportional

to the input voltage. To eliminate this dependence, a feedforward voltage inversely proportional to the input

voltage is introduced.

8.3.4.4 Internal Synchronous Rectification

While in PWM mode, the buck uses an internal NFET as a synchronous rectifier to reduce rectifier forward

voltage drop and associated power loss. Synchronous rectification provides a significant improvement in

efficiency whenever the output voltage is relatively low compared to the voltage drop across an ordinary rectifier

diode.

8.3.4.5 Current Limiting

A current limit feature allows the converter to protect itself and external components during overload conditions.

PWM mode implements current limiting using an internal comparator that trips at 1.7 A for Buck1 and Buck2

(typical). If the output is shorted to ground the device enters a timed current limit mode where the NFET is turned

on for a longer duration until the inductor current falls below a low threshold, ensuring inductor current has more

time to decay, thereby preventing runaway.

8.3.4.6 SW1, SW2 Operation

SW1 and SW2 have selectable output voltages ranging from 0.8875 V to 1.675 V (typ.). Both SW1 and SW2 in

the LP8731-Q1 are I²C register controlled and are enabled by default through the internal state machine of the

LP8731-Q1 following a power-on event that moves the operating mode to the Active state. (See Flexible Power

Sequencing of Multiple Power Supplies.) The SW1 and SW2 output voltages revert to default values when the

power-on sequence has been completed. The default output voltage for each buck converter is factory

programmable. (See Application and Implementation.)

8.3.4.7 SW1, SW2 Control Registers

SW1, SW2 can be enabled/disabled through the corresponding control register.

8.3.4.8 Shutdown Mode

During shutdown the PFET switch, reference, control and bias circuitry of the converters are turned off. The

NFET switch is on in shutdown to discharge the output. When the converter is enabled, soft start is activated. It

is recommended to disable the converter during the system power up and undervoltage conditions when the

supply is less than 2.8 V.

8.3.4.9 Soft Start

The soft-start feature allows the power converter to gradually reach the initial steady state operating point, thus

reducing startup stresses and surges. The two LP8731-Q1 buck converters have a soft-start circuit that limits in-

rush current during start-up. During start-up the switch current limit is increased in steps. Soft start is activated

only if EN goes from logic low to logic high after V_INreaches 2.8 V. Soft start is implemented by increasing switch

current limit in steps of 180 mA, 300 mA, and 720 mA for Buck1; 180 mA, 300 mA and 720 mA for Buck2 (typical

switch current limit). The start-up time thereby depends on the output capacitor and load current demanded at

start-up.

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Features Description (continued)

8.3.4.10 Low Dropout Operation

The LP8731-Q1 can operate at 100% duty cycle (no switching; PMOS switch completely on) for low dropout

support of the output voltage. In this way the output voltage is controlled down to the lowest possible input

voltage. When the device operates near 100% duty cycle, output voltage ripple is approximately 25 mV. The

minimum input voltage needed to support the output voltage is

V_{IN, MIN}= I_LOAD× (R_{DSON, PFET}+ R_INDUCTOR) + V_OUT

where

•

I_LOAD: Load current

R_{DSON, PFET}: Drain to source resistance of PFET switch in the triode region

R_INDUCTOR: Inductor resistance

(3)

8.3.4.11 Flexible Power Sequencing of Multiple Power Supplies

The LP8731-Q1 provides several options for power on sequencing. The two bucks can be individually controlled

with ENSW1 and ENSW2. The two LDOs can also be individually controlled with ENLDO1 and ENLDO2.

If the user desires a set power-on sequence, the device can be programmed through I²C by raising EN_T from

LOW to HIGH.

8.3.4.12 Power-Up Sequencing Using the EN_T Function

EN_T assertion causes the LP8731-Q1 to emerge from Standby mode to Full Operation mode at a preset timing

sequence. By default, the enables for the LDOs and Bucks (ENLDO1, ENLDO2, EN_T, ENSW1, ENSW2) are

internally pulled down by a 500-kΩ resistor, which causes the part to stay OFF until enabled. If the user wishes

to use the preset timing sequence to power on the regulators, transition the EN_T pin from LOW to HIGH.

Otherwise, simply tie the enables of each specific regulator HIGH to turn on automatically.

EN_T is edge triggered with rising edge signaling the device to power on. The EN_T input is deglitched, and the

default is set at 1 ms. As shown in Figure 12 and Figure 13, a rising EN_T edge starts a power-on sequence,

while a falling EN_T edge starts a shutdown sequence. If EN_T is high, toggling the external enables of the

regulators has no effect on the device.

The regulators can also be programmed through I²C to turn on and off. By default, I²C enables for the regulators

on ON.

The regulators are on following the pattern: Regulators on = (I²C enable) AND (External pin enable OR EN_T

high).

NOTE

The EN_T power-up sequencing may also be employed immediately after V_INis applied to

the device. However, V_INmust be stable for approximately 8 ms minimum before EN_T be

asserted high to ensure internal bias, reference, and the Flexible POR timing are

stabilized. This initial EN_T delay is necessary only upon first time device power on for

power-sequencing function to operate properly.

2

I C

Regulator ON

Ext_Enable

Pins

0

1

Start Programmed

Timing Sequence

EN_T

Figure 12. Enable Logic Diagram

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Features Description (continued)

EN_T

t

1

Vout Buck1

Vout Buck2

t

2

t

3

Vout LDO1

Vout LDO2

t

4

Figure 13. LP8731-Q1 Default Power-Up Sequence

Table 4. Power-On Timing Specification

MIN

NOM

MAX

UNIT

ms

t₁

t₂

t₃

t₄

Programmable delay from EN_T assertion to V_CC_Buck1 on

Programmable delay from EN_T assertion to V_CC_Buck2 on

Programmable delay from EN_T assertion to V_CC_LDO1 on

Programmable delay from EN_T assertion to V_CC_LDO2 on

1.5

2

ms

3

ms

6

ms

EN_T

Vout Buck1

t

1

Vout Buck2

Vout LDO1

t

2

t

3

Vout LDO2

t

4

Figure 14. LP8731-Q1 Default Power-Off Sequence

MIN

NOM

MAX

UNIT

ms

t₁

Programmable delay from EN_T deassertion to V_CC_Buck1 off

1.5

2

t₂

t₃

t₄

Programmable delay from EN_T deassertion to V_CC_Buck2 off

Programmable delay from EN_T deassertion to V_CC_LDO1 off

Programmable delay from EN_T deassertion to V_CC_LDO2 off

ms

3

ms

6

ms

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NOTE

The LP8731-Q1 default power-off delay setting is the same as the on sequence.

8.3.5 Flexible Power-On Reset (for example, Power Good with Delay)

The LP8731-Q1 is equipped with an internal Power-On-Reset (“POR”) circuit which monitors the output voltage

levels on bucks 1 and 2. The nPOR is an open-drain logic output which is logic LOW when either of the buck

outputs are below 91% of the rising value, or when one or both outputs fall below 82% of the desired value. The

time delay between output voltage level and when nPOR is enabled is (50 µs, 50 ms, 100 ms, 200 ms), 50 µs by

default. The system designer can choose the external pull-up resistor (for example, 100 kΩ) for the nPOR pin.

t2

t1

Case1

EN1

EN2

RDY1

RDY2

nPOR

0V

Counter

delay

t2

t1

Case2

EN1

EN2

RDY1

0V

RDY2

nPOR

Counter

delay

t2

t1

Case3

EN1

EN2

RDY1

RDY2

nPOR

Counter

delay

Figure 15. nPOR With Counter Delay

Figure 15 shows the simplest application of the Power-On Reset, where both switcher enables are tied together.

In Case 1, EN1 causes nPOR to transition LOW and triggers the nPOR delay counter. If the power supply for

Buck2 does not come on within that period, nPOR stays LOW, indicating a power fail mode. Case 2 indicates the

vice-versa scenario if Buck1 supply did not come on. In both cases the nPOR remains LOW.

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Case 3 shows a typical application of the Power On Reset, where both switcher enables are tied together. Even

if RDY1 ramps up slightly faster than RDY2 (or vice versa), then nPOR signal triggers a programmable delay

before going HIGH, as explained in Figure 16.

t0 t1

t2

t3

t4

EN1

RDY1

Counter

delay

Counter

delay

nPOR

EN2

RDY2

Figure 16. Faults Occurring in Counter Delay after Start-Up

The Figure 16 timing diagram details the power-good with delay with respect to the enable signals EN1, and

EN2. The RDY1, RDY2 are internal signals derived from the output of two comparators. Each comparator has

been trimmed as follows:

COMPARATOR LEVEL

BUCK SUPPLY LEVEL

Greater than 94%

Less than 85%

HIGH

LOW

The circuits for EN1 and RDY1 are symmetrical to EN2 and RDY2, so each reference to EN1 and RDY1 also

works for EN2 and RDY2 and vice versa.

If EN1 and RDY1 signals are HIGH at time t1, then the RDY1 signal rising edge triggers the programmable delay

counter (50 μs, 50 ms, 100 ms, 200 ms). This delay forces nPOR LOW between time interval t1 and t2. nPOR is

then pulled HIGH after the programmable delay is completed. If EN2 and RDY2 are initiated during this interval,

the nPOR signal ignores this event.

If either RDY1or RDY2 were to go LOW at t3 then the programmable delay is triggered again.

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t0 t1

t2

t3

t4

EN1

RDY1

nPOR

Counter

delay

Case 1:

EN2

RDY2

Mask Time

nPOR

Mask

Window

Counter

delay

Case 2:

EN2

RDY2

0V

Mask

Window

Mask Time

Counter

delay

nPOR

Figure 17. nPOR Mask Window

If the EN1 and RDY1 are initiated in normal operation, then nPOR is asserted and deasserted .

Case 1 in Figure 17 shows a case where EN2 and RDY2 are initiated after triggered programmable delay. To

prevent the nPOR being asserted again, a masked window (5 ms) counter delay is triggered off the EN2 rising

edge. nPOR is still held HIGH for the duration of the mask, whereupon the nPOR status afterwards depends on

the status of both RDY1 and RDY2 lines.

Case 2 shows the case where EN2 is initiated after the RDY1 triggered programmable delay, but RDY2 never

goes HIGH (Buck2 never turns on). Normal operation of nPOR occurs with respect to EN1 and RDY1, and the

nPOR signal is held HIGH for the duration of the mask window. nPOR goes LOW after the masking window has

timed out because it is now dependent on RDY1 and RDY2, where RDY2 is LOW.

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Delay Mask Counter

EN1

RDY1

S

R

Q

EN2

nPOR

RDY2

Delay

POR

Delay Mask Counter

Figure 18. Design Implementation Of The Flexible Power-On Reset

An internal power-on reset of the device is used with EN1 and EN2 to produce a reset signal (LOW) to the delay

timer nPOR. EN1 and RDY1 or EN2 and RDY2 are used to generate the set signal (HIGH) to the delay timer.

S = R = 1 never occurs. The mask timers are triggered by EN1 and EN2 which are gated with RDY1 and RDY2

to generate outputs to the final AND gate to generate the nPOR.

8.3.6 Undervoltage Lockout

The LP8731-Q1 features an undervoltage lockout circuit. The function of this circuit is to continuously monitor the

raw input supply voltage (VINLDO12) and automatically disables the four voltage regulators whenever this supply

voltage is less than 2.8 VDC.

The circuit incorporates a bandgap-based circuit that establishes the reference used to determine the 2.8-VDC

trip point for a V_INOK – Not OK detector. This V_INOK signal is then used to gate the enable signals to the four

regulators of the LP8731-Q1. When VINLDO12 is greater than 2.8 VDC, the four enables control the four

regulators, when VINLDO12 is less than 2.8 VDC, the four regulators are disabled by the V_INdetector being in

the “Not OK” state. The circuit has built-in hysteresis to prevent chattering from occurring.

8.4 Device Functional Modes

8.4.1 Shutdown Mode

During shutdown the PFET switch, reference, control, and bias circuitry of the converters are turned off. The

NFET switch is turned on during shutdown to discharge the output. When the converter is enabled, soft start is

activated. It is recommended that the converter be disabled during the system power up and undervoltage

conditions when the supply is less than 2.8 V.

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8.5 Programming

8.5.1 I²C-Compatible Serial Interface

8.5.1.1 I²C Signals

The LP8731-Q1 features an I²C-compatible serial interface, using two dedicated pins: SCL and SDA for I²C clock

and data, respectively. Both signals need a pullup resistor according to the I²C specification. The LP8731-Q1

interface is an I²C slave that is clocked by the incoming SCL clock.

Signal timing specifications are according to the I²C bus specification. The maximum bit rate is 400 kbit/s. See

I²C specification from NXP Semiconductors for further details.

8.5.1.2 I²C Data Validity

The data on the SDA line must be stable during the HIGH period of the clock signal (SCL), that is, the state of

the data line can only be changed when CLK is LOW.

2

I C_SCL

2

I C_SDA

data

change

allowed

data

valid

data

change

allowed

data

valid

data

change

allowed

Figure 19. I²C Signals: Data Validity

8.5.1.3 I²C Start and Stop Conditions

START and STOP bits classify the beginning and the end of the I²C session. START condition is defined as the

SDA signal transitioning from HIGH to LOW while the SCL line is HIGH. STOP condition is defined as the SDA

transitioning from LOW to HIGH while the SCL is HIGH. The I²C master always generates START and STOP

bits. The I²C bus is considered to be busy after START condition and free after STOP condition. During data

transmission, I²C master can generate repeated START conditions. First START and repeated START

conditions are equivalent, function-wise.

2

I C_SDA

2

I C_SCL

S

P

START condition

STOP condition

Figure 20. Start And Stop Conditions

8.5.1.4 Transferring Data

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.

Each byte of data has to be followed by an acknowledge bit. The acknowledged related clock pulse is generated

by the master. The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver

must pull down the SDA line during the 9th clock pulse, signifying acknowledgment. A receiver which has been

addressed must generate an acknowledgment (“ACK”) after each byte has been received.

After the START condition, the I²C master sends a chip address. This address is seven bits long followed by an

eighth bit which is a data direction bit (R/W).

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Programming (continued)

NOTE

According to industry I²C standards for 7-bit addresses, the MSB of an 8-bit address is

removed, and communication actually starts with the 7th most significant bit. For the

eighth bit (LSB), a “0” indicates a WRITE and a “1” indicates a READ. The second byte

selects the register to which the data is written. The third byte contains data to write to the

selected register.

The LP8731-Q1 has factory-programmed I²C addresses. The device has a chip address of 59'h.

MSB

LSB

ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0

R/W

bit0

bit7

bit6

bit5

bit4

bit3

bit2

bit1

1

0

I²C SLAVE address (chip address)

Figure 21. I²C Chip Address (see NOTE above)

ack from slave

ack stop

ack from slave

start

MSB Chip id LSB

w

ack MSB Register Addr LSB ack

MSB Data LSB

SCL

SDA

start

id = 101 1001b

w

ack

Register address

ack

data

ack stop

w = write (SDA = “0”)

r = read (SDA = “1”)

ack = acknowledge (SDA pulled down by either master or slave)

rs = repeated start

id = LP8731-Q1 chip address: 0x59

Figure 22. I²C Write Cycle

When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in

the Read Cycle waveform.

Repeated start

ack from slave data from slave

ack from master

ack from slave

rs

ack

stop

ack

start

MSB Chip id LSB

w

ack MSB Register Addr LSB ack

r

MSB Chip id LSB

MSB Data LSB

SCL

SDA

start

ack stop

id = 101 1001b

data

id = 101 1001b

w

ack

Register address

ack rs

ack

Figure 23. I²C Read Cycle

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8.6 LP8731-Q1 Register Maps

REGISTER ADDRESS REGISTER NAME

READ/WRITE

R

REGISTER DESCRIPTION

Interrupt Status Register A

0x02

0x07

0x10

0x11

0x20

0x23

0x24

0x25

0x29

0x2A

0x2B

0x38

0x39

0x3A

ICRA

SCR1

R/W

R

System Control 1 Register

BKLDOEN

BKLDOSR

VCCR

Buck and LDO Output Voltage Enable Register

Buck and LDO Output Voltage Status Register

Voltage Change Control Register 1

Buck1 Target Voltage 1 Register

Buck1 Target Voltage 2 Register

Buck1 Ramp Control

R/W

B1TV1

B1TV2

B1RC

B2TV1

Buck2 Target Voltage 1 Register

Buck2 Target Voltage 2 Register

Buck2 Ramp Control

B2TV2

B2RC

BFCR

Buck Function Register

LDO1VCR

LDO2VCR

LDO1 Voltage control Registers

LDO2 Voltage control Registers

8.6.1 Interrupt Status Register (ISRA) 0x02

This register informs the system engineer of the temperature status of the chip.

D7-D2

D1

D0

Name

Access

Data

—

Temp 125°C

R

—

Reserved

0

Status bit for thermal warning

PMIC T > 125°C

0 – PMIC Temp. < 125°C

1 – PMIC Temp. > 125°C

Reserved

0

Reset

0

8.6.2 System Control 1 Register (SCR1) 0x07

This register allows the user to select the preset delay sequence for power-on timing and to select between an

internal and external clock for the bucks.

D7

D6-D4

EN_DLY

D3

D2

D1

D0

Name

Access

Data

—

FPWM2⁽¹⁾

R/W

FPWM1⁽¹⁾

R/W

ECEN

R/W

Reserved

Selects the preset

delay sequence from

EN_T assertion

Reserved

Buck2 PWM /PFM Mode Buck 1 PWM /PFM

Reserved

select

Mode select

0 – Auto Switch PFM -

PWM operation

1 – PWM Mode Only

0 – Auto Switch PFM -

PWM operation

1 – PWM Mode Only

(shown below)

Reset

0

Factory-Programmed

Default

1

Factory-Programmed

Default

Factory-Programmed

Default

0

(1) Default PWM mode only — please contact TI sales office if Auto switch/PFM mode operation is needed.

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8.6.3 EN_DLY Preset Delay Sequence after EN_T Assertion

DELAY (ms)

EN_DLY<2:0>

Buck1

1

Buck2

LDO1

LDO2

000

001

010

011

100

101

110

111

1

1.5

2

1

2

3

1

3

2

1

6

1

2

1

1.5

3

6

2

1

2

6

1.5

2

1.5

11

2

3

8.6.4 Buck and LDO Output Voltage Enable Register (BKLDOEN) – 0x10

This register controls the enables for the Bucks and LDOs.

D7

D6

LDO2EN

R/W

D5

D4

LDO1EN

R/W

D3

D2

BK2EN

D1

D0

BK1EN

Name

Access

Data

—

R/W

Reserved

0 – Disable

1 – Enable

Reserved

0 – Disable

1 – Enable

Reserved

0 – Disable

1 – Enable

Reserved

0 – Disable

1 – Enable

Reset

0

1

0

1

0

1

8.6.5 Buck and LDO Status Register (BKLDOSR) – 0x11

This register monitors whether the Bucks and LDOs meet the voltage output specifications.

D7

BKS_OK

R

D6

LDOS_OK

R

D5

LDO2_OK

R

D4

LDO1_OK

R

D3

D2

BK2_OK

D1

D0

Name

Access

Data

—

BK1_OK

R

0 – Buck 1-2

Not Valid

0 – LDO 1-2

Not Valid

0 – LDO2 Not

Valid

0 – LDO1 Not

Valid

Reserve 0 – Buck2 Not

Reserve 0 – Buck1 Not

d

Valid

d

Valid

1 – Bucks Valid 1 – LDOs Valid 1 – LDO2 Valid 1 – LDO1 Valid

1 – Buck2 Valid

1 – Buck1 Valid

Reset

0

8.6.6 BUCK Voltage Change Control Register 1 (VCCR) – 0x20

This register selects and controls the output target voltages for the buck regulators.

D7-D6

D5

D4

D3-2

D1

D0

Name

Access

Data

—

B2VS

R/W

B2GO

R/W

—

B1VS

R/W

B1GO

R/W

Reserved

Buck2 Target Voltage

Select

Buck2 Voltage Ramp

CTRL

Reserved

Buck1 Target Voltage

Select

Buck1 Voltage Ramp

CTRL

0 – B2VT1

0 – Hold

0 – B1VT1

0 – Hold

1 – B2VT2

1 – Ramp to B2VS

selection

1 – B1VT2

1 – Ramp to B1VS

selection

Reset

00

0

00

0

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8.6.7 BUCK1 Target Voltage 1 Register (B1TV1) – 0x23

This register allows the user to program the output target voltage of Buck1 (target voltage 1).

D7-D6

—

D5

Buck1 12p5 mV step

R/W

D4-0

B1TV1

R/W

BUCK1 OUTPUT VOLTAGE (V)

Name

—

Access

—

1’h0

5’h00

5’h01

5’h02

5’h03

5’h04

5’h05

5’h06

5’h07

5’h08

5’h09

5’h0A

5’h0B

5’h0C

5’h0D

5’h0E

5’h0F

0.8875

0.9000

0.9125

0.9250

0.9375

0.9500

0.9625

0.9750

0.9875

1.0000

1.0125

1.0250

1.0375

1.0500

1.0625

1.0750

1.0875

1.1000

1.1125

1.1250

1.1375

1.1500

1.1625

1.1750

1.1875

1.2000

1.2125

1.2250

1.2375

1.2500

1.2625

1.2750

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

Data

Reserved

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

24

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D7-D6

D5

D4-0

5'h10

5'h11

5'h12

5'h13

5'h14

5'h15

5'h16

5'h17

5'h18

5'h19

5'h1A

5'h1B

5'h1C

5'h1D

5'h1E

5'h1F

BUCK1 OUTPUT VOLTAGE (V)

Data

Register

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1'h0

1'h1

1'h0

1'h1

1'h0

1'h1

1.2875

1.3000

1.3125

1.3250

1.3375

1.3500

1.3625

1.3750

1.3875

1.4000

1.4125

1.4250

1.4375

1.4500

1.4625

1.4750

1.4875

1.5000

1.5125

1.5250

1.5375

1.5500

1.5625

1.5750

1.5875

1.6000

1.6125

1.6250

1.6375

1.6500

1.6625

1.6750

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8.6.8 BUCK1 Target Voltage 2 Register (B1TV2) - 0x24

This register allows the user to program the output target voltage of Buck1 (target voltage 2).

D7-D6

—

D5

Buck1 12p5 mV step

R/W

D4-D0

B1TV2

R/W

BUCK1 OUTPUT VOLTAGE (V)

Name

—

Access

—

1’h0

5’h00

5’h01

5’h02

5’h03

5’h04

5’h05

5’h06

5’h07

5’h08

5’h09

5’h0A

5’h0B

5’h0C

5’h0D

5’h0E

5’h0F

0.8875

0.9000

0.9125

0.9250

0.9375

0.9500

0.9625

0.9750

0.9875

1.0000

1.0125

1.0250

1.0375

1.0500

1.0625

1.0750

1.0875

1.1000

1.1125

1.1250

1.1375

1.1500

1.1625

1.1750

1.1875

1.2000

1.2125

1.2250

1.2375

1.2500

1.2625

1.2750

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

Data

Reserved

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

26

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D7-D6

D5

D4-D0

5'h10

5'h11

5'h12

5'h13

5'h14

5'h15

5'h16

5'h17

5'h18

5'h19

5'h1A

5'h1B

5'h1C

5'h1D

5'h1E

5'h1F

BUCK1 OUTPUT VOLTAGE (V)

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1'h0

1'h1

1'h0

1'h1

1'h0

1'h1

1.2875

1.3000

1.3125

1.3250

1.3375

1.3500

1.3625

1.3750

1.3875

1.4000

1.4125

1.4250

1.4375

1.4500

1.4625

1.4750

1.4875

1.5000

1.5125

1.5250

1.5375

1.5500

1.5625

1.5750

1.5875

1.6000

1.6125

1.6250

1.6375

1.6500

1.6625

1.6750

Data

Reserved

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8.6.9 BUCK1 Ramp Control Register (B1RC) - 0x25

This register allows the user to program the rate of change between the target voltages of Buck1.

D7

- - - -

D6-D4

- - - -

D3-D0

B1RS

R/W

Name

Access

Data

- - - -

Reserved

Data Code

4'h0

Ramp Rate mV/us

Instant

4'h1

1

2

4'h2

4'h3

3

4'h4

4

4'h'5

5

4'h6

6

4'h7

7

4'h8

8

4'h9

9

4'hA

10

4'hB - 4'hF

28

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8.6.10 BUCK2 Target 1 Register (B2TV1) - 0x29

This register allows the user to program the output target voltage of Buck2 (target voltage 1).

D7-D6

—

D5

Buck1 12.5 mV step

R/W

D4-D0

B2TV1

R/W

BUCK2 OUTPUT VOLTAGE (V)

Name

—

Access

—

1’h0

5’h00

5’h01

5’h02

5’h03

5’h04

5’h05

5’h06

5’h07

5’h08

5’h09

5’h0A

5’h0B

5’h0C

5’h0D

5’h0E

5’h0F

0.8875

0.9000

0.9125

0.9250

0.9375

0.9500

0.9625

0.9750

0.9875

1.0000

1.0125

1.0250

1.0375

1.0500

1.0625

1.0750

1.0875

1.1000

1.1125

1.1250

1.1375

1.1500

1.1625

1.1750

1.1875

1.2000

1.2125

1.2250

1.2375

1.2500

1.2625

1.2750

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

Data

Reserved

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

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D7-D6

D5

D4-D0

5'h10

5'h11

5'h12

5'h13

5'h14

5'h15

5'h16

5'h17

5'h18

5'h19

5'h1A

5'h1B

5'h1C

5'h1D

5'h1E

5'h1F

BUCK2 OUTPUT VOLTAGE (V)

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1'h0

1'h1

1'h0

1'h1

1'h0

1'h1

1.2875

1.3000

1.3125

1.3250

1.3375

1.3500

1.3625

1.3750

1.3875

1.4000

1.4125

1.4250

1.4375

1.4500

1.4625

1.4750

1.4875

1.5000

1.5125

1.5250

1.5375

1.5500

1.5625

1.5750

1.5875

1.6000

1.6125

1.6250

1.6375

1.6500

1.6625

1.6750

Data

Reserved

30

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8.6.11 BUCK2 Target 2 Register (B2TV2) - 0x2A

This register allows the user to program the output target voltage of Buck2 (target voltage 2).

D7-D6

—

D5

Buck1 12.5 mV step

R/W

D4-D0

B2TV2

R/W

BUCK2 OUTPUT VOLTAGE (V)

Name

—

Access

—

1’h0

5’h00

5’h01

5’h02

5’h03

5’h04

5’h05

5’h06

5’h07

5’h08

5’h09

5’h0A

5’h0B

5’h0C

5’h0D

5’h0E

5’h0F

0.8875

0.9000

0.9125

0.9250

0.9375

0.9500

0.9625

0.9750

0.9875

1.0000

1.0125

1.0250

1.0375

1.0500

1.0625

1.0750

1.0875

1.1000

1.1125

1.1250

1.1375

1.1500

1.1625

1.1750

1.1875

1.2000

1.2125

1.2250

1.2375

1.2500

1.2625

1.2750

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

Data

Reserved

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

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D7-D6

D5

D4-D0

5'h10

5'h11

5'h12

5'h13

5'h14

5'h15

5'h16

5'h17

5'h18

5'h19

5'h1A

5'h1B

5'h1C

5'h1D

5'h1E

5'h1F

BUCK2 OUTPUT VOLTAGE (V)

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1’h0

1'h1

1'h0

1'h1

1'h0

1'h1

1'h0

1'h1

1.2875

1.3000

1.3125

1.3250

1.3375

1.3500

1.3625

1.3750

1.3875

1.4000

1.4125

1.4250

1.4375

1.4500

1.4625

1.4750

1.4875

1.5000

1.5125

1.5250

1.5375

1.5500

1.5625

1.5750

1.5875

1.6000

1.6125

1.6250

1.6375

1.6500

1.6625

1.6750

Data

Reserved

32

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8.6.12 BUCK2 Ramp Control Register (B2RC) - 0x2B

This register allows the user to program the rate of change between the target voltages of Buck2.

D7

- - - -

D6-D4

- - - -

D3-D0

B2RS

R/W

Name

Access

Data

- - - -

Reserved

Data Code

4'h0

Ramp Rate mV/us

Instant

4'h1

1

2

4'h2

4'h3

3

4'h4

4

4'h5

5

4'h6

6

4'h7

7

4'h8

8

4'h9

9

4'hA

10

4'hB - 4'hF

Reset

0

010

1000

8.6.13 BUCK Function Register (BFCR) – 0x38

This register allows the Buck switcher clock frequency to be spread across a wider range, allowing for less

Electro-magnetic Interference (EMI). The spread spectrum modulation frequency refers to the rate at which the

frequency ramps up and down, centered at 2 MHz.

Spread Spectrum

frequency

Peak frequency deviation

2 kHz triangle

wave

10 kHz triangle

wave

2 MHz

Time

Figure 24. Spread Spectrum Frequency Modulation

8.6.14 Spread Spectrum Function

Periodic switching in the buck regulator is inherently a noisier function block compared to an LDO. It can be

challenging in some critical applications to comply with stringent regulatory standards or simply to minimize

interference to sensitive circuits in space limited portable systems. The regulator’s switching frequency and

harmonics can cause "noise" in the signal spectrum. The magnitude of this noise is measured by its power

spectral density. The power spectral density of the switching frequency, FC, is one parameter that system

designers want to be as low as practical to reduce interference to the environment and subsystems within their

products. The LP8731-Q1 has a user-selectable function on the device, allowing a noise-reduction technique

known as spread spectrum to be employed to ease customer’s design and production issues.

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The principle behind spread spectrum is to modulate the switching frequency slightly and slowly, and spread the

signal frequency over a broader bandwidth. Thus, its power spectral density becomes attenuated, used as a

spread spectrum clock via two I₂C control register bits bk_ssen, and slomod. With this feature enabled, the

intense energy of the clock frequency can be spread across a small band of frequencies in the neighborhood of

the center frequency. The results in a reduction of the peak energy!

The LP8731-Q1 spread spectrum clock uses a triangular modulation profile with equal rise and fall slopes. The

modulation has the following characteristics:

•

The center frequency: FC = 2 MHz, and

The modulating frequency, ƒM = 6.8 kHz or 12 kHz.

Peak frequency deviation: Δ_ƒ = ±100 kHz (or ±5%)

Modulation index β = Δ_ƒ/ƒM = 14.7 or 8.3

This register also allows dynamic scaling of the nPOR Delay Timing. The LP8731-Q1 is equipped with an internal

Power-On Reset (POR) circuit which monitors the output voltage levels on the buck regulators, allowing the user

to more actively monitor the power status of the device. The undervoltage lockout feature continuously monitor

the raw input supply voltage (VINLDO12) and automatically disables the four voltage regulators whenever this

supply voltage is less than 2.8 VDC. This prevents the user from damaging the power source (for example, the

battery), but can be disabled if the user wishes.

The UVLO feature continuously monitor the raw input supply voltage (VINLDO12) and automatically disables the

four voltage regulators whenever this supply voltage is less than 2.8 VDC. This prevents the user from damaging

the power source (for example, the battery), but can be disabled if the user wishes.

NOTE

If the supply to VINs is close to 2.8 V with a heavy load current on the regulators, the

device could power down due to UVLO. If the user wishes to keep the device active under

those conditions, the bypass UVLO feature should be enabled.

D7-D5

—

D4

BP_UVLO

D3-D2

D1

BK_SLOMOD

D0

Name

Access

Data

TPOR

R/W

BK_SSEN

R/W

—

R/W

Reserved

Bypass UVLO

monitoring

nPOR Delay Timing

00 - 50 µs

Buck Spread Spectrum

Modulation

Spread Spectrum

Function Output

0 - Allow UVLO

1 - Disable UVLO

01 - 50 ms

10 - 100 ms

11 - 200 ms

0 – 10-kHz triangular wave 0 – Disabled

1 – 2-kHz triangular wave

1 – Enabled

Reset

000

Factory-Programmed Default

1

0

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8.6.15 LDO1 Control Register (LDO1VCR) – 0x39

This register allows the user to program the output target voltage of LDO1.

D7-D5

D4-D0

LDO1_OUT

Name

Access

Data

—

R/W

Reserved

LDO1 Output voltage (V)

5’h00

5’h01

5’h02

5’h03

5’h04

5’h05

5’h06

5’h07

5’h08

5’h09

5’h0A

5’h0B

5’h0C

5’h0D

5’h0E

5’h0F

5’h10

5’h11

5’h12

5’h13

5’h14

5’h15

5’h16

5’h17

5’h18

5’h19

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

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8.6.16 LDO2 Control Register (LDO2VCR) – 0x3A

This register allows the user to program the output target voltage of LDO2.

D7-D5

D4-D0

LDO2_OUT

Name

Access

Data

—

R/W

Reserved

LDO2 Output voltage (V)

5’h00

5’h01

5’h02

5’h03

5’h04

5’h05

5’h06

5’h07

5’h08

5’h09

5’h0A

5’h0B

5’h0C

5’h0D

5’h0E

5’h0F

5’h10

5’h11

5’h12

5’h13

5’h14

5’h15

5’h16

5’h17

5’h18

5’h19

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

One of the key features of this integrated PMU is that it requires effectively no design procedures because the

output voltage is digitally programmable and bounded, compensation components are internally fixed or selected,

and the external support capacitors and inductors and optimized for typical applications and performance. Given

the I/O range and maximum loading are fixed and target transient and output ripple are prescribed, as reflected

in Design Requirements, the external components values are optimized as follows:

•

LDO C_IN= 1 µF, C_OUT= 0.47 µF

Buck C_IN= C_OUT= 10 µF

Buck Inductor = 2.2 µH

The Component Selection section also details the background and sample calculations for capacitor and inductor

selections, should users choose to operate with different component values than those recommended in order to

achieve other performance characteristics that typically suggested.

9.2 Typical Application

LDO1

EN_T

I/O Voltage

Domain

VDD

100k

VINLDO12

1 PF

ENLDO1

ENLDO2

nPOR

VIN1

ENSW1

ENSW2

LDO1

SDA

SCL

Advanced

Power

Controller

10 PF

2.2 PH

SW1

FB1

10 PF

0.47 PF

VINLDO1

VINLDO2

LDO2

GND_SW1

Buck1

LDO1

Core ADAS

Domain

Block

1 PF

LP8731

VIN2

10 PF

2.2 PH

0.47 PF

SW2

FB2

Buck2

LDO2

Peripheral

ADAS

Blocks

SDA

SCL

10 PF

GND_SW2

AVDD

GND_L

GND_C

Application

System or SoC

1 PF

Figure 25. LP8731-Q1 Simplified Schematic

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Typical Application (continued)

9.2.1 Design Requirements

Table 5. Design Parameters

DESIGN PARAMETER

Input voltage range

EXAMPLE VALUE

2.8 V to 5.5 V

2 MHz ±10%

0.8875 V to 1.675 V

1.2 A

Switching frequency

Output voltage range: bucks

Output current rating: bucks

Output voltage range: LDOs

Output current rating: LDOs

0.8 V to 3.3 V

300 mA

Transient response at max load with Tr = Tf = 10 µs

Bucks output typical ripple voltage

ΔV_OUTapproximately equals ±1%

< 10 mV PWM, < 20 mV PFM

9.2.2 Detailed Design Procedure

9.2.2.1 Component Selection

9.2.2.1.1 Inductors for SW1 and SW2

There are two main considerations when choosing an inductor: the inductor should not saturate, and the inductor

current ripple is small enough to achieve the desired output voltage ripple. Care should be taken when reviewing

the different saturation current ratings that are specified by different manufacturers. Saturation current ratings are

typically specified at 25°C, so ratings at maximum ambient temperature of the application should be requested

from the manufacturer.

There are two methods to choose the inductor saturation current rating:

9.2.2.1.1.1 Method 1:

The saturation current is greater than the sum of the maximum load current and the worst case average to peak

inductor current. This can be written as follows:

I_sat> I_outmax+ I_ripple

V_IN- V_OUT

2L

· _x§^V^OUT

·

¹

1

§ ·

§

©

x

where

I_ripple

⁼© _f¹

V

¹ ©

IN

where

•

I_RIPPLE: Average to peak inductor current

I_OUTMAX: Maximum load current

V_IN: Maximum input voltage to the buck

L: Min inductor value including worse case tolerances (30% drop can be considered for method 1)

ƒ: Minimum switching frequency (1.6 MHz)

V_OUT: Buck Output voltage

(4)

9.2.2.1.1.2 Method 2:

A more conservative and recommended approach is to choose an inductor that has saturation current rating

greater than the maximum current limit of 1800 mA for Buck1 and Buck2.

Given a peak-to-peak current ripple (I_PP) the inductor needs to be at least:

V_IN- V_OUT

I_PP

· _x§^V^OUT

·

¹

§ ·

1

§

©

x

L t

V

¹ ©

IN

(5)

38

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INDUCTOR

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Table 6. Suggested Inductors

IRMS RATING

VALUE

UNIT

L × W × H (mm)

DCR

VENDORS

PART ID

TYP

2.1 A

1.85 A

2.1 A

2 A

L_SW1,2

2.2

µH

3.2 × 2.5 × 1.2

3.2 × 2.5 × 1.55

3.2 × 2.5 × 1.2

5.0 × 5.0 × 1.5

70 mΩ

64 mΩ

70 mΩ

Toko

Murata

DFE322512C

LQH32PN2R2NNCL

MHCD322512-2R2M-A8DY

NP04SZB 2R2N

Chilisin

Taiyo Yuden

9.2.2.1.2 External Capacitors

The regulators on the LP8731-Q1 require external capacitors for regulator stability. These are specifically

designed for portable applications requiring minimum board space and smallest components. These capacitors

must be correctly selected for good performance.

9.2.2.2 LDO Capacitor Selection

9.2.2.2.1 Input Capacitor

An input capacitor is required for stability. It is recommended that a 1-μF capacitor be connected between the

LDO input pin and ground (this capacitance value may be increased without limit).

This capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean

analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.

NOTE

Tantalum capacitors can suffer catastrophic failures due to surge currents when

connected to a low impedance source of power (like a battery or a very large capacitor). If

a tantalum capacitor is used at the input, it must be ensured by the manufacturer to have

a surge current rating sufficient for the application.

There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance and

temperature coefficient must be considered when selecting the capacitor to ensure the capacitance remains

approximately 1 μF over the entire operating temperature range.

9.2.2.2.2 Output Capacitor

The LDOs on the LP8731-Q1 are designed specifically to work with very small ceramic output capacitors. A 0.47-

µF ceramic capacitor (temperature types Z5U, Y5V or X7R) with ESR between 5 mΩ to 500 mΩ, is suitable in

the application circuit.

It is also possible to use tantalum or film capacitors at the device output, C_OUT(or V_OUT), but these are not as

attractive for reasons of size and cost.

The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR

value that is within the range 5 mΩ to 500 mΩ for stability.

9.2.2.2.3 Capacitor Characteristics

The LDOs are designed to work with ceramic capacitors on the output to take advantage of the benefits they

offer. For capacitance values in the range of 0.47 µF to 4.7 µF, ceramic capacitors are the smallest, least

expensive, and have the lowest ESR values, thus making them best for eliminating high-frequency noise. The

ESR of a typical 1-µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR

requirement for stability for the LDOs.

For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure

correct device operation. The capacitor value can change greatly, depending on the operating conditions and

capacitor type.

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In particular, the output capacitor selection should take account of all the capacitor parameters, to ensure that the

specification is met within the application. The capacitance can vary with DC bias conditions as well as

temperature and frequency of operation. Capacitor values also show some decrease over time due to aging. The

capacitor parameters are also dependent on the particular case size, with smaller sizes giving poorer

performance figures in general. As an example, Figure 26 is typical graph comparing different capacitor case

sizes in a capacitance vs DC bias plot.

0603, 10V, X5R

100%

80%

60%

0402, 6.3V, X5R

40%

20%

0

1.0

2.0

3.0

4.0

5.0

DC BIAS (V)

Figure 26. Typical Variation In Capacitance vs DC Bias

As shown in Figure 26, increasing the DC bias condition can result in the capacitance value that falls below the

minimum value given in the recommended capacitor specifications table. Note that the graph shows the

capacitance out of spec for the 0402 case size capacitor at higher bias voltages. It is therefore recommended

that the capacitor manufacturers' specifications for the nominal value capacitor are consulted for all conditions,

as some capacitor sizes (e.g. 0402) may not be suitable in the actual application.

The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a

temperature range of −55°C to 125°C, only varies the capacitance to within ±15%. The capacitor type X5R has a

similar tolerance over a reduced temperature range of −55°C to 85°C. Many large value ceramic capacitors,

larger than 1 µF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance can drop by

more than 50% as the temperature varies from 25°C to 85°C. Therefore X7R is recommended over Z5U and

Y5V in applications where the ambient temperature changes significantly above or below 25°C.

Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more

expensive when comparing equivalent capacitance and voltage ratings in the 0.47-µF to 4.7-µF range.

Another important consideration is that tantalum capacitors have higher ESR values than equivalent size

ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the

stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic

capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum increases about

2:1 as the temperature goes from 25°C down to −40°C, so some guard band must be allowed.

9.2.2.2.4 Input Capacitor Selection for SW1 And SW2

A ceramic input capacitor of 10 µF, 6.3 V is sufficient for the magnetic DC-DC converters. Place the input

capacitor as close as possible to the input of the device. A large value may be used for improved input voltage

filtering. The recommended capacitor types are X7R or X5R. Y5V type capacitors should not be used. DC bias

characteristics of ceramic capacitors must be considered when selecting case sizes like 0805 and 0603. The

input filter capacitor supplies current to the PFET switch of the DC-DC converter in the first half of each cycle

and reduces voltage ripple imposed on the input power source. A ceramic capacitor’s low Equivalent Series

Resistance (ESR) provides the best noise filtering of the input voltage spikes due to fast current transients. A

capacitor with sufficient ripple current rating should be selected. The Input current ripple can be calculated as:

r²

V_OUT

§

©

·

¹

(V_in± V_out) x V_out

I_rms= I_outmax

1 +

where

r =

V_IN

12

L x f x I_outmaxx V_in

(6)

The worse case is when V_IN= 2 × V_OUT

.

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9.2.2.2.5 Output Capacitor Selection for SW1, SW2

A 10-μF, 6.3-V ceramic capacitor should be used on the output of the SW1 and SW2 magnetic DC-DC

converters. The output capacitor needs to be mounted as close as possible to the output of the device. A large

value may be used for improved input voltage filtering. The recommended capacitor types are X7R or X5R. Y5V

type capacitors should not be used. DC bias characteristics of ceramic capacitors must be considered when

selecting case sizes like 0805 and 0603. DC bias characteristics vary from manufacturer to manufacturer and DC

bias curves should be requested from them and analyzed as part of the capacitor selection process.

The output filter capacitor of the magnetic DC-DC converter smooths out current flow from the inductor to the

load, helps maintain a steady output voltage during transient load changes and reduces output voltage ripple.

These capacitors must be selected with sufficient capacitance and sufficiently low ESD to perform these

functions.

The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its

ESR and can be calculated as follows:

I_ripple

V_pp-c

=

4 x f x C

(7)

(8)

Voltage peak-to-peak ripple due to ESR can be expressed as follows:

V_PP–ESR= 2 × I_RIPPLE× R_ESR

Because the V_PP-Cand V_PP-ESRare out of phase, the rms value can be used to get an approximate value of the

peak-to-peak ripple:

V_pp-c²+ V_pp-esr

2

V_pp-rms

=

(9)

NOTE

The output voltage ripple is dependent on the inductor current ripple and the equivalent

series resistance of the output capacitor (R_ESR). The R_ESRis frequency dependent as well

as temperature dependent. The R_ESRshould be calculated with the applicable switching

frequency and ambient temperature.

Table 7. Suggested Capacitors

CAPACITOR

CLDO1, CLDO2

CSW1, CSW2

CIN

VALUE

0.47 µF

10 µF

1 µF

L × W × H (mm)

1.0 × 0.5 × 0.5 (0402)

3.2 × 1.6 × 1.6 (1206)

2 × 1.25 × 1.45 (0805)

0.6 × 0.3 × 0.1 (0603)

1.0 × 0.5× 0.5 (0402)

TYPE

TOLERANCE VENDORS

PART ID

X7S, 10 V

X7R, 16 V

X5R, 16 V

X7R, 6.3 V

X7S, 10 V

10%

20%

10%

Murata

TDK

GCM155C71A474KE36

C3216XR71C106M

TDK

CGA4J1X5R1C106M125AC

C2012XR71C105K

TDK

CIN

1 µF

Murata

GCM155C71A105KE38

9.2.2.2.6 I²C Pull-up Resistor

Both SDA and SCL pins need to have pull-up resistors connected to VINLDO12 or to the power supply of the I²C

master. The values of the pull-up resistors (typical approximately1.8 kΩ) are determined by the capacitance of

the bus. Too large of a resistor combined with a given bus capacitance results in a rise time that would violate

the maximum rise time specification. A too small resistor results in a contention with the pull-down transistor on

either slave(s) or master.

9.2.2.2.7 Operation Without I²C Interface

Operation of the LP8731-Q1 without the I²C interface is possible if the system can operate with default values for

the LDO and buck regulators. The I²C-less system must rely on the correct default output values of the LDO and

Buck converters.

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9.2.2.3 Junction Temperature

The maximum junction temperature T_J-MAX-OPis 125°C of the IC package.

The following equations demonstrate junction temperature determination, ambient temperature T_A-MAX, and total

device power must be controlled to keep T_Jbelow this maximum:

T_J-MAX-OP= T_A-MAX+ (R_θJA) [°C/ Watt] * (P_D-MAX) [Watts]

Total IC power dissipation P_D-MAXis the sum of the individual power dissipation of the four regulators plus a minor

amount for device overhead. Device overhead is Bias, TSD and LDO analog.

P_D-MAX= P_LDO1+ P_LD02+ P_BUCK1+ P_BUCK2+ (0.0001 A × V_IN) [Watts].

Power dissipation of LDO1

P_LDO1= (V_INLDO1– V_OUTLDO1) × I_OUTLDO1[V × A]

Power dissipation of LDO2

P_LDO2= (V_INLDO2– V_OUTLDO2) × I_OUTLDO2[V × A]

Power dissipation of Buck1

P_Buck1= P_IN– P_OUT

=

V_OUTBuck1× I_OUTBuck1× (1 -η₁) / η₁[V × A]

η₁= efficiency of buck 1

Power dissipation of Buck2

P_Buck2= P_IN– P_OUT

=

V_OUTBuck2× I_OUTBuck2× (1 - η₂) / η₂[V × A]

η₂= efficiency of Buck2

Where η is the efficiency for the specific condition taken from efficiency graphs.

9.2.3 Application Curves (LDO)

Vin Step

(500 mV/DIV)

EN LDO

(2 V/DIV)

Vout LDO

(1 V/DIV)

Vout LDO

Iin_rush

(10 mV/DIV)

(200 mA/DIV)

Time (100 µs/DIV)

V_IN= 3.6 V to 4.2 V

V_OUT= 1.8 V

I_OUT= 300 mA

Tr = Tf = 30 µs

V_IN= 3.6 V

V_OUT= 1.8 V

I_OUT= 200 mA

EN Tr = 18 ns

Figure 27. Line Transient 300-mA, 30-µs Edge Rate

Figure 28. LDO Enable Start-Up Time and Inrush

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9.2.4 Application Curves (BUCK)

Vin Step

(500 mV/DIV)

Buck-2

(20 mV/DIV)

Iout

(200 mA/DIV)

Vout LDO

(20 mV/DIV)

Time (50 µs/DIV)

I_OUT= 300 mA to 500 mA PWM

V_INStep

I_OUT= 300 mA

Tr = Tf = 30 µs

Figure 29. Buck Load Transient PWM Mode

Figure 30. Buck Line Transient PWM

10 Power Supply Recommendations

The device is designed to operate from an input voltage supply range between 2.8 V and 5.5 V. This input supply

may be a battery or regulated source with sufficient low internal resistance such that it is able to deliver the

maximum input current and maintain stable voltage without significant voltage drop during start-up and at load

transient conditions. Additional bulk capacitance may be necessary should the supply source is located more

than five centimeters away from the LP8731-Q1.

10.1 Analog Power Signal Routing

All power inputs should be tied to the main VDD source (for example, battery), unless the user wishes to power it

from another source. (that is, external LDO output).

The analog VDD input pins power the internal bias and error amplifiers, so they should be tied to the main VDD.

The analog VDD inputs must have an input voltage between 2.8 and 5.5 V, as specified in the General Electrical

Characteristics table.

The other input pins (VINLDO1, VINLDO2, VIN1, and VIN2) can actually have inputs lower than 2.8 V, as long as

it is higher than the programmed output (0.3 V, to be safe).

The analog and digital grounds should be tied together outside of the device to reduce noise coupling.

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11 Layout

11.1 Layout Guidelines

The LP8731-Q1 is a monolithic device with integrated power FETs. For that reason, it is important to pay special

attention to the use of appropriate to input, output, power, and ground track dimensions in the PCB layout in

order to achieve low impedance small current loop paths and tracks with adequate current density to carry the

target currents.

The device pin solder bumps are arranged with power and ground bumps at the edges of the package to

facilitate PCB layout considerations. This enables using the top metal layer to route the power and ground tracks.

Thus, the current loops for the bucks can be very short and this also makes placing the bypass caps on the

device side of the PCB possible. (See Figure 31.) Avoid using vias to tap power and ground planes for the

switcher supply pins, because they can be very inductive and could incur large i*dv/dt transient voltage drops. If

vias are unavoidable, use them liberally to minimize the impedance they may present.

For more information on board layout techniques, refer to Texas Instruments AN-1112 DSBGA Wafer Level Chip

Scale Package (SNVA009). This application note also discusses recommended PCB pad geometry, package

handling, solder stencil and the assembly process. See also Texas Instruments AN-1229 SIMPLE SWITCHER^®

PCB Layout Guidelines (SNVA054) and Texas Instruments AN-2078 PCB Layout for Texas Instrument' SIMPLE

SWITCHER® Power Modules (SNVA452).

11.2 Layout Example

All C_INand C_OUTcaps

VIN, SW, VOUT, GND,

should be placed as

C_INand C_OUTtracks be

close to VIN, VOUT and

Suitably sized for low

GND pads as practical.

Impedance path and

carry the target current.

GND2

GND1

C_INBK2

C_INBK1

C_OUTBK1

C_OUTBK2

BUCK2

BUCK1

L2

L1

VIN2

VIN1

Figure 31. LP8731-Q1 Layout Example

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12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation, see the following:

Texas Instruments AN-1112 DSBGA Wafer Level Chip Scale Package (SNVA009).

Texas Instrument AN-1229 SIMPLE SWITCHER^®PCB Layout Guidelines (SNVA054).

Texas Instruments AN-2078 PCB Layout for Texas Instrument'sSIMPLE SWITCHER^®Power Modules

(SNVA452).

12.3 Trademarks

SIMPLE SWITCHER is a registered trademark of Texas Instruments Incorporated.

All other trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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MECHANICAL DATA

YZR0025xxx

0.600±0.075

D

E

TLA25XXX (Rev D)

D: Max = 2.521 mm, Min = 2.46 mm

E: Max = 2.521 mm, Min = 2.46 mm

4215055/A

12/12

A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.

B. This drawing is subject to change without notice.

NOTES:

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型号：	LP8731-Q1
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