LP8758-B0 [TI]
四相、单路 16A 输出直流/直流降压转换器;
| 型号： | LP8758-B0 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 四相、单路 16A 输出直流/直流降压转换器 转换器 |
| 文件： | 总55页 (文件大小：1911K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LP8758-B0
ZHCSDQ0C –MARCH 2015–REVISED AUGUST 2018
LP8758-B0 四相直流/直流降压转换器
1 特性
3 说明
1
•
高效降压四相直流/直流转换器内核：
LP8758 专为满足最新应用处理器的电源管理要求而设
计，这些应用处理器适用于手机和类似便携式 应用。
该器件包含 4 个降压直流/直流转换器内核，它们一起
捆绑在单个四相降压转换器中。该器件通过 I2C 兼容串
行接口进行控制。
–
–
–
–
–
最大输出电流：16A
自动 PWM-PFM 和强制 PWM 操作
自动相位增加/减少和强制多相操作
远程差分反馈电压感测
可编程输出电压转换率范围：0.5mV/µs 至
30mV/µs
自动 PWM-PFM（AUTO 模式）操作搭配自动相位增
加/减少操作，可在较宽输出电流范围内以最大限度提
高效率。LP8758 支持远程差分电压感测，可补偿稳压
器输出与负载点之间的 IR 压降 (IR drop)，从而提高输
出电压的精度。
–
VOUT 范围：0.5V 至 3.36V（支持动态电压调节
(DVS)）
•
•
可通过使能信号编程启动和关断延迟
I2C 兼容接口，支持标准 (100kHz)、快速
(400kHz)、快速+ (1MHz) 和高速 (3.4MHz) 四种模
式
LP8758 支持可编程启动和关断延迟与使能信号同步。
该器件的保护 功能 包括短路保护、电流限制、输入电
源欠压锁定 (UVLO) 以及过热警告和关断功能。该器件
还具有一些错误标志，用于提供自身的状态信息。此
外，LP8758 器件无需添加外部电流感测电阻即可支持
负载电流测量。在器件启动和电压变化期间，器件会对
转换率加以控制，以便最大限度减少输出电压过冲和浪
涌电流。
•
•
•
•
具有可编程屏蔽的中断功能
负载电流测量
输出短路和过载保护
用于降低电磁干扰 (EMI) 的扩展频谱模式和相位交
错
•
•
过热警告和保护
欠压闭锁 (UVLO)
器件信息(1)
2 应用
器件编号
LP8758-B0
封装
封装尺寸（标称值）
•
•
智能手机、电子书和平板电脑
游戏设备
DSBGA (35)
2.88mm x 2.13mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
效率与输出电流 (VIN = 3.7V)
4 简化原理图
95
90
85
80
75
70
65
60
LP8758
VIN
VIN_B0
VIN_B1
VIN_B2
VIN_B3
VANA
SW_B0
SW_B1
SW_B2
SW_B3
VOUT
LOAD
NRST
SDA
SCL
nINT
EN1
EN2
FB_B0
FB_B1
FB_B2
FB_B3
1.2 V
1.0 V
55
50
GNDs
0.001
0.01
0.1
1
10 20
Output Current (A)
D038
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SNVSA06
LP8758-B0
ZHCSDQ0C –MARCH 2015–REVISED AUGUST 2018
www.ti.com.cn
目录
8.4 Device Functional Modes........................................ 24
8.5 Programming........................................................... 25
8.6 Register Maps......................................................... 29
Application and Implementation ........................ 40
9.1 Application Information............................................ 40
9.2 Typical Application .................................................. 40
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
简化原理图............................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5
7.4 Thermal Information.................................................. 6
7.5 Electrical Characteristics........................................... 6
7.6 I2C Serial Bus Timing Parameter.............................. 9
7.7 Switching Characteristics........................................ 11
7.8 Typical Characteristics............................................ 12
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 14
8.3 Feature Description................................................. 14
9
10 Power Supply Recommendations ..................... 47
11 Layout................................................................... 48
11.1 Layout Guidelines ................................................. 48
11.2 Layout Example .................................................... 49
12 器件和文档支持 ..................................................... 50
12.1 器件支持................................................................ 50
12.2 文档支持................................................................ 50
12.3 接收文档更新通知 ................................................. 50
12.4 社区资源................................................................ 50
12.5 商标....................................................................... 50
12.6 静电放电警告......................................................... 50
12.7 术语表 ................................................................... 50
13 机械、封装和可订购信息....................................... 50
8
5 修订历史记录
Changes from Revision B (May 2016) to Revision C
Page
•
•
•
Changed logic low level to 0 V and high level to VANA up to 3.6 V ...................................................................................... 5
Added support for I2C signals up to 3.3V ............................................................................................................................. 5
Changed "700 µs" to "1.2 ms".............................................................................................................................................. 17
Changes from Revision A (May 2015) to Revision B
Changes from Original (March 2015) to Revision A
Page
Page
•
•
第一个 WEB 版本 .................................................................................................................................................................. 1
已添加 添加了“社区资源” 部分 .............................................................................................................................................. 50
2
Copyright © 2015–2018, Texas Instruments Incorporated
LP8758-B0
www.ti.com.cn
ZHCSDQ0C –MARCH 2015–REVISED AUGUST 2018
6 Pin Configuration and Functions
YFF Package
35-Pin DSBGA
VIN
_B2
SW
_B2
PGND
_B23
SW
_B3
VIN
_B3
VIN
_B3
SW
_B3
PGND
_B23
SW
_B2
VIN
_B2
G
F
VIN
_B2
SW
_B2
PGND
_B23
SW
_B3
VIN
_B3
VIN
_B3
SW
_B3
PGND
_B23
SW
_B2
VIN
_B2
FB
_B2
PGND
_B23
FB
_B3
FB
_B3
PGND
_B23
FB
_B2
SCL
SDA
EN1
VANA
AGND
SGND
VANA
AGND
SGND
SCL
SDA
EN1
E
D
C
B
A
NRST
EN2
nINT
nINT
EN2
NRST
FB
_B0
PGND
_B01
FB
_B1
FB
_B1
PGND
_B01
FB
_B0
VIN
_B0
SW
_B0
PGND
_B01
SW
_B1
VIN
_B1
VIN
_B1
SW
_B1
PGND
_B01
SW
_B0
VIN
_B0
VIN
_B0
SW
_B0
PGND
_B01
SW
_B1
VIN
_B1
VIN
_B1
SW
_B1
PGND
_B01
SW
_B0
VIN
_B0
5
4
3
2
1
1
2
3
4
5
Top View (Bump-side down)
Bottom View
Copyright © 2015–2018, Texas Instruments Incorporated
3
LP8758-B0
ZHCSDQ0C –MARCH 2015–REVISED AUGUST 2018
www.ti.com.cn
Pin Functions
PIN
TYPE
DESCRIPTION
NUMBER
NAME
Input for Buck 1. The separate power pins VIN_Bx are not connected together internally - VIN_Bx
pins must be connected together in the application and be locally bypassed.
A1, B1
VIN_B1
P
A2, B2
SW_B1
PGND_B01
SW_B0
A
G
A
Buck 1 switch node.
A3, B3, C3
A4, B4
Power Ground for Buck 0 and Buck 1.
Buck 0 switch node.
Input for Buck 0. The separate power pins VIN_Bx are not connected together internally - VIN_Bx
pins must be connected together in the application and be locally bypassed.
A5, B5
VIN_B0
P
C1
C2
C4
SGND
FB_B1
FB_B0
G
A
A
Substrate Ground.
Output ground feedback (negative) for Buck 0.
Output voltage feedback (positive) for Buck 0.
Programmable Enable signal for Buck regulator. Can be also configured to switch between two
output voltage levels.
C5
EN1
D/I
D1
D2
AGND
nINT
G
Ground.
D/O
Open-drain interrupt output. Active LOW.
Programmable Enable signal for Buck regulator. Can be also configured to switch between two
output voltage levels.
D3
EN2
D/I
D4
D5
NRST
SDA
D/I
Reset signal for the device.
D/I/O Serial interface data input and output for system access. Connect a pull-up resistor.
Supply voltage for Analog and Digital blocks. VANA pin must be connected to same voltage as
VIN_Bx pins.
E1
VANA
P
E2
E4
E5
FB_B3
FB_B2
SCL
A
A
Output voltage feedback (positive) for Buck 3 - Connect to ground in 4-phase configuration.
Output voltage feedback (positive) for Buck 2. - Connect to ground in 4-phase configuration.
Serial interface clock input for system access. Connect a pull-up resistor.
D/I
Input for Buck 3. The separate power pins VIN_Bx are not connected together internally - VIN_Bx
pins must be connected together in the application and be locally bypassed.
F1, G1
VIN_B3
P
F2, G2
SW_B3
PGND_B23
SW_B2
A
G
A
Buck 3 switch node.
E3, F3, G3
F4, G4
Power Ground for Buck 2 and Buck 3.
Buck 2 switch node.
Input for Buck 2. The separate power pins VIN_Bx are not connected together internally - VIN_Bx
pins must be connected together in the application and be locally bypassed.
F5, G5
VIN_B2
P
A: Analog Pin, D: Digital Pin, G: Ground Pin, P: Power Pin, I: Input Pin, O: Output Pin
4
Copyright © 2015–2018, Texas Instruments Incorporated
LP8758-B0
www.ti.com.cn
ZHCSDQ0C –MARCH 2015–REVISED AUGUST 2018
7 Specifications
7.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN
MAX
UNIT
INPUT VOLTAGE
VIN_Bx, VANA
SW_Bx
Voltage on power connections
Voltage on buck switch nodes
–0.3
–0.3
6
V
V
(VIN_Bx + 0.3 ) with 6 V
max
–0.3
(VANA + 0.3 ) with
6 V max
V
V
FB_Bx
NRST
Voltage on buck voltage sense nodes
Voltage on NRST input
–0.3
–0.3
3.6
3.6
ENx, SDA, SCL, nINT Voltage on logic pins (input or output pins)
CURRENT
VIN_Bx, SW_Bx,
PGND_Bx
Current on power pins (average current over 100k hour
lifetime, TJ = 125°C)
0.62
A/pin
TEMPERATURE
Junction temperature, TJ-MAX
−40
150
150
260
°C
°C
°C
Storage temperature, Tstg
Maximum lead temperature (soldering, 10 sec.)(3)
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground.
(3) For detailed soldering specifications and information, refer to AN-1112 DSBGA Wafer Level Chip Scale Package (SNVA009).
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
INPUT VOLTAGE
VIN_Bx, VANA
NRST
Voltage on power connections
Voltage on NRST
2.5
0
5.5
V
V
VANA up to
3.6
ENx, nINT
Voltage on logic pins (input or output pins)
0
VANA up to
3.6
V
V
V
Voltage on I2C interface, standard (100 kHz), fast (400
khz),
fast+ (1 MHz), and high-speed (3.4 MHz) modes
Voltage on I2C interface, standard (100 kHz), fast (400
kHz), and fast+ (1 MHz) modes
0
0
1.95
SCL, SDA
VANA up to
3.6
TEMPERATURE
Junction temperature, TJ
Ambient temperature, TA
−40
−40
125
85
°C
°C
Copyright © 2015–2018, Texas Instruments Incorporated
5
LP8758-B0
ZHCSDQ0C –MARCH 2015–REVISED AUGUST 2018
www.ti.com.cn
7.4 Thermal Information
LP8758
THERMAL METRIC(1)
YFF (DSBGA)
UNIT
35 PINS
56.1
0.2
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJCtop
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
8.5
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.9
ψJB
8.4
RθJCbot
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics
Limits apply over the junction temperature range –40°C ≤ TJ ≤ +125°C, specified V(VANA), VIN , V(NRST), VOUT and IOUT range,
unless otherwise noted. Typical values are at TJ = 25°C, ƒSW = 3 MHz, V(VANA) = VIN = 3.7 V and VOUT = 1 V unless otherwise
noted.(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
EXTERNAL COMPONENTS
CIN
Input filtering capacitance
Connected from VIN_Bx to PGND_Bx
Capacitance per phase
1.9
10
10
22
µF
µF
Output filtering capacitance,
local
COUT
Output capacitance, total
(local and remote)
Total output capacitance, 4-phase
configuration
COUT-TOTAL
ESRC
40
200
10
µF
Input and output capacitor
ESR
[1-10] MHz
2
mΩ
0.33 or 0.47
µH
L
Inductor
Inductance of the inductor
TOKO, DFE252010F-R33M
–30%
30%
DCRL
Inductor DCR
16
mΩ
BUCK REGULATOR
Voltage between VIN_Bx and ground
pins. VANA must be connected to the
same supply as VIN_Bx.
VIN
Input voltage range
2.5
0.5
3.7
5.5
V
V
Programmable voltage range
1
10
5
3.36
Step size, 0.5 V ≤ VOUT < 0.73 V
Step size, 0.73 V ≤ VOUT < 1.4 V
Step size, 1.4 V ≤ VOUT ≤ 3.36 V
Output current, 4-phase configuration
VOUT
Output voltage
mV
20
12(3)
16(3)
IOUT
Output current
A
V
Output current, 4-phase configuration,
VIN > 3 V, VOUT < 2 V
Dropout voltage
VIN – VOUT
0.7
Forced PWM mode, 0.8 V ≤ VOUT ≤ 1.2
V, 2.5 V ≤ VIN ≤ 4.5 V, TJ = 25°C, 0 ≤
-1%
1.5%
DC output voltage accuracy,
includes voltage reference,
DC load and line regulations,
process and temperature
IOUT ≤ IOUT(max)
max ( 2%,
15 mV) 20
mV
PFM mode, the average output voltage
level is increased by max. 20 mV
min (–2%,
–15 mV)
(1) All voltage values are with respect to network ground.
(2) Minimum (MIN) and maximum (MAX) limits are specified by design, test, or statistical analysis. Typical (TYP) numbers are not verified,
but do represent the most likely norm.
(3) The maximum output current is also limited by the junction temperature and maximum average current over lifetime. The power
dissipation inside the die increases the junction temperature and limits the maximum current depending of the length of the current
pulse, efficiency, board and ambient temperature. The maximum average current/pin over lifetime is described in Absolute Maximum
Ratings.
6
Copyright © 2015–2018, Texas Instruments Incorporated
LP8758-B0
www.ti.com.cn
ZHCSDQ0C –MARCH 2015–REVISED AUGUST 2018
Electrical Characteristics (continued)
Limits apply over the junction temperature range –40°C ≤ TJ ≤ +125°C, specified V(VANA), VIN , V(NRST), VOUT and IOUT range,
unless otherwise noted. Typical values are at TJ = 25°C, ƒSW = 3 MHz, V(VANA) = VIN = 3.7 V and VOUT = 1 V unless otherwise
noted.(1)(2)
PARAMETER
TEST CONDITIONS
PWM mode, L = 0.33 µH
MIN
TYP
10
MAX
UNIT
mVp-p
%/V
Ripple, 4-phase
configuration
PFM mode, L = 0.33 µH
IOUT = IOUT(max)
10
DCLNR
DCLDR
DC line regulation
±0.05
DC load regulation in PWM
mode
IOUT from 0 to IOUT(max)
0.3%
-45
IOUT = 1 A to 8 A, TR = 400 ns, PWM
mode, COUT = 100 µF, L = 0.33 µH
mV
mV
2.5 V ≤ VIN ≤ 4.5 V, 0.8 V ≤ VOUT ≤ 1.2
Undershoot for transient load V, IOUT = 0.1 A to 4.1 A, TR = 100 ns,
–35
step response, 4-phase
configuration
AUTO mode, COUT = 100 µF, L = 0.33
µH
3 V ≤ VIN ≤ 4.5 V, 0.8 V ≤ VOUT ≤ 1.2 V,
IOUT from 1 A to 12 A, TR = 1000 ns,
COUT = 100 µF, L = 0.33 µH
–45
45
mV
mV
TLDSR
IOUT = 8 A to 1 A, TF = 400 ns, PWM
mode, COUT = 100 µF, L = 0.33 µH
2.5 V ≤ VIN ≤ 4.5 V, 0.8 V ≤ VOUT ≤ 1.2
Overshoot for transient load V, IOUT = 4.1 A to 0.1 A, TF = 100 ns,
25
mV
mV
step response, 4-phase
configuration
AUTO mode, COUT = 100 µF, L = 0.33
µH
3 V ≤ VIN ≤ 4.5 V, 0.8 V ≤ VOUT ≤ 1.2 V,
IOUT from 12 A to 1 A, TF = 1000 ns,
COUT = 100 µF, L = 0.33 µH
50
VIN stepping 2.5 V ↔ 3 V, TR = TF = 10
µs, IOUT = IOUT(max)
TLNSR
Transient line response
±20
mV
A
Programmable range
1.5
5
Step size
0.5
7.5%
7.5%
2
Forward current limit (peak
for every switching cycle)
ILIM FWD
Accuracy, 3 V ≤ VIN ≤ 5.5 V, ILIM = 5 A
Accuracy, 2.5 V ≤ VIN < 3 V, ILIM = 5 A
–5%
–20%
1.6
20%
20%
2.4
ILIM NEG
RDS(ON) HS
Negative current limit
A
On-resistance, high-side
FET
Each phase, between VIN_Bx and
SW_Bx pins (I = 1 A)
40
33
90
50
mΩ
FET
RDS(ON) LS
FET
Each phase, between SW_Bx and
PGND_Bx pins (I = 1 A)
On-resistance, low-side FET
mΩ
Current mismatch between phases, IOUT
Current balancing
> 1000 mA / phase, 0.8 V ≤ VOUT ≤ 1.2
V
10%
50
Overshoot during start-up
VOUT = 1 V, Slew rate = 10 mV/µs
mV
mA
PFM-to-PWM transition -
current threshold(4)
IPFM-PWM
IPWM-PFM
600
240
PWM-to-PFM transition -
current threshold(4)
mA
mA
From 1-phase to 2-phase
From 2-phase to 3-phase
From 3-phase to 4-phase
From 2-phase to 1-phase
From 3-phase to 2-phase
From 4-phase to 3-phase
Regulator disabled
1000
2000
3000
750
IADD
Phase-adding level
ISHED
Phase-shedding level
1500
2300
250
mA
Output pulldown resistance
150
350
Ω
(4) The final PFM-to-PWM and PWM-to-PFM transition current varies slightly and is dependant on the output voltage, input voltage, and the
magnitude of inductor's ripple current.
Copyright © 2015–2018, Texas Instruments Incorporated
7
LP8758-B0
ZHCSDQ0C –MARCH 2015–REVISED AUGUST 2018
www.ti.com.cn
Electrical Characteristics (continued)
Limits apply over the junction temperature range –40°C ≤ TJ ≤ +125°C, specified V(VANA), VIN , V(NRST), VOUT and IOUT range,
unless otherwise noted. Typical values are at TJ = 25°C, ƒSW = 3 MHz, V(VANA) = VIN = 3.7 V and VOUT = 1 V unless otherwise
noted.(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Powergood threshold for
interrupt
Rising ramp voltage, enable or voltage
change
–23
–17
–10
BUCKx_INT(BUCKx_SC_IN
T), difference from final
voltage
mV
Falling ramp, voltage change
10
17
23
Powergood threshold for
status signal
BUCKx_STAT(BUCKx_PG_ to '0' during voltage change
STAT)
During operation, status signal is forced
–23
–17
–10
mV
PROTECTION FEATURES
Temperature rising,
CONFIG(TDIE_WARN_LEVEL) = 0
125
105
Thermal warning
Temperature rising,
CONFIG(TDIE_WARN_LEVEL) = 1
°C
°C
Hysteresis
15
150
15
Temperature rising
Hysteresis
Thermal shutdown
Voltage falling
Hysteresis
2.3
2.4
50
2.5
V
VANAUVLO
VANA undervoltage lockout
mV
LOAD CURRENT MEASUREMENT
Current measurement range Maximum code
20.46
20
A
Resolution
Measurement accuracy
LSB
OUT ≥ 2 A
mA
I
<10%
CURRENT CONSUMPTION
Shutdown current
consumption
V(NRST) = 0 V
1
6
µA
µA
Standby current
consumption, regulator
disabled
V(NRST) = 1.8 V
Active current consumption
during PFM operation
V(NRST) = 1.8 V, IOUT = 0 mA, not
switching
71
18
µA
Active current consumption
during PWM operation
V(NRST) = 1.8 V, IOUT = 0 mA
mA
8
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Electrical Characteristics (continued)
Limits apply over the junction temperature range –40°C ≤ TJ ≤ +125°C, specified V(VANA), VIN , V(NRST), VOUT and IOUT range,
unless otherwise noted. Typical values are at TJ = 25°C, ƒSW = 3 MHz, V(VANA) = VIN = 3.7 V and VOUT = 1 V unless otherwise
noted.(1)(2)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUT SIGNALS NRST, ENx, SCL, SDA
VIL
VIH
Input low level
Input high level
0.4
V
V
1.2
10
Hysteresis of Schmitt trigger
inputs (SCL, SDA)
VHYS
80
160
mV
ENx pulldown resistance
NRST pulldown resistance
ENx_PD = 1
500
kΩ
kΩ
Always present
800
1200
1700
0.4
DIGITAL OUTPUT SIGNALS nINT, SDA
VOL
Output low level
ISOURCE = 2 mA
To VIO Supply
V
External pullup resistor for
nINT
RP
10
kΩ
ALL DIGITAL INPUTS
ILEAK Input current
All logic inputs over pin voltage range
−1
1
µA
7.6 I2C Serial Bus Timing Parameter
See(1) and Figure 1.
MIN
MAX
UNIT
Standard mode
Fast mode
100
400
1
kHz
kHz
ƒSCL
Serial clock frequency
Fast mode +
MHz
MHz
MHz
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
Standard mode
3.4
1.7
4.7
1.3
0.5
160
320
4
Fast mode
µs
ns
µs
ns
tLOW
SCL low time
Fast mode +
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
Standard mode
Fast mode
0.6
0.26
60
120
250
100
50
10
0
tHIGH
SCL high time
Data setup time
Data hold time
Fast mode +
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
Standard mode
Fast mode
tSU;DAT
ns
Fast mode +
High-speed mode
Standard mode
3.45
0.9
Fast mode
0
µs
ns
tHD;DAT
Fast mode +
0
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
0
70
0
150
(1) Cb refers to the capacitance of one bus line. Cb is expressed in pF units.
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I2C Serial Bus Timing Parameter (continued)
See(1) and Figure 1.
MIN
4.7
0.6
0.26
160
4
MAX
UNIT
µs
Standard mode
Setup time for a start or
Fast mode
tSU;STA
a repeated start
condition
Fast mode +
High-speed mode
Standard mode
Fast mode
ns
0.6
0.26
160
4.7
1.3
0.5
4
µs
Hold time for a start or a
repeated start condition
tHD;STA
Fast mode +
High-speed mode
Standard mode
Fast mode
ns
Bus free time between a
stop and start condition
tBUF
µs
Fast mode +
Standard mode
Fast mode
0.6
0.26
160
µs
ns
Setup time for a stop
condition
tSU;STO
Fast mode +
High-speed mode
Standard mode
Fast mode
1000
300
120
80
trDA
tfDA
trCL
trCL1
tfCL
Rise time of SDA signal Fast mode +
High-speed mode, Cb = 100 pF
ns
ns
ns
ns
ns
High-speed mode, Cb = 400 pF
Standard mode
160
250
250
120
80
Fast mode
Fall time of SDA signal
Fast mode +
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
Standard mode
160
1000
300
120
40
Fast mode
Rise time of SCL signal Fast mode +
High-speed Mode, Cb = 100 pF
High-speed Mode, Cb = 400 pF
Standard mode
80
1000
300
120
80
Rise time of SCL signal
after a repeated start
condition and after an
acknowledge bit
Fast mode
Fast mode +
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
Standard mode
160
300
300
120
40
Fast mode
Fall time of a SCL signal Fast mode +
High-speed mode, Cb = 100 pF
High-speed mode, Cb = 400 pF
80
Capacitive load for each
bus line (SCL and SDA)
Cb
400
50
pF
ns
Pulse width of spike
suppressed in SCL and
SDA lines (spikes that
are less than the
indicated width are
suppressed)
Fast mode, fast mode +
High-speed mode
tSP
10
10
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7.7 Switching Characteristics
Limits apply over the junction temperature range –40°C ≤ TJ ≤ 125°C, specified V(VANA), VIN , V(NRST), VOUT and IOUT range,
unless otherwise noted. Typical values are at TJ = 25°C, ƒSW = 3 MHz, V(VANA) = VIN = 3.7 V and VOUT = 1 V unless otherwise
noted.(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Switching frequency, PWM
mode
MHz
ƒSW
2.7
3
3.3
Maximum switching
VOUT ≥ 0.6 V
2.7
3
3.3
frequency, PWM mode
Automatically limited to
smaller of ƒSW and ƒSW-MAX
ƒSW-MAX
MHz
µs
VOUT < 0.6 V
1.8
2
2.2
From ENx to VOUT = 0.225 V (slew-rate
control begins), COUT_TOTAL = 88 µF, no
load
Regulator start-up time (soft
start)
90
SLEW_RATEx[2:0] = 000, VOUT ≥ 0.5 V
SLEW_RATEx[2:0] = 001, VOUT ≥ 0.5 V
SLEW_RATEx[2:0] = 010, VOUT ≥ 0.5 V
SLEW_RATEx[2:0] = 011, VOUT ≥ 0.5 V
SLEW_RATEx[2:0] = 100, VOUT ≥ 0.5 V
SLEW_RATEx[2:0] = 101, VOUT ≥ 0.5 V
SLEW_RATEx[2:0] = 110, VOUT ≥ 0.5 V
SLEW_RATEx[2:0] = 111, VOUT ≥ 0.5 V
–15%
–15%
–15%
–15%
–15%
–15%
–15%
–15%
30
15
15%
15%
15%
15%
15%
15%
15%
15%
10
7.5
3.8
1.9
0.94
0.4
Output voltage slew-rate(2)
mV/µs
PFM mode (automatically changing to
PWM mode for the measurement)
50
4
Load current measurement
time
µs
PWM mode
(1) Minimum (MIN) and maximum (MAX) limits are specified by design, test, or statistical analysis. Typical (TYP) numbers are not verified,
but do represent the most likely norm.
(2) The slew-rate can be limited by the current limit (forward or negative current limit), output capacitance and load current.
tBUF
SDA
tHD;STA
trCL
tfDA
trDA
tSP
tLOW
tfCL
SCL
tHD;STA
tSU;STA
tSU;STO
tHIGH
tHD;DAT
S
tSU;DAT
S
RS
P
START
REPEATED
START
STOP
START
Figure 1. I2C Timing
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7.8 Typical Characteristics
Unless otherwise specified: TA = 25°C, VIN = 3.7 V, ƒSW = 3 MHz.
2
1.8
1.6
1.4
1.2
1
8
7.6
7.2
6.8
6.4
6
0.8
0.6
0.4
0.2
0
5.6
5.2
4.8
4.4
4
2.5
3
3.5
4
4.5
5
5.5
2.5
3
3.5
4
4.5
5
5.5
Input Voltage (V)
Input Voltage (V)
D011
D010
V(NRST) = 0 V
V(NRST) = 1.8 V
Regulator disabled
Figure 2. Shutdown Current Consumption vs Input Voltage
Figure 3. Standby Current Consumption vs Input Voltage
80
25
78
76
74
72
70
68
66
64
62
60
24
23
22
21
20
19
18
17
16
15
2.5
3
3.5
4
4.5
5
5.5
2.5
3
3.5
4
4.5
5
5.5
Input Voltage (V)
Input Voltage (V)
D012
D039
V(NRST) = 1.8 V
Load = 0 mA
V(EN1) = 1.8 V
L = 330 nH
VOUT = 1 V
V(NRST) = 1.8 V
Load = 0 mA
V(EN1) = 1.8 V
1 phase active
VOUT = 1 V
L = 330 nH
Figure 4. PFM Mode Current Consumption vs Input Voltage
Figure 5. PWM Mode Current Consumption vs Input Voltage
80
78
76
74
72
70
68
66
64
62
60
2.5
3
3.5
4
4.5
5
5.5
Input Voltage (V)
D040
V(NRST) = 1.8 V
Load = 0 mA
V(EN1) = 1.8 V
VOUT = 1 V
L = 330 nH
4 phases active
Figure 6. Forced Multi-Phase Current Consumption vs Input Voltage
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8 Detailed Description
8.1 Overview
The LP8758 is a high-efficiency, high-performance power supply device with four step-down DC-DC converter
cores. The cores are configured for a single 4-phase configuration. The device delivers 0.5-V to 3.36-V regulated
voltage rail from 2.5-V to 5.5-V battery or supply voltage to portable devices such as cell phones, tablets, and
PDAs.
There are two modes of operation for the converter, depending on the output current required: pulse-width
modulation (PWM) and pulse-frequency modulation (PFM). The converter operates in PWM mode at high load
currents of approximately 400 mA or higher. When operating in PWM mode the phases are automatically
added/shedded based on the load current level. Lighter output current loads will cause the converter to
automatically switch into PFM mode for reduced current consumption and a longer battery life when forced PWM
mode is disabled. The forced multi-phase mode can be enabled for highest transient performance.
Additional features include soft-start, undervoltage lockout, overload protection, thermal warning, and thermal
shutdown.
8.1.1 Buck Information
The LP8758 has four integrated high-efficiency buck converter cores. The cores are designed for flexibility; most
of the functions are programmable, thus giving a possibility to optimize the regulator operation for each
application.
8.1.1.1 Operating Modes
•
•
•
OFF: Output is isolated from the input voltage rail in this mode. Output has an optional pulldown resistor.
PWM: Converter operates in buck configuration with fixed switching frequency.
PFM: Converter switches only when output voltage decreases below programmed threshold. Inductor current
is discontinuous.
8.1.1.2 Features
•
•
•
•
•
•
Output voltage
Forced PWM operation
Forced multi-phase operation (forces also the PWM operation)
Switch current limit
Output voltage slew rate
Enable and disable delays
8.1.1.3 Programmability
The following parameters can be programmed via registers:
•
•
•
•
•
•
•
•
•
•
•
•
DVS support with programmable slew-rate
Automatic mode control based on the loading
Synchronous rectification
Current mode loop with PI compensator
Optional spread spectrum technique to reduce EMI
Soft start
Power good flag with maskable interrupt
Phase control for optimized EMI
Average output current sensing (for PFM entry, phase shedding/adding, and load current measurement)
Current balancing between the phases of the converter
Differential voltage sensing from point of the load
Dynamic phase shedding/adding, each output being phase shifted
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8.2 Functional Block Diagram
VANA
Buck0
ILIM Det
nINT
Interrupts
Pwrgood Det
Overload and
SC Det
Enable,
Roof/Floor,
Slew-Rate
Control
Iload ADC
EN1
EN2
Buck1
ILIM Det
Pwrgood Det
SDA
SCL
I2C
Overload and
SC Det
Iload ADC
OTP
EPROM
Registers
Buck2
ILIM Det
Pwrgood Det
Digital
Logic
Overload and
SC Det
UVLO
Iload ADC
Oscillator
NRST
Buck3
ILIM Det
Pwrgood Det
Ref &
Bias
Thermal
Monitor
SW
Reset
Overload and
SC Det
Iload ADC
8.3 Feature Description
8.3.1 Multi-Phase DC-DC Converters
8.3.1.1 Overview
A multi-phase synchronous buck converter offers several advantages over a single power stage converter. For
application processor power delivery, lower ripple on the input and output currents and faster transient response
to load steps are the most significant advantages. Also, since the load current is evenly shared among multiple
channels, the heat generated is greatly reduced for each channel due to the fact that power loss is proportional
to square of current. Physical size of the output inductor shrinks significantly due to this heat reduction. A block
diagram of a single core is shown in Figure 7.
Interleaving switching action of the converters and channels in a four-phase configuration is illustrated in
Figure 8.
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Feature Description (continued)
PMOS
Current
Sense
Differential to Single-
Ended
FBP
FBN
+
-
VIN
POS
Current
Limit
œ
Slave
Phase
Control
Ramp
Generator
VOUT
œ
Gate
Error
Control
Amp
SW
+
Loop
Comp
Voltage
Setting
Slew Rate
Control
NEG
Current
Limit
Power
Good
+
-
VDAC
Zero
Cross
Detect
NMOS
Current
Sense
Programmable
Parameters
Master
Interface
Control
Block
Slave
Interface
IADC
GND
Copyright © 2017, Texas Instruments Incorporated
Figure 7. Detailed Block Diagram Showing One Core
IL_TOT_4PH
IL0
IL1
IL2
IL3
0
90
180
270
360
450
540
630
720
PWM0
PWM1
PWM2
PWM3
Switching Cycle 360º
0
90
180
270
360
450
540
630
720
Phase (Degrees)
(1)
Figure 8. PWM Timings and Inductor Current Waveforms in 4-phase Configuration
(1) Graph is not in scale and is for illustrative purposes only.
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Feature Description (continued)
8.3.1.2 Multi-Phase Operation and Phase Adding/Shedding
Under heavy load conditions, the 4-phase converter switches each channel 90° apart. As a result, the 4-phase
converter has an effective ripple frequency four times greater than the switching frequency of any one phase.
However, the parallel operation decreases the efficiency at light load conditions. In order to overcome this
operational inefficiency, the LP8758 can change the number of active phases to optimize efficiency for the
variations of the load. This is called phase adding/shedding. The concept is illustrated below in Figure 9.
The converter can be forced to multi-phase operation by the BUCK0_CTRL1.BUCK0_FPWM_MP bit. If the
regulator operates in forced multi-phase mode the forced PWM operation is automatically used. If the multi-
phase operation is not forced, the number of phases are added and shedded automatically to follow the required
output current.
Best efficiency obtained with
N=1
N=2
N=3
N=4
Load Current
Figure 9. Multi-Phase Buck Converter Efficiency vs Number of Phases -
(2)
All Converters in PWM Mode
8.3.1.3 Transition Between PWM and PFM Modes
Normal PWM mode operation with phase-adding or phase-shedding optimizes efficiency at mid-to-full load at the
expense of light-load efficiency. The LP8758 converter operates in PWM mode at load current of about 400 mA
or higher. At lighter load current levels the device automatically switches into PFM mode for reduced current
consumption when Forced PWM mode is disabled (AUTO mode operation). By combining the PFM and the
PWM modes a high efficiency is achieved over a wide output-load current range.
8.3.1.4 Multi-Phase Switcher Configurations
In the multi-phase configuration the control of the multi-phase regulator settings is done using the control
registers of the master buck. The following slave registers are ignored:
•
•
•
BUCKx_CTRL1
BUCKx_CTRL2, except ILIMx[2:0] bits
interrupt bits related to the slave buck, except BUCKx_ILIM_INT
(2) Graph is not in scale and is for illustrative purposes only.
16
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Feature Description (continued)
8.3.1.5 Buck Converter Load Current Measurement
Buck load current can be monitored via I2C registers. The monitored buck converter is selected with the
SEL_I_LOAD.LOAD_CURRENT_BUCK_SELECT[1:0] register bits. A write to this selection register starts a
current measurement sequence. The measurement sequence is typically 50 µs long. The LP8758 device can be
configured to give out an interrupt INT_TOP.I_LOAD_READY after the load current measurement sequence is
finished. Load current measurement interrupt can be masked with TOP_MASK.I_LOAD_READY_MASK bit. The
measurement result can be read from registers I_LOAD_1 and I_LOAD_2. Register I_LOAD_1 bits
BUCK_LOAD_CURRENT[7:0] give out the LSB bits and register I_LOAD_2 bits BUCK_LOAD_CURRENT[9:8]
the MSB bits. The measurement result BUCK_LOAD_CURRENT[9:0] LSB is 20 mA, and maximum value of the
measurement is 20.46 A. The measured current is the total value of the master and slave phases.
8.3.1.6 Spread-Spectrum Mode
Systems with periodic switching signals may generate a large amount of switching noise in a set of narrowband
frequencies (the switching frequency and its harmonics). The usual solution to reduce noise coupling is to add
EMI-filters and shields to the boards. The LP8758's register selectable spread-spectrum mode minimizes the
need for output filters, ferrite beads, or chokes. In spread spectrum mode, the switching frequency varies
randomly by ±5% (depending on selected switching frequency) about the center frequency, reducing the EMI
emissions radiated by the converter and associated passive components and PCB traces (see Figure 10). This
feature is enabled with the CONFIG.EN_SPREAD_SPEC bit, and it affects all the buck cores.
Frequency
Where a fixed frequency converter exhibits large amounts of spectral energy at the switching frequency, the spread
spectrum architecture of the LP8758 spreads that energy over a large bandwidth.
Figure 10. Spread-Spectrum Modulation
8.3.2 Power-Up
The power-up sequence for the LP8758 is as follows:
•
•
VANA (and VIN_Bx) reach min recommended levels (V(VANA) > VANAUVLO).
NRST is set to high level. This initiates power-on-reset (POR), OTP reading and enables the system I/O
interface. The I2C host allows at least 1.2 ms before writing or reading data to the LP8758.
•
•
•
Device enters STANDBY mode.
The host can change the default register setting by I2C if needed.
The regulator can be enabled/disabled by ENx pin(s) and by I2C interface.
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Feature Description (continued)
8.3.3 Regulator Control
8.3.3.1 Enabling and Disabling Regulator
The regulator can be enabled when the device is in STANDBY state. There are two ways for enable and disable
the regulator:
•
•
Using BUCK0_CTRL1.EN_BUCK0 register bit (BUCK0_CTRL1.EN_PIN_CTRL0 register bit is '0').
Using EN1/2 control pins (BUCK0_CTRL1.EN_BUCK0 register bit is
BUCK0_CTRL1.EN_PIN_CTRL0 register bit is '1').
'1'
AND
If the EN1/2 control pins are used for enable and disable then the delay from the control signal rising edge to
startup is set by BUCK0_DELAY.BUCK0_STARTUP_DELAY[3:0] bits and the delay from control signal falling
edge to shutdown is set by BUCK0_DELAY.BUCK0_SHUTDOWN_DELAY[3:0] bits. The delays are valid only for
EN1/2 signal and not for control with BUCK0_CTRL1.EN_BUCK0 bit. The delay time implemented by EN1/2 has
overall +/-10% timing accuracy.
The control of the regulator (with 0 ms delays) is shown in Table 1. The multi-phase regulator is controlled with
registers of the master phase.
Table 1. Regulator Control
CONTROL
METHOD
BUCK0_CTRL1
EN_PIN_CTRL0
BUCK0_CTRL1
EN_PIN_SELECT0
BUCK0_CTRL1
EN_ROOF_FLOOR0
BUCK0
OUTPUT VOLTAGE
ROW
EN_BUCKx0
EN1 PIN
EN2 PIN
Enable/disable
control with
EN_BUCK0 bit
1
2
0
1
Don't Care
0
Don't Care
Don't Care
Don't Care
Don't Care
Don't Care
Don't Care
Don't Care Disabled
Don't Care BUCK0_VOUT.BUCK0_VSET[7:0]
Enable/disable
control with EN1
pin
3
4
1
1
1
1
0
0
0
0
Low
Don't Care Disabled
High
Don't Care BUCK0_VOUT.BUCK0_VSET[7:0]
Enable/disable
control with EN2
pin
5
6
1
1
1
1
1
1
0
0
Don't Care
Don't Care
Low
Disabled
High
BUCK0_VOUT.BUCK0_VSET[7:0]
Roof/floor
control with EN1
pin
7
1
1
0
1
Low
Don't Care BUCK0_FLOOR_VOUT.BUCK0_F
LOOR_VSET[7:0]
8
9
1
1
1
1
0
1
1
1
High
Don't Care BUCK0_VOUT.BUCK0_VSET[7:0]
Roof/floor
control with EN2
pin
Don't Care
Low
BUCK0_FLOOR_VOUT.BUCK0_F
LOOR_VSET[7:0]
10
1
1
1
1
Don't Care
High
BUCK0_VOUT.BUCK0_VSET[7:0]
The following configuration allows the enable/disable control using ENx pin:
•
•
•
•
•
BUCK0_CTRL1.EN_BUCK0 = 1
BUCK0_CTRL1.EN_PIN_CTRL0 = 1
BUCK0_CTRL1.EN_ROOF_FLOOR0 = 0
BUCK0_VOUT.BUCK0_VSET[7:0] = Required voltage when ENx is high
The enable pin for control is selected with BUCK0_CTRL1.EN_PIN_SELECT0
When the ENx pin is low, Table 1 row 3 (or 5) is valid, and the regulator is disabled. By setting ENx pin high,
Table 1 row 4 (or 6) is valid, and the regulator is enabled with required voltage.
If the regulator is enabled all the time, and the ENx pin controls selection between two voltage level, the following
configuration is used:
•
•
•
•
•
BUCK0_CTRL1.EN_BUCK0 = 1
BUCK0_CTRL1.EN_PIN_CTRL0 = 1
BUCK0_CTRL1.EN_ROOF_FLOOR0 = 1
BUCK0_VOUT.BUCK0_VSET[7:0] = Required voltage when ENx is high
The enable pin for control is selected with BUCK0_CTRL1.EN_PIN_SELECT0
When the ENx pin is low, Table 1 row 7(or 9) is valid, and the regulator is enabled with a voltage defined by
BUCK0_FLOOR_VOUT.BUCK0_FLOOR_VSET[7:0] bits. Setting the ENx pin high, Table 1 row 8 (or 10) is valid,
and the regulator is enabled with a voltage defined by BUCK0_VOUT.BUCK0_VSET[7:0] bits.
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If the regulator is controlled by I2C writings, the BUCK0_CTRL1.EN_PIN_CTRL0 bit is set to 0. The
enable/disable is controlled by the BUCK0_CTRL1.EN_BUCK0 bit, and when the regulator is enabled, the output
voltage is defined by the BUCK0_VOUT.BUCK0_VSET[7:0] bits. The Table 1 rows 1 and 2 are valid for I2C
controlled operation (ENx pins are ignored).
The regulator is enabled by the ENx pin or by I2C writing as shown in Figure 11. The soft-start circuit limits the in-
rush current during start-up. Output voltage increase rate is around 30 mV/μsec during soft-start. When the
output voltage rises to approximately 0.3 V, the output voltage becomes slew-rate controlled. If there is a short
circuit at the output, and the output voltage does not increase above a 0.35-V level in 1 ms, the regulator is
disabled, and interrupt is set. When the output voltage reaches the powergood threshold level the
INT_BUCK_0_1.BUCK0_PG_INT interrupt flag is set. The powergood interrupt flag can be masked using
BUCK_0_1_MASK.BUCK0_PG_MASK bit.
The ENx input pins have integrated pull-down resistors. The pull-down resistors are enabled by default and host
can disable those with CONFIG.ENx_PD bits.
Voltage decrease because of load
No new Powergood interrupt
Voltage
BUCK0_VSET[7:0]
Powergood
Ramp
BUCK0_CTRL2.SLEW_RATE0[2:0]
0.6V
0.35V
Time
Resistive pull-down
(if enabled)
Soft start
Enable
BUCK_0_1_STAT.BUCK0_STAT
BUCK_0_1_STAT.BUCK0_PG_STAT
INT_BUCK_0_1.BUCK0_PG_INT
nINT
0
0
0
1
0
0
1
1
0
1
0
Powergood
interrupt
Host clears
interrupt
Figure 11. Regulator Enable and Disable
8.3.3.2 Changing Output Voltage
The regulator's output voltage can be changed by the ENx pin (voltage levels defined by the BUCK0_VOUT and
BUCK0_FLOOR_VOUT registers) or by writing to the BUCK0_VOUT and BUCK0_FLOOR_VOUT registers. The
voltage change is always slew-rate controlled, and the slew-rate is defined by the
BUCKx_CTRL2.SLEW_RATE[2:0] bits. During voltage change the Forced PWM mode is used automatically. If
the multi-phase operation is forced by the BUCK0_CTRL1. BUCK0_FPWM_MP bit, the regulator operates in
multi-phase mode (four phases active). If the multi-phase operation is not forced, the number of phases are
added and shedded automatically to follow the required slew rate. When the programmed output voltage is
achieved, the mode becomes the one defined by load current, and the BUCK0_CTRL1.BUCK0_FPWM and
BUCK0_CTRL1.BUCK0_FPWM_MP bits.
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Voltage
BUCK0_VSET
Powergood
Ramp
Powergood
BUCK0_CTRL2.SLEW_RATE0[2:0]
BUCK0_FLOOR_VSET
Time
ENx
BUCK_0_1_STAT.BUCK0_STAT
BUCK_0_1_STAT.BUCK0_PG_STAT
INT_BUCK_0_1.BUCK0_PG_INT
nINT
1
1
0
0
1
1
0
1
1
0
Powergood
interrupt
Host clears
interrupt
Powergood
interrupt
Host clears
interrupt
Figure 12. Regulator Output Voltage Change
8.3.4 Device Reset Scenarios
There are three reset methods implemented on the LP8758:
•
•
•
Software reset with RESET.SW_RESET register bit
Reset from low logic level of NRST signal
Undervoltage lockout (UVLO) reset from VANA supply
An SW reset occurs when RESET.SW_RESET bit is written '1'. The bit is automatically cleared after writing. This
event disables the regulator immediately, resets all the register bits to the default values and OTP bits are loaded
(see Figure 14). I2C interface is not reset during software reset.
If VANA supply voltage falls below UVLO threshold level or NRST signal is set low, then the regulator is disabled
immediately, and all the register bits are reset to the default values. When the VANA supply voltage is above
UVLO threshold level and NRST signal rises above threshold level an internal power-on reset (POR) occurs.
OTP bits are loaded to the registers, and a start-up is initiated according to the register settings.
8.3.5 Diagnosis and Protection Features
The LP8758 is capable of providing three levels of protection features:
•
•
•
Warnings for diagnosis which sets interrupt;
Protection events which are disabling the regulator; and
Faults which are causing the device to shutdown.
When the device detects warning/protection condition(s), the LP8758 sets the flag bits indicating what protection
or warning conditions have occurred, and the nINT pin will be pulled low. nINT will be released again after a
clear of flags is complete. The nINT signal stays low until all the pending interrupts are cleared.
When a fault is detected, it is indicated by a INT_TOP.RESET_REG interrupt flag after next start-up.
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EVENT
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Table 2. Summary of Interrupt Signals
RESULT
No effect
INTERRUPT REGISTER
AND BIT
INTERRUPT MASK
STATUS BIT
RECOVERY /
INTERRUPT CLEAR
Current limit
triggered (20 µs
debounce)
INT_TOP.INT_BUCKx = 1
INT_BUCKx.BUCKx_ILIM_I
NT = 1
BUCKx_MASK.BUCKx_ILI BUCKx_STAT.BUCKx_IL Write 1 to
M_MASK
N/A
IM_STAT
INT_BUCKx.BUCKx_ILI
M_INT bit
Interrupt is not cleared if
current limit is active
Short circuit (VOUT
<
Regulator disable
INT_TOP.INT_BUCK0 = 1
INT_BUCK_0_1.BUCK0_SC
_INT = 1
N/A
Write 1 to
0.35 V at 1 ms after
enable) or Overload
(VOUT decreasing
below 0.35V during
operation, 1 ms
debounce)
INT_BUCK_0_1.BUCK0_
SC_INT bit
Thermal Warning
No effect
INT_TOP.TDIE_WARN = 1 TOP_MASK.TDIE_WARN TOP_STAT.TDIE_WARN Write 1 to
_MASK
_STAT
INT_TOP.TDIE_WARN
bit
Interrupt is not cleared if
temperature is above
thermal warning level
Thermal Shutdown
Regulator disabled
INT_TOP.TDIE_SD = 1
N/A
TOP_STAT.TDIE_SD_S Write 1 to
TAT INT_TOP.TDIE_SD bit
Interrupt is not cleared if
temperature is above
thermal shutdown level
Powergood, output
voltage reaches the
programmed value
No effect
No effect
INT_TOP.INT_BUCK0 = 1 BUCK_0_1_MASK.BUCK0 BUCK_0_1_STAT.BUCK Write 1 to
INT_BUCK_0_1.BUCK0_PG
_INT = 1
_PG_MASK
0_PG_STAT
INT_BUCK_0_1.BUCK0_
PG_INT bit
Load current
measurement ready
INT_TOP.I_LOAD_READY TOP_MASK.I_LOAD_REA
= 1 DY_MASK
N/A
Write 1 to
INT_TOP.I_LOAD_REA
DY bit
Start-up (NRST
rising edge)
Device ready for
operation, registers
reset to default values
INT_TOP.RESET_REG = 1 TOP_MASK.RESET_REG
_MASK
N/A
N/A
Write 1 to
INT_TOP.RESET_REG
bit
Glitch on supply
voltage and UVLO
triggered (VANA
falling and rising)
Immediate shutdown
followed by powerup,
registers reset to
default values
INT_TOP.RESET_REG = 1 TOP_MASK.RESET_REG
_MASK
Write 1 to
INT_TOP.RESET_REG
bit
Software requested Immediate shutdown
INT_TOP.RESET_REG = 1 TOP_MASK.RESET_REG
_MASK
N/A
Write 1 to
INT_TOP.RESET_REG
bit
reset
followed by powerup,
registers reset to
default values
8.3.5.1 Warnings for Diagnosis (Interrupt)
8.3.5.1.1 Output Current Limit
The buck regulators have programmable output peak current limits. The limits are individually programmed for all
buck regulators with BUCKx_CTRL2.ILIMx[2:0] bits. The current limit settings of master and slave regulators
used for the same output voltage rail must be identical. If the load current is increased so that the current limit is
triggered, the regulator continues to regulate to the limit current level (current peak regulation). The voltage may
decrease if the load current is higher than limit current. If the current regulation continues for 20 µs, the LP8758
device sets the INT_BUCKx.BUCKx_ILIM_INT bit and pulls the nINT pin low. The host processor can read
BUCKx_STAT.BUCKx_ILIM_STAT bits to see if the regulator is still in peak current regulation mode.
If the load is so high that the output voltage decreases below a 350-mV level, the LP8758 device disables the
regulator and sets the INT_BUCK_0_1.BUCK0_SC_INT bit. In addition the BUCK_0_1_STAT.BUCK0_STAT bit
is set to 0. The interrupt is cleared when the host processor writes 1 to INT_BUCK_0_1.BUCK0_SC_INT bit. The
overload situation is shown in Figure 13.
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Regulator disabled
by digital
New startup if
enable is valid
Voltage
BUCK0_VSET
350mV
Resistive
pull-down
1ms
Time
Time
Current
ILIMx
25ms
0
0
1
1
0
INT_BUCKx.BUCKx_ILIM_INT
INT_BUCK_0_1.BUCK0_SC_INT
BUCK_0_1_STAT.BUCK0_STAT
nINT
1
0
0
1
Host clearing the interrupt by writing to flags
Figure 13. Overload Situation
8.3.5.1.2 Thermal Warning
The LP8758 device includes protection feature against over-temperature by setting an interrupt for host
processor. The threshold level of the thermal warning is selected with CONFIG.TDIE_WARN_LEVEL bit.
If the LP8758 device temperature increases above thermal warning level the device sets INT_TOP.TDIE_WARN
bit and pulls nINT pin low. The status of the thermal warning can be read from TOP_STAT.TDIE_WARN_STAT
bit and the interrupt is cleared by writing 1 to INT_TOP.TDIE_WARN bit.
8.3.5.2 Protection (Regulator Disable)
If the regulator is disabled because of protection or fault (short-circuit protection, overload protection, thermal
shutdown, or undervoltage lockout), the output power FETs are set to high-impedance mode, and the output pull-
down resistor is enabled (if enabled with BUCKx_CTRL1.EN_RDISx bits). The turn-off time of the output voltage
is defined by the output capacitance, load current, and the resistance of the integrated pulldown resistor.
8.3.5.2.1 Short-Circuit and Overload Protection
A short-circuit protection feature allows the LP8758 to protect itself and external components against short circuit
at the output or against overload during start-up. The fault threshold is 350 mV, and the protection is triggered,
and the regulator disabled, if the output voltage is below the threshold level 1 ms after the regulator is enabled.
In a similar way the overload situation is protected during normal operation. If the regulator's feedback-pin
voltage falls below 0.35 V, and remains below the threshold level for 1 ms, the regulator is disabled.
In the short-circuit and overload situations the INT_BUCK_0_1.BUCK0_SC_INT and the INT_TOP.INT_BUCK0
bits are set to 1, the BUCK_0_1_STAT.BUCK0_STAT bit is set to 0 and the nINT signal is pulled low. The host
processor clears the interrupt by writing 1 to the INT_BUCK_0_1.BUCK0_SC_INT bit. Upon clearing the interrupt
the regulator makes a new start-up attempt if the enable register bits and/or ENx control signal is valid.
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8.3.5.2.2 Thermal Shutdown
The LP8758 has an overtemperature protection function that operates to protect itself from short-term misuse
and overload conditions. When the junction temperature exceeds around 150°C, the regulator is disabled, the
INT_TOP.TDIE_SD bit is set to 1, the nINT signal is pulled low, and the device enters STANDBY. nINT will be
cleared by writing 1 to the INT_TOP.TDIE_SD bit. If the temperature is above thermal shutdown level the
interrupt is not cleared. The host can read the status of the thermal shutdown from the
TOP_STAT.TDIE_SD_STAT bit. Regulator cannot be enabled as long as the junction temperature is above
thermal shutdown level or the thermal shutdown interrupt is pending.
8.3.5.3 Fault (Power Down)
8.3.5.3.1 Undervoltage Lockout
When the input voltage falls below VANAUVLO at the VANA pin, the buck converters are disabled immediately,
and the output capacitor is discharged using the pulldown resistor and the LP8758 device enters SHUTDOWN.
When VANA voltage is above UVLO threshold level and NRST signal is high, the device powers up to STANDBY
state.
If the reset interrupt is unmasked by default (TOP_MASK.RESET_REG_MASK = 0) the INT_TOP.RESET_REG
interrupt indicates that the device has been in SHUTDOWN. The host processor must clear the interrupt by
writing 1 to the INT_TOP.RESET_REG bit. If the host processor reads the INT_TOP.RESET_REG flag after
detecting an nINT low signal, it knows that the input supply voltage has been below UVLO level (or the host has
requested reset), and the registers are reset to default values.
8.3.6 Digital Signal Filtering
The digital signals have a debounce filtering. The signal/supply is sampled with a clock signal and a counter.
This results as an accuracy of one clock period for the debounce window.
Table 3. Digital Signal Filtering
EVENT
SIGNAL / SUPPLY
RISING EDGE LENGTH
FALLING EDGE LENGTH
Enable/Disable/Voltage Select for
BUCK0
(1)
(1)
EN1
3µs
3µs
Enable/Disable/Voltage Select for
BUCK0
(1)
(1)
EN2
3µs
3µs
VANA undervoltage lockout
Thermal warning
VANA
Immediate
20 µs
Immediate
20 µs
TDIE_WARN
TDIE_SD
Thermal shutdown
Current limit
20 µs
20 µs
VOUTx_ILIM
20 µs
20 µs
FB_B0 - FB_B1, FB_B2 -
FB_F3
Overload
1 ms
1 ms
FB_B0 - FB_B1, FB_B2 -
FB_F3
Powergood
20 µs
20 µs
(1) No glitch filtering, only synchronization.
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8.4 Device Functional Modes
8.4.1 Modes of Operation
SHUTDOWN: The V(NRST) voltage is below threshold level. All switch, reference, control and bias circuitry of the
LP8758 device are turned off.
WAIT-ON: The V(NRST) voltage is above threshold level. The reference and bias circuitry are enabled. The
regulator of the LP8758 device is turned off.
READ OTP: The main supply voltage V(VANA) is above VANAUVLO level and V(NRST) voltage is above threshold
level. The regulator is disabled and the reference and bias circuitry of the LP8758 are enabled. The
OTP bits are loaded to registers.
STANDBY: The main supply voltage V(VANA) is above VANAUVLO level and V(NRST) voltage is above threshold
level. The regulator is disabled and the reference, control and bias circuitry of the LP8758 are
enabled. All registers can be read or written by the host processor via the system serial interface.
The regulator can be enabled if needed.
ACTIVE:
The main supply voltage V(VANA) is above VANAUVLO level and V(NRST) voltage is above threshold
level. At least one regulated DC-DC converter is enabled. All registers can be read or written by the
host processor via the system serial interface.
The operating modes and transitions between the modes are shown in Figure 14.
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Device Functional Modes (continued)
SHUTDOWN
NRST high
NRST low
FROM ANY STATE
EXCEPT SHUTDOWN
WAIT-ON
V(
> VANAUVLO
VANA)
V(
< VANAUVLO
VANA)
READ
OTP
FROM ANY STATE
EXCEPT SHUTDOWN
REG
RESET
STANDBY
2
I C RESET
REGULATOR
ENABLED
REGULATOR(S)
DISABLED
ACTIVE
Figure 14. Device Operation Modes
8.5 Programming
8.5.1 I2C-Compatible Interface
The I2C-compatible synchronous serial interface provides access to the programmable functions and registers on
the device. This protocol uses a two-wire interface for bidirectional communications between the devices
connected to the bus. The two interface lines are the Serial Data Line (SDA), and the Serial Clock Line (SCL).
Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on
whether it generates or receives the serial clock SCL. The SCL and SDA lines should each have a pullup resistor
placed somewhere on the line and remain HIGH even when the bus is idle. The LP8758 supports standard mode
(100 kHz), fast mode (400 kHz), fast mode plus (1 MHz), and high-speed mode (3.4 MHz).
8.5.1.1 Data Validity
The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the
state of the data line can only be changed when clock signal is LOW.
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Programming (continued)
SCL
SDA
data
change
allowed
data
change
allowed
data
change
allowed
data
valid
data
valid
Figure 15. Data Validity Diagram
8.5.1.2 Start and Stop Conditions
The LP8758 is controlled via an I2C-compatible interface. START and STOP conditions classify the beginning
and end of the I2C session. A START condition is defined as SDA transitions from HIGH to LOW while SCL is
HIGH. A STOP condition is defined as SDA transition from LOW to HIGH while SCL is HIGH. The I2C master
always generates the START and STOP conditions.
SDA
SCL
S
P
START
STOP
Condition
Condition
Figure 16. Start and Stop Sequences
The I2C bus is considered busy after a START condition and free after a STOP condition. During data
transmission the I2C master can generate repeated START conditions. A START and a repeated START
condition are equivalent function-wise. The data on SDA must be stable during the HIGH period of the clock
signal (SCL). In other words, the state of SDA can only be changed when SCL is LOW. Figure 17 shows the
SDA and SCL signal timing for the I2C-Compatible Bus. See the I2C Serial Bus Timing Parameter for timing
values.
tBUF
SDA
tHD;STA
trCL
tfDA
trDA
tSP
tLOW
tfCL
SCL
tHD;STA
tSU;STA
tSU;STO
tHIGH
tHD;DAT
S
tSU;DAT
S
RS
P
START
REPEATED
START
STOP
START
Figure 17. I2C-Compatible Timing
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Programming (continued)
8.5.1.3 Transferring Data
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.
Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated
by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LP8758 pulls
down the SDA line during the 9th clock pulse, signifying an acknowledge. The LP8758 generates an
acknowledge after each byte has been received.
There is one exception to the “acknowledge after every byte” rule. When the master is the receiver, it must
indicate to the transmitter an end of data by not-acknowledging (“negative acknowledge”) the last byte clocked
out of the slave. This “negative acknowledge” still includes the acknowledge clock pulse (generated by the
master), but the SDA line is not pulled down.
NOTE
If the NRST signal is low during I2C communication the LP8758 device does not drive
SDA line. The ACK signal and data transfer to the master is disabled at that time.
After the START condition, the bus master sends a chip address. This address is seven bits long followed by an
eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a “0” indicates a WRITE and a “1”
indicates a READ. The second byte selects the register to which the data will be written. The third byte contains
data to write to the selected register.
ACK from slave
ACK from slave
ACK from slave
START MSB Chip Address LSB
W
ACK MSB Register Address LSB ACK
MSB Data LSB
ACK STOP
SCL
SDA
START
id = 0x60
W
ACK
address = 0x40
ACK
address 0x40 data
ACK STOP
Figure 18. Write Cycle (w = write; SDA = '0'), id = Device Address = 60Hex for LP8758
ACK from slave
ACK from slave REPEATED START
ACK from slave Data from slave NACK from master
START MSB Chip Address LSB
W
MSB Register Address LSB
RS
MSB Chip Address LSB
R
MSB Data LSB
STOP
SCL
SDA
START
ACK
ACK
ACK
NACK
STOP
id = 0x60
W
address = 0x3F
RS
id = 0x60
R
address 0x3F data
When READ function is to be accomplished, a WRITE function must precede the READ function as shown above.
Figure 19. Read Cycle ( r = read; SDA = '1'), id = Device Address = 60Hex for LP8758
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Programming (continued)
8.5.1.4 I2C-Compatible Chip Address
The device address for the LP8758 is 0x60. After the START condition, the I2C master sends the 7-bit address
followed by an eighth bit, read or write (R/W). R/W = 0 indicates a WRITE and R/W = 1 indicates a READ. The
second byte following the device address selects the register address to which the data will be written. The third
byte contains the data for the selected register.
MSB
LSB
1
Bit 7
1
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
R/W
Bit 0
2
I C Slave Address (chip address)
Here device address is 110 0000Bin = 60Hex.
Figure 20. Device Address
8.5.1.5 Auto Increment Feature
The auto-increment feature allows writing several consecutive registers within one transmission. Every time an 8-
bit word is sent to the LP8758, the internal address index counter will be incremented by one and the next
register will be written. Table 4 below shows writing sequence to two consecutive registers. Note that the auto-
increment feature does not work for read.
Table 4. Auto-Increment Example
Master
Action
Start
Device
Address
= 60H
Write
Register
Address
Data
Data
Stop
LP8758
Action
ACK
ACK
ACK
ACK
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8.6 Register Maps
8.6.1 Register Descriptions
The LP8758 is controlled by a set of registers through the system serial interface port. The device registers, their
addresses and their abbreviations are listed in Table 5. A more detailed description is given in sections
DEV_REV to I_LOAD_1.
Table 5. Summary of LP8758 Control Registers
Addr
Register
Read /
Write
D7
D6
D5
D4
D3
D2
D1
D0
0x01
0x02
OTP_REV
R
OTP_ID[7:0]
BUCK0
_FPWM
_MP
BUCK0_
CTRL1
EN_PIN_
CTRL0
EN_PIN_
SELECT0
EN_ROOF
_FLOOR0
BUCK0_
FPWM
R/W
EN_BUCK0
EN_RDIS0
Reserved
BUCK0_
CTRL2
0x03
0x05
0x07
0x09
0x0A
R/W
R/W
R/W
R/W
R/W
Reserved
ILIM0[2:0]
ILIM1[2:0]
ILIM2[2:0]
ILIM3[2:0]
SLEW_RATE0[2:0]
Reserved
BUCK1_
CTRL2
Reserved
Reserved
Reserved
BUCK2_
CTRL2
Reserved
BUCK3_
CTRL2
Reserved
BUCK0_
VOUT
BUCK0_VSET[7:0]
BUCK0_
FLOOR_
VOUT
0x0B
R/W
BUCK0_FLOOR_VSET[7:0]
BUCK0_
DELAY
0x12
0x16
R/W
R/W
BUCK0_SHUTDOWN_DELAY[3:0]
BUCK0_STARTUP_DELAY[3:0]
SW_
RESET
RESET
CONFIG
INT_TOP
Reserved
TDIE
_WARN
_LEVEL
EN_
SPREAD
_SPEC
0x17
R/W
Reserved
EN2_PD
EN1_PD
INT_
BUCK3
INT_
INT_
INT_
BUCK0
TDIE_
WARN
RESET_
REG
I_LOAD_
READY
0x18
0x19
0x1A
R/W
R/W
R/W
TDIE_SD
Reserved
BUCK2
BUCK1
INT_BUCK_
0_1
BUCK1_
ILIM_INT
BUCK0_
PG_INT
BUCK0_
SC_INT
BUCK0_
ILIM_INT
Reserved
Reserved
INT_BUCK_
2_3
BUCK3_
ILIM_INT
BUCK2_
ILIM_INT
Reserved
TDIE_
WARN_
STAT
TOP_
STAT
TDIE_SD
_STAT
0x1B
R
Reserved
Reserved
BUCK1_
ILIM_
STAT
BUCK0_
ILIM_
STAT
BUCK_0_1_
STAT
BUCK0_
STAT
BUCK0_
PG_STAT
0x1C
0x1D
0x1E
R
R
Reserved
Reserved
Reserved
BUCK_2_3_
STAT
BUCK3_
ILIM_STAT
BUCK2_
ILIM_STAT
Reserved
I_LOAD_
READY_
MASK
TOP_
MASK
TDIE_WAR
N_MASK
RESET_
REG_MASK
R/W
Reserved
BUCK1_
ILIM_
MASK
BUCK0_
ILIM_
MASK
BUCK_0_1_
MASK
BUCK0_
PG_MASK
0x1F
R/W
Reserved
Reserved
Reserved
Reserved
BUCK3_
ILIM_
MASK
BUCK2_
ILIM_
MASK
BUCK_2_3_
MASK
0x20
0x21
R/W
R/W
Reserved
SEL_I_
LOAD
LOAD_CURRENT_
BUCK_SELECT[1:0]
Reserved
Reserved
BUCK_LOAD_CURRENT[7:0]
BUCK_LOAD_CURRENT[
9:8]
0x22
0x23
I_LOAD_2
I_LOAD_1
R/W
R/W
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8.6.1.1 DEV_REV
Address: 0x00
D7
D6
D5
D4
D3
D2
METAL_LAYER[3:0]
Description
D1
D0
DEVICE_ID[1:0]
ALL_LAYER[1:0]
Bits
7:6
Field
Type
R
Default
00
DEVICE_ID[1:0]
ALL_LAYER[1:0]
Device specific ID code.
5:4
R
00
Shows the all layer version of the device:
00 - First all layer version
01 - Second all layer version
10 - Third all layer version
11 - Fourth all layer version
3:0
METAL_LAYER
[3:0]
R
0001
Shows the metal layer version of the device:
0000 - All layer version
0001 - First metal layer spin
...
1111 - 15th metal layer spin
8.6.1.2 OTP_REV
Address: 0x01
D7
D6
D5
D4
D3
D2
D1
D0
OTP_ID[7:0]
Bits
Field
Type
Default
Description
7:0
OTP_ID[7:0]
R
1011 0000 Identification Code of the OTP EPROM Version.
8.6.1.3 BUCK0_CTRL1
Address: 0x02
D7
D6
D5
D4
D3
D2
D1
D0
EN_BUCK0
EN_PIN_
CTRL0
EN_PIN_
SELECT0
EN_ROOF_
FLOOR0
EN_RDIS0
Reserved
BUCK0_FPWM BUCK0_FPWM
_MP
Bits
Field
Type
Default
Description
7
6
5
4
3
EN_BUCK0
EN_PIN_CTRL0
EN_PIN_SELECT0
R/W
1
Enable BUCK0 regulator:
0 - BUCK0 regulator is disabled
1 - BUCK0 regulator is enabled.
R/W
R/W
R/W
R/W
1
0
0
1
Enable EN1/2 pin control for BUCK0:
0 - only EN_BUCK0 bit controls BUCK0
1 - EN_BUCK0 bit AND EN1/2 pin control BUCK0.
Select which ENx pin controls BUCK0 if EN_PIN_CTRL0 = 1:
0 - EN1 pin
1 - EN2 pin.
EN_ROOF_
FLOOR0
Enable Roof/Floor control of EN1/2 pin if EN_PIN_CTRL0 = 1:
0 - Enable/Disable (1/0) control
1 - Roof/Floor (1/0) control.
EN_RDIS0
Enable output discharge resistor when BUCK0 is disabled:
0 - Discharge resistor disabled
1 - Discharge resistor enabled.
2
1
Reserved
R/W
R/W
0
0
BUCK0_FPWM
Forces the BUCK0 regulator to operate in PWM mode:
0 - Automatic transitions between PFM and PWM modes (AUTO mode).
1 - Forced to PWM operation.
0
BUCK0_FPWM
_MP
R/W
0
Forces the BUCK0 regulator to operate always in multi-phase and forced PWM
operation mode:
0 - Automatic phase adding and shedding.
1 - Forced to multi-phase operation, 2 phases in the 2-phase configuration, 3 phases
in the 3-phase configuration and 4 phases in the 4-phase configuration.
30
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8.6.1.4 BUCK0_CTRL2
Address: 0x03
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
ILIM0[2:0]
SLEW_RATE0[2:0]
Bits
7:6
Field
Type
R/W
R/W
Default
00
Description
Reserved
ILIM0[2:0]
5:3
111
Sets the switch current limit of BUCK0. Can be programmed at any time during
operation:
000 - 1.5 A
001 - 2.0 A
010 - 2.5 A
011 - 3.0 A
100 - 3.5 A
101 - 4.0 A
110 - 4.5 A
111 - 5.0 A (Default)
2:0 SLEW_RATE0[2:0]
R/W
010
Sets the output voltage slew rate for BUCK0 regulator (rising and falling edges):
000 - 30 mV/µs
001 - 15 mV/µs
010 - 10 mV/µs (Default)
011 - 7.5 mV/µs
100 - 3.8 mV/µs
101 - 1.9 mV/µs
110 - 0.94 mV/µs
111 - 0.4 mV/µs
8.6.1.5 BUCK1_CTRL2
Address: 0x05
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
ILIM1[2:0]
Reserved
Bits
7:6
Field
Type
R/W
R/W
Default
00
Description
Reserved
ILIM1[2:0]
5:3
111
Sets the switch current limit of BUCK1. Can be programmed at any time during
operation:
000 - 1.5 A
001 - 2.0 A
010 - 2.5 A
011 - 3.0 A
100 - 3.5 A
101 - 4.0 A
110 - 4.5 A
111 - 5.0 A (Default)
2:0
Reserved
R/W
010
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8.6.1.6 BUCK2_CTRL2
Address: 0x07
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
ILIM2[2:0]
Reserved
Bits
7:6
Field
Type
R/W
R/W
Default
00
Description
Reserved
ILIM2[2:0]
5:3
111
Sets the switch current limit of BUCK2. Can be programmed at any time during
operation:
000 - 1.5 A
001 - 2.0 A
010 - 2.5 A
011 - 3.0 A
100 - 3.5 A
101 - 4.0 A
110 - 4.5 A
111 - 5.0 A (Default)
2:0
Reserved
R/W
010
8.6.1.7 BUCK3_CTRL2
Address: 0x09
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
ILIM3[2:0]
Reserved
Bits
7:6
Field
Type
R/W
R/W
Default
00
Description
Reserved
ILIM3[2:0]
5:3
111
Sets the switch current limit of BUCK3. Can be programmed at any time during
operation:
000 - 1.5 A
001 - 2.0 A
010 - 2.5 A
011 - 3.0 A
100 - 3.5 A
101 - 4.0 A
110 - 4.5 A
111 - 5.0 A (Default)
2:0
Reserved
R/W
010
8.6.1.8 BUCK0_VOUT
Address: 0x0A
D7
D6
D5
D4
D3
D2
D1
D0
BUCK0_VSET[7:0]
Bits
Field
Type
Default
Description
7:0 BUCK0_VSET[7:0]
R/W
0110 0001 Sets the output voltage of BUCK0 regulator
0.5 V - 0.73 V, 10 mV steps
0000 0000 - 0.5V
...
0001 0111 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0001 1000 - 0.735 V
...
1001 1101 - 1.4 V
1.4 V - 3.36 V, 20 mV steps
1001 1110 - 1.42 V
...
1111 1111 - 3.36 V
32
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8.6.1.9 BUCK0_FLOOR_VOUT
Address: 0x0B
D7
D6
D5
D4
BUCK0_FLOOR
_VSET[7:0]
D3
D2
D1
D0
Bits
Field
Type
Default
Description
7:0
BUCK0_FLOOR
_VSET[7:0]
R/W
0000 0000 Sets the output voltage of BUCK0 regulator when Floor state is used
0.5 V - 0.73 V, 10 mV steps
0000 0000 - 0.5V
...
0001 0111 - 0.73 V
0.73 V - 1.4 V, 5 mV steps
0001 1000 - 0.735 V
...
1001 1101 - 1.4 V
1.4 V - 3.36 V, 20 mV steps
1001 1110 - 1.42 V
...
1111 1111 - 3.36 V
8.6.1.10 BUCK0_DELAY
Address: 0x12
D7
D6
D5
D4
D3
D2
D1
D0
BUCK0_SHUTDOWN_DELAY[3:0]
BUCK0_STARTUP_DELAY[3:0]
Bits
Field
Type
Default
Description
7:4
BUCK0_
SHUTDOWN_
DELAY[3:0]
R/W
0000
Shutdown delay of BUCK0 from falling edge of ENx signal:
0000 - 0 ms
0001 - 1 ms
...
1111 - 15 ms
3:0
BUCK0_
STARTUP_
DELAY[3:0]
R/W
0000
Start-up delay of BUCK0 from rising edge of ENx signal:
0000 - 0 ms
0001 - 1 ms
...
1111 - 15 ms
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8.6.1.11 RESET
Address: 0x16
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
SW_RESET
Bits
7:1
0
Field
Type
R/W
R/W
Default
000 0000
0
Description
Reserved
SW_RESET
Software commanded reset. When written to 1, the registers will be reset to default
values, OTP memory is read, and the I2C interface is reset.
The bit is automatically cleared.
8.6.1.12 CONFIG
Address: 0x17
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
TDIE_WARN_
LEVEL
EN2_PD
EN1_PD
EN_SPREAD
_SPEC
Bits
7:4
3
Field
Type
R/W
R/W
Default
0000
0
Description
Reserved
TDIE_WARN_
LEVEL
Thermal warning threshold level.
0 - 125°C
1 - 105°C.
2
1
0
EN2_PD
EN1_PD
R/W
R/W
R/W
1
1
0
Selects the pull down resistor on the EN2 input pin.
0 - Pull-down resistor is disabled.
1 - Pull-down resistor is enabled.
Selects the pull down resistor on the EN1 input pin.
0 - Pull-down resistor is disabled.
1 - Pull-down resistor is enabled.
EN_SPREAD
_SPEC
Enable spread spectrum feature:
0 - Disabled
1 - Enabled
8.6.1.13 INT_TOP
Address: 0x18
D7
D6
D5
D4
D3
D2
D1
D0
INT_BUCK3
INT_BUCK2
INT_BUCK1
INT_BUCK0
TDIE_SD
TDIE_WARN
RESET_REG
I_LOAD_
READY
Bits
Field
Type
Default
Description
7
6
5
4
3
INT_BUCK3
INT_BUCK2
INT_BUCK1
INT_BUCK0
TDIE_SD
R
0
Interrupt indicating that output BUCK3 has a pending interrupt. The reason for the
interrupt is indicated in INT_BUCK3 register.
This bit is cleared automatically when INT_BUCK3 register is cleared to 0x00.
R
R
0
0
0
0
Interrupt indicating that output BUCK2 has a pending interrupt. The reason for the
interrupt is indicated in INT_BUCK2 register.
This bit is cleared automatically when INT_BUCK2 register is cleared to 0x00.
Interrupt indicating that output BUCK1 has a pending interrupt. The reason for the
interrupt is indicated in INT_BUCK1 register.
This bit is cleared automatically when INT_BUCK1 register is cleared to 0x00.
R
Interrupt indicating that output BUCK0 has a pending interrupt. The reason for the
interrupt is indicated in INT_BUCK0 register.
This bit is cleared automatically when INT_BUCK0 register is cleared to 0x00.
R/W
Latched status bit indicating that the die junction temperature has exceeded the
thermal shutdown level. The regulator has been disabled if it was enabled. The
regulator cannot be enabled if this bit is active. The actual status of the thermal
warning is indicated by TOP_STAT.TDIE_SD_STAT bit.
Write 1 to clear interrupt.
34
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Bits
ZHCSDQ0C –MARCH 2015–REVISED AUGUST 2018
Field
Type
Default
Description
2
TDIE_WARN
R/W
0
Latched status bit indicating that the die junction temperature has exceeded the
thermal warning level. The actual status of the thermal warning is indicated by
TOP_STAT.TDIE_WARN_STAT bit.
Write 1 to clear interrupt.
1
RESET_REG
R/W
R/W
0
0
Latched status bit indicating that either startup (NRST rising edge) has done, VANA
supply voltage has been below undervoltage threshold level or the host has requested
a reset (RESET.SW_RESET). The regulator has been disabled, and registers are
reset to default values and the normal startup procedure is done.
Write 1 to clear interrupt.
0
I_LOAD_READY
Latched status bit indicating that the load current measurement result is available in
I_LOAD_1 and I_LOAD_2 registers.
Write 1 to clear interrupt.
8.6.1.14 INT_BUCK_0_1
Address: 0x19
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
BUCK1_ILIM
_INT
Reserved
BUCK0_PG
_INT
BUCK0_SC
_INT
BUCK0_ILIM
_INT
Bits
7:5
4
Field
Reserved
Type
R/W
R/W
Default
000
Description
BUCK1_ILIM_INT
0
Latched status bit indicating that output current limit has been active.
Write 1 to clear.
3
2
Reserved
R/W
R/W
0
0
BUCK0_PG_INT
Latched status bit indicating that BUCK0 output voltage has reached powergood
threshold level.
Write 1 to clear.
1
0
BUCK0_SC_INT
BUCK0_ILIM_INT
R/W
R/W
0
0
Latched status bit indicating that the BUCK0 output voltage has fallen below 0.35V
level during operation or BUCK0 output didn't reach 0.35 V level in 1 ms from enable.
Write 1 to clear.
Latched status bit indicating that output current limit has been active.
Write 1 to clear.
8.6.1.15 INT_BUCK_2_3
Address: 0x1A
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
BUCK3_ILIM
_INT
Reserved
BUCK2_ILIM
_INT
Bits
7:5
4
Field
Reserved
Type
R/W
R/W
Default
000
Description
BUCK3_ILIM_INT
0
Latched status bit indicating that output current limit has been active.
Write 1 to clear.
3:1
0
Reserved
R/W
R/W
000
0
BUCK2_ILIM_INT
Latched status bit indicating that output current limit has been active.
Write 1 to clear.
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8.6.1.16 TOP_STAT
Address: 0x1B
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
TDIE_SD
_STAT
TDIE_WARN
_STAT
Reserved
Bits
7:4
3
Field
Type
R
Default
0000
0
Description
Reserved
TDIE_SD_STAT
R
Status bit indicating the status of thermal shutdown:
0 - Die temperature below thermal shutdown level
1 - Die temperature above thermal shutdown level.
2
TDIE_WARN
_STAT
R
R
0
Status bit indicating the status of thermal warning:
0 - Die temperature below thermal warning level
1 - Die temperature above thermal warning level.
1:0
Reserved
00
8.6.1.17 BUCK_0_1_STAT
Address: 0x1C
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
BUCK1_ILIM
_STAT
BUCK0_STAT
BUCK0_PG
_STAT
Reserved
BUCK0_ILIM
_STAT
Bits
7:5
4
Field
Type
R
Default
000
Description
Reserved
BUCK1_ILIM
_STAT
R
0
Status bit indicating BUCK1 current limit status (raw status)
0 - BUCK1 output current is below current limit level
1 - BUCK1 output current limit is active.
3
2
BUCK0_STAT
R
R
0
0
Status bit indicating the enable/disable status of BUCK0:
0 - BUCK0 regulator is disabled
1 - BUCK0 regulator is enabled.
BUCK0_PG_STAT
Reserved
Status bit indicating BUCK0 output voltage validity (raw status)
0 - BUCK0 output is above powergood threshold level
1 - BUCK0 output is below powergood threshold level.
1
0
R
R
0
0
BUCK0_ILIM
_STAT
Status bit indicating BUCK0 current limit status (raw status)
0 - BUCK0 output current is below current limit level
1 - BUCK0 output current limit is active.
8.6.1.18 BUCK_2_3_STAT
Address: 0x1D
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
BUCK3_ILIM
_STAT
Reserved
BUCK2_ILIM
_STAT
Bits
7:5
4
Field
Type
R
Default
000
Description
Reserved
BUCK3_ILIM
_STAT
R
0
Status bit indicating BUCK3 current limit status (raw status)
0 - BUCK3 output current is below current limit level
1 - BUCK3 output current limit is active.
3:1
0
Reserved
R
R
000
0
BUCK2_ILIM
_STAT
Status bit indicating BUCK2 current limit status (raw status)
0 - BUCK2 output current is below current limit level
1 - BUCK2 output current limit is active.
36
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8.6.1.19 TOP_MASK
Address: 0x1E
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
TDIE_WARN
_MASK
RESET_REG
_MASK
I_LOAD_
READY_MASK
Bits
7:3
2
Field
Type
R/W
R/W
Default
0 0000
0
Description
Reserved
TDIE_WARN
_MASK
Masking for thermal warning interrupt INT_TOP.TDIE_WARN:
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect TOP_STAT.TDIE_WARN_STAT status bit.
1
0
RESET_REG
_MASK
R/W
R/W
1
0
Masking for register reset interrupt INT_TOP.RESET_REG:
0 - Interrupt generated
1 - Interrupt not generated.
I_LOAD_
READY_MASK
Masking for load current measurement ready interrupt INT_TOP.I_LOAD_READY.
0 - Interrupt generated
1 - Interrupt not generated.
8.6.1.20 BUCK_0_1_MASK
Address: 0x1F
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
BUCK1_ILIM
_MASK
Reserved
BUCK0_PG
_MASK
Reserved
BUCK0_ILIM
_MASK
Bits
7:5
4
Field
Type
R/W
R/W
Default
000
Description
Reserved
BUCK1_ILIM
_MASK
1
Masking for BUCK1 current limit detection interrupt INT_BUCK_0_1.BUCK1_ILIM_INT:
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect BUCK_0_1_STAT.BUCK1_ILIM_STAT status bit.
3
2
Reserved
R/W
R/W
0
0
BUCK0_PG_MASK
Masking for BUCK0 power good interrupt INT_BUCK_0_1.BUCK0_PG_INT:
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect BUCK_0_1_STAT.BUCK1_PG_STAT status bit.
1
0
Reserved
R
0
0
BUCK0_ILIM
_MASK
R/W
Masking for BUCK0 current limit detection interrupt INT_BUCK_0_1.BUCK0_ILIM_INT:
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect BUCK_0_1_STAT.BUCK1_ILIM_STAT status bit.
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8.6.1.21 BUCK_2_3_MASK
Address: 0x20
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
BUCK3_ILIM
_MASK
Reserved
BUCK2_ILIM
_MASK
Bits
7:5
4
Field
Type
R/W
R/W
Default
000
Description
Reserved
BUCK3_ILIM
_MASK
1
Masking for BUCK3 current limit detection interrupt INT_BUCK_2_3.BUCK3_ILIM_INT:
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect BUCK_2_3_STAT.BUCK3_ILIM_STAT status bit.
3:1
0
Reserved
R/W
R/W
000
1
BUCK2_ILIM
_MASK
Masking for BUCK2 current limit detection interrupt INT_BUCK_2_3.BUCK2_ILIM_INT:
0 - Interrupt generated
1 - Interrupt not generated.
This bit does not affect BUCK_2_3_STAT.BUCK1_ILIM_STAT status bit.
8.6.1.22 SEL_I_LOAD
Address: 0x21
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
LOAD_CURRENT_BUCK
_SELECT[1:0]
Bits
Field
Type
R/W
R/W
Default
00 0000
00
Description
7:2
Reserved
1:0 LOAD_CURRENT_
BUCK_SELECT
[1:0]
Start the current measurement on the selected regulator:
00 - BUCK0
01 - BUCK1
10 - BUCK2
11 - BUCK3
The measurement is started when register is written.
If the selected buck is master, the measurement result is a sum current of master and
slave bucks.
If the selected buck is slave, the measurement result is a current of the selected slave
bucks.
8.6.1.23 I_LOAD_2
Address: 0x22
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
BUCK_LOAD_CURRENT[9:8]
Bits
7:2
Field
Type
R
Default
00 0000
00
Description
Reserved
1:0
BUCK_LOAD_
CURRENT[9:8]
R
This register describes 3 MSB bits of the average load current on selected regulator
with a resolution of 20 mA per LSB and max 20 A current.
8.6.1.24 I_LOAD_1
Address: 0x23
D7
D6
D5
D4
D3
D2
D1
D0
BUCK_LOAD_CURRENT[7:0]
38
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Bits
ZHCSDQ0C –MARCH 2015–REVISED AUGUST 2018
Field
Type
Default
Description
7:0
BUCK_LOAD_
CURRENT[7:0]
R
0000 0000 This register describes 8 LSB bits of the average load current on selected regulator
with a resolution of 10 mA per LSB and max 20 A current.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LP8758 is a multi-phase step-down converter with four switcher cores bundled together.
9.2 Typical Application
4-Phase configuration
0.33mH
VIN_B0
VIN_B1
VIN_B2
VIN_B3
SW_B0
SW_B1
VBAT
0.33mH
22mF
22mF
Load
CPOL
10mF
10mF
10mF
10mF
0.33mH
0.33mH
SW_B2
SW_B3
VANA
100nF
AGND
SGND
22mF
22mF
1.8V IO
10kW
1.8kW 1.8kW
FB_B0
FB_B1
SDA
SCL
FB_B2
FB_B3
nINT
Host
Digital
Processor
NRST
Control
EN1
EN2
Figure 21. LP8758 Typical Application Circuit
Table 6. Design Parameters
9.2.1 Design Requirements
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
Output voltage
2.5 V to 5.5 V
1.1 V
Converter operation mode
Maximum load current
Inductor current limit
Auto mode (PWM-PFM)
16 A
5 A
40
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ZHCSDQ0C –MARCH 2015–REVISED AUGUST 2018
9.2.2 Detailed Design Procedure
The performance of the LP8758 device depends greatly on the care taken in designing the printed circuit board
(PCB). The use of low-inductance and low serial-resistance ceramic capacitors is strongly recommended, while
proper grounding is crucial. Attention must be given to decoupling the power supplies. Decoupling capacitors
must be connected close to the device and between the power and ground pins to support high peak currents
being drawn from system power rail during turn-on of the switching MOSFETs. Keep input and output traces as
short as possible, because trace inductance, resistance, and capacitance can easily become the performance
limiting items. The separate power pins VIN_Bx are not connected together internally. The VIN_Bx power
connections shall be connected together outside the package using power plane construction.
9.2.2.1 Application Components
9.2.2.1.1 Inductor Selection
DC bias current characteristics of inductors must be considered. Different manufacturers follow different
saturation current rating specifications, so attention must be given to details. DC bias curves should be requested
from them as part of the inductor selection process. Minimum effective value of inductance to ensure good
performance is 0.22 μH at 4-A bias current over the inductor's operating temperature range. The inductor’s DC
resistance should be less than 0.05 Ω for good efficiency at high current condition. The inductor AC loss
(resistance) also affects conversion efficiency. Higher Q factor at switching frequency usually gives better
efficiency at light load to middle load. See Table 7. Shielded inductors are preferred as they radiate less noise.
Table 7. Recommended Inductors
MANUFACTURER
PART NUMBER
VALUE
DIMENSIONS L×W×H
(mm)
DCR (mΩ)
TOKO
TDK
DFE252010F-R33M
VLS252010HBX-R33M
VLS252010HBX-R47M
TFM2016GHM-0R47M
DFE322512C R47
0.33 µH
0.33 µH
0.47 µH
0.47 µH
0.47 µH
2.5 × 2.0 × 1.0
2.5 × 2.0 × 1.0
2.5 × 2.0 × 1.0
2.0 × 1.6 × 1.0
3.2 × 2.5 × 1.2
16 (typ), 21 (max)
25 (typ), 31 (max)
29 (typ), 35 (max)
46 (max)
TDK
TDK
TOKO
21 (typ), 31 (max)
9.2.2.1.2 Input Capacitor Selection
A ceramic input capacitor of 10 μF, 6.3 V is sufficient for most applications. Place the power input capacitor as
close as possible to the VIN_Bx pin and PGND_Bx pin of the device. A larger value or higher voltage rating may
be used to improve input voltage filtering. Use X7R or X5R types, do not use Y5V or F. DC bias characteristics of
ceramic capacitors must be considered when selecting case sizes like 0402. Minimum effective input
capacitance to ensure good performance is 1.9 μF per buck input at maximum input voltage DC bias including
tolerances and over ambient temp range, assuming that there are at least 22 μF of additional capacitance
common for all the power input pins on the system power rail. See Table 8.
The input filter capacitor supplies current to the high-side FET switch in the first half of each cycle and reduces
voltage ripple imposed on the input power source. A ceramic capacitor's low equivalent series resistance (ESR)
provides the best noise filtering of the input voltage spikes due to this rapidly changing current. Select an input
filter capacitor with sufficient ripple current rating.
The VANA input is used to supply analog and digital circuits in the device. See recommended components from
Table 9 for VANA input supply filtering.
Table 8. Recommended Power Input Capacitors (X5R Dielectric)
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
DIMENSIONS L×W×H
(mm)
VOLTAGE
RATING
Murata
GRM188R60J106ME47
10 µF (20%)
0603
1.6 × 0.8 × 0.8
6.3 V
Copyright © 2015–2018, Texas Instruments Incorporated
41
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www.ti.com.cn
Table 9. Recommended VANA Supply Filtering Components
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
DIMENSIONS L×W×H VOLTAGE RATING
(mm)
Samsung
Murata
CL03A104KP3NNNC
100 nF (10%)
100 nF (10%)
0201
0201
0.6 × 0.3 × 0.3
0.6 × 0.3 × 0.3
10 V
GRM033R61A104KE84
6.3 V
9.2.2.1.3 Output Capacitor Selection
Use ceramic capacitors, X7R or X5R types; do not use Y5V or F. DC bias voltage characteristics of ceramic
capacitors must be considered. DC bias characteristics vary from manufacturer to manufacturer, and DC bias
curves should be requested from them as part of the capacitor selection process. The output filter capacitor
smooths out current flow from the inductor to the load, helps maintain a steady output voltage during transient
load changes and reduces output voltage ripple. These capacitors must be selected with sufficient capacitance
and sufficiently low ESR and ESL to perform these functions. Minimum effective output capacitance to ensure
good performance is 10 μF per phase at the output voltage DC bias including tolerances and over ambient temp
range.
The output voltage ripple is caused by the charging and discharging of the output capacitor and also due to its
RESR. The RESR is frequency dependent (as well as temperature dependent); make sure the value used for
selection process is at the switching frequency of the part. See Table 10.
A higher output capacitance improves the load step behavior and reduces the output voltage ripple as well as
decreases the PFM switching frequency. For most 4-phase applications 4 x 22 μF 0603 capacitors for COUT are
suitable. A point-of-load (POL) capacitance CPOL can be added with remove feedback as shown in Figure 21.
Although a converter's loop compensation can be programmed to adapt to virtually several hundreds of
microfarads COUT, it is preferable for COUT to be < 200 µF (4-phase configuration). Choosing higher than that is
not necessarily of any benefit. Note that the output capacitor may be the limiting factor in the output voltage
ramp, especially for very large (> 100 µF) output capacitors. For large output capacitors, the output voltage might
be slower than the programmed ramp rate at voltage transitions, because of the higher energy stored on the
output capacitance. Also at start-up, the time required to charge the output capacitor to target value might be
longer. At shutdown, if the output capacitor is discharged by the internal discharge resistor, more time is required
to settle VOUT down as a consequence of the increased time constant.
Table 10. Recommended Output Capacitors (X5R Dielectric)
MANUFACTURER
PART NUMBER
VALUE
CASE SIZE
DIMENSIONS L×W×H
(mm)
VOLTAGE
RATING
Samsung
Murata
CL10A226MP8NUNE
22 µF (20%)
22 µF (20%)
0603
0603
1.6 × 0.8 × 0.8
1.6 × 0.8 × 0.8
10 V
GRM188R60J226MEA0
6.3 V
42
Copyright © 2015–2018, Texas Instruments Incorporated
LP8758-B0
www.ti.com.cn
ZHCSDQ0C –MARCH 2015–REVISED AUGUST 2018
9.2.3 Application Curves
Unless otherwise specified: VIN = 3.7 V, VOUT = 1 V, V(NRST) = 1.8 V, TA = 25 °C, ƒSW = 3 MHz, L = 330 nH
(TOKO DFE252010F-R33M), CPOL = 22 µF. Measurements done with connections in Figure 21.
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
VOUT = 1.2V
VOUT = 1V
VOUT = 0.8V
VOUT = 1.2V
VOUT = 1V
VOUT = 0.8V
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
Output Current (A)
Output Current (A)
D014
D015
VIN = 3.7 V
Figure 22. Efficiency in Forced PWM Mode
VIN = 3.7 V
Inductor = TDK VLS252010HBX-R47M
Figure 23. Efficiency in Forced PWM Mode
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
VOUT = 1.2V
VOUT = 1.1V
VOUT = 1V
VOUT = 0.9V
VOUT = 0.8V
AUTO
FPWM
FMP
0.001
0.01
0.1
1
10 20
2.5
3
3.5
4
4.5
5
5.5
Output Current (A)
Input Voltage (V)
D002
D016
VIN = 3.7 V
VOUT = 1 V
Load = 1 A
Figure 25. Efficiency vs Input Voltage
Figure 24. Efficiency in PFM, PWM and Forced Multi-Phase
Mode
100
95
90
85
80
75
70
100
95
90
85
80
75
70
65
60
55
50
65
60
55
50
VOUT = 1.2V
VOUT = 1.1V
VOUT = 1V
VOUT = 0.9V
VOUT = 0.8V
VOUT = 1.2V
VOUT = 1.1V
VOUT = 1V
VOUT = 0.9V
VOUT = 0.8V
2.5
3
3.5
4
4.5
5
5.5
2.5
3
3.5
4
4.5
5
5.5
Input Voltage (V)
Input Voltage (V)
D017
D018
Load = 8 A
Figure 26. Efficiency vs Input Voltage
Load = 12 A
Figure 27. Efficiency vs Input Voltage
Copyright © 2015–2018, Texas Instruments Incorporated
43
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1.005
1.004
1.003
1.002
1.001
1
1.01
1.008
1.006
1.004
1.002
1
0.999
0.998
0.997
0.996
0.995
0.998
0.996
0.994
0.992
0.99
VIN = 2.5V
VIN = 3.7V
VIN = 5.5V
VIN = 2.5V
VIN = 3.7V
VIN = 5.5V
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Output Current (A)
1
Output Current (A)
D005
D004
VOUT = 1 V
VOUT = 1 V
Figure 28. Output Voltage vs Load Current in Forced PWM
Mode
Figure 29. Output Voltage vs Load Current in PWM-PFM
Mode
1.015
1.005
PWM Mode
PFM Mode
1.004
1.003
1.002
1.001
1
1.010
1.005
1.000
0.995
0.990
0.999
0.998
0.997
0.996
0.995
-50
-25
0
25
50
75
100
125
2.5
3
3.5
4
4.5
5
5.5
Temperature (èC)
D048
Input Voltage (V)
D044
VOUT = 1 V
VOUT = 1 V
Load = 1 A
Load = 3 A (PWM Mode) and 100 mA (PFM Mode)
Figure 31. Output Voltage vs Temperature
Figure 30. Output Voltage vs Input Voltage in PWM Mode
5
V(EN1) (500 mV/div)
4
3
2
1
0
VOUT (200 mV/div)
V(SW_B0) (2 V/div)
SHEDDING
ADDING
Time (40 µs/div)
0
0.5
1
1.5
2
2.5
3
3.5
4
Load = 0 A
Output Current (A)
D041
Figure 32. Phase Adding and Shedding vs Load Current
Figure 33. Start-up with EN1, Forced PWM
44
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LP8758-B0
www.ti.com.cn
ZHCSDQ0C –MARCH 2015–REVISED AUGUST 2018
V(EN1) (500 mV/div)
V(EN1) (500 mV/div)
VOUT (200 mV/div)
VOUT (200 mV/div)
ILOAD (2 A/div)
ILOAD (2 A/div)
V(SW_B0) (2 V/div)
V(SW_B0) (2 V/div)
Time (40 µs/div)
Time (20 µs/div)
Load = 3 A
Load = 3 A
Figure 34. Start-up with EN1, Forced PWM
Figure 35. Shutdown with EN1, Forced PWM
VOUT (10 mV/div)
VOUT (10 mV/div)
V(SW_B0) (2 V/div)
V(SW_B0) (2 V/div)
Time (40 µs/div)
Time (200 ns/div)
Load = 10 mA
Load = 200 mA
Figure 36. Output Voltage Ripple, PFM Mode
Figure 37. Output Voltage Ripple, Forced PWM Mode
VOUT (10 mV/div)
V(SW_B0) (1 V/div)
VOUT (10 mV/div)
V(SW_B0) (1 V/div)
Time (2 µs/div)
Time (4 µs/div)
Figure 38. Transient from PFM-to-PWM Mode
Figure 39. Transient from PWM-to-PFM Mode
Copyright © 2015–2018, Texas Instruments Incorporated
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LP8758-B0
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VOUT (10 mV/div)
VOUT (10 mV/div)
V(SW_B1) (2 V/div)
V(SW_B1) (2 V/div)
V(SW_B0) (2 V/div)
V(SW_B0) (2V/div)
Time (10 µs/div)
Time (10 µs/div)
Figure 41. Transient from 2-Phase to 1-Phase Operation
Figure 40. Transient from 1-Phase to 2-Phase Operation
VOUT (20 mV/div)
VOUT (20 mV/div)
ILOAD (1 A/div)
ILOAD (4 A/div)
Time (40 µs/div)
Time (40 µs/div)
Load = 1 A → 8 A → 1 A
TR = TF = 400 ns
Load = 0.1 A → 4.1 A → 0.1 A
TR = TF = 100 ns
Figure 43. Transient Load Step Response, FPWM Mode
Figure 42. Transient Load Step Response, AUTO Mode
VIN 500 mV/DIV
VOUT (20 mV/div)
VOUT 20 mV/DIV
ILOAD (4 A/div)
TIME 400 µs/DIV
Load = 12 A
Time (40 µs/div)
Load = 1 A → 12 A → 1 A
TR = TF = 10 µs
TR = TF = 1 µs
VIN = 2.5 V → 3 V → 2.5 V
Figure 45. Transient Line Response
Figure 44. Transient Load Step Response, FPWM Mode
46
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LP8758-B0
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ZHCSDQ0C –MARCH 2015–REVISED AUGUST 2018
VOUT (200 mV/div)
VOUT (200 mV/div)
Time (400 µs/div)
Time (400 µs/div)
Figure 46. VOUT Transition from 0.6 V to 1.4 V with
Different Slew Rate Settings
Figure 47. VOUT Transition from 1.4 V to 0.6 V with
Different Slew Rate Settings
V(EN1) (1 V/div)
V(nINT) (1 V/div)
VOUT (50 mV/div)
IOUT (5 A/div)
Time (200 µs/div)
Figure 48. Start-up with Short on Output
10 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 2.5 V and 5.5 V. This input supply
should be well-regulated and able to withstand maximum input current and maintain stable voltage without
voltage drop even at load transition condition. The resistance of the input supply rail should be low enough that
the input current transient does not cause too high drop in the LP8758 supply voltage that can cause false UVLO
fault triggering. If the input supply is located more than a few inches from the LP8758 additional bulk capacitance
may be required in addition to the ceramic bypass capacitors.
Copyright © 2015–2018, Texas Instruments Incorporated
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ZHCSDQ0C –MARCH 2015–REVISED AUGUST 2018
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11 Layout
11.1 Layout Guidelines
The high frequency and large switching currents of the LP8758 make the choice of layout important. Good power
supply results only occur when care is given to proper design and layout. Layout affects noise pickup and
generation and can cause a good design to perform with less-than-expected results. With a range of output
currents from milliamps to 10 A and over, good power supply layout is much more difficult than most general
PCB design. Use the following steps as a reference to ensure the device is stable and maintains proper voltage
and current regulation across its intended operating voltage and current range.
1. Place CIN as close to the VIN_Bx pin and the PGND_Bxx pin as possible. Route the VIN trace wide and thick
to avoid IR drops. The trace between the input capacitor's positive node and LP8758’s VIN_Bx pin(s) as well
as the trace between the input capacitor's negative node and power PGND_Bxx pin(s) must be kept as short
as possible. The input capacitance provides a low-impedance voltage source for the switching converter. The
inductance of the connection is the most important parameter of a local decoupling capacitor — parasitic
inductance on these traces must be kept as tiny as possible for proper device operation.
2. The output filter, consisting of Lx and COUTx, converts the switching signal at SW_Bx to the noiseless output
voltage. Place the output filter as close to the device as possible, keeping the switch node small, for best
EMI behavior. Route the traces between the LP8758's output capacitors and the load's input capacitors
direct and wide to avoid losses due to the IR drop.
3. Input for analog blocks (VANA and AGND) must be isolated from noisy signals. Connect VANA directly to a
quiet system voltage node and AGND to a quiet ground point where no IR drop occurs. Place the decoupling
capacitor as close to the VANA pin as possible. VANA must be connected to the same power node as
VIN_Bx pins.
4. If the processor load supports remote voltage sensing, connect the LP8758’s feedback pins FB_Bx to the
respective sense pins on the processor. The sense lines are susceptible to noise. They must be kept away
from noisy signals such as PGND_Bxx, VIN_Bx, and SW_Bx, as well as high bandwidth signals such as the
I2C. Avoid both capacitive as well as inductive coupling by keeping the sense lines short, direct and close to
each other. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane if
possible. TI recommends running the signal as a differential pair.
5. Route PGND_Bxx, VIN_Bx and SW_Bx on thick layers. They must not surround inner signal layers which are
not able to withstand interference from noisy PGND_Bxx, VIN_Bx and SW_Bx.
Due to the small package of this converter and the overall small solution size, the thermal performance of the
PCB layout is important. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and
convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of
a given component. Proper PCB layout, focusing on thermal performance, results in lower die temperatures.
Wide power traces come with the ability to sink dissipated heat. This can be improved further on multi-layer PCB
designs with vias to different planes. This results in reduced junction-to-ambient (RθJA) and junction-to-board
(RθJB) thermal resistances, thereby reducing the device junction temperature, TJ. Performing a careful system-
level 2D or full 3D dynamic thermal analysis at the beginning product design process is strongly recommended,
using a thermal modeling analysis software.
48
Copyright © 2015–2018, Texas Instruments Incorporated
LP8758-B0
www.ti.com.cn
ZHCSDQ0C –MARCH 2015–REVISED AUGUST 2018
11.2 Layout Example
Via to GND plane
Via to VIN plane
L2
COUT2
COUT3
L3
VIN
GND
CIN2
VIN
CIN3
VIN
_B2
SW
_B2
PGND
_B23
SW
_B3
VIN
_B3
CIN5
VIN
VIN
_B2
SW
_B2
PGND
_B23
SW
_B3
VIN
_B3
FB
_B2
PGND
_B23
FB
_B3
VIN
GND
CVANA
SCL
SDA
EN1
VANA
AGND
SGND
VOUT
GND
NRST
EN2
nINT
FB
_B0
PGND
_B01
FB
_B1
VIN
_B0
SW
_B0
PGND
_B01
SW
_B1
VIN
_B1
VIN
_B0
SW
_B0
PGND
_B01
SW
_B1
VIN
_B1
VIN
CIN0
VIN
Pin A1
CIN4
CIN1
GND
VIN
L0
COUT0
COUT1
L1
Figure 49. LP8758 Board Layout
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49
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ZHCSDQ0C –MARCH 2015–REVISED AUGUST 2018
www.ti.com.cn
12 器件和文档支持
12.1 器件支持
12.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
12.2 文档支持
12.2.1 相关文档
请参阅如下相关文档：
《AN-1112 DSBGA 晶圆级芯片级封装》
12.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
12.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
50
版权 © 2015–2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LP8758A1B0YFFR
ACTIVE
DSBGA
YFF
35
3000 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
-40 to 85
8758A1B0
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Sep-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LP8758A1B0YFFR
DSBGA
YFF
35
3000
180.0
8.4
2.28
3.03
0.74
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Sep-2018
*All dimensions are nominal
Device
Package Type Package Drawing Pins
DSBGA YFF 35
SPQ
Length (mm) Width (mm) Height (mm)
182.0 182.0 20.0
LP8758A1B0YFFR
3000
Pack Materials-Page 2
D: Max = 2.91 mm, Min = 2.85 mm
E: Max = 2.16 mm, Min = 2.1 mm
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