LV4066A [TI]
QUADRUPLE BILATERAL ANALOG SWITCHES; 翻两番双边模拟开关型号: | LV4066A |
厂家: | TEXAS INSTRUMENTS |
描述: | QUADRUPLE BILATERAL ANALOG SWITCHES |
文件: | 总23页 (文件大小:858K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅꢃ ꢆ ꢇ ꢇ ꢈꢉ ꢀꢁꢊ ꢃꢄꢅ ꢃꢆ ꢇꢇ ꢈ
ꢋ ꢌꢈꢍꢎ ꢌꢏꢄ ꢐ ꢑꢒ ꢄꢈꢓ ꢐꢎꢈꢄ ꢈꢁꢈ ꢄꢔ ꢕ ꢀ ꢖꢒ ꢓꢗ ꢘꢐ ꢀ
SCLS427I − APRIL 1999 − REVISED APRIL 2005
SN54LV4066A . . . J OR W PACKAGE
SN74LV4066A . . . D, DB, DGV, N, NS, OR PW PACKAGE
(TOP VIEW)
D
D
2-V to 5.5-V V
Operation
CC
Support Mixed-Mode Voltage Operation on
All Ports
1A
1B
2B
2A
2C
V
CC
1
2
3
4
5
6
7
14
13
12
11
10
9
D
D
D
D
D
High On-Off Output-Voltage Ratio
Low Crosstalk Between Switches
Individual Switch Controls
1C
4C
4A
4B
3B
3A
Extremely Low Input Current
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
3C
GND
8
SN74LV4066A . . . RGY PACKAGE
(TOP VIEW)
− 1000-V Charged-Device Model (C101)
description/ordering information
This quadruple silicon-gate CMOS analog switch
1
14
is designed for 2-V to 5.5-V V
operation.
CC
1B
2B
2A
2C
3C
13 1C
12 4C
2
3
4
5
6
These switches are designed to handle both
analog and digital signals. Each switch permits
signals with amplitudes up to 5.5 V (peak) to be
transmitted in either direction.
11
10
9
4A
4B
3B
7
8
Each switch section has its own enable-input
control (C). A high-level voltage applied to C turns
on the associated switch section.
NC − No internal connection
Applications include signal gating, chopping,
modulation or demodulation (modem), and signal
multiplexing
for
analog-to-digital
and
digital-to-analog conversion systems.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
Tube of 25
SN74LV4066AN
SN74LV4066AN
LW066A
QFN − RGY
Reel of 1000
Tube of 50
SN74LV4066ARGYR
SN74LV4066AD
SOIC − D
LV4066A
Reel of 2500
Reel of 2000
Reel of 2000
Tube of 90
SN74LV4066ADR
SN74LV4066ANSR
SN74LV4066ADBR
SN74LV4066APW
SN74LV4066APWR
SN74LV4066APWT
SN74LV4066ADGVR
SNJ54LV4066AJ
SOP − NS
74LV4066A
LW066A
−40°C to 85°C
SSOP − DB
Reel of 2000
Reel of 250
Reel of 2000
Tube of 25
TSSOP − PW
LW066A
TVSOP − DGV
CDIP − J
LW066A
SNJ54LV4066AJ
SNJ54LV4066AW
−55°C to 125°C
CFP − W
Tube of 150
SNJ54LV4066AW
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2005, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢃ ꢆ ꢇꢇ ꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅ ꢃ ꢆꢇ ꢇ ꢈ
ꢋꢌ ꢈ ꢍꢎ ꢌ ꢏꢄ ꢐ ꢑꢒ ꢄ ꢈꢓꢐ ꢎ ꢈꢄ ꢈꢁ ꢈꢄ ꢔꢕ ꢀ ꢖꢒ ꢓꢗ ꢘꢐꢀ
SCLS427I − APRIL 1999 − REVISED APRIL 2005
FUNCTION TABLE
(each switch)
INPUT
CONTROL
(C)
SWITCH
L
OFF
ON
H
logic diagram (positive logic)
A
V
CC
V
CC
B
C
One of Four Switches
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Switch I/O voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
IO
CC
Control-input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
IK
I
I/O diode current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IOK IO
On-state switch current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
T
IO
CC
CC
Continuous current through V
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
JA
(see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
(see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
(see Note 3): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢃ ꢆ ꢇ ꢇ ꢈꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢃꢆ ꢇꢇ ꢈ
ꢌꢈꢍꢎ ꢌꢏꢄ ꢐ ꢑꢒ ꢄꢈꢓ ꢐꢎꢈꢄ ꢈꢁꢈ ꢄꢔ ꢕ ꢀ ꢖꢒ ꢓꢗ ꢘꢐ ꢀ
ꢋ
SCLS427I − APRIL 1999 − REVISED APRIL 2005
recommended operating conditions (see Note 5)
SN54LV4066A
MIN MAX
SN74LV4066A
UNIT
MIN
MAX
†
†
V
V
Supply voltage
2
5.5
2
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
1.5
1.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
V
CC
V
CC
V
CC
× 0.7
× 0.7
× 0.7
V
CC
V
CC
V
CC
× 0.7
× 0.7
× 0.7
High-level input voltage, control inputs
V
IH
0.5
0.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
V
V
V
× 0.3
× 0.3
× 0.3
5.5
V
V
V
× 0.3
CC
CC
CC
CC
CC
CC
V
IL
Low-level input voltage, control inputs
V
× 0.3
× 0.3
5.5
V
V
Control input voltage
Input/output voltage
0
0
0
0
V
V
I
V
V
CC
IO
CC
V
CC
V
CC
V
CC
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
200
100
20
200
100
20
∆t/∆v Input transition rise or fall rate
Operating free-air temperature
ns/V
T
A
−55
125
−40
85
°C
†
With supply voltages at or near 2 V, the analog switch on-state resistance becomes very nonlinear. Only digital signals should be transmitted
at these low supply voltages.
NOTE 5: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
CC
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3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢃ ꢆ ꢇꢇ ꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅ ꢃ ꢆꢇ ꢇ ꢈ
ꢋꢌ ꢈ ꢍꢎ ꢌ ꢏꢄ ꢐ ꢑꢒ ꢄ ꢈꢓꢐ ꢎ ꢈꢄ ꢈꢁ ꢈꢄ ꢔꢕ ꢀ ꢖꢒ ꢓꢗ ꢘꢐꢀ
SCLS427I − APRIL 1999 − REVISED APRIL 2005
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
TYP
38
SN54LV4066A SN74LV4066A
PARAMETER
TEST CONDITIONS
= −1 mA,
UNIT
V
CC
MIN
MAX
180
150
75
MIN
MAX
225
190
100
600
225
125
40
MIN
MAX
225
190
100
600
225
125
40
2.3 V
3 V
I
T
On-state
switch resistance
V = V
or GND,
I
CC
IH
29
r
r
Ω
on
V
C
= V
4.5 V
2.3 V
3 V
21
(see Figure 1)
143
57
500
180
100
30
I
= −1 mA,
T
Peak
on-state resistance
V = V
to GND,
Ω
I
V
CC
on(p)
= V
C
IH
4.5 V
2.3 V
3 V
31
6
Difference in
on-state resistance
between switches
I = −1 mA,
T
3
20
30
30
V = V
to GND,
∆r
Ω
I
CC
on
V
C
= V
IH
4.5 V
0 to 5.5 V
2
15
20
20
I
I
Control input current V = 5.5 V or GND
0.1
1
1
µA
I
V = V
and
= GND, or
I
CC
V
O
Off-state
V = GND and
I
I
switch leakage
current
5.5 V
0.1
0.1
1
1
µA
µA
S(off)
V
O
V
C
= V
= V
,
CC
IL
(see Figure 2)
On-state
switch leakage
current
V = V or GND,
I
CC
I
I
V
= V
5.5 V
5.5 V
1
1
S(on)
C
IH
(see Figure 3)
Supply current
V = V or GND
20
20
µA
CC
I
CC
Control input
capacitance
C
C
C
1.5
5.5
0.5
pF
ic
io
F
Switch input/output
capacitance
pF
pF
Feed-through
capacitance
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4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢃ ꢆ ꢇ ꢇ ꢈꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢃꢆ ꢇꢇ ꢈ
ꢋ ꢌꢈꢍꢎ ꢌꢏꢄ ꢐ ꢑꢒ ꢄꢈꢓ ꢐꢎꢈꢄ ꢈꢁꢈ ꢄꢔ ꢕ ꢀ ꢖꢒ ꢓꢗ ꢘꢐ ꢀ
SCLS427I − APRIL 1999 − REVISED APRIL 2005
switching characteristics over recommended operating free-air temperature range,
= 2.5 V 0.2 V (unless otherwise noted)
V
CC
T = 25°C
A
SN54LV4066A SN74LV4066A
FROM
(INPUT)
TO
TEST
PARAMETER
UNIT
(OUTPUT) CONDITIONS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
t
t
Propagation
delay time
C
= 15 pF,
PLH
PHL
L
A or B
C
B or A
A or B
1.2
10
16
16
ns
(see Figure 4)
C
R
= 15 pF,
= 1 kΩ
L
L
t
t
Switch
turn-on time
PZH
PZL
3.3
15
20
20
ns
(see Figure 5)
C
R
= 15 pF,
= 1 kΩ
L
L
t
t
Switch
turn-off time
PLZ
PHZ
C
A or B
C
A or B
B or A
A or B
6
2.6
4.2
15
12
25
23
18
32
23
18
32
ns
ns
ns
(see Figure 5)
t
t
Propagation
delay time
C
= 50 pF,
PLH
PHL
L
(see Figure 4)
C
R
= 50 pF,
= 1 kΩ
L
L
t
t
Switch
turn-on time
PZH
PZL
(see Figure 5)
C
R
= 50 pF,
= 1 kΩ
L
L
t
t
Switch
turn-off time
PLZ
PHZ
C
A or B
9.6
25
32
32
ns
(see Figure 5)
switching characteristics over recommended operating free-air temperature range,
= 3.3 V 0.3 V (unless otherwise noted)
V
CC
T = 25°C
A
SN54LV4066A SN74LV4066A
FROM
(INPUT)
TO
TEST
PARAMETER
UNIT
(OUTPUT) CONDITIONS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
t
t
Propagation
delay time
C
= 15 pF,
PLH
PHL
L
A or B
C
B or A
A or B
0.8
6
10
10
ns
(see Figure 4)
C
R
= 15 pF,
= 1 kΩ
L
L
t
t
Switch
turn-on time
PZH
PZL
2.3
11
15
15
ns
(see Figure 5)
C
R
= 15 pF,
= 1 kΩ
L
L
t
t
Switch
turn-off time
PLZ
PHZ
C
A or B
C
A or B
B or A
A or B
4.5
1.5
3
11
9
15
12
22
15
12
22
ns
ns
ns
(see Figure 5)
t
t
Propagation
delay time
C
= 50 pF,
PLH
PHL
L
(see Figure 4)
C
R
= 50 pF,
= 1 kΩ
L
L
t
t
Switch
turn-on time
PZH
PZL
18
(see Figure 5)
C
R
= 50 pF,
= 1 kΩ
L
L
t
t
Switch
turn-off time
PLZ
PHZ
C
A or B
7.2
18
22
22
ns
(see Figure 5)
ꢏ
ꢎ
ꢔ
ꢍ
ꢌ
ꢗ
ꢓ
ꢏ
ꢎ
ꢐ
ꢅ
ꢒ
ꢐ
ꢖ
ꢛ
ꢣ
ꢥ
ꢞ
ꢦ
ꢡ
ꢤ
ꢙ
ꢛ
ꢞ
ꢣ
ꢟ
ꢞ
ꢣ
ꢟ
ꢢ
ꢦ
ꢣ
ꢜ
ꢧ
ꢦ
ꢞ
ꢝ
ꢠ
ꢟ
ꢙ
ꢜ
ꢛ
ꢣ
ꢙ
ꢚ
ꢢ
ꢥ
ꢞ
ꢦ
ꢡ
ꢤ
ꢙ
ꢛ
ꢯ
ꢢ
ꢞ
ꢦ
ꢝ
ꢢ
ꢜ
ꢢ
ꢤ
ꢛ
ꢟ
ꢣ
ꢮ
ꢣ
ꢧ
ꢚ
ꢣ
ꢝ
ꢤ
ꢜ
ꢜ
ꢟ
ꢢ
ꢤ
ꢞ
ꢞ
ꢥ
ꢝ
ꢢ
ꢣ
ꢯ
ꢢ
ꢮ
ꢜ
ꢩ
ꢞ
ꢞ
ꢤ
ꢢ
ꢧ
ꢩ
ꢧ
ꢡ
ꢢ
ꢓ
ꢝ
ꢣ
ꢢ
ꢠ
ꢙ
ꢪ
ꢫ
ꢟ
ꢗ
ꢚ
ꢣ
ꢛ
ꢤ
ꢜ
ꢙ
ꢦ
ꢙ
ꢚ
ꢤ
ꢟ
ꢙ
ꢡ
ꢢ
ꢦ
ꢢ
ꢣ
ꢛ
ꢣ
ꢜ
ꢙ
ꢞ
ꢙ
ꢜ
ꢙ
ꢛ
ꢟ
ꢦ
ꢟ
ꢝ
ꢤ
ꢦ
ꢙ
ꢯ
ꢤ
ꢢ
ꢤ
ꢣ
ꢢ
ꢝ
ꢞ
ꢙ
ꢚ
ꢙ
ꢢ
ꢦ
ꢜ
ꢧ
ꢛ
ꢥ
ꢛ
ꢟ
ꢤ
ꢙ
ꢛ
ꢞ
ꢦ
ꢢ
ꢝ
ꢢ
ꢠ
ꢜ
ꢛ
ꢮ
ꢜ
ꢪ
ꢤ
ꢙ
ꢜ
ꢒ
ꢦ
ꢠ
ꢢ
ꢜ
ꢢ
ꢜ
ꢙ
ꢚ
ꢦ
ꢛ
ꢮ
ꢚ
ꢙ
ꢞ
ꢟ
ꢚ
ꢮ
ꢢ
ꢞ
ꢦ
ꢛ
ꢜ
ꢣ
ꢙ
ꢛ
ꢣ
ꢢ
ꢙ
ꢚ
ꢢ
ꢦ
ꢞ
ꢜ
ꢬ
ꢞ
ꢠ
ꢙ
ꢛ
ꢢ
ꢪ
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢃ ꢆ ꢇꢇ ꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅ ꢃ ꢆꢇ ꢇ ꢈ
ꢋꢌ ꢈ ꢍꢎ ꢌ ꢏꢄ ꢐ ꢑꢒ ꢄ ꢈꢓꢐ ꢎ ꢈꢄ ꢈꢁ ꢈꢄ ꢔꢕ ꢀ ꢖꢒ ꢓꢗ ꢘꢐꢀ
SCLS427I − APRIL 1999 − REVISED APRIL 2005
switching characteristics over recommended operating free-air temperature range,
= 5 V 0.5 V (unless otherwise noted)
V
CC
T = 25°C
A
SN54LV4066A SN74LV4066A
FROM
(INPUT)
TO
TEST
PARAMETER
UNIT
(OUTPUT) CONDITIONS
MIN
TYP
MAX
MIN
MAX
MIN
MAX
t
t
Propagation
delay time
C
= 15 pF,
PLH
PHL
L
A or B
C
B or A
A or B
0.3
4
7
7
ns
(see Figure 4)
C
R
= 15 pF,
= 1 kΩ
L
L
t
t
Switch
turn-on time
PZH
PZL
1.6
7
10
10
ns
(see Figure 5)
C
R
= 15 pF,
= 1 kΩ
L
L
t
t
Switch
turn-off time
PLZ
PHZ
C
A or B
C
A or B
B or A
A or B
3.2
0.6
2.1
7
6
10
8
10
8
ns
ns
ns
(see Figure 5)
t
t
Propagation
delay time
C
= 50 pF,
PLH
PHL
L
(see Figure 4)
C
R
= 50 pF,
= 1 kΩ
L
L
t
t
Switch
turn-on time
PZH
PZL
12
16
16
(see Figure 5)
C
R
= 50 pF,
= 1 kΩ
L
L
t
t
Switch
turn-off time
PLZ
PHZ
C
A or B
5.1
12
16
16
ns
(see Figure 5)
analog switch characteristics over operating free-air temperature range (unless otherwise noted)
T
A
= 25°C
TYP MAX
30
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
PARAMETER
V
UNIT
CC
MIN
2.3 V
3 V
C
f
= 50 pF, R = 600 Ω,
= 1 MHz (sine wave)
20log (V /V ) = −3 dB (see Figure 6)
L
in
L
Frequency response
(switch on)
35
A or B
A or B
C
B or A
B or A
A or B
B or A
MHz
10
O
I
4.5 V
2.3 V
3 V
50
−45
−45
−45
15
Crosstalk
(between any switches)
C
= 50 pF, R = 600 Ω,
= 1 MHz (sine wave) (see Figure 7)
L
L
L
L
dB
mV
dB
f
in
4.5 V
2.3 V
3 V
Crosstalk
(control input to
signal output)
C
= 50 pF, R = 600 Ω,
= 1 MHz (square wave) (see Figure 8)
L
20
f
in
4.5 V
2.3 V
3 V
50
−40
−40
−40
0.1
Feed-through attenuation
(switch off)
C
= 50 pF, R = 600 Ω, f = 1 MHz
in
L
A or B
(see Figure 9)
4.5 V
2.3 V
V = 2 V
p-p
I
C = 50 pF, R = 10 kΩ,
L
L
Sine-wave distortion
A or B
B or A
3 V
0.1
0.1
%
V = 2.5 V
I p-p
f
in
= 1 kHz (sine wave)
(see Figure 10)
4.5 V
V = 4 V
I p-p
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
= 50 pF, f = 10 MHz
L
TYP
UNIT
C
Power dissipation capacitance
C
4.5
pF
pd
ꢏ
ꢎ
ꢔ
ꢍ
ꢌ
ꢗ
ꢓ
ꢏ
ꢎ
ꢐ
ꢅ
ꢒ
ꢐ
ꢖ
ꢛ
ꢣ
ꢥ
ꢞ
ꢦ
ꢡ
ꢤ
ꢙ
ꢛ
ꢞ
ꢣ
ꢟ
ꢞ
ꢣ
ꢟ
ꢢ
ꢦ
ꢣ
ꢜ
ꢧ
ꢦ
ꢞ
ꢝ
ꢠ
ꢟ
ꢝ ꢢ ꢜ ꢛ ꢮ ꢣ ꢧꢚ ꢤ ꢜ ꢢ ꢞꢥ ꢝꢢ ꢯ ꢢ ꢩ ꢞꢧ ꢡꢢ ꢣ ꢙꢪ ꢗ ꢚꢤ ꢦꢤ ꢟꢙ ꢢꢦ ꢛꢜ ꢙꢛ ꢟ ꢝꢤ ꢙꢤ ꢤꢣ ꢝ ꢞꢙ ꢚꢢꢦ
ꢙ
ꢜ
ꢛ
ꢣ
ꢙ
ꢚ
ꢢ
ꢥ
ꢞ
ꢦ
ꢡ
ꢤ
ꢙ
ꢛ
ꢯ
ꢢ
ꢞ
ꢦ
ꢜ
ꢧ
ꢢ
ꢟ
ꢛ
ꢥ
ꢛ
ꢟ
ꢤ
ꢙ
ꢛ
ꢞ
ꢣ
ꢜ
ꢤ
ꢦ
ꢢ
ꢝ
ꢢ
ꢜ
ꢛ
ꢮ
ꢣ
ꢮ
ꢞ
ꢤ
ꢩ
ꢜ
ꢪ
ꢓ
ꢢ
ꢫ
ꢤ
ꢜ
ꢒ
ꢣ
ꢜ
ꢙ
ꢦ
ꢠ
ꢡ
ꢢ
ꢣ
ꢟ ꢚ ꢤ ꢣ ꢮꢢ ꢞꢦ ꢝꢛ ꢜ ꢟ ꢞꢣ ꢙꢛ ꢣꢠ ꢢ ꢙ ꢚꢢ ꢜ ꢢ ꢧꢦ ꢞ ꢝꢠꢟ ꢙꢜ ꢬ ꢛꢙꢚ ꢞꢠꢙ ꢣꢞꢙ ꢛꢟꢢ ꢪ
ꢙ
ꢜ
ꢦ
ꢢ
ꢜ
ꢢ
ꢦ
ꢯ
ꢢꢜ
ꢙ
ꢚ
ꢢ
ꢦ
ꢛ
ꢮ
ꢚ
ꢙ
ꢙ
ꢞ
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢃ ꢆ ꢇ ꢇ ꢈꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢃꢆ ꢇꢇ ꢈ
ꢋ ꢌꢈꢍꢎ ꢌꢏꢄ ꢐ ꢑꢒ ꢄꢈꢓ ꢐꢎꢈꢄ ꢈꢁꢈ ꢄꢔ ꢕ ꢀ ꢖꢒ ꢓꢗ ꢘꢐ ꢀ
SCLS427I − APRIL 1999 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
V
C
= V
IH
V
CC
V = V
I CC or GND
V
O
(ON)
GND
VI – VO
10–3
ron
+
W
1 mA
V
V − V
I
O
Figure 1. On-State Resistance Test Circuit
V
CC
V
C
= V
IL
V
CC
A
V
I
V
O
(OFF)
GND
Condition 1: V = 0, V = V
CC
I
O
Condition 2: V = V , V = 0
I
CC
O
Figure 2. Off-State Switch Leakage-Current Test Circuit
V
CC
V
C
= V
IH
V
CC
A
V
I
Open
(ON)
GND
V = V
I CC
or GND
Figure 3. On-State Leakage-Current Test Circuit
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢃ ꢆ ꢇꢇ ꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅ ꢃ ꢆꢇ ꢇ ꢈ
ꢋꢌ ꢈ ꢍꢎ ꢌ ꢏꢄ ꢐ ꢑꢒ ꢄ ꢈꢓꢐ ꢎ ꢈꢄ ꢈꢁ ꢈꢄ ꢔꢕ ꢀ ꢖꢒ ꢓꢗ ꢘꢐꢀ
SCLS427I − APRIL 1999 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
V
C
= V
IH
V
CC
V
O
V
I
(ON)
GND
50 Ω
C
L
TEST CIRCUIT
t
t
f
r
V
CC
V
90%
50%
10%
90%
50%
I
A or B
10%
0 V
t
t
PHL
PLH
V
V
OH
V
O
50%
50%
B or A
OL
VOLTAGE WAVEFORMS
Figure 4. Propagation Delay Time, Signal Input to Signal Output
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢃ ꢆ ꢇ ꢇ ꢈꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢃꢆ ꢇꢇ ꢈ
ꢋ ꢌꢈꢍꢎ ꢌꢏꢄ ꢐ ꢑꢒ ꢄꢈꢓ ꢐꢎꢈꢄ ꢈꢁꢈ ꢄꢔ ꢕ ꢀ ꢖꢒ ꢓꢗ ꢘꢐ ꢀ
SCLS427I − APRIL 1999 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
TEST
S1
S2
50 Ω
t
t
t
t
GND
V
CC
GND
PZL
PZH
V
C
V
GND
CC
V
GND
V
CC
PLZ
CC
R
= 1 kΩ
V
CC
L
PHZ
V
V
O
I
S1
S2
C
L
GND
TEST CIRCUIT
V
CC
V
CC
V
C
50%
50%
0 V
0 V
t
t
PZH
PZL
≈V
CC
V
OH
V
O
50%
50%
V
OL
≈0 V
(t
, t )
PZL PZH
V
CC
V
CC
V
C
50%
50%
0 V
0 V
t
t
PHZ
PLZ
≈V
CC
V
OH
V
OH
− 0.3 V
V
O
V
OL
+ 0.3 V
V
≈0 V
OL
(t
, t )
PLZ PHZ
VOLTAGE WAVEFORMS
Figure 5. Switching Time (t
, t
t
, t
), Control to Signal Output
PZL PLZ, PZH PHZ
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢃ ꢆ ꢇꢇ ꢈ ꢉ ꢀ ꢁꢊ ꢃ ꢄꢅ ꢃ ꢆꢇ ꢇ ꢈ
ꢋꢌ ꢈ ꢍꢎ ꢌ ꢏꢄ ꢐ ꢑꢒ ꢄ ꢈꢓꢐ ꢎ ꢈꢄ ꢈꢁ ꢈꢄ ꢔꢕ ꢀ ꢖꢒ ꢓꢗ ꢘꢐꢀ
SCLS427I − APRIL 1999 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
V
CC
0.1 µF
V
CC
V
I
f
V
in
50 Ω
(ON)
GND
O
R
= 600 Ω
C = 50 pF
L
L
V
CC
/2
Figure 6. Frequency Response (Switch On)
V
CC
V
C
= V
CC
V
CC
V
I
f
V
in
50 Ω
(ON)
GND
O1
C = 50 pF
L
600 Ω
0.1 µF
R
= 600 Ω
L
V
CC
/2
V
I
V
CC
V
C
= GND
V
CC
(OFF)
GND
V
O2
C
= 50 pF
R
= 600 Ω
L
600 Ω
L
V
CC
/2
Figure 7. Crosstalk Between Any Two Switches
V
CC
V
C
50 Ω
V
CC
V
O
GND
R
= 600 Ω
C = 50 pF
L
600 Ω
L
V
CC
/2
V
CC
/2
Figure 8. Crosstalk (Control Input − Switch Output)
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢃ ꢆ ꢇ ꢇ ꢈꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢃꢆ ꢇꢇ ꢈ
ꢋ ꢌꢈꢍꢎ ꢌꢏꢄ ꢐ ꢑꢒ ꢄꢈꢓ ꢐꢎꢈꢄ ꢈꢁꢈ ꢄꢔ ꢕ ꢀ ꢖꢒ ꢓꢗ ꢘꢐ ꢀ
SCLS427I − APRIL 1999 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
V
C
= GND
0.1 µF
V
CC
V
I
f
in
V
O
(OFF)
GND
50 Ω
600 Ω
C
= 50 pF
R
= 600 Ω
L
L
V
CC
/2
V
CC
/2
Figure 9. Feed-Through Attenuation (Switch Off)
V
CC
V
C
= V
CC
10 µF
10 µF
V
CC
V
I
f
in
600 Ω
V
(ON)
GND
O
C
= 50 pF
R
= 10 kΩ
L
L
V
CC
/2
Figure 10. Sine-Wave Distortion
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
SN74LV4066AD
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV4066ADBR
SN74LV4066ADBRG4
SN74LV4066ADE4
SN74LV4066ADGVR
SN74LV4066ADGVRE4
SN74LV4066ADR
SSOP
SSOP
SOIC
DB
DB
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TVSOP
TVSOP
SOIC
DGV
DGV
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV4066ADRE4
SN74LV4066AN
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74LV4066ANE4
SN74LV4066ANSR
SN74LV4066ANSRE4
SN74LV4066APW
PDIP
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SO
NS
NS
PW
PW
PW
PW
PW
PW
PW
PW
PW
RGY
RGY
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
QFN
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV4066APWE4
SN74LV4066APWG4
SN74LV4066APWR
SN74LV4066APWRE4
SN74LV4066APWRG4
SN74LV4066APWT
SN74LV4066APWTE4
SN74LV4066APWTG4
SN74LV4066ARGYR
SN74LV4066ARGYRG4
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
QFN
1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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