MCT8317A [TI]
24V 最大电压、5A 峰值电流无传感器梯形控制三相 BLDC 电机驱动器;
| 型号： | MCT8317A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 24V 最大电压、5A 峰值电流无传感器梯形控制三相 BLDC 电机驱动器 电机 驱动 传感器 驱动器 |
| 文件： | 总164页 (文件大小：4176K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCT8317A
ZHCSQ32 –JANUARY 2023
MCT8317A 高速无传感器梯形控制集成FET BLDC 驱动器
1 特性
3 说明
• 采用集成无传感器电机控制算法的三相BLDC 电机
驱动器
MCT8317A 为需要高速运行（高达 3kHz 电气）或极
快启动速度 (< 50ms) 的客户提供了一个单芯片无代码
无传感器梯形解决方案，此解决方案适用于峰值电流高
达 5A 的 12V 无刷直流电机。MCT8317A 集成了三个
½ 桥，具有 24V 的绝对最大电压和 130mΩ 的极低
RDS(ON)（高侧+ 低侧FET）。MCT8317A 还具有一个
LDO，可生成 3.3V 电压轨，并可提供高达 20mA 的电
流为外部电路供电。
– 无代码高速梯形控制
– 支持高达3kHz（电气频率）
– 非常短的启动时间(< 50ms)
– 快速减速(< 150ms)
– 支持120° 或150° 调制，以改善声学性能
– 闭环速度或功率控制
– 用于速度或功率输入基准的可配置配置文件
– 通过正向重新同步和反向驱动支持风力机
– 模拟，PWM，频率或基于I2C 的速度输入
– 可配置的电机启动和停止选项
– 抗电压浪涌(AVS) 保护可防止电机减速期间出现
直流总线电压尖峰
无传感器梯形控制可通过寄存器设置进行多种配置，范
围从电机启动行为到闭环运行。MCT8317A 的寄存器
设置可在非易失性EEPROM 中设置，从而允许器件在
配置后独立运行。该器件通过PWM 输入、模拟电压、
可变频率方波或 I2C 命令接收速度命令。MCT8317A,
集成多种保护特性，旨在出现故障事件时保护该器件、
电机和系统。
– 通过DACOUT 进行变量监控
• 4.5V 至20V 工作电压（绝对最大值24V）
• 高输出电流能力：5A 峰值
器件信息(1)
• 低MOSFET 导通状态电阻
封装尺寸（标称值）
器件型号
封装
WQFN (36)
– TA = 25°C 时的RDS(ON) (HS + LS)：130mΩ
• 低功耗睡眠模式
MCT8317A0I
5.00mm × 4.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– VVM = 12V、TA = 25°C 时为7µA（最大值）
• 速度环路精度：3% 使用内部时钟，1% 使用外部时
钟参考
参考文档：
• 支持高达100kHz 的PWM 频率，以支持低电感电
机
• 请参阅MCT8317A EVM GUI
LDO out
3.3-V, up to 20-mA
4.5 to 20-V (24-V abs max)
• 不需要外部电流检测电阻器
• 内置3.3V ±5%、20mA LDO 稳压器
• 展频和压摆率，用于降低EMI
• 整套集成保护特性
SPEED
PWM, analog, frequency or
MCT8317A
A
B
C
commanded over I2C
DIRECTION
Sensorless
Trap
BRAKE
A
FG
Speed feecback
– 电源欠压锁定(UVLO)
– 电机锁定检测（5 种不同类型）
– 过流保护(OCP)
– 过热警告和关断(OTW/OTS)
– 故障条件指示引脚(nFAULT)
– 可选择通过I2C 接口进行故障诊断
EEPROM
nFAULT
I2C
Op onal during opera on
for I2C speed, diagnos cs,
or on-the- y con gura on
LDO Regulator
5-A peak output current,
typically 12-V
Integrated Current Sensing
DACOUTx
Op onal real- me variable
monitoring, 12-bit DAC
简化版原理图
2 应用
• 无刷直流(BLDC) 电机模块
• 机器人真空吸水电机
• 服务器风扇
• 电器风扇和泵
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSFQ2
MCT8317A
ZHCSQ32 –JANUARY 2023
www.ti.com.cn
Table of Contents
8.6 EEPROM access and I2C interface.......................... 68
8.7 EEPROM (Non-Volatile) Register Map..................... 74
8.8 RAM (Volatile) Register Map...................................128
9 Application and Implementation................................145
9.1 Application Information........................................... 145
9.2 Typical Applications................................................ 145
10 Power Supply Recommendations............................153
10.1 Bulk Capacitance..................................................153
11 Layout.........................................................................154
11.1 Layout Guidelines................................................. 154
11.2 Layout Example.................................................... 155
11.3 Thermal Considerations........................................156
12 Device and Documentation Support........................157
12.1 支持资源................................................................157
12.2 Trademarks...........................................................157
12.3 静电放电警告........................................................ 157
12.4 术语表................................................................... 157
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings............................................................... 6
7.3 Recommended Operating Conditions.........................6
7.4 热性能信息..................................................................7
7.5 Electrical Characteristics.............................................7
7.6 Characteristics of the SDA and SCL bus for
Standard and Fast mode.............................................14
8 Detailed Description......................................................17
8.1 Overview...................................................................17
8.2 Functional Block Diagram.........................................18
8.3 Feature Description...................................................19
8.4 Device Functional Modes..........................................66
8.5 External Interface......................................................66
Information.................................................................. 157
13.1 Tape and Reel Information....................................158
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
DATE
REVISION
NOTES
January 2023
*
Initial Release
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5 Device Comparison Table
表5-1. Differences between PMCT8317 and MCT8317
Parameter
PMCT8317A0I
MCT8317A0I
Over Temperature Warning
Over Temperature Warning Response
Not EEPROM configurable; always enabled
EEPROM configurable
FETs are in Hi-Z, reported on nFAULT and
GATE_DRIVER_FAULT_STATUS bits
FETs are Active, reported on nFAULT and
GATE_DRIVER_FAULT_STATUS bits
Over Voltage Fault Mode
One mode: FETs are in Hi-Z, reported on
nFAULT and
Two modes configurable through EEPROM :
1. FETs are in Hi-Z, reported on nFAULT and
GATE_DRIVER_FAULT_STATUS bits when GATE_DRIVER_FAULT_STATUS bits when
VM > VOVP (rising)
VM > VOVP (rising)
2.
1. FETs are Active, reported on nFAULT and
GATE_DRIVER_FAULT_STATUS bits when
VM > VOVP (rising)
Brake during ISD
Time based brake
Time or current based brake - EEPROM
configurable option
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6 Pin Configuration and Functions
36 35 34 33 32 31 30 29
DVDD
DGND
AVDD
1
2
3
4
5
6
7
8
9
10
28
27 SCL
DIR
SDA
26
25
24
CPL
CPH
FG
SPEED/WAKE
CP
23 AVDD
VIN_AVDD
VM
AGND
VM
22
21
20
VM
VM
Thermal Pad
PGND
19 PGND
11 12 13 14 15 16 17 18
图6-1. MCT8317A 36-pin WQFN with Exposed Thermal Pad Top View
表6-1. Pin Functions
40-pin
PIN
TYPE(1)
DESCRIPTION
Package
MCT8317A
22
NAME
AGND
GND
Device analog ground.
3.3-V internal regulator output. Connect a X5R or X7R, 2.2-µF (no load) or 4.7-µF (up to 20
mA load), 6.3-V ceramic capacitor between the AVDD1 and AGND pins. This regulator can
source up to 20 mA externally.
AVDD
23
PWR O
High →Brake the motor
Low →Normal motor operation
If BRAKE pin is not used, connect to AGND directly.
BRAKE
CP
31
6
I
If BRAKE pin is used to brake the motor, use an external 100-kΩ pull-down resistor (to
AGND).
Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the CP
and VM pins.
PWR
CPH
CPL
5
4
PWR
PWR
Charge pump switching node. Connect a X5R or X7R, 100-nF, ceramic capacitor between the
CPH and CPL pins. TI recommends a capacitor voltage rating at least twice the normal
operating voltage of the device.
Multipurpose pin:
DAC output when configured as DACOUT2
CSA output configured as SOX
DACOUT2/S
OX
32
O
DACOUT1
DACOUT2
DGND
34
33
2
O
O
DAC output DACOUT1
DAC output DACOUT2
GND
Device digital ground. Refer Layout Guidelines for connections recommendation.
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表6-1. Pin Functions (continued)
40-pin
Package
PIN
TYPE(1)
DESCRIPTION
NAME
MCT8317A
Direction of motor spinning;
When low, phase driving sequence is OUT A →OUT C →OUT B
When high, phase driving sequence is OUT A →OUT B →OUT C
If DIR pin is not used, connect to AGND or AVDD directly (depending on phase driving
DIR
28
I
sequence needed).
If DIR pin is used for changing motor spin direction, use an external 100-kΩ pull-down resistor
(to AGND).
1.5-V internal regulator output. Connect a X5R or X7R, 2.2-µF, 6.3-V ceramic capacitor
between the DVDD and DGND pins.
DVDD
1
PWR
EXT_CLK
EXT_WD
30
29
I
I
External clock reference input in external clock reference mode.
External watchdog input.
Motor speed indicator output. Open-drain output requires an external pull-up resistor to 1.8-V
to 5-V.
FG
25
-
O
I
ILIMIT
nFAULT
Connect resistor to AGND for parameter configuration.
Fault indicator. Pulled logic-low with fault condition; Open-drain output requires an external
pull-up resistor to 1.8-V to 5-V.
36
O
OUTA
OUTB
OUTC
PGND
SCL
11,12
14, 15
17, 18
10, 13, 16, 19
27
PWR O
PWR O
PWR O
GND
I
Half-bridge output A
Half-bridge output B
Half-bridge output C
Device power ground.
I2C clock input
SDA
26
I/O
I2C data line
SPEED/
WAKE
Device speed input; supports analog, frequency or PWM speed input. The speed pin input
can be configured through SPD_CTRL_MODE.
24
7
I
VIN_AVDD
PWR I
Input supply for AVDD LDO
Device and motor power supply. Connect to motor supply voltage; bypass to PGND with a
0.1-µF capacitor plus one bulk capacitor. TI recommends a capacitor voltage rating at least
twice the normal operating voltage of the device.
VM
8, 9, 20, 21
PWR I
GND
Thermal pad
Must be connected to AGND
(1) I = input, O = output, GND = ground pin, PWR = power, NC = no connect
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7 Specifications
7.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
MIN
MAX UNIT
Power supply pin voltage (VM, VIN_AVDD)
Power supply voltage ramp during power up (VM)
Voltage difference between ground pins (DGND,PGND, AGND)
Charge pump voltage (CP)
24
V
V/µs
V
–0.3
4
0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–1
VM + 6
V
Analog regulator pin voltage (AVDD)
Digital regulator pin voltage (DVDD)
4
V
2
V
Logic pin input voltage (DIR, SPEED, BRAKE, SDA, SCL)
Open drain pin output voltage (nFAULT ,FG)
Output pin voltage (OUTA, OUTB, OUTC)
Ambient temperature, TA
6
6
V
V
VM + 1 (2)
125
V
°C
°C
°C
–40
–40
–65
Junction temperature, TJ
150
Storage tempertaure, Tstg
150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime
(2) Maximum voltage supported on OUTx pin is 24V
7.2 ESD Ratings
VALUE
±2500
±750
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX UNIT
VVM
Power supply voltage
VVM, VVIN_AVDD
4.5
12
20
5
V
A
VVM ≥6 V, OUTA, OUTB, OUTC
4.5 V ≤VVM < 6 V, OUTA, OUTB, OUTC
SPEED, SDA, SCL
(1)
IOUT
Peak output winding current
3
A
VIN_LOGIC
VOD
IOD
Logic input voltage
5.5
5.5
5
V
–0.3
–0.3
Open drain pullup voltage
nFAULT, FG
V
Open drain output current capability
Operating ambient temperature
Operating Junction temperature
nFAULT, FG
mA
°C
°C
TA
125
150
–40
–40
TJ
(1) Power dissipation and thermal limits must be observed
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7.4 热性能信息
MCT8317A
热指标(1)
REE (WQFN)
36
单位
RθJA
36.6
22.2
14.7
3.4
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
结至环境热阻（JEDEC 4 层PCB，6 个散热孔）
结至外壳（顶部）热阻
结至电路板热阻
RθJC(top)
RθJB
ΨJT
结至顶部特征参数
14.7
4.5
ΨJB
结至电路板特征参数
RθJC(bot)
结至外壳（底部）热阻
(1) 有关新旧热指标的更多信息，请参阅半导体和IC 封装热指标应用报告。
7.5 Electrical Characteristics
TJ = –40°C to +150°C, VVM = 4.5 to 20 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 12 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER SUPPLIES
5
7
µA
µA
V
V
SPEED ≤VIL (Max), TA = 25 °C
SPEED ≤VIL (Max) TA = 125 °C
IVMQ
VM sleep mode current
15
20
[DEV_MODE = 1b (Sleep Mode) with
VSPEED > VIH(Min), I2C Speed command
= 0] or [DEV_MODE = 0b (Standby
Mode) with VSPEED ≤VIL (Max) or I2C
speed command = 0]
IVMS
VM standby mode current
25
28
30
mA
mA
VSPEED > VIH (Min) in PWM mode or
non-zero speed command in I2C mode,
Output PWM Freq = 25 kHz, TA = 25 °C,
No Motor Connected
25
25
IVM
VM operating mode current
VSPEED > VIH (Min) in PWM mode or
non-zero speed command in I2C mode,
Output PWM Freq = 25 kHz, No Motor
Connected
30
mA
V
VVM ≥6 V, VVIN_AVDD ≥6 V, 0 mA ≤
3.15
3.15
3.3
3.3
3.45
IAVDD ≤20 mA, including voltage, temp,
load and line transients
VAVDD
Analog regulator voltage
4.5 V ≤VVM < 6 V, 4.5 V ≤VVIN_AVDD
6 V, 0 mA ≤IAVDD ≤20 mA, including
voltage, temp, load and line transients
<
<
3.45
20
V
4.5 V ≤VVM < 6 V, 4.5 V ≤VVIN_AVDD
Analog regulator external load
mA
6 V
IAVDD
Analog regulator external load
Analog regulator current limit
20
150
mA
mA
uF
VVM ≥6V, VVIN_AVDD ≥6V
IAVDD_LIM
CAVDD
100
0.5
125
2.2
4.7
V
AVDD ≥2.7V, soft short to GND
External load IAVDD = 0 mA
7.05
7.05
Capacitance for AVDD
Digital regulator voltage
2.35
uF
External load 0mA ≤IAVDD ≤20 mA
No External load, including voltage,
temp, load and line transients
VDVDD
1.45
1.55
1.65
V
IDVDD
External digital regulator load
Capacitance for DVDD
No Load
7.05
mA
uF
CDVDD
External load IDVDD = 0 mA
0.6
3
2.2
5
4.2 V ≤VVM < 6 V, CP with respect to
VM
5.5
5.5
V
VCP
Charge pump regulator voltage
Charge pump switching frequency
4.5
5
V
VVM ≥6V, CP with respect to VM
fCP
400
kHz
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TJ = –40°C to +150°C, VVM = 4.5 to 20 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 12 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
DRIVER OUTPUTS
130
180
157
V
V
VM ≥6 V, IOUT = 1 A, TJ = 25°C
VM ≥6 V, IOUT = 1 A, TJ = 125°C
mΩ
mΩ
Total MOSFET on resistance (High-side
+ Low-side)
RDS(ON)
221.5
4.5 V ≤VVM < 6 V, IOUT = 1 A, TJ =
25°C
155
225
210
290
mΩ
mΩ
Total MOSFET on resistance (High-side
+ Low-side)
RDS(ON)
4.5 V ≤VVM < 6 V, IOUT = 1 A, TJ =
125°C
VVM = 12V, SLEW_RATE = 00b
VVM = 12V, SLEW_RATE = 01b
VVM = 12V, SLEW_RATE = 10b
VVM = 12V, SLEW_RATE = 11b
VVM = 12V, SLEW_RATE = 00b
VVM = 12V, SLEW_RATE = 01b
VVM = 12V, SLEW_RATE = 10b
VVM = 12V, SLEW_RATE = 11b
VVM = VOUTx = 20 V, Standby State
VOUTx = 0 V, Standby State
13.75
27.5
62.5
80
25
50
36.25
72.5
187.5
320
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
V/µs
mA
Phase pin slew rate switching low to high
(Rising from 20 % to 80 % of VM)
SR_RISE
SR_FALL
125
200
25
13.75
27.5
62.5
80
36.25
72.5
187.5
320
50
Phase pin slew rate switching high to low
(Falling from 80 % to 20 % of VM)
125
200
0.7
-10
575
325
250
250
ILEAK
ILEAK
Leakage current OUTx
Leakage current OUTx
2
-50
µA
VVM = 12V, SLEW_RATE = 00b
VVM = 12V, SLEW_RATE = 01b
VVM = 12V, SLEW_RATE = 10b
VVM = 12V, SLEW_RATE = 11b
1500
1400
1300
1200
ns
ns
Driver output dead time (high to low / low
to high)
tDRV_DEAD
ns
ns
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TJ = –40°C to +150°C, VVM = 4.5 to 20 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 12 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VVM = 12 V; HS driver ON to LS driver
OFF; DIG_DEAD_TIME = 0001b,
50
55
110
165
220
275
330
385
440
495
550
660
770
880
990
1100
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VVM = 12 V; HS driver ON to LS driver
OFF; DIG_DEAD_TIME = 0010b,
100
150
200
250
300
350
400
450
500
600
700
800
900
1000
VVM = 12 V; HS driver ON to LS driver
OFF; DIG_DEAD_TIME = 0011b,
VVM = 12 V; HS driver ON to LS driver
OFF; DIG_DEAD_TIME = 0100b,
VVM = 12 V; HS driver ON to LS driver
OFF; DIG_DEAD_TIME = 0101b,
VVM = 12 V; HS driver ON to LS driver
OFF; DIG_DEAD_TIME = 0110b,
VVM = 12 V; HS driver ON to LS driver
OFF; DIG_DEAD_TIME = 0111b,
tDIG_DEAD_TI Gate input signal dead time from digital VVM = 12 V; HS driver ON to LS driver
controller (high to low / low to high)
OFF; DIG_DEAD_TIME = 1000b,
ME
VVM = 12 V; HS driver ON to LS driver
OFF; DIG_DEAD_TIME = 1001b,
VVM = 12 V; HS driver ON to LS driver
OFF; DIG_DEAD_TIME = 1010b,
VVM = 12 V; HS driver ON to LS driver
OFF; DIG_DEAD_TIME = 1011b,
VVM = 12 V; HS driver ON to LS driver
OFF; DIG_DEAD_TIME = 1100b,
VVM = 12 V; HS driver ON to LS driver
OFF; DIG_DEAD_TIME = 1101b,
VVM = 12 V; HS driver ON to LS driver
OFF; DIG_DEAD_TIME = 1110b,
VVM = 12 V; HS driver ON to LS driver
OFF; DIG_DEAD_TIME = 1111b,
SLEEP MODE
VEN_SL Analog voltage to enter sleep mode
VEX_SL
SPD_CTRL_MODE = 00b (analog
mode)
40
mV
V
SPD_CTRL_MODE = 00b (analog
mode)
Analog voltage to exit sleep mode
2.2
0.5
SPD_CTRL_MODE = 00b (analog
mode)
VSPEED > VEX_SL
Time needed to detect wake up signal on
SPEED pin
tDET_ANA
1
3
1.5
5
μs
VSPEED > VEX_SL to DVDD voltage
available, SPD_CTRL_MODE = 01b
(PWM mode)
tWAKE
Wakeup time from sleep mode
ms
SPD_CTRL_MODE = 00b (analog
mode)
VSPEED > VEN_SL, ISD detection disabled
tEX_SL_DR_A Time taken to drive motor after exiting
20
1.5
5
ms
μs
ms
ms
from sleep mode
NA
Time needed to detect wake up signal on SPD_CTRL_MODE = 01b (PWM mode)
tDET_PWM
0.5
1
3
SPEED pin
VSPEED > VIH
VSPEED > VIH to DVDD voltage available
and release nFault, SPD_CTRL_MODE
= 01b (PWM mode)
tWAKE_PWM Wakeup time from sleep mode
tEX_SL_DR_P Time taken to drive motor after wakeup SPD_CTRL_MODE = 01b (PWM mode)
20
from sleep state
VSPEED > VIH, ISD detection disabled
WM
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TJ = –40°C to +150°C, VVM = 4.5 to 20 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 12 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SPD_CTRL_MODE = 00b (analog
mode)
VSPEED < VEN_SL , SLEEP_TIME = 00b
0.035
0.05
0.065
0.26
26
ms
ms
ms
ms
ms
ms
ms
SPD_CTRL_MODE = 00b (analog
mode)
VSPEED < VEN_SL , SLEEP_TIME = 01b
0.14
14
0.2
20
tDET_SL_ANA Time needed to detect sleep command
SPD_CTRL_MODE = 00b (analog
mode)
VSPEED < VEN_SL , SLEEP_TIME = 10b
SPD_CTRL_MODE = 00b (analog
mode)
VSPEED < VEN_SL , SLEEP_TIME = 11b
140
0.035
0.14
14
200
0.05
0.2
20
260
0.065
0.26
26
SPD_CTRL_MODE = 01b (PWM mode)
or 11b (Freq mode)
VSPEED < VIL, SLEEP_TIME = 00b
SPD_CTRL_MODE = 01b (PWM mode)
or 11b (Freq mode)
VSPEED < VIL, SLEEP_TIME = 01b
tDET_SL_PWM Time needed to detect sleep command
SPD_CTRL_MODE = 01b (PWM mode)
or 11b (Freq mode)
VSPEED < VIL, SLEEP_TIME = 10b
SPD_CTRL_MODE = 01b (PWM mode)
or 11b (Freq mode)
VSPEED < VIL, SLEEP_TIME = 11b
140
200
1
260
2
ms
ms
Time needed to stop driving motor after VSPEED < VEN_SL (analog mode) or
tEN_SL
detecting sleep command
VSPEED < VIL (PWM mode)
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TJ = –40°C to +150°C, VVM = 4.5 to 20 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 12 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
STANDBY MODE
SPD_CTRL_MODE = 00b (analog
mode)
VSPEED > VEN_SB, ISD detection disabled
tEX_SB_DR_A Time taken to drive motor after exiting
6
6
2
ms
ms
ms
standby mode
NA
tEX_SB_DR_P Time taken to drive motor after exiting
SPD_CTRL_MODE = 01b (PWM mode)
VSPEED > VIH, ISD detection disabled
standby mode
WM
SPD_CTRL_MODE = 00b (analog
mode)
VSPEED < VEN_SB
tDET_SB_ANA Time needed to detect standby mode
0.5
0.035
0.14
14
1
0.05
0.2
SPD_CTRL_MODE = 01b (PWM mode)
or 11b (Freq mode)
VSPEED < VIL, SLEEP_TIME = 00b
0.065
0.26
26
ms
ms
ms
SPD_CTRL_MODE = 01b (PWM mode)
or 11b (Freq mode)
VSPEED < VIL, SLEEP_TIME = 01b
Time needed to detect standby
tEN_SB_PWM
command
SPD_CTRL_MODE = 01b (PWM mode)
or 11b (Freq mode)
20
VSPEED < VIL, SLEEP_TIME = 10b
SPD_CTRL_MODE = 01b (PWM mode)
or 11b (Freq mode)
VSPEED < VIL, SLEEP_TIME = 11b
140
200
1
260
2
ms
ms
ms
SPD_CTRL_MODE = 10b (I2C mode),
SPEED_CMD = 0
tEN_SB_DIG
Time needed to detect standby mode
VSPEED < VEN_SL (analog mode) or
VSPEED < VDIG_IL (PWM mode) or
SPEED_CMD = 0 (I2C mode)
Time needed to stop driving motor after
detecting standby command
tEN_SB
1
2
LOGIC-LEVEL INPUTS (DIR, SPEED)
0.25*AV
DD
VIL
VIH
Input logic low voltage
Input logic high voltage
AVDD = 3 to 3.6 V
AVDD = 3 to 3.6 V
V
V
0.65*AV
DD
VHYS
IIL
Input hysteresis
110
0
400
0.1
mV
µA
µA
µA
Input logic low current
AVDD = 3 to 3.6 V
AVDD < VPIN
-5
IIH
Input logic high current
-0.1
900
0
AVDD≥VPIN
RPD_SPEED Input pulldown resistance
SPEED pin To GND
1000
1100
kΩ
OPEN-DRAIN OUTPUTS (nFAULT, FG, etc)
VOL
Output logic low voltage
IOD = -5 mA
VOD = 3.3 V
0.4
0.5
V
IOZ
Output logic high current
0
µA
I2C Serial Interface
0.3*AVD
D
VI2C_L
Low-level input voltage
-0.5
mV
mV
mV
0.7*AVD
D
VI2C_H
High-level input voltage
Hysteresis
0.05*AV
DD
VI2C_HYS
VI2C_OL
II2C_OL
II2C_IL
Ci
Low-level output voltage
open-drain at 2 mA sink current
VI2C_OL = 0.6V
0
0.4
6
V
mA
µA
pF
ns
Low-level output current
Input current on SDA and SCL
Capacitance for SDA and SCL
-10
10
TJ = -40 to +150 ℃
10
Standard Mode
Fast Mode
250
250
Output fall time from VI2C_H(min) to
VI2C_L(max)
tof
ns
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TJ = –40°C to +150°C, VVM = 4.5 to 20 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 12 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Pulse width of spikes that must be
suppressed by the input filter
tSP
Fast Mode
0
50
ns
SPEED INPUT - PWM MODE
PWM input frequency
PWM input resolution
PWM input resolution
PWM input resolution
PWM input resolution
0.01
11
12
11
13
12
11
10
8
100
13
14
15
14
13
12
11
kHz
bits
bits
bits
bits
bits
bits
bits
bits
ƒPWM
ResPWM
ResPWM
ResPWM
ResPWM
fPWM = 0.01 to 0.35 kHz
fPWM = 0.350 to 2 kHz
fPWM = 2 to 3.5 kHz
fPWM = 3.5 to 7 kHz
fPWM = 7 to 14 kHz
12
13
14
13.5
12.5
11.5
10.5
9
ResPWM
ResPWM
PWM input resolution
PWM input resolution
fPWM = 14 to 29.2 kHz
fPWM = 29.3 to 58.5 kHz
fPWM = 60 to 100 kHz
10
SPEED INPUT - ANALOG MODE
VANA_FS
Analog full-speed voltage
Analog voltage resolution
2.95
3
3
3.05
V
VANA_RES
732
μV
SPEED INPUT - FREQUENCY MODE
PWM input frequency range
Duty cycle = 50%
32767
Hz
ƒPWM_FREQ
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TJ = –40°C to +150°C, VVM = 4.5 to 20 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 12 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
PROTECTION CIRCUITS
VM rising
VM falling
21
20
22
21
23
22
V
V
VOVP
Supply overvoltage protection (OVP)
VOVP_HYS
tOVP
Supply overvoltage protection hysteresis Falling to rising threshold
900
1000
1100
mV
Supply overvoltage protection deglitch
time
3
5
7
µs
VM rising
Supply undervoltage lockout (UVLO)
VM falling
4.25
4.1
4.4
4.2
4.61
4.35
350
V
V
VUVLO
VUVLO_HYS Supply undervoltage lockout hysteresis Rising to falling threshold
140
210
mV
Supply undervoltage lockout deglitch
time
tUVLO
3
5
7
µs
VIN_AVDD rising
VIN_AVDD falling
4.25
4.1
4.4
4.2
4.61
4.35
V
V
VVIN_AVDD_U AVDD supply input undervoltage lockout
(VIN_AVDD_UV)
V
VVIN_AVDD_U
Supply undervoltage lockout hysteresis Rising to falling threshold
140
210
350
mV
V_HYS
Supply rising
Supply falling
2.64
2.4
2.8
2.6
2.95
2.7
V
V
Charge pump undervoltage lockout
(above VM)
VCPUV
Charge pump undervoltage lockout
hysteresis
VCPUV_HYS
tCPUV
Rising to falling threshold
180
3
210
5
245
7
mV
µs
Charge pump undervoltage lockout
deglitch time
Supply rising
Supply falling
2.7
2.6
2.8
2.7
2.9
2.8
V
V
VAVDD_UV
Analog regulator undervoltage lockout
VAVDD_UV_H Analog regulator undervoltage lockout
Rising to falling threshold
80
100
150
mV
hysteresis
YS
IOCP
Overcurrent protection trip point
6
0.15
0.45
0.7
9.5
0.3
12
0.45
0.85
1.25
1.5
A
OCP_TBLANK = 00b
OCP_TBLANK = 01b
OCP_TBLANK = 10b
OCP_TBLANK = 10b
OCP_DEG = 00b
µs
µs
µs
µs
µs
µs
µs
µs
ms
ms
ms
ms
°C
°C
°C
°C
0.7
(1)
tBLANK
Overcurrent protection blanking time
1
0.9
1.2
0.1
0.3
0.45
0.85
1.25
1.5
OCP_DEG = 01b
0.35
0.6
0.6
(1)
tOCP
Overcurrent protection deglitch time
OCP_DEG = 10b
0.9
OCP_DEG = 11b
0.8
1.2
TRETRY = 00b
350
750
1650
4350
110
15
500
1000
2000
5000
125
20
700
1300
2450
5850
140
25
TRETRY = 01b
tRETRY
Fault retry time
TRETRY = 10b
TRETRY = 11b
TOTW
TOTW_HYS
TOTS
Thermal warning temperature
Thermal warning hysteresis
Thermal shutdown temperature
Thermal shutdown hysteresis
Die temperature (TJ) Rising
Die temperature (TJ)
Die temperature (TJ) Rising
Die temperature (TJ)
145
15
160
20
175
25
TOTS_HYS
(1) (tOCP + tBLANK) must not exceed 2.2 µs
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7.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
at TJ = –25°C to +125°C, VVM = 6 to 18 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 12 V
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
Standard-mode
fSCL
SCL clock frequency
0
100
kHz
After this period, the first clock pulse is
generated
tHD_STA
Hold time (repeated) START condition
SCL fall (Tf 70% to 30% =
6.5ns-106.5ns),
4
µs
SDA fall (Tf 70% to 30% = 6.5ns-106.5ns)
tLOW
tHIGH
Low period of the SCL clock
High period of the SCL clock
4.7
4
µs
µs
SCL rise (Tr 30% to 70% =
600ns-1000ns),
SDA fall (Tf 70% to 30% = 6.5ns-106.5ns)
Set-up time for a repeated START
condition
tSU_STA
4.7
µs
SCL fall (Tf 70% to 30% =
6.5ns-106.5ns),
SDA rise (Tr 30% to 70%=
600ns-1000ns) or fall (Tf 70% to 30% =
6.5ns-106.5ns)
I2C Start Data Hold Time (1)
0 (2)
µs
(3)
(3)
tHD_DAT
SCL fall (Tf 70% to 30% =
6.5ns-106.5ns),
SDA rise (Tr 30% to 70%=
600ns-1000ns) or fall (Tf 70% to 30% =
6.5ns-106.5ns)
I2C Input Data Transfer Hold Time (1)
I2C False Start/Stop Data Set-up Time
0 (2)
250
250
µs
ns
ns
SCL rise (Tr 30% to 70% =
600ns-1000ns),
SDA rise (Tr 30% to 70%=
600ns-1000ns) or fall (Tf 70% to 30% =
6.5ns-106.5ns)
tSU_DAT
SCL rise (Tr 30% to 70% =
600ns-1000ns),
SDA rise (Tr 30% to 70%=
600ns-1000ns) or fall (Tf 70% to 30% =
6.5ns-106.5ns)
I2C Input Data Transfer Set-up Time
tr
tf
Rise time for both SDA and SCL signals
1000
300
ns
ns
Fall time of both SDA and SCL signals (2)
(5) (6) (7)
SCL rise (Tr 30% to 70% =
600ns-1000ns),
SDA rise (Tr 30% to 70% =
600ns-1000ns)
tSU_STO
Set-up time for STOP condition
4
µs
µs
Bus free time between STOP and START
condition
tBUF
4.7
Cb
Capacitive load for each bus line (8)
Data valid time (9)
400
3.45 (3)
3.45 (3)
pF
µs
µs
tVD_DAT
tVD_ACK
Data valid acknowledge time (10)
For each connected device (including
hysteresis)
VnL
Vnh
Noise margin at the Low level
Noise margin at the High level
0.12
0.24
V
V
For each connected device (including
hysteresis)
Fast-mode
fSCL SCL clock frequency
0
400
kHz
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at TJ = –25°C to +125°C, VVM = 6 to 18 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 12 V
PARAMETER
TEST CONDITIONS
MIN
NOM
MAX
UNIT
After this period, the first clock pulse is
generated
tHD_STA
Hold time (repeated) START condition
SCL fall (Tf 70% to 30% =
6.5ns-106.5ns),
0.6
µs
SDA fall (Tf 70% to 30% = 6.5ns-106.5ns)
tLOW
tHIGH
Low period of the SCL clock
High period of the SCL clock
1.3
0.6
µs
µs
SCL rise (Tr 30% to 70% =
180ns-300ns),
SDA fall (Tf 70% to 30% = 6.5ns-106.5ns)
Set-up time for a repeated START
condition
tSU_STA
0.6
µs
µs
SCL fall (Tf 70% to 30% =
6.5ns-106.5ns),
SDA rise (Tr 30% to 70% = 180ns-300ns)
or fall (Tf 70% to 30% = 6.5ns-106.5ns)
I2C Start Data Hold Time (1)
0 (2)
(3)
(3)
tHD_DAT
SCL fall (Tf 70% to 30% =
6.5ns-106.5ns),
SDA rise (Tr 30% to 70% = 180ns-300ns)
or fall (Tf 70% to 30% =6.5ns-106.5ns)
I2C Input Data Transfer Hold Time (1)
I2C False Start/Stop Data Set-up Time
0 (2)
µs
SCL rise (Tr 30% to 70% = 180ns-300ns),
SDA rise (Tr 30% to 70% = 180ns-300ns)
or fall (Tf 70% to 30% = 6.5ns-106.5ns)
100 (4)
100 (4)
ns
ns
tSU_DAT
SCL rise (Tr 30% to 70% = 180ns-300ns),
SDA rise (Tr 30% to 70% = 180ns-300ns)
or fall (Tf 70% to 30% = 6.5ns-106.5ns)
I2C Input Data Transfer Set-up Time
tr
tf
Rise time for both SDA and SCL signals
20
300
300
ns
ns
Fall time of both SDA and SCL signals (2)
4.36
(5) (6) (7)
SCL rise (Tr 30% to 70% =
180ns-300ns),
SDA rise (Tr 30% to 70% = 180ns-300ns)
tSU_STO
Set-up time for STOP condition
0.6
1.3
µs
µs
Bus free time between STOP and START
condition
tBUF
Cb
Capacitive load for each bus line (8)
Data valid time (9)
150
0.9 (3)
0.9 (3)
pF
µs
µs
V
tVD_DAT
tVD_ACK
VnL
Data valid acknowledge time (10)
Noise margin at the Low level
Noise margin at the High level
No chattering at output for noise at VOL
No chattering at output for noise at VOH
0.12
0.24
Vnh
V
(1) tHD_DAT is the data hold time that is measured from the falling edge of SCL, applies to data in transmission and the acknowledge.
(2) A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
(3) The maximum tHD_DAT could be 3.45 us and .9 us for Standard-mode and Fast-mode, but must be less than the maximum of tVD_DAT or
tVD_ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If
the clock stretched the SCL, the data must be valid by the set-up time before it releases the clock.
(4) A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU_DAT 250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period if the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU_DAT = 1000 + 250 = 1250 ns (according to the
Standard-mode I2C-bus specification) before the SCL line is released. Also, the acknowledge timing must meet this set-up time.
(5) If mixed with Hs-mode devices, faster fall times according to Table 10 are allowed.
(6) The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at
250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified tf.
(7) In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should
allow for this when considering bus timing.
(8) The maximum bus capacitance allowable may vary from the value depending on the actual operating voltage and frequency of the
application.
(9) tVD_DAT = time for data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
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(10) tVD_ACK = time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
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8 Detailed Description
8.1 Overview
The MCT8317A provides a single-chip, code-free sensorless trapezoidal solution for customers requiring high
speed operation (up to 3 kHz electrical speed) or very fast start-up time (< 50ms) for 12-V brushless-DC motors
requiring up to 5-A peak phase currents.
The MCT8317A integrates three 1/2-H bridges with 24-V absolute maximum capability and a very low RDS(ON) of
130-mΩ (high-side + low-side) to enable high power drive capability. Current is sensed using an integrated
current sensing circuit which eliminates the need for external sense resistors. An integrated LDO generates the
necessary voltage rail for the device that can also be used to power external circuits sourcing up to 20 mA.
Sensorless trapezoidal control is highly configurable through register settings ranging from motor start-up
behavior to closed loop operation. Register settings can be stored in non-volatile EEPROM, which allows the
device to operate stand-alone once it has been configured. MCT8317A allows for a high level of monitoring; any
variable in the algorithm can be displayed and observed as an analog output via two 12-bit DACs. This feature
provides an effective method to tune speed loops as well as motor acceleration. The device receives a speed
command through a PWM input, analog voltage, frequency input or I2C command.
In-built protection features include power-supply under voltage lockout (UVLO), charge-pump under voltage
lockout (CPUV), over current protection (OCP), AVDD under voltage lockout (AVDD_UV), motor lock detection
and over temperature warning and shutdown (OTW and OTS). Fault events are indicated by the nFAULT pin
with detailed fault information available in the status registers.
The MCT8317A device is available in a 0.4-mm pin pitch, WQFN surface-mount package. The WQFN package
size is 5-mm × 4-mm with a height of 0.8-mm.
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8.2 Functional Block Diagram
CVIN_AVDD
1µF
Note : VIN_AVDD can be tied to VM also
PGND
CFLY 47nF
CAVDD 1µF
VM
AVDD
Out
AVDD AGND
CPL
CPH
CP
VIN_AVDD
CCP
1µF
VM
VM
AVDD LDO
Regulator
Charge Pump
CVM1
0.1µF
+
CVM2
>10µF
DVDD
DGND
DVDD
LDO
Regulator
CDVDD
1µF
Protection
VM
VCP
EEPROM
OUTA
OUTA
PWM, Freq.
or Analog
Input
SPEED/WAKE
BRAKE
Sensorless Trap
Engine
VGLS
Integrated
current
sensing
AVDD
IO Interface
AVDD
DIR
ALARM
FG
PGND
ISENA
PGND
VM
Protection
PGND
A
Protection
VCP
nFAULT
AVDD
OUTB
OUTB
Speed/power loop
with profiles
VGLS
SCL
Integrated
current
sensing
AVDD
I2C
Fast accel & decel
120° & 150° comm.
SDA
PGND
ISENB
PGND
VM
Protection
PGND
Optional external
clock reference
EXT_WD
Protection
Built-in 60-MHz
Oscillator
VCP
EXT_CLK
DACOUT1
12-bit
DAC
12-bit
ADC
OUTC
OUTC
Op onal external
clock reference
VGLS
Integrated
current
sensing
DACOUT2
Variable
monitoring on
DACOUT1 &
DACOUT2 pins,
SOX output
VM
ISENA
ISENB
ISENC
OUTA
OUTB
OUTC
PGND
DACOUT2/SOX
PGND
ISENC
PGND
Protection
图8-1. MCT8317A Functional Block Diagram
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8.3 Feature Description
8.3.1 Output Stage
The MCT8317A consists of an integrated 130-mΩ (high-side + low-side) NMOS FETs connected in a three-
phase bridge configuration. A doubler charge pump provides the proper gate-bias voltage to the high-side
NMOS FETs across a wide operating-voltage range in addition to providing 100% duty-cycle support. An internal
linear regulator provides the gate-bias voltage for the low-side MOSFETs.
8.3.2 Device Interface
MCT8317A supports I2C interface to provide end application design with adequate flexibility. MCT8317A allows
controlling the motor operation and system through BRAKE, DIR, EXT_CLK, EXT_WD and SPEED/WAKE pins.
MCT8317A also provides different signals for monitoring algorithm variables, speed, fault and phase current
feedback through DACOUT1, DACOUT2, FG, nFAULT, ALARM and SOX pins.
8.3.2.1 Interface - Control and Monitoring
Motor Control Signals
• When BRAKE pin is driven 'High', MCT8317A enters brake state. Low-side braking (see Low-Side Braking) is
implemented during this brake state. MCT8317A decreases output speed to value defined by
BRAKE_DUTY_THRESHOLD before entering brake state. As long as BRAKE is driven 'High', MCT8317A
stays in brake state. Brake pin input can be overwritten by configuring BRAKE_INPUT over the I2C interface.
• The DIR pin decides the direction of motor spin; when driven 'High', the sequence is OUT A →OUT C →
OUT B, and when driven 'Low' the sequence is OUT A →OUT B →OUT C. DIR pin input can be overwritten
by configuring DIR_INPUT over the I2C interface.
• SPEED/WAKE pin is used to control motor speed and wake up MCT8317A from sleep mode. SPEED pin can
be configured to accept PWM, frequency or analog input signals. It is used to enter and exit from sleep and
standby mode (see 表8-2).
External Oscillator and Watchdog Signals (Optional)
• EXT_CLK pin may be used to provide an external clock reference (see External Clock Source ).
• EXT_WD pin may be used to provide an external watchdog signal (see External Watchdog).
Output Signals
• DACOUT1 outputs internal variable defined by address in register DACOUT1_VAR_ADDR, the output of
DACOUT1 is refreshed every PWM cycle (see DAC outputs).
• DACOUT2 outputs internal variable defined by address in register DACOUT2_VAR_ADDR, the output of
DACOUT2 is refreshed every PWM cycle (see DAC outputs).
• FG pin provides pulses which are proportional to motor speed (see FG Configuration).
• nFAULT pin provides fault status in device or motor operation.
• SOX pin provides the output of one of the current sense amplifiers.
8.3.2.2 I2C Interface
The MCT8317A supports an I2C serial communication interface that allows an external controller to send and
receive data. This I2C interface lets the external controller configure the EEPROM and read detailed fault and
motor state information. The I2C bus is a two-wire interface using the SCL and SDA pins which are described as
follows:
• The SCL pin is the clock signal input.
• The SDA pin is the data input and output.
8.3.3 AVDD Linear Voltage Regulator
A 3.3-V linear regulator is integrated into the MCT8317A and is available for use by external circuitry. The AVDD
regulator is used for powering up the internal circuitry of the device and additionally, this regulator can also
provide the supply voltage for an external low-power MCU or other circuitry supporting low current (up to 20 mA).
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The AVDD nominal, no-load output voltage is 3.3-V.
VIN_AVDD
REF
+
–
AVDD
AGND
External Load
CAVDD
图8-2. AVDD Linear Regulator Block Diagram
Use 方程式 1 to calculate the power dissipated in the device by the AVDD linear regulator to deliver an external
load, IAVDD
.
P = (VVIN_AVDD - VAVDD) x IAVDD
(1)
8.3.4 Charge Pump
Since the output stages use N-channel FETs, the device requires a gate-drive voltage higher than the VM power
supply to turn-on the high-side FETs. The MCT8317A integrates a charge-pump circuit that generates a voltage
above the VM supply for this purpose.
The charge pump requires two external capacitors(CCP, CFLY) for operation. See the block diagram and pin
descriptions for details on these capacitors (value, connection, and so forth).
VM
VM
CCP
CP
CPH
VM
Charge
Pump
Control
CFLY
CPL
图8-3. Charge Pump
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8.3.5 Slew Rate Control
An adjustable gate-drive current control for the MOSFETs in the output stage is provided to achieve configurable
slew rate for EMI mitigation. The MOSFET VDS slew rate is a critical factor for optimizing radiated emissions,
total energy and duration of diode recovery spikes and switching voltage transients related to parasitic elements
of the PCB. This slew rate is predominantly determined by the control of the internal MOSFET gate current as
shown in 图8-4.
VM
VCP (Internal)
Slew Rate
Control
OUTx
VCP (Internal)
Slew Rate
Control
GND
图8-4. Slew Rate Circuit Implementation
The slew rate of each half-bridge can be adjusted through SLEW_RATE settings. Slew rate can be configured as
25-V/µs, 50-V/µs, 125-V/µs or 200-V/µs. The slew rate is calculated by the rise-time and fall-time of the voltage
on OUTx pin as shown in 图8-5.
VOUTx
VM
VM
80%
80%
20%
20%
0
Time
tfall
trise
图8-5. Slew Rate Timings
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8.3.6 Cross Conduction (Dead Time)
The device is fully protected against any cross conduction of the MOSFETs. The high-side and low-side
MOSFETs are carefully controlled to avoid any shoot-through events by inserting a dead time (tdead). This is
implemented by sensing the gate-source voltage (VGS) of the high-side and low-side MOSFETs and ensuring
that the VGS of high-side MOSFET has reached below turn-off levels before switching on the low-side MOSFET
of same half-bridge as shown in 图8-6 and 图8-7 and vice versa.
VM
Gate
Control
+
VGS
VGS_HS
VGS_LS
–
OUTx
tDEAD
Gate
Control
+
GND
VGS
–
图8-6. Cross Conduction Protection
OUTx HS
OUTx
Gate
(VGS_HS)
10%
tDEAD
OUTx
Gate
(VHS_LS)
10%
OUTx LS
Time
图8-7. Dead Time
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8.3.7 Motor Control Input Options
The MCT8317A offers three ways of controlling the motor:
1. SPEED Control: In speed control mode, the speed of the motor is controlled using a closed loop PI control
according to the input reference.
2. POWER Control: In power control mode, the DC input power of the inverter power stage is controlled using a
closed loop PI control according to the input reference.
3. VOLTAGE Control: In voltage control mode, the voltage (duty cycle) applied to the motor is controlled
according to the input reference.
The MCT8317A offers four methods of directly controlling the reference input of the motor. The reference control
method is configured by SPD_CTRL_MODE.
The reference (speed or power or voltage) input command can be controlled in one of the following four ways.
• PWM input on SPEED/WAKE pin by varying duty cycle of input signal
• Frequency input on SPEED/WAKE pin by varying frequency of input signal
• Analog input on SPEED/WAKE pin or DACOUT/SOx/SPEED_ANA pin by varying amplitude of input signal
• Over I2C by configuring SPEED_CTRL
The signal path from SPEED pin input (or I2C based speed input) to output duty cycle (DUTY_OUT) applied to
FETs is shown in 图8-8.
CLOSED_LOOP_MODE
VOLTAGE_REF (TARGET_DUTY)
Freq based
Freq
Duty
REF_PROFILE_
CONFIG != 00b
Linear / Stair
SPEED_REF
AVS, CL_ACC
case / Forw-
Rev Profiles
DUTY_CMD
PWM
PWM Duty
ADC
SPEED Pin
Speed/Power
PI Loop
POWER_REF
Analog
Transfer
Function
REF_PROFILE_
CONFIG = 00b
DUTY_OUT
FETs
PWM
I2C
图8-8. Multiplexing the Control Input Command
8.3.7.1 Analog Mode Speed Control
Analog input based speed control can be configured by setting SPD_CTRL_MODE to 00b. In this mode, the
duty command (DUTY_CMD) varies with the analog voltage input on the SPEED pin (VSPEED). When 0 ≤
VSPEED ≤ VEN_SB, DUTY_CMD is set to zero and the motor is stopped. When VEX_SB ≤ VSPEED ≤ VANA_FS
,
DUTY_CMD varies linearly with VSPEED as shown in 图 8-9. VEX_SB and VEN_SB are the standby entry and exit
thresholds - refer 节 8.4.1.2 for more information on VEX_SB and VEN_SB. When VSPEED > VANA_FS, DUTY_CMD
is clamped to 100%.
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DUTY_CMD
100%
SPEED pin voltage
VANA_FS
VEN_SB VEX_SB
0
图8-9. Analog Mode Speed Control
8.3.7.2 PWM-Mode Speed Control
PWM based speed control can be configured by setting SPD_CTRL_MODE to 01b. In this mode, the PWM duty
cycle applied to the SPEED pin can be varied from 0 to 100% and duty command (DUTY_CMD) varies linearly
with the applied PWM duty cycle. When 0 ≤ DutySPEED ≤ DutyEN_SB, DUTY_CMD is set to zero and the motor
is stopped. When DutyEX_SB ≤ DutySPEED ≤ 100%, DUTY_CMD varies linearly with DutySPEED as shown in 图
8-10. DutyEX_SB and DutyEN_SB are the standby entry and exit thresholds - refer 节 8.4.1.2 for more information
on DutyEX_SB and DutyEN_SB. The frequency of the PWM input signal applied to the SPEED pin is defined as
fPWM and the range for this frequency can be configured through SPD_PWM_RANGE_SELECT.
备注
1. fPWM is the frequency of the PWM signal the device can accept at SPEED pin to control motor
speed. It does not correspond to the PWM output frequency that is applied to the motor phases.
The PWM output frequency can be configured through PWM_FREQ_OUT (see 节8.3.14).
2. SLEEP_TIME should be set longer than the off time in PWM signal (VSPEED < VIL) at lowest duty
input. For example, if fPWM is 10 kHz and lowest duty input is 2%, SLEEP_TIME should be more
than 98 µs to ensure there is no unintended sleep entry.
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DUTY_CMD
100%
PWM Duty at SPEED pin
DutyEN_SB DutyEX_SB
100%
0
图8-10. PWM Mode Speed Control
8.3.7.3 I2C based Speed Control
I2C based serial interface can be used for speed control by setting SPD_CTRL_MODE to 10b. In this mode, the
speed command can be written directly into SPEED_CTRL. The SPEED pin can be used to control the sleep
entry and exit - if SPEED pin input is set to a value lower than VEN_SL after SPEED_CTRL has been set to 0b for
a time longer than SLEEP_TIME, MCT8317A enters sleep state. When SPEED pin > VEX_SL, MCT8317A exits
sleep state and speed is controlled through SPEED_CTRL. If 0 ≤ SPEED_CTRL ≤ SPEED_CTRLEN_SB and
SPEED pin > VEX_SL, MCT8317A is in standby state. The relationship between DUTY_CMD and SPEED_CTRL
is shown in 图8-11. Refer 节8.4.1.2 for more information on SPEED_CTRLEN_SB EX_SB and SPEED_CTRLEN_SB
.
EN_SB
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DUTY_CMD
100%
SPEED_CTRL
32767
0
SPEED_CTRLEX_SB
SPEED_CTRLEN_SB
图8-11. I2C Mode Speed Control
8.3.7.4 Frequency-Mode Speed Control
Frequency based speed control is configured by setting SPD_CTRL_MODE to 11b. In this mode, duty command
varies linearly as a function of the frequency of the square wave input at SPEED pin. When 0 ≤ FreqSPEED
FreqEN_SB, DUTY_CMD is set to zero and the motor is stopped. When FreqEX_SB ≤ FreqSPEED
≤
≤
INPUT_MAX_FREQUENCY, DUTY_CMD varies linearly with FreqSPEED as shown in 图 8-12. FreqEX_SB and
FreqEN_SB are the standby entry and exit thresholds - refer 节 8.4.1.2 for more information on FreqEX_SB and
FreqEN_SB. Input frequency greater than INPUT_MAX_FREQUENCY clamps the DUTY_CMD to 100%.
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DUTY_CMD
100%
Frequency at SPEED pin
INPUT_MAX_FREQUENCY
FreqEN_SB FreqEX_SB
0
图8-12. Frequency Mode Speed Control
8.3.7.5 Reference Profiles
MCT8317A supports three different kinds of reference (speed/power) profiles (linear, step, forward-reverse) to
enable a variety of end-user applications. The different reference profiles can be configured through
REF_PROFILE_CONFIG. When REF_PROFILE_CONFIG is set to 00b, the voltage/speed/power reference or
target duty is a function of the duty command as shown in 图8-13.
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SPEED_REF /
POWER_REF/
TARGET_DUTY
MAX_SPEED /
MAX_POWER/
100%
MIN_DUTY x MAX_SPEED /
MIN_DUTY x MAX_POWER /
MIN_DUTY
DUTY_CMD
MIN_
DUTY
ZERO_
DUTY_
THR +
ZERO_
DUTY_
HYST
ZERO_
DUTY_
THR
0
100%
图8-13. Control Input Transfer Function
When speed/power loop is disabled (CLOSED_LOOP_MODE = 00b), DUTY_CMD sets the TARGET_DUTY in
% - TARGET_DUTY is 100% when DUTY_CMD is 100% and TARGET_DUTY is equal to MIN_DUTY when
DUTY_CMD is set to MIN_DUTY. TARGET_DUTY stays clamped at MIN DUTY for ZERO_DUTY_THR ≤
DUTY_CMD ≤MIN_DUTY.
When speed loop is enabled (CLOSED_LOOP_MODE = 01b), DUTY_CMD sets the SPEED_REF in Hz.
MAX_SPEED sets the SPEED_REF at DUTY_CMD of 100%. MIN_DUTY sets the minimum SPEED_REF
(MIN_DUTY
x
MAX_SPEED). SPEED_REF stays clamped at (MIN_DUTY
x
MAX_SPEED) for
ZERO_DUTY_THR ≤DUTY_CMD ≤MIN_DUTY.
When power loop is enabled (CLOSED_LOOP_MODE = 10b), DUTY_CMD sets the POWER_REF in W.
MAX_POWER sets the POWER_REF at DUTY_CMD of 100%. MIN_DUTY sets the minimum POWER_REF
(MIN_DUTY
x MAX_POWER). POWER_REF stays clamped at (MIN_DUTY x POWER_REF) for
ZERO_DUTY_THR ≤DUTY_CMD ≤MIN_DUTY.
ZERO_DUTY_THR sets the DUTY_CMD below which SPEED_REF / POWER_REF / TARGET_DUTY is set to
zero and motor is in stopped state. AVS, CL_ACC configure the transient characteristics of DUTY_OUT; the
steady state value of DUTY_OUT is directly configured in % through TARGET_DUTY (when speed/power loop is
disabled) or through SPEED_REF/POWER_REF (when speed/power loop is enabled).
8.3.7.5.1 Linear Reference Profile
备注
For all types of reference profiles, duty command < ZERO_DUTY_THR stops the motor irrespective of
the speed profile register settings.
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REFERENCE (SPEED/POWER)
REF_CLAMP2
REF_E
REF_D
REF_C
REF_B
REF_A
REF_CLAMP1
REF_OFF1
REF_OFF2
DUTY_CMD (%)
DUTY_E DUTY_CLAMP2 DUTY_ON2
DUTY_OFF2
DUTY_A
DUTY_OFF1 DUTY_ON1 DUTY_CLAMP1
DUTY_B
DUTY_C DUTY_D
图8-14. Linear Reference Profile
Linear reference profile can be configured by setting REF_PROFILE_CONFIG to 01b. Linear reference profile
features speed/power references which change linearly between REF_CLAMP1 and REF_CLAMP2 with
different slopes which can be set by configuring DUTY_x and REF_x combination.
• DUTY_ON1 configures the duty command above which MCT8317A starts driving the motor (to speed/power
reference set by REF_CLAMP1) when the current speed/power reference is zero. When current speed/power
reference is zero and duty command is below DUTY_ON1, MCT8317A continues to be in off state and motor
is stationary.
• DUTY_OFF1 configures the duty command below which the speed/power reference changes to REF_OFF1.
• DUTY_CLAMP1 configures the duty command till which speed/power reference will be constant.
REF_CLAMP1 configures this constant speed/power reference between DUTY_OFF1 and DUTY_CLAMP1.
• DUTY_A configures the duty command for speed/power reference REF_A. The speed/power reference
changes linearly between DUTY_CLAMP1 and DUTY_A.
• DUTY_B configures the duty command for speed/power reference REF_B. The speed/power reference
changes linearly between DUTY_A and DUTY_B.
• DUTY_C configures the duty command for speed/power reference REF_C. The speed/power reference
changes linearly between DUTY_B and DUTY_C.
• DUTY_D configures the duty command for speed/power reference REF_D. The speed/power reference
changes linearly between DUTY_C and DUTY_D.
• DUTY_E configures the duty command for speed/power reference REF_E. The speed/power reference
changes linearly between DUTY_D and DUTY_E.
• DUTY_CLAMP2 configures the duty command above which the speed/power reference will be constant at
REF_CLAMP2. REF_CLAMP2 configures this constant speed/power reference between DUTY_CLAMP2
and DUTY_OFF2 . The speed/power reference changes linearly between DUTY_E and DUTY_CLAMP2.
• DUTY_ON2 configures the duty command below which MCT8317A starts driving the motor (to speed/power
reference set by REF_CLAMP2) when the current speed/power reference is zero. When current speed/power
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reference is zero and duty command is above DUTY_ON2, MCT8317A continues to be in off state and motor
is stationary.
• DUTY_OFF2 configures the duty command above which the speed/power reference will change from
REF_CLAMP2 to REF_OFF2.
8.3.7.5.2 Staircase Reference Profile
REFERENCE (SPEED/POWER)
REF_CLAMP2
REF_E
REF_D
REF_C
REF_B
REF_A
STEP_
HYST_
BAND
REF_CLAMP1
REF_OFF2
DUTY_CMD (%)
REF_OFF1
DUTY_A
DUTY_E
DUTY_CLAMP2 DUTY_ON2 DUTY_OFF2
DUTY_OFF1 DUTY_ON1 DUTY_CLAMP1
DUTY_B
DUTY_C DUTY_D
图8-15. Staircase Reference Profile
Staircase reference profiles can be configured by setting REF_PROFILE_CONFIG to 10b. Staircase reference
profiles feature reference changes in steps between REF_CLAMP1 and REF_CLAMP2. DUTY_x configures the
duty command at which the next staircase level reference (REF_x) is set .
• DUTY_ON1 configures the duty command above which MCT8317A starts driving the motor (to speed/power
reference set by REF_CLAMP1) when the current speed/power reference is zero. When current speed/power
reference is zero and duty command is below DUTY_ON1, MCT8317A continues to be in off state and motor
is stationary.
• DUTY_OFF1 configures the duty command below which the speed/power reference changes from
REF_CLAMP1 to REF_OFF1.
• DUTY_CLAMP1 configures the duty command till which speed/power reference will be constant.
REF_CLAMP1 configures this constant speed/power reference between DUTY_OFF1 and DUTY_CLAMP1.
• DUTY_A configures the duty command for speed/power reference REF_A. There is a step change in speed/
power reference from REF_CLAMP1 to REF_A at DUTY_CLAMP1.
• DUTY_B configures the duty command for speed/power reference REF_B. There is a step change in speed/
power reference from REF_A to REF_B at DUTY_A.
• DUTY_C configures the duty command for speed/power reference REF_C. There is a step change in speed/
power reference from REF_B to REF_C at DUTY_B.
• DUTY_D configures the duty command for speed/power reference REF_D. There is a step change in speed/
power reference from REF_C to REF_D at DUTY_C.
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• DUTY_E configures the duty command for speed/power reference REF_E. There is a step change in speed/
power reference from REF_D to REF_E at DUTY_D.
• DUTY_CLAMP2 configures the duty command above which the speed/power reference will be constant at
REF_CLAMP2. REF_CLAMP2 configures this constant speed/power reference between DUTY_CLAMP2
and DUTY_OFF2. There is a step change in speed/power reference from REF_E to REF_CLAMP2 at
DUTY_E.
• DUTY_ON2 configures the duty command below which MCT8317A starts driving the motor (to speed/power
reference set by REF_CLAMP2) when the current speed/power reference is zero. When current speed/power
reference is zero and duty command is above DUTY_ON2, MCT8317A continues to be in off state and motor
is stationary.
• DUTY_OFF2 configures the duty command above which the speed/power reference will change from
REF_CLAMP2 to REF_OFF2.
8.3.7.5.3 Forward-Reverse Reference Profile
REFERENCE (SPEED/POWER)
Forward Direction
OUT B OUT C
Reverse Direction
OUT C OUT B
OUT A
OUT A
REF_CLAMP2
REF_CLAMP1
REF_D
REF_A
STEP_
HYST_
BAND
STEP_
HYST_
BAND
REF_OFF2
DUTY_CMD (%)
REF_OFF1
DUTY_C
DUTY_E
DUTY_CLAMP2 DUTY_ON2 DUTY_OFF2
DUTY_OFF1 DUTY_ON1 DUTY_CLAMP1
DUTY_A DUTY_B
DUTY_D
图8-16. Forward-Reverse Reference Profile
Forward-Reverse speed/power profile can be configured by setting REF_PROFILE_CONFIG to 11b. Forward-
Reverse speed/power profile features direction change through adjusting the duty command. DUTY_C
configures duty command at which the direction will be changed. The Forward-Reverse speed/power profile can
be used to eliminate the separate signal used to control the motor direction.
• DUTY_ON1 configures the duty command above which MCT8317A starts driving the motor in the forward
direction (to speed/power reference set by REF_CLAMP1) when the current speed/power reference is zero.
When current speed/power reference is zero and duty command is below DUTY_ON1, MCT8317A continues
to be in off state and motor is stationary.
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• DUTY_OFF1 configures the duty command below which the speed/power reference changes in the forward
direction from REF_CLAMP1 to REF_OFF1.
• DUTY_CLAMP1 configures the duty command below which speed/power reference will be the constant in
forward direction. REF_CLAMP1 configures constant speed/power reference between DUTY_CLAMP1 and
DUTY_OFF1.
• DUTY_A configures the duty command for speed/power reference REF_A. The speed/power reference
changes linearly between DUTY_CLAMP1 and DUTY_A.
• DUTY_B configures the duty command above which MCT8317A will be in off state. The speed/power
reference remains constant at REF_A between DUTY_A and DUTY_B.
• DUTY_C configures the duty command at which the direction is changed
• DUTY_D configures the duty command above which the MCT8317A will be in running state in the reverse
direction. REF_D configures constant speed/power reference between DUTY_D and DUTY_E.
• DUTY_CLAMP2 configures the duty command above which speed/power reference will be constant at
REF_CLAMP2 in reverse direction. The speed/power reference changes linearly between DUTY_E and
DUTY_CLAMP2.
• DUTY_ON2 configures the duty command below which MCT8317A starts driving the motor in the reverse
direction (to speed/power reference set by REF_CLAMP2) when the current speed/power reference is zero.
When current speed/power reference is zero and duty command is above DUTY_ON2, MCT8317A continues
to be in off state and motor is stationary.
• DUTY_OFF2 configures the duty command above which the speed/power reference changes in the reverse
direction from REF_CLAMP2 to REF_OFF2.
8.3.8 Starting the Motor Under Different Initial Conditions
The motor can be in one of three states when MCT8317A begins the start-up process. The motor may be
stationary, spinning in the forward direction, or spinning in the reverse direction. The MCT8317A includes a
number of features to allow for reliable motor start-up under all of these conditions. 图 8-17 shows the motor
start-up flow for each of the three initial motor states.
Brake
Align
Double Align
Sta onary
IPD
Slow rst cycle
Spinning in forward
direc on
Closed Loop
Coast (Hi-Z)
Brake
Spinning in reverse
direc on
Reverse Drive
图8-17. Starting the motor under different initial conditions
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备注
"Forward" means "spinning in the same direction as the commanded direction", and "Reverse" means
"spinning in the opposite direction as the commanded direction".
8.3.8.1 Case 1 –Motor is Stationary
If the motor is stationary, the commutation must be initialized to be in phase with the position of the motor. The
MCT8317A provides various options to initialize the commutation logic to the motor position and reliably start the
motor.
• The align and double align techniques force the motor into alignment by applying a voltage across a
particular motor phase to force the motor to rotate in alignment with this phase.
• Initial position detect (IPD) determines the position of the motor based on the deterministic inductance
variation, which is often present in BLDC motors.
• The slow first cycle method starts the motor by applying a low frequency cycle to align the rotor position to
the applied commutation by the end of one electrical rotation.
MCT8317A also provides a configurable brake option to ensure the motor is stationary before initiating one of
the above start-up methods. Device enters open loop acceleration after going through the configured start-up
method.
8.3.8.2 Case 2 –Motor is Spinning in the Forward Direction
If the motor is spinning forward (same direction as the commanded direction) with sufficient speed (BEMF), the
MCT8317A resynchronizes with the spinning motor and continues commutation by going directly to closed loop
operation. By resynchronizing to the spinning motor, the user achieves the fastest possible start-up time for this
initial condition. This resynchronization feature can be enabled or disabled through RESYNC_EN. If
resynchronization is disabled, the MCT8317A can be configured to wait for the motor to coast to a stop and/or
apply a brake. After the motor has stopped spinning, the motor start-up sequence proceeds as in Case 1,
considering the motor is stationary.
8.3.8.3 Case 3 –Motor is Spinning in the Reverse Direction
If the motor is spinning in the reverse direction (the opposite direction as the commanded direction), the
MCT8317A provides several methods to change the direction and drive the motor to the target speed reference
in the commanded direction.
The reverse drive method allows the motor to be driven so that it decelerates through zero speed. The motor
achieves the shortest possible spin-up time when spinning in the reverse direction.
If reverse drive is not enabled, then the MCT8317A can be configured to wait for the motor to coast to a stop
and/or apply a brake. After the motor has stopped spinning, the motor start-up sequence proceeds as in Case 1,
considering the motor is stationary.
备注
Take care when using the reverse drive or brake feature to ensure that the current is limited to an
acceptable level and that the supply voltage does not surge as a result of energy being returned to the
power supply.
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8.3.9 Motor Start Sequence (MSS)
图8-18 shows the motor-start sequence implemented in MCT8317A.
Power On
Sleep/Standby
(SPEED_REF/
TARGET_DUTY = 0)
SPEED_REF/
TARGET_DUTY > 0
N
Y
0b
ISD_EN
1b
BEMF <
STAT_DETECT_THR ||
Y
BEMF <
FG_BEMF_THR
N
Direc on
of spin
Reverse
0b
Forward
0b
RVS_DR_EN
1b
RESYNC_EN
1b
0b
HIZ_EN
BEMF >
RESYNC_MIN_TH
RESHOLD
N
1b
N
Speed >
MIN_DUTY
BEMF <
STAT_DETECT_THR
Y
Hi-Z
Y
N
Y
Motor
coast
meout
Time >
HIZ_TIME
N
0b
Reverse
Open Loop
Decelera on
Reverse Closed
Loop
Decelera on
Y
N
STAT_BRK_
EN
1b
Brake
Y
0b
BRAKE_EN
Time >
STARTUP_BRK
N
_TIME
1b
Brake_Rou ne
Y
Direc on Reversal :
Zero Speed
Motor Start-up
Open loop
Crossover
Closed Loop
图8-18. Motor Start Sequence
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Brake_Rou ne
Brake
Time >
N
BRK_TIME
Y
Brake_Rou ne_End
图8-19. Brake Routine
Power-On State
Sleep/Standby
This is the initial state of the Motor Start Sequence (MSS) when MCT8317A
is powered on. In this state, MCT8317A configures the peripherals,
initializes the algorithm parameters from EEPROM and prepares for driving
the motor.
In this state, SPEED_REF/TARGET_DUTY is set to zero and MCT8317A is
either in sleep or standby mode depending on DEV_MODE and SPEED/
WAKE pin voltage.
SPEED_REF/TARGET_DUTY > When SPEED_REF is set to greater than zero, MCT8317A exits the sleep
0 Judgement
(SPEED pin voltage > VIL)/standby state and proceeds to ISD_EN
judgement. As long as SPEED_REF is set to zero, MCT8317A stays in
sleep/standby state.
ISD_EN Judgement
MCT8317A checks to see if the initial speed detect (ISD) function is enabled
(ISD_EN = 1b). If ISD is enabled, MSS proceeds to the BEMF <
STAT_DETECT_THR judgement. Instead, if ISD is disabled, the MSS
proceeds directly to the BRAKE_EN judgement.
BEMF < STAT_DETECT_THR || ISD determines the initial condition (speed, angle, direction of spin) of the
BEMF < FG_BEMF_THR
Judgement
motor (see 节8.3.9.1). If motor is deemed to be stationary (BEMF <
STAT_DETECT_THR || BEMF < FG_BEMF_THR), the MSS proceeds to
BEMF < STAT_DETECT_THR judgement. If the motor is not stationary,
MSS proceeds to verify the direction of spin.
STAT_BRK_EN Judgement
Stationary Brake Routine
Direction of spin Judgement
The MSS checks if the stationary brake function is enabled (STAT_BRK_EN
=1b). If the stationary brake function is enabled, the MSS advances to the
stationary brake routine. If the stationary brake function is disabled, the MSS
advances to motor start-up state (see 节8.3.9.4).
The stationary brake routine can be used to ensure the motor is completely
stationary before attempting to start the motor. The stationary brake is
applied by turning on all three low-side driver MOSFETs for a time
configured by STARTUP_BRK_TIME.
The MSS determines whether the motor is spinning in the forward or the
reverse direction. If the motor is spinning in the forward direction, the
MCT8317A proceeds to the RESYNC_EN judgement. If the motor is
spinning in the reverse direction, the MSS proceeds to the RVS_DR_EN
judgement.
RESYNC_EN Judgement
If RESYNC_EN is set to 1b, MCT8317A proceeds to BEMF >
RESYNC_MIN_THRESHOLD judgement. If RESYNC_EN is set to 0b, MSS
proceeds to HIZ_EN judgement.
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BEMF >
If motor speed is such that BEMF > RESYNC_MIN_THRESHOLD,
RESYNC_MIN_THRESHOLD
Judgement
MCT8317A uses the speed and position information from ISD to transition to
the closed loop state (see 节8.3.9.2 ) directly. If BEMF <
RESYNC_MIN_THRESHOLD, MCT8317A proceeds to BEMF <
STAT_DETECT_THR judgement.
BEMF < STAT_DETECT_THR
Judgement
If motor speed is such that BEMF > STAT_DETECT_THR, MCT8317A
proceeds to motor coast timeout. If BEMF < STAT_DETECT_THR,
MCT8317A proceeds to STAT_BRK_EN judgement.
Motor Coast Timeout
MCT8317A waits for 200000 PWM cycles for the motor to coast down to a
speed where BEMF < STAT_DETECT_THR; after 200000 PWM cycles
lapse in the motor coast state, MCT8317A proceeds to STAT_BRK_EN
judgement irrespective of BEMF. If BEMF < STAT_DETECT_THR during
motor coast before the 200000 cycle timeout, MCT8317A proceeds to
STAT_BRK_EN judgement immediately.
RVS_DR_EN Judgement
The MSS checks to see if the reverse drive function is enabled
(RVS_DR_EN = 1b). If it is enabled, the MSS transitions to check speed of
the motor in reverse direction. If the reverse drive function is not enabled
(RVS_DR_EN = 0b), the MSS advances to the HIZ_EN judgement.
Speed > MIN_DUTY Judgement The MSS checks if the speed (in reverse direction) is higher than the speed
at MIN_DUTY - till the speed (in reverse direction) is higher than the speed
at MIN_DUTY, MSS stays in reverse closed loop deceleration. When speed
(in reverse direction) drops below the speed at MIN_DUTY, the MSS
transitions to reverse open loop deceleration.
Reverse Open Loop
Deceleration and Zero Speed
Crossover
In reverse open loop deceleration, the MCT8317A decelerates the motor in
open-loop till speed reaches zero. At zero speed, direction changes and
MCT8317A begins open loop acceleration.
HIZ_EN Judgement
The MSS checks to determine whether the coast (Hi-Z) function is enabled
(HIZ_EN = 1b). If the coast function is enabled (HIZ_EN = 1b), the MSS
advances to the coast routine. If the coast function is disabled (HIZ_EN =
0b), the MSS advances to the BRAKE_EN judgement.
Coast (Hi-Z) Routine
The device coasts the motor by turning OFF all six MOSFETs for a certain
time configured by HIZ_TIME.
BRAKE_EN Judgement
The MSS checks to determine whether the brake function is enabled
(BRAKE_EN = 1b). If the brake function is enabled (BRAKE_EN = 1b), the
MSS advances to the brake routine. If the brake function is disabled
(BRAKE_EN = 0b), the MSS advances to the motor start-up state (see 节
8.3.9.4).
Brake Routine
MCT8317A implements either a time based brake (duration configured by
BRK_TIME) or a current based brake (brake applied till phase currents <
BRK_CURR_THR) based on BRK_CONFIG. Current based brake is
followed by an additional brake time to ensure the motor is stationary before
start-up; this additional brake time is configured by STARTUP_BRK_TIME.
Brake is applied either using high-side or low-side MOSFETs based on
BRK_MODE configuration.
Closed Loop
In this state, the MCT8317A drives the motor with sensorless trapezoidal
commutation based on either zero cross detection or BEMF integration.
8.3.9.1 Initial Speed Detect (ISD)
The ISD function is used to identify the initial condition of the motor and is enabled by setting ISD_EN to 1b. The
initial speed, position and direction is determined by sampling the phase voltage through the internal ADC. ISD
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can be disabled by setting ISD_EN to 0b. If the function is disabled (ISD_EN set to 0b), the MCT8317A does not
perform the initial speed detect function and proceeds to check if the brake routine (BRAKE_EN) is enabled.
8.3.9.2 Motor Resynchronization
The motor resynchronization function works when the ISD and resynchronization functions are both enabled and
the device determines that the initial state of the motor is spinning in the forward direction (same direction as the
commanded direction). The speed and position information measured during ISD are used to initialize the drive
state of the MCT8317A, which can transition directly into closed loop state without needing to stop the motor. In
the MCT8317A, motor resynchronization can be enabled/disabled through RESYNC_EN bit. If motor
resynchronization is disabled, the device proceeds to check if the motor coast (Hi-Z) routine is enabled.
8.3.9.3 Reverse Drive
The MCT8317A uses the reverse drive function to change the direction of the motor rotation when ISD_EN and
RVS_DR_EN are both set to 1b and the ISD determines the motor spin direction to be opposite to that of the
commanded direction. Reverse drive includes synchronizing with the motor speed in the reverse direction,
reverse decelerating the motor through zero speed, changing direction, and accelerating in open loop in forward
(or commanded) direction until the device transitions into closed loop in forward direction (see 图 8-20).
MCT8317A uses the same parameter values for open to closed loop handoff threshold
(OPN_CL_HANDOFF_THR), open loop acceleration rates (OL_ACC_A1, OL_ACC_A2) and open loop current
limit (OL_ILIMIT) in the reverse direction as in the forward direction..
Speed
Close loop
Handoff to close loop
Open loop
Time
Handoff to open loop
Open Loop
Reverse Deceleration
图8-20. Reverse Drive Function
8.3.9.4 Motor Start-up
There are different options available for motor start-up from a stationary position and these options can be
configured by MTR_STARTUP. In align and double align mode, the motor is aligned to a known position by
injecting a DC current. In IPD mode, the rotor position is estimated by applying 6 different high-frequency pulses.
In slow first cycle mode, the motor is started by applying a low frequency cycle.
8.3.9.4.1 Align
Align is enabled by configuring MTR_STARTUP to 00b. The MCT8317A aligns the motor by injecting a DC
current using a particular phase pattern (phase-C high-side FET and phase-B low-side FET are ON) - current
flowing into phase-B and flowing out from phase-C for a certain time configured by ALIGN_TIME.
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The duty cycle during align is defined by ALIGN_DUTY. In MCT8317A, current limit during align is configured
through OL_ILIMIT_CONFIG and is determined by ILIMIT or OL_ILIMIT based on configuration of
OL_ILIMIT_CONFIG.
A fast change in the phase current during align may result in a sudden change in the driving torque and this
could result in acoustic noise. To avoid this, the MCT8317A ramps up duty cycle from 0 to until it reaches
ALIGN_DUTY at a configurable rate set by ALIGN_RAMP_RATE. At the end of align routine, the motor will be
aligned at the known position.
8.3.9.4.2 Double Align
Double align is enabled by configuring MTR_STARTUP to 01b. Single align is not reliable when the initial
position of the rotor is 180o out of phase with the applied phase pattern. In this case, it is possible to have start-
up failures using single align. In order to improve the reliabilty of align based start-up, the MCT8317A provides
the option of double align start-up. In double align start-up, MCT8317A uses a phase pattern for the second align
that is 60o out of phase with the first align phase pattern in the commanded direction. In double align, relevant
parameters like align time, current limit, ramp rate are the same as in the case of single align - two different
phase patterns are applied in succession with the same parameters to ensure that the motor will be aligned to a
known position irrespective of initial rotor position.
8.3.9.4.3 Initial Position Detection (IPD)
Initial Position Detection (IPD) can be enabled by configuring MTR_STARTUP to 10b. In IPD, inductive sense
method is used to determine the initial position of the motor using the spatial variation in the motor inductance.
Align or double align may result in the motor spinning in the reverse direction before starting open loop
acceleration. IPD can be used in such applications where reverse rotation of the motor is unacceptable. IPD
does not wait for the motor to align with the commutation and therefore can allow for a faster motor start-up
sequence. IPD works well when the inductance of the motor varies as a function of position. IPD works by
pulsing current in to the motor and hence can generate acoustics which must be taken into account when
determining the best start-up method for a particular application.
8.3.9.4.3.1 IPD Operation
IPD operates by sequentially applying six different phase patterns according to the following sequence: BC->
CB-> AB-> BA-> CA-> AC (see 图 8-21). When the current reaches the threshold configured by
IPD_CURR_THR, the MCT8317A stops driving the particular phase pattern and measures the time taken to
reach the current threshold from when the particular phase pattern was applied. Thus, the time taken to reach
IPD_CURR_THR is measured for all six phase patterns - this time varies as a function of the inductance in the
motor windings. The state with the shortest time represents the state with the minimum inductance. The
minimum inductance is because of the alignment of the north pole of the motor with this particular driving state.
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IPD_CLK
Clock
Drive
C
B C
C B
A B
B A
C A
A C
IPD_CURR_THR
Current
Search the Minimum Time
Minimum
Time
Smallest
Inductance
Saturation Position of
the Magnetic Field
Permanent
Magnet Position
图8-21. IPD Function
8.3.9.4.3.2 IPD Release Mode
Two modes are available for configuring the way the MCT8317A stops driving the motor when the current
threshold is reached. The recirculate (or brake) mode is selected if IPD_RLS_MODE = 0b. In this configuration,
the low-side (LSC) MOSFET remains ON to allow the current to recirculate between the MOSFET (LSC) and
body diode (LSA) (see 图 8-22). Hi-Z mode is selected if IPD_RLS_MODE = 1b. In Hi-Z mode, both the high-
side (HSA) and low-side (LSC) MOSFETs are turned OFF and the current recirculates through the body diodes
back to the power supply (see 图8-23).
In the Hi-Z mode, the phase current has a faster settle-down time, but that can result in a voltage increase on
VM. The user must manage this with an appropriate selection of either a clamp circuit or by providing sufficient
capacitance between VM and GND to absorb the energy. If the voltage surge cannot be contained or if it is
unacceptable for the application, recirculate mode must be used. When using the recirculate mode, select the
IPD_CLK_FREQ appropriately to give the current in the motor windings enough time to decay to to 0-A before
the next IPD phase pattern is applied.
HSB
HSC
LSC
HSA
VM
LSA
HSB
LSB
HSC
LSC
HSA
VM
LSA
M
M
LSB
Driving
Brake (Recirculate)
图8-22. IPD Release Mode 0
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HSB
HSC
LSC
HSA
HSB
HSC
LSC
HSA
VM
LSA
M
VM
LSA
M
LSB
LSB
Driving
Hi-Z (Tri-State)
图8-23. IPD Release Mode 1
8.3.9.4.3.3 IPD Advance Angle
After the initial position is detected, the MCT8317A begins driving the motor in open loop at an angle specified
by IPD_ADV_ANGLE.
Advancing the drive angle anywhere from 0° to 180° results in positive torque. Advancing the drive angle by 90°
results in maximum initial torque. Applying maximum initial torque could result in uneven acceleration to the
rotor. Select the IPD_ADV_ANGLE to allow for smooth acceleration in the application (see 图8-24).
Motor spinning direction
C
B
A
B
A
B
A
A
B
C
C
C
C
30 advance
90 advance
120 advance
60 advance
图8-24. IPD Advance Angle
8.3.9.4.4 Slow First Cycle Startup
Slow First Cycle start-up is enabled by configuring MTR_STARTUP to 11b. In slow first cycle start-up, the
MCT8317A starts motor commutation at a frequency defined by SLOW_FIRST_CYCLE_FREQ. The frequency
configured is used only for first cycle, and then the motor commutation follows acceleration profile configured by
open loop acceleration coefficients A1 and A2. The slow first cycle frequency has to be configured to be slow
enough to allow motor to synchronize with the commutation sequence. This mode is useful when fast startup is
desired as it significantly reduces the align time.
8.3.9.4.5 Open loop
Upon completing the motor position initialization with either align, double align, IPD or slow first cycle, the
MCT8317A begins to accelerate the motor in open loop. During open loop, fixed duty cycle is applied and the
cycle by cycle current limit functionality is used to regulate the current.
In MCT8317A, open loop current limit threshold is selected through OL_ILIMIT_CONFIG and is set either by
ILIMIT or OL_ILIMIT based on the configuration of OL_ILIMIT_CONFIG. Open loop duty cycle is configured
through OL_DUTY. While the motor is in open loop, speed (and commutation instants) is determined by 方程式
2. In MCT8317A, open loop acceleration coefficients, A1 and A2 are configured through OL_ACC_A1 and
OL_ACC_A2 respectively. The function of the open-loop operation is to drive the motor to a speed at which the
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motor generates sufficient BEMF to allow the BEMF zero-crossing based commutation control to accurately
drive the motor.
Speed (t) = A1 * t + 0.5 * A2 * t2
(2)
8.3.9.4.6 Transition from Open to Closed Loop
MCT8317A has an internal mechanism to determine the motor speed for transition from open loop commutation
to BEMF zero crossing based closed loop commutation. This feature of automatically deciding the open to
closed handoff speed can be enabled by configuring AUTO_HANDOFF to 1b. If AUTO_HANDOFF is set to 0b,
the open to closed loop handoff speed needs to be configured by OPN_CL_HANDOFF_THR. The closed loop in
this section does not refer to closed speed loop - it refers to the commutation control changing from open loop
(equation based) to closed loop (BEMF zero crossing based).
8.3.10 Closed Loop Operation
In closed loop operation, the MCT8317A drives the motor using trapezoidal commutation. The commutation
instant is determined by the BEMF zero crossing on the phase which is not driven (Hi-Z). The duty cycle of the
applied motor voltage is determined by DUTY OUT (see Motor Control Input Options).
8.3.10.1 120o Commutation
In 120o commutation, each phase is driven for 120o and is Hi-Z for 60o within each half electrical cycle as shown
in 图 8-25. In 120o commutation there are six different commutation states. 120o commutation can be configured
by setting COMM_CONTROL to 00b. MCT8317A supports different modulation modes with 120o commutation
which can be configured through PWM_MODUL.
©
©
©
©
©
©
©
ZC
ZC
ZC
ZC
ZC
ZC
ZC
Commuta on point
©
ZC Back-EMF zero crossings
Phase
PHASE CURRENT
PHASE VOLTAGE
A
Phase
B
Phase
C
图8-25. 120o commutation
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8.3.10.1.1 High-Side Modulation
High-side modulation can be configured by setting PWM_MODUL to 00b. In high-side modulation, for a given
commutation state, one of the high-side FETs is switching with the commanded duty cycle DUTY_OUT, while the
low-side FET is ON with 100% duty cycle (see 图8-26).
ZC
ZC
ZC
ZC
ZC
ZC
ZC
ZC
ZC
ZC
Phase
Voltage A
Phase
Voltage B
Phase
Voltage C
图8-26. 120o commutation in High Side Modulation Mode
8.3.10.1.2 Low-Side Modulation
Low-side modulation can be configured by setting PWM_MODUL to 01b. In low-side modulation, for a given
commutation state, one of the low-side FETs is switching with the commanded duty cycle DUTY_OUT, while the
high-side FET is ON with 100% duty cycle (see 图8-27).
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ZC
ZC
ZC
ZC
ZC
ZC
ZC
ZC
ZC
ZC
Phase
Voltage A
Phase
Voltage B
Phase
Voltage C
图8-27. 120 o commutation in Low Side Modulation Mode
8.3.10.1.3 Mixed Modulation
Mixed modulation can be configured by setting PWM_MODUL to 10b. In mixed modulation, MCT8317A
dynamically switches between high and low-side modulation (see 图 8-28). The switching losses are distributed
evenly amongst the high and low-side MOSFETs in mixed modulation mode.
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ZC
ZC
ZC
ZC
ZC
ZC
ZC
ZC
ZC
ZC
Phase
Voltage A
Phase
Voltage B
Phase
Voltage C
图8-28. 120o commutation in Mixed Modulation Mode
8.3.10.2 Variable Commutation
Variable commutation can be configured by setting COMM_CONTROL to 01b. 120o commutation may result in
acoustic noise due to the long Hi-Z period causing some torque ripple in the motor. In order to reduce this torque
ripple and acoustic noise, the MCT8317A uses variable commutation to reduce the phase current ripple at
commutation by extending 120o driving time and gradually decreasing duty cycle prior to entering Hi-Z state. In
this mode, the phase is Hi-Z between 30o and 60o and this window size is dynamically adjusted based on speed.
A smaller window size will typically give better acoustic performance. 图 8-29 shows 150o commutation with 30o
window size.
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©
©
©
©
©
©
©
ZC
ZC
ZC
ZC
ZC
ZC
ZC
Commuta on point
©
ZC Back-EMF zero crossings
Phase
A
PHASE CURRENT
PHASE VOLTAGE
15 deg
30 deg
Phase
B
15 deg
Phase
C
图8-29. 150o commutation
备注
Different modulation modes are supported only with 120o commutation; variable commutation uses
mixed modulation mode only.
8.3.10.3 Lead Angle Control
To achieve the best efficiency, it is often desirable to control the drive state of the motor so that the motor phase
current is aligned with the motor BEMF voltage. MCT8317A provides the option to advance or delay the phase
voltage from the commutation point by adjusting the lead angle. The lead angle can be adjusted to obtain
optimal efficiency. This can be accomplished by operating the motor at constant speed and load conditions and
adjusting the lead angle (LD_ANGLE) until the minimum current is achieved. The MCT8317A has the capability
to apply both positive and negative lead angle (by configuring LD_ANGLE_POLARITY) as shown in 图8-30
Lead angle can be calculated by {LD_ANGLE x 0.12}o; for example, if the LD_ANGLE is 0x1E and
LD_ANGLE_POLARITY is 1b, then a lead angle of +3.6o(advance) is applied. If LD_ANGLE_POLARITY is 0b,
then a lead angle of -3.6o(delay) is applied.
备注
For 120o commutation, the negative lead angle is limited to -20o; any lead angle lower than that will be
clamped to -20o.
For variable commutation, negative lead angle is not supported and positive lead angle is limited to
+15o. Anything configured higher than +15o or lower than 00 will be clamped to 15o and 0o
respectively.
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(a)
Phase
Voltage
Phase
BEMF
}
POS
(b)
Phase
Voltage
Phase
BEMF
}
NEG
图8-30. Positive and Negative Lead Angle Definition
8.3.10.4 Closed loop accelerate
To prevent sudden changes in the torque applied to the motor which could result in acoustic noise, the
MCT8317A device provides the option of limiting the maximum rate at which the speed command can change.
The closed loop acceleration rate parameter sets the maximum rate at which the speed command changes
(shown in 图8-31). In the MCT8317A, closed loop acceleration rate is configured through CL_ACC.
y%
Speed command
input
x%
y%
Speed command
after closed loop
accelerate buffer
x%
Closed loop
accelerate settings
图8-31. Closed loop accelerate
8.3.11 Speed Loop
MCT8317A has a speed loop which can be used to maintain constant speed under varying operating conditions.
Speed loop is enabled by setting CLOSED_LOOP_MODE to 01b. Kp and Ki coefficients are configured through
SPD_POWER_KP and SPD_POWER_KI. The output of speed loop (SPEED_PI_OUT) is used to generate the
DUTY_OUT (see 图 8-8). The PI controller output upper (VMAX) and lower bound (VMIN) saturation limits are
configured through SPD_POWER_V_MAX and SPD_POWER_V_MIN respectively. When output of the speed
loop saturates, the integrator is disabled to prevent integral wind-up. The speed loop PI controller is as in 图
8-32.
SPEED_REF is derived from duty command input and maximum motor speed (MAX_SPEED) configured by
user (see 方程式3). In speed loop mode, minimum SPEED_REF is set by MIN_DUTY * MAX_SPEED.
SPEED_REF = DUTY CMD * MAX_SPEED
(3)
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MAX_SPEED
VMAX
SPEED_REF
SPEED_PI_OUT
OUT
Kp
Ki
+
DUTY CMD
+
-
+
VMIN
SPEED_MEAS
+
+
Z-1
Switch Close
If VMIN<OUT <VMAX
图8-32. Speed Loop
8.3.12 Input Power Regulation
MCT8317A provides an option of regulating the (input) power instead of motor speed - this input power
regulation can be done in two modes, namely, closed loop power control and power limit control. Input power
regulation (instead of motor speed) mode is selected by setting CLOSED_LOOP_MODE to 10b. This should be
accompanied by setting CONST_POWER_MODE to 01b for closed loop power control or to 10b for power limit
control. In either of the power regulation modes, the maximum power that MCT8317A can draw from the DC
input supply is set by MAX_POWER - the power reference (POWER_REF in 图 8-33) varies as function of the
duty command input (DUTY_CMD) and MAX_POWER as given by 方程式 4. The hysteresis band for the power
reference is set by CONST_POWER_LIMIT_HYST. In both the power regulation modes, the minimum power
reference is set by MIN_DUTY x MAX_POWER.
POWER_REF = DUTY_CMD x MAX_POWER
(4)
In both the power regulation modes, MCT8317A uses the same PI controller parameters as in the speed loop
mode. Kp and Ki coefficients are configured through SPD_POWER_KP and SPD_POWER_KI. The PI controller
output upper (VMAX) and lower bound (VMIN) saturation limits are configured through SPD_POWER_V_MAX and
SPD_POWER_V_MIN respectively. The key difference between closed loop power control and power limit
control is in the when the PI controller decides the DUTY_OUT (see 图 8-8) applied to FETs. In closed loop
power control, DUTY_OUT is always equal to POWER_PI_OUT from the PI controller output in 图 8-33.
However, in power limit control, the PI controller decides the DUTY_OUT only if POWER_MEAS >
POWER_REF
+
CONST_POWER_LIMIT_HYST.
If
POWER_MEAS
<
POWER_REF
+
CONST_POWER_LIMIT_HYST, the PI controller is not used and DUTY_OUT is equal to DUTY_CMD.
Essentially, in closed loop power control, input power is always actively regulated to POWER_REF whereas, in
power limit control, input power is only limited to POWER_REF and not actively regulated to POWER_REF.
When output of the power PI loop saturates, the integrator is disabled to prevent integral wind-up.
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MAX_POWER
VMAX
POWER_REF
POWER_PI_OUT
OUT
Kp
Ki
+
DUTY CMD
+
-
+
VMIN
POWER_MEAS
+
+
ESTIMATED
INPUT DC
CURRENT
Z-1
MEASURED INPUT
DC VOLTAGE
Switch Close
If VMIN<OUT <VMAX
图8-33. Power Regulation
8.3.13 Anti-Voltage Surge (AVS)
When a motor is driven, energy is transferred from the power supply into the motor. Some of this energy is
stored in the form of inductive and mechanical energy. If the speed command suddenly drops such that the
BEMF voltage generated by the motor is greater than the voltage that is applied to the motor, then the
mechanical energy of the motor is returned to the power supply and the VM voltage surges. The AVS feature
works to prevent this voltage surge on VM and can be enabled by setting AVS_EN to 1b. AVS can be disabled by
setting AVS_EN to 0b. When AVS is disabled, the deceleration rate is configured through CL_DEC_CONFIG
8.3.14 Output PWM Switching Frequency
MCT8317A provides the option to configure the output PWM switching frequency of the MOSFETs through
PWM_FREQ_OUT. PWM_FREQ_OUT has range of 5-100 kHz. In order to select optimal output PWM switching
frequency, user has to make tradeoff between the current ripple and the switching losses. Generally, motors
having lower L/R ratio require higher PWM switching frequency to reduce current ripple.
8.3.15 Fast Start-up (< 50 ms)
MCT8317A has the capability to accelerate a motor from 0 to 100% speed within 50 ms. This will only work on
low inertia motors which are capable of this level of acceleration. In order to achieve fast start-up, the
commutation instant detection needs to be configured to hybrid mode by setting INTEG_ZC_METHOD to 1b. In
the hybrid mode, the commutation instant is determined by using back-EMF integration at low-medium speeds
and by using built-in comparators (BEMF zero crossing) at higher speeds. MCT8317A automatically transitions
between back-EMF integration and comparator based commutation depending on the motor speed as shown in
图 8-34. The duty cycles for commutation method transition at lower speeds are directly configured by
INTEG_DUTY_THR_LOW and INTEG_DUTY_THR_HIGH and at higher speeds are indirectly configured by
INTEG_CYC_THR_LOW and INTEG_CYC_THR_HIGH. These duty cycles should be configured to provide a
sufficient hysteresis band to avoid repeated commutation method transitions near threshold duty cycles. The
BEMF threshold values used to determine the commutation instant in the back-EMF integration method are
configured by BEMF_THRESHOLD1 and BEMF_THRESHOLD2.
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Commutation method
Integration based
ZC based
Duty cycle
INTEG_DUTY INTEG_DUTY
_THR_LOW _THR_HIGH
Duty 1 Duty 2
Duty 1- Duty cycle at which motor speed is such that number
of BEMF samples per 30o is > INTEG_CYCL_THR_HIGH
Duty 2 - Duty cycle at which motor speed is such that number
of BEMF samples per 30o is < INTEG_CYCL_THR_LOW
图8-34. Commutation Method Transition
8.3.15.1 BEMF Threshold
图 8-35 shows the three-phase voltages during 120o trapezoidal operation. It is seen that one of the phases will
always be floating within a 60o commuation interval and MCT8317A integrates this floating phase voltage (which
denotes the motor back-EMF) in the back-EMF integration method to detect the next commutation instant. The
floating phase voltage can either be increasing or decreasing and the algorithm starts the integration after the
zero cross detection in order to eliminate integration errors due to variable degauss time. The floating phase
voltage is periodically sampled (after zero cross) and added (discrete form of integration). BEMF threshold
(BEMF_THRESHOLD1 and BEMF_THRESHOLD2) value is set such that the integral value of the floating phase
voltage crosses the BEMF_THRESHOLD1 or BEMF_THRESHOLD2 value at (or very near) to the commutation
instant. BEMF_THRESHOLD1 is the threshold for rising floating phase voltage and BEMF_THRESHOLD2 is the
threshold for falling floating phase voltage. If BEMF_THRESHOLD2 is set to 0, then BEMF_THRESHOLD1 is
used as the threshold for both rising and falling floating phase voltage.
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Vpeak
Vpeak
2
Tc
Vpeak
Vpeak
2
Vpeak
Vpeak
2
0o
60o
300o
180o
240o
360o
120o
Electrical Angle, θ (degree)
图8-35. Back-EMF integration using floating phase voltage
In 图 8-35 , Vpeak is the peak-peak value of the back-EMF , Vpeak/2 denotes the zero cross of the back-EMF
and Tc is the commutation interval or time period of the 60o window. The highlighted triangle in each 60o window
is the integral value of back-EMF used by the algorithm to determine the commutation instant. This integral
value, which can be approximated as the area of the highlighted triangle, is given by 方程式5.
(½)* (Vpeak/2) * Tc/2
(5)
See for an example application on setting the BEMF threshold.
8.3.15.2 Dynamic Degauss
In MCT8317A, the degauss time can be dynamically computed after the commutation for a precise detection of
the zero crossing instant. This is done by enabling the dynamic degauss feature (DYN_DEGAUSS_EN is set to
1b). This feature allows the motor control algorithm to capture the zero crossing instant after the outgoing
(floating) phase voltage is completely settled; that is, when the outgoing phase current has decayed to zero and
the outgoing (floating) phase voltage is not clamped (to either VM or PGND) and represents the true back-EMF.
This accurate measurement of zero cross instant allows fast acceleration of the motors (< 50ms) using
MCT8317A.
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VM
*
*
VM
2
*
*
PGND
Degauss time(shown by double-sided arrow) after commutation during which the outgoing(floating) phase
voltage is clamped to VM(by negative outgoing phase current) during increasing back-EMF; sampling of
back-EMF(denoted by *) should start after degauss time is over for accurate zero cross instant detection
VM
VM
2
*
*
*
*
PGND
Degauss time(shown by double-sided arrow) after commutation during which the outgoing(floating) phase
voltage is clamped to PGND(by positive outgoing phase current) during decreasing back-EMF; sampling of
back-EMF(denoted by *) should start after degauss time is over for accurate zero cross instant detection
图8-36. Degauss Time
8.3.16 Fast Deceleration
MCT8317A has the capability to decelerate a motor quickly (100% to 10% speed reduction within tens of ms)
without pumping energy back into the input DC supply using the fast deceleration feature in conjunction with the
AVS feature. The fast deceleration feature can be enabled by setting FAST_DECEL_EN to 1b; AVS_EN should
be set to 1b to prevent energy pump-back into the input DC supply. This combination enables a linear braking
effect resulting in a fast and smooth speed reduction without energy pump-back into the DC input supply. This
feature combination can also be used during reverse drive (see Reverse Drive) or motor stop (see Active Spin-
Down) to reduce the motor speed quickly without energy pump-back into the DC input supply.
The deceleration time can be controlled by appropriately configuring the current limit during deceleration,
FAST_DECEL_CURR_LIM. A higher current limit results in a lower deceleration time and vice-versa. A higher
than necessary current limit setting may result in motor stall faults, at low target speeds, due to excessive
braking torque. This can also lead to higher losses in MCT8317A, especially in repeated acceleration-
deceleration cycles. Therefore, the FAST_DECEL_CURR_LIM should be chosen appropriately, so as to
decelerate within the required time without resulting in stall faults or overheating.
FAST_BRK_DELTA is used to configure the target speed hysteresis band to exit the fast deceleration mode and
re-enter motoring mode when motor reaches the target speed. For example, if FAST_BRK_DELTA is set to 1%,
the fast deceleration is deemed complete when motor speed reaches within 1% of target speed. Setting a higher
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value for FAST_BRK_DELTA may eliminate motor stall faults, especially when high FAST_DECEL_CURR_LIM
values are used. Setting a higher value for FAST_BRK_DETLA will also result in higher speed error between
target speed and motor speed at the end of deceleration mode - motor will eventually reach the target speed
once motoring mode is resumed. FAST_DECEL_CURR_LIM and FAST_BRK_DELTA should be configured in
tandem to optimize between lower deceleration time and reliable (no stall faults) deceleration profile.
FAST_DEC_DUTY_THR configures the speed below which fast deceleration will be implemented. For example,
if FAST_DEC_DUTY_THR is set to 70%, any deceleration from speeds above 70% will not use fast deceleration
until the speed goes below 70%. FAST_DEC_DUTY_WIN is used to set the minimum deceleration window
(initial speed - target speed) below which fast deceleration will not be implemented. For example, if
FAST_DEC_DUTY_WIN is set to 15% and 50%->40% deceleration command is received, fast deceleration is
not used to reduce the speed from 50% to 40% since the deceleration window (10%) is smaller than
FAST_DEC_DUTY_WIN.
MCT8317A provides a dynamic current limit option during fast deceleration to improve the stability of fast
deceleration when braking to very low speeds; using this feature the current limit during fast deceleration can be
reduced as the motor speed decreases. This feature can be enabled by setting DYNAMIC_BRK_CURR to 1b.
The current limit at the start of fast deceleration (at FAST_DEC_DUTY_THR) is configured by
FAST_DECEL_CURR_LIM and the current limit at zero speed is configured by DYN_BRK_CURR_LOW_LIM;
the current limit during fast deceleration varies linearly with speed between these two operating points when
dynamic current limit is enabled. If dynamic current limit is disabled, current limit during fast deceleration stays
constant and is configured by FAST_DECEL_CURR_LIM.
8.3.17 Motor Stop Options
The MCT8317A provides different options for stopping the motor which can be configured by MTR_STOP.
8.3.17.1 Coast (Hi-Z) Mode
Coast (Hi-Z) mode is configured by setting MTR_STOP to 000b. When motor stop command is received, the
MCT8317A will transition into a high impedance (Hi-Z) state by turning off all MOSFETs. When the MCT8317A
transitions from driving the motor into a Hi-Z state, the inductive current in the motor windings continues to flow
and the energy returns to the power supply through the body diodes in the MOSFET output stage (see example
图8-37).
HSC
LSC
HSA
LSA
HSB
HSC
LSC
HSA
LSA
HSB
LSB
VM
M
VM
M
LSB
Driving State
High-Impedance State
图8-37. Coast (Hi-Z) Mode
In this example, current is applied to the motor through the high-side phase-A MOSFET (HSA) and returned
through the low-side phase-C MOSFET (LSC). When motor stop command is received all 6 MOSFETs transition
to Hi-Z state and the inductive energy returns to supply through body diodes of MOSFETs LSA and HSC.
8.3.17.2 Recirculation Mode
Recirculation mode is configured by setting MTR_STOP to 001b. In order to prevent the inductive energy from
returning to DC input supply during motor stop, the MCT8317A allows current to circulate within the MOSFETs
by selectively turning OFF some of the active (ON) MOSFETs for a certain time (auto calculated recirculation
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time to allow the inductive current to decay to zero) before transitioning into Hi-Z by turning OFF the remaining
MOSFETs.
If high-side modulation was active, prior to motor stop command, then the high-side MOSFET is turned OFF on
receiving motor stop command and the current recirculation takes place through low-side MOSFET (see
example 图 8-38). Once the recirculation time lapses, the low-side MOSFET also turns OFF and all MOSFETs
are in Hi-Z state.
HSB
HSC
LSC
HSA
LSA
HSB
LSB
HSC
LSC
HSA
LSA
VM
M
VM
M
LSB
Low-Side Recirculaꢀon Mode
Driving State
图8-38. Low-Side Recirculation
If low-side modulation was active, prior to motor stop command, then the low-side MOSFET is turned OFF on
receiving motor stop command and the current recirculation takes place through high-side MOSFET (see
example 图 8-39). Once the recirculation time lapses, the high-side MOSFET also turns OFF and all MOSFETs
are in Hi-Z state
HSB
HSC
HSA
LSA
HSB
LSB
HSC
LSC
HSA
LSA
VM
M
VM
M
LSB
LSC
High-Side Recircula on Mode
Driving State
图8-39. High-Side Recirculation
8.3.17.3 Low-Side Braking
Low-side braking mode is configured by setting MTR_STOP to 010b. When a motor stop command is received,
the output speed is reduced to a value defined by ACT_SPIN_BRK_THR prior to turning all low-side MOSFETs
ON (see example 图 8-40) for a time configured by MTR_STOP_BRK_TIME. If the motor speed is below
ACT_SPIN_BRK_THR prior to receiving stop command, then the MCT8317A transitions directly into the brake
state. After applying the brake for MTR_STOP_BRK_TIME, the MCT8317A transitions into the Hi-Z state by
turning OFF all MOSFETs.
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HSC
LSC
HSA
HSB
LSB
HSC
LSC
HSA
LSA
HSB
LSB
VM
M
VM
M
LSA
Low-Side Braking
Driving State
图8-40. Low-Side Braking
The MCT8317A can also enter low-side braking through BRAKE pin input. When BRAKE pin is pulled to HIGH
state, the output speed is reduced to a value defined by BRAKE_DUTY_THRESHOLD prior to turning all low-
side MOSFETs ON. In this case, MCT8317A stays in low-side brake state till BRAKE pin changes to LOW state.
8.3.17.4 High-Side Braking
High-side braking mode is configured by setting MTR_STOP to 011b. When a motor stop command is received,
the output speed is reduced to a value defined by ACT_SPIN_BRK_THR prior to turning all high-side MOSFETs
ON (see example 图 8-41) for a time configured by MTR_STOP_BRK_TIME. If the motor speed is below
ACT_SPIN_BRK_THR prior to receiving stop command, then the MCT8317A transitions directly into the brake
state. After applying the brake for MTR_STOP_BRK_TIME, the MCT8317A transitions into Hi-Z state by turning
OFF all MOSFETs.
HSC
LSC
HSC
LSC
HSA
LSA
HSB
HSA
LSA
HSB
LSB
VM
M
VM
M
LSB
High-Side Braking
Driving State
图8-41. High-Side Braking
8.3.17.5 Active Spin-Down
Active spin down mode is configured by setting MTR_STOP to 100b. When motor stop command is received,
MCT8317A reduces duty cycle to ACT_SPIN_BRK_THR and then transitions to Hi-Z state by turning all
MOSFETs OFF. The advantage of this mode is that by reducing duty cycle, the motor is decelerated to a lower
speed thereby reducing the phase currents before entering Hi-Z. Now, when motor transitions into Hi-Z state, the
energy transfer to power supply is reduced. The threshold ACT_SPIN_BRK_THR needs to configured high
enough for MCT8317A to not lose synchronization with the motor.
8.3.18 FG Configuration
The MCT8317A provides information about the motor speed through the Frequency Generate (FG) pin. In
MCT8317A, the FG pin output is configured through FG_CONFIG. When FG_CONFIG is configured to 1b, the
FG output is active as long as the MCT8317A is driving the motor. When FG_CONFIG is configured to 0b, the
MCT8317A provides an FG output until the motor back-EMF falls below FG_BEMF_THR.
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8.3.18.1 FG Output Frequency
The FG output frequency can be configured by FG_DIV_FACTOR. In MCT8317A, FG toggles once every
commutation cycle if FG_DIV_FACTOR is set to 0000b. Many applications require the FG output to provide a
pulse for every mechanical rotation of the motor. Different FG_DIV_FACTOR configurations can accomplish this
for 2-pole up to 30-pole motors.
图 8-42 shows the FG output when MCT8317A has been configured to provide FG pulses once every
commutation cycle (electrical cycle/3), once every electrical cycle (2 poles), once every two electrical cycle (4
poles), once every three electrical cycles (6 poles), once every four electrical cycles (8 poles), and so on.
Phase A
Voltage
FG_DIV_FACTOR = 0000b
(Commuta on cycle)
FG_DIV_FACTOR = 0001b
(Elec cycle)
FG_DIV_FACTOR = 0010b
(Elec cycle*2)
FG_DIV_FACTOR = 0011b
(Elec cycle*3)
FG_DIV_FACTOR = 0100b
(Elec cycle*4)
图8-42. FG Frequency Divider
8.3.18.2 FG Open-Loop and Lock Behavior
During closed loop operation, the driving speed (FG output frequency) and the actual motor speed are
synchronized. During open-loop operation, however, FG may not reflect the actual motor speed. During motor-
lock condition, the FG output is driven high.
The MCT8317A provides three options for controlling the FG output during open loop, as shown in 图 8-43. The
selection of these options is configured through FG_SEL.
If FG_SEL is set to,
• 00b: When in open loop, the FG output is based on the driving frequency.
• 01b: When in open loop, the FG output will be driven high.
• 10b: The FG output will reflect the driving frequency during open loop operation in the first motor start-up
cycle after power-on, sleep/standby; FG will be held high during open loop operation in subsequent start-up
cycles.
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Open Loop
Close Loop
Phase A
Voltage
FG_SEL = 00
FG_SEL = 01
Close Loop
Open Loop
Open Loop
Close Loop
Phase A
Voltage
FG_SEL
= 10
Startup after power on or wake up from
sleep or standby mode
Rest of startups
图8-43. FG Behavior During Open Loop
8.3.19 Protections
The MCT8317A is protected from a host of fault events including motor lock, VM undervoltage, AVDD
undervoltage, buck undervoltage, charge pump undervoltage, overtemperature and overcurrent events. 表 8-1
summarizes the response, recovery modes, power stage status, reporting mechanism for different faults.
表8-1. Fault Action and Response
FAULT
CONDITION
CONFIGURATION
REPORT
PRE_DRIVER
DIGITAL
RECOVERY
nFAULT and
GATE_DRIVER_FA
ULT_STATUS
registe
VM undervoltage
(VM_UV)
Automatic:
TRETRY and VVM > VUVLO (rising)
VVM < VUVLO (falling)
Hi-Z
Active
—
VIN_AVDD under
voltage
(VIN_AVDD_UV)
VVIN_AVDD < VVIN_AVDD_UV
Automatic: VVIN_AVDD > VVIN_AVDD_UV
Hi-Z
Hi-Z
Disabled
Disabled
—
—
—
—
(falling)
(rising)
Automatic:
VAVDD > VAVDD_UV (rising)
AVDD undervoltage VAVDD < VAVDD_UV (falling)
nFAULT and
GATE_DRIVER_FA
ULT_STATUS
register
Charge pump
undervoltage
(CP_UV)
Automatic:
TRETRY and VCP > VCPUV (rising)
VCP < VCPUV (falling)
Hi-Z
Active
—
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表8-1. Fault Action and Response (continued)
FAULT
CONDITION
CONFIGURATION
REPORT
PRE_DRIVER
DIGITAL
RECOVERY
nFAULT and
GATE_DRIVER_FA
ULT_STATUS
register
Over Voltage
Protection
(OVP)
Automatic:
TRETRY and VVM < VOVP (falling)
VVM > VOVP (rising)
Hi-Z
Active
—
nFAULT and
GATE_DRIVER_FA
ULT_STATUS
register
OCP_MODE = 000b
OCP_MODE = 010b
Hi-Z
Hi-Z
Active
Active
Automatic : TRETRY
nFAULT and
GATE_DRIVER_FA
ULT_STATUS
register
Latched:
CLR_FLT
Overcurrent
Protection
(OCP)
IPHASE > IOCP
nFAULT and
GATE_DRIVER_FA
ULT_STATUS
register
OCP_MODE = 011b
OCP_MODE = 111b
Active
Active
Hi-Z
Active
Active
Active
No action
No action
None
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
MTR_LCK_MODE =
0000b
Latched:
CLR_FLT
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
MTR_LCK_MODE =
0001b
Latched:
CLR_FLT
Recirculation
High side brake
Low side brake
Hi-Z
Active
Active
Active
Active
Active
Active
Active
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
MTR_LCK_MODE =
0010b
Latched:
CLR_FLT
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
MTR_LCK_MODE =
0011b
Latched:
CLR_FLT
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
MTR_LCK_MODE =
0100b
Retry:
tLCK_RETRY
Motor lock: Abnormal
Speed; No Motor Lock;
Loss of Sync
Motor Lock
(MTR_LCK )
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
MTR_LCK_MODE =
0101b
Retry:
tLCK_RETRY
Recirculation
High side brake
Low side brake
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
MTR_LCK_MODE =
0110b
Retry:
tLCK_RETRY
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
MTR_LCK_MODE =
0111b
Retry:
tLCK_RETRY
CONTROLLER_FA
ULT_STATUS
register
MTR_LCK_MODE =
1000b
Active
Active
Active
Active
No action
No action
MTR_LCK_MODE =
1xx1b
None
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表8-1. Fault Action and Response (continued)
FAULT
CONDITION
CONFIGURATION
REPORT
PRE_DRIVER
DIGITAL
RECOVERY
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
CBC_ILIMIT_MODE =
0000b
Automatic:
Next PWM cycle
Recirculation
Active
CBC_ILIMIT_MODE =
0001b
Automatic:
Next PWM cycle
None
Recirculation
Recirculation
Recirculation
Recirculation
Active
Active
Active
Active
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
CBC_ILIMIT_MODE =
0010b
Automatic:
VSOX < ILIMIT
CBC_ILIMIT_MODE =
0011b
Automatic:
VSOX < ILIMIT
Cycle by Cycle
Current Limit
(CBC_ILIMIT)
None
VSOX > CBC_ILIMIT
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
CBC_ILIMIT_MODE =
0100b
Automatic:
PWM cycle > CBC_RETRY_PWM_CYC
CBC_ILIMIT_MODE =
0101b
Automatic:
PWM cycle > CBC_RETRY_PWM_CYC
None
Recirculation
Active
Active
Active
Active
CONTROLLER_FA
ULT_STATUS
register
CBC_ILIMIT_MODE=
0110b
No action
No action
CBC_ILIMIT_MODE =
0111b, 1xxxb
None
Active
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
LOCK_ILIMIT_MODE =
0000b
Latched:
CLR_FLT
Hi-Z
Active
Active
Active
Active
Active
Active
Active
Active
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
LOCK_ILIMIT_MODE =
0001b
Latched:
CLR_FLT
Recirculation
High-side brake
Low-side brake
Hi-Z
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
LOCK_ILIMIT_MODE =
0010b
Latched:
CLR_FLT
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
LOCK_ILIMIT_MODE =
0011b
Latched:
CLR_FLT
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
LOCK_ILIMIT_MODE =
0100b
Retry:
tLCK_RETRY
Lock-Detection
Current Limit
VSOX > LOCK_ILIMIT
(LOCK_ILIMIT)
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
LOCK_ILIMIT_MODE =
0101b
Retry:
tLCK_RETRY
Recirculation
High-side brake
Low-side brake
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
LOCK_ILIMIT_MODE =
0110b
Retry:
tLCK_RETRY
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
LOCK_ILIMIT_MODE =
0111b
Retry:
tLCK_RETRY
CONTROLLER_FA
ULT_STATUS
register
LOCK_ILIMIT_MODE=
1000b
Active
Active
Active
Active
No action
No action
LOCK_ILIMIT_MODE =
1xx1b
None
IPD Timeout Fault
(IPD_T1_FAULT
and
IPD TIME > 500ms
(approx), during IPD
current ramp up or ramp
down
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
Latched:
CLR_FLT
Hi-Z
Hi-Z
Hi-Z
Active
Active
Active
—
—
—
IPD_T2_FAULT)
IPD Frequency
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
IPD pulse before the
current decay in previous
IPD
Fault
Latched:
CLR_FLT
(IPD_FREQ_FAULT
)
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
Over temperature
warning
Automatic:
TJ < TOTW –TOTW_HYS
TJ > TOTW
(OTW)
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表8-1. Fault Action and Response (continued)
FAULT
CONDITION
CONFIGURATION
REPORT
PRE_DRIVER
DIGITAL
RECOVERY
nFAULT and
CONTROLLER_FA
ULT_STATUS
register
Over temperature
shutdown
Automatic:
TJ < TOTS –TOTS_HYS
TJ > TOTS
Hi-Z
Active
—
(OTS)
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8.3.19.1 VM Supply Undervoltage Lockout
If at any time the voltage on VM pin falls below the VM under voltage lockout falling threshold (VVM_UV (falling)),
FETs are in Hi-Z, nFAULT pin is driven low, DRIVER_FAULT and VM_UV bits in
GATE_DRIVER_FAULT_STATUS register are set to 1b. Normal operation resumes automatically (pre-driver
operation and the nFAULT pin is released) once the retry time (TRETRY) lapses after VM voltage is above the
VM under voltage lockout rising threshold (VVM_UV (rising)). The DRIVER_FAULT, VM_UV bits stay set to 1b until
a clear fault command is issued by writing 1b to the CLR_FLT bit.
8.3.19.2 VIN_AVDD Undervoltage Lockout (VIN_AVDD_UV)
If at any time the voltage on the VIN_AVDD pin falls lower than the VVIN_AVDD_UV (falling) threshold, all the
integrated FETs, charge-pump and digital logic controller are disabled. Device operation resumes when
VIN_AVDD voltage rises above the VVIN_AVDD_UV (rising) threshold.
8.3.19.3 AVDD Undervoltage Lockout (AVDD_UV)
If at any time the voltage on the AVDD pin falls lower than the VAVDD_UV (falling) threshold, all the integrated FETs,
charge-pump and digital logic controller are disabled. Since internal circuitry in MCT8317A is powered through
the AVDD regulator, MCT8317A goes into reset state whenever an AVDD UV event occurs. Device operation
resumes when AVDD voltage rises above the VAVDD_UV (rising) threshold.
8.3.19.4 Charge Pump Undervoltage Lockout (CP_UV)
If at any time the voltage on CP pin falls below the CP under voltage falling threshold (VCP_UV (falling)), FETs are in
Hi-Z, charge pump is disabled, nFAULT pin is driven low, DRIVER_FAULT and CP_UV bits in
GATE_DRIVER_FAULT_STATUS register are set to 1b. Normal operation resumes automatically (pre-driver,
charge pump operation and the nFAULT pin is released) once the retry time (TRETRY) lapses after CP voltage
is above the CP under voltage rising threshold (VCP_UV (rising)). The DRIVER_FAULT, CP_UV bits stay set to 1b
until a clear fault command is issued by writing 1b to CLR_FLT bit.
8.3.19.5 Overvoltage Protection (OVP)
If at any time input supply voltage on the VM pins rises higher lower than the VOVP (rising) threshold voltage, FETs
are in Hi-Z and the nFAULT pin is driven low. The DRIVER_FAULT and OVP bits are set to 1b in the
GATE_DRIVER_FAULT_STATUS register. Normal operation resumes (driver operation and the nFAULT pin is
released) once the retry time (TRETRY) lapses after VM voltage is below the VM over voltage falling threshold
(VOVP (falling)). The DRIVER_FAULT and OVP bits stay set to 1b until cleared by writing to the CLR_FLT bit.
8.3.19.6 Overcurrent Protection (OCP)
MOSFET overcurrent event is sensed by monitoring the current flowing through FETs. If the current across a
FET exceeds the IOCP threshold for longer than the tOCP deglitch time, an OCP event is recognized and action is
taken according to the OCP_MODE bit. The IOCP threshold is set through the OCP_LVL, the tOCP_DEG is set
through the OCP_DEG and the OCP_MODE bit can operate in four different modes: OCP latched shutdown,
OCP automatic retry, OCP report only and OCP disabled.
8.3.19.6.1 OCP Latched Shutdown (OCP_MODE = 010b)
When an OCP event happens in this mode, all MOSFETs are disabled and the nFAULT pin is driven low. The
DRIVER_FAULT and OCP bits are set to 1b in the GATE_DRIVER_FAULT_STATUS registers. Normal operation
resumes (driver operation and the nFAULT pin is released) when the OCP condition clears and a clear fault
command is issued by writing 1b to the CLR_FLT bit.
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Peak Current due
to deglitch time
IOCP
IOUTx
tOCP
nFAULT Released
nFAULT Pulled High
Fault Condition
nFAULT
Clear Fault
Time
图8-44. Overcurrent Protection - Latched Shutdown Mode
8.3.19.6.2 OCP Automatic Retry (OCP_MODE = 000b)
When an OCP event happens in this mode, all the FETs are disabled and the nFAULT pin is driven low. The
DRIVER_FAULT and OCP bits are set to 1b in the GATE_DRIVER_FAULT_STATUS register. Normal operation
resumes automatically (gate driver operation and the nFAULT pin is released) after the TRETRY time lapses.The
DRIVER_FAULT, OCP and corresponding FET's OCP bits are set to 1b until cleared through the CLR_FLT bit.
Peak Current due
to deglitch time
IOCP
IOUTx
tRETRY
tOCP
nFAULT Released
nFAULT Pulled High
Fault Condition
nFAULT
Time
图8-45. Overcurrent Protection - Automatic Retry Mode
8.3.19.6.3 OCP Report Only (OCP_MODE = 011b)
No protective action is taken when an OCP event happens in this mode. The overcurrent event is reported by
setting the DRIVER_FAULT and OCP bits to 1b in the GATE_DRIVER_FAULT_STATUS register. The device
continues to operate as usual. The external controller manages the overcurrent condition by acting appropriately.
The reporting clears when the OCP condition clears and a clear fault command is issued by writing 1b to the
CLR_FLT bit.
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8.3.19.6.4 OCP Disabled (OCP_MODE = 111b)
No action is taken and no reporting (nFAULT or status register bits) is done when an OCP event happens in this
mode.
8.3.19.7 Cycle-by-Cycle (CBC) Current Limit (CBC_ILIMIT)
Cycle-by-cycle (CBC) current limit provides a means of controlling the amount of current delivered to the motor.
This is useful when the system must limit the amount of current pulled from the power supply during motor
operation. The CBC current limit limits the current applied to the motor from exceeding the configured threshold.
CBC current limit functionality is achieved by connecting the output of current sense amplifier VSOX to a
hardware comparator. If the voltage at output of current sense amplifier exceeds the CBC_ILIMIT threshold, a
CBC_ILIMIT event is recognized and action is taken according to CBC_ILIMIT_MODE. Total delay in reaction to
this event is dependent on the current sense amplifier gain and the comparator delay. CBC current limit in closed
loop is set through CBC_ILIMIT while configuration of OL_ILIMIT_CONFIG sets the CBC current limit in open
loop operation. Different modes can be configured through CBC_ILIMIT_MODE: CBC_ILIMIT automatic
recovery next PWM cycle, CBC_ILIMIT automatic recovery threshold based, CBC_ILIMIT automatic recovery
number of PWM cycles based, CBC_ILIMIT report only, CBC_ILIMIT disabled.
8.3.19.7.1 CBC_ILIMIT Automatic Recovery next PWM Cycle (CBC_ILIMIT_MODE = 000xb)
When a CBC_ILIMIT event happens in this mode, MCT8317A stops driving the FETs using recirculation mode to
prevent the inductive energy from entering the DC input supply. The CBC_ILIMIT bit is set to 1b in the fault
status registers. Normal operation resumes at the start of next PWM cycle and CBC_ILIMIT bit is reset to 0b.
The status of CONTROLLER_FAULT bit and nFAULT pin will be determined by CBC_ILIMIT_MODE. When
CBC_ILIMIT_MODE is 0000b, CONTROLLER_FAULT bit is set to 1b and nFAULT pin driven low until next PWM
cycle. When CBC_ILIMIT_MODE is 0001b, CONTROLLER_FAULT bit is not set to 1b and nFAULT is not driven
low.
8.3.19.7.2 CBC_ILIMIT Automatic Recovery Threshold Based (CBC_ILIMIT_MODE = 001xb)
When a CBC_ILIMIT event happens in this mode, MCT8317A stops driving the FETs using recirculation mode to
prevent the inductive energy from entering the DC input supply. The CBC_ILIMIT bit is set to 1b in the status
registers. Normal operation resumes after VSOX falls below CBC_ILIMIT threshold and CBC_ILIMIT bit is set to
0b. The status of CONTROLLER_FAULT bit and nFAULT pin will be determined by CBC_ILIMIT_MODE. When
CBC_ILIMIT_MODE is 0010b, CONTROLLER_FAULT bit is set to 1b and nFAULT pin driven low until VSOX falls
below CBC_ILIMIT threshold. When CBC_ILIMIT_MODE is 0011b, CONTROLLER_FAULT bit is not set to 1b
and nFAULT is not driven low.
8.3.19.7.3 CBC_ILIMIT Automatic Recovery after 'n' PWM Cycles (CBC_ILIMIT_MODE = 010xb)
When a CBC_ILIMIT event happens in this mode, MCT8317A stops driving the FETs using recirculation mode to
prevent the inductive energy from entering the DC input supply. The CBC_ILIMIT bit is set to 1b in the fault
status registers. Normal operation resumes after (CBC_RETRY_PWM_CYC +1) PWM cycles and CBC_ILIMIT
bit is set to 0b. The status of CONTROLLER_FAULT bit and nFAULT pin will be determined by
CBC_ILIMIT_MODE. When CBC_ILIMIT_MODE is 0100b, CONTROLLER_FAULT bit is set to1b and nFAULT
pin driven low until (CBC_RETRY_PWM_CYC +1) PWM cycles lapse. When CBC_ILIMIT_MODE is 0101b,
CONTROLLER_FAULT bit is not set to 1b and nFAULT is not driven low.
8.3.19.7.4 CBC_ILIMIT Report Only (CBC_ILIMIT_MODE = 0110b)
No protective action is taken when a CBC_ILIMIT event happens in this mode. The CBC current limit event is
reported by setting the CONTROLLER_FAULT and CBC_ILIMIT bits to 1b in the fault status registers. The gate
drivers continue to operate. The external controller manages the overcurrent condition by acting appropriately.
The reporting clears when the CBC_ILIMIT condition clears and a clear fault command is issued through the
CLR_FLT bit.
8.3.19.7.5 CBC_ILIMIT Disabled (CBC_ILIMIT_MODE = 0111b or 1xxxb)
No action is taken when a CBC_ILIMIT event happens in this mode.
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8.3.19.8 Lock Detection Current Limit (LOCK_ILIMIT)
The lock detection current limit function provides a configurable threshold for limiting the current to prevent
damage to the system. The MCT8317A continuously monitors the output of the current sense amplifier (CSA)
through the ADC. If at any time, the voltage on the output of CSA exceeds LOCK_ILIMIT for a time longer than
tLCK_ILIMIT, a LOCK_ILIMIT event is recognized and action is taken according to LOCK_ILIMIT_MODE. The
threshold is set through LOCK_ILIMIT, the tLCK_ILIMIT is set through LOCK_ILIMIT_DEG. LOCK_ILIMIT_MODE
can be set to four different modes: LOCK_ILIMIT latched shutdown, LOCK_ILIMIT automatic retry, LOCK_ILIMIT
report only and LOCK_ILIMIT disabled.
8.3.19.8.1 LOCK_ILIMIT Latched Shutdown (LOCK_ILIMIT_MODE = 00xxb)
When a LOCK_ILIMIT event happens in this mode, the status of MOSFETs will be configured by
LOCK_ILIMIT_MODE and nFAULT is driven low. Status of MOSFETs during LOCK_ILIMIT:
• LOCK_ILIMIT_MODE = 0000b: All MOSFETs are turned OFF.
• LOCK_ILIMIT_MODE = 0001b: MOSFET which was switching is turned OFF while the one which was
conducting stays ON till inductive energy is completely recirculated.
• LOCK_ILIMIT_MODE = 0010b: All high-side MOSFETs are turned ON.
• LOCK_ILIMIT_MODE = 0011b: All low-side MOSFETs are turned ON.
The CONTROLLER_FAULT and LOCK_ILIMIT bits are set to 1b in the fault status registers. Normal operation
resumes (gate driver operation and the nFAULT pin is released) when the LOCK_ILIMIT condition clears and a
clear fault command is issued through the CLR_FLT bit.
8.3.19.8.2 LOCK_ILIMIT Automatic Recovery (LOCK_ILIMIT_MODE = 01xxb)
When a LOCK_ILIMIT event happens in this mode, the status of MOSFETs will be configured by
LOCK_ILIMIT_MODE and nFAULT is driven low. Status of MOSFETs during LOCK_ILIMIT:
• LOCK_ILIMIT_MODE = 0100b: All MOSFETs are turned OFF.
• LOCK_ILIMIT_MODE = 0101b: MOSFET which was switching is turned OFF while the one which was
conducting stays ON till inductive energy is completely recirculated.
• LOCK_ILIMIT_MODE = 0110b: All high-side MOSFETs are turned ON
• LOCK_ILIMIT_MODE = 0111b: All low-side MOSFETs are turned ON
The CONTROLLER_FAULT and LOCK_ILIMIT bits are set to 1b in the fault status registers. Normal operation
resumes automatically (gate driver operation and the nFAULT pin is released) after the tLCK_RETRY (configured by
LCK_RETRY) time lapses. The CONTROLLER_FAULT and LOCK_ILIMIT bits are reset to 0b after the
tLCK_RETRY period expires.
8.3.19.8.3 LOCK_ILIMIT Report Only (LOCK_ILIMIT_MODE = 1000b)
No protective action is taken when a LOCK_ILIMIT event happens in this mode. The lock detection current limit
event is reported by setting the CONTROLLER_FAULT and LOCK_ILIMIT bits to 1b in the fault status registers.
The gate drivers continue to operate. The external controller manages this condition by acting appropriately. The
reporting clears when the LOCK_ILIMIT condition clears and a clear fault command is issued through the
CLR_FLT bit.
8.3.19.8.4 LOCK_ILIMIT Disabled (LOCK_ILIMIT_MODE = 1xx1b)
No action is taken when a LOCK_ILIMIT event happens in this mode.
8.3.19.9 Over Temperature Warning (OTW)
If the die temperature exceeds the over temperature warning limit (TOTW), all the FETs are disabled and the
nFAULT pin is driven low. In addition, the DRIVER_FAULT and OTW bits in the
GATE_DRIVER_FAULT_STATUS register are set to 1b. Normal operation resumes (driver operation and the
nFAULT pin is released) when the die temperature decreases below the hysteresis point of the over temperature
warning limit (TOTW - TOTW_HYS). The OTW bit stays latched high indicating that a thermal event occurred until a
clear fault command is issued through the CLR_FLT bit. This protection feature cannot be disabled.
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8.3.19.10 Over Temperature Shutdown (OTS)
If the die temperature exceeds the thermal shutdown limit (TOTS), all the FETs are disabled and the nFAULT pin
is driven low. In addition, the DRIVER_FAULT and OTS bits in the GATE_DRIVER_FAULT_STATUS register are
set to 1b. Normal operation resumes (driver operation and the nFAULT pin is released) when the die
temperature decreases below the hysteresis point of the over temperature shutdown limit (TOTS - TOTS_HYS). The
OTS bit stays latched high indicating that a thermal event occurred until a clear fault command is issued through
the CLR_FLT bit. This protection feature cannot be disabled.
8.3.19.11 Motor Lock (MTR_LCK)
The MCT8317A continuously checks for different motor lock conditions (see Motor Lock Detection) during motor
operation. When one of the enabled lock condition happens, a MTR_LCK event is recognized and action is
taken according to the MTR_LCK_MODE.
In MCT8317A, all locks can be enabled or disabled individually and retry times can be configured through
LCK_RETRY . MTR_LCK_MODE bit can operate in four different modes: MTR_LCK latched shutdown,
MTR_LCK automatic retry, MTR_LCK report only and MTR_LCK disabled.
8.3.19.11.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
When a MTR_LCK event happens in this mode, the status of MOSFETs will be configured by MTR_LCK_MODE
and nFAULT is driven low. Status of MOSFETs during MTR_LCK:
• MTR_LCK_MODE = 0000b: All MOSFETs are turned OFF.
• MTR_LCK_MODE = 0001b: MOSFET which was switching is turned OFF while the one which was
conducting stays ON till inductive energy is completely recirculated.
• MTR_LCK_MODE = 0010b: All high-side MOSFETs are turned ON.
• MTR_LCK_MODE = 0011b: All low-side MOSFETs are turned ON.
The CONTROLLER_FAULT, MTR_LCK and respective motor lock condition bits are set to 1b in the fault status
registers. Normal operation resumes (gate driver operation and the nFAULT pin is released) when the MTR_LCK
condition clears and a clear fault command is issued through the CLR_FLT bit.
8.3.19.11.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
When a MTR_LCK event happens in this mode, the status of MOSFETs will be configured by MTR_LCK_MODE
and nFAULT is driven low. Status of MOSFETs during MTR_LCK:
• MTR_LCK_MODE = 0100b: All MOSFETs are turned OFF.
• MTR_LCK_MODE = 0101b: MOSFET which was switching is turned OFF while the one which was
conducting stays ON till inductive energy is completely recirculated.
• MTR_LCK_MODE = 0110b: All high-side MOSFETs are turned ON.
• MTR_LCK_MODE = 0111b: All low-side MOSFETs are turned ON.
The CONTROLLER_FAULT, MTR_LCK and respective motor lock condition bits are set to 1b in the fault status
registers. Normal operation resumes automatically (gate driver operation and the nFAULT pin is released) after
the tLCK_RETRY (configured by LCK_RETRY) time lapses. The CONTROLLER_FAULT, MTR_LCK and respective
motor lock condition bits are reset to 0b after the tLCK_RETRY period expires.
8.3.19.11.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
No protective action is taken when a MTR_LCK event happens in this mode. The motor lock event is reported by
setting the CONTROLLER_FAULT, MTR_LCK and respective motor lock condition bits to 1b in the fault status
registers. The gate drivers continue to operate. The external controller manages this condition by acting
appropriately. The reporting clears when the MTR_LCK condition clears and a clear fault command is issued
through the CLR_FLT bit.
8.3.19.11.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
No action is taken when a MTR_LCK event happens in this mode.
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8.3.19.12 Motor Lock Detection
The MCT8317A provides different lock detect mechanisms to determine if the motor is in a locked state. Multiple
detection mechanisms work together to ensure the lock condition is detected quickly and reliably. In addition to
detecting if there is a locked motor condition, the MCT8317A can also identify and take action if there is no motor
connected to the system. Each of the lock detect mechanisms and the no-motor detection can be disabled by
their respective register bits (LOCK1/2/3_EN).
8.3.19.12.1 Lock 1: Abnormal Speed (ABN_SPEED)
MCT8317A monitors the speed continuously and at any time the speed exceeds LOCK_ABN_SPEED, an
ABN_SPEED lock event is recognized and action is taken according to the MTR_LCK_MODE.
threshold is set through the LOCK_ABN_SPEED register. ABN_SPEED lock can be enabled/disabled by
LOCK1_EN.
8.3.19.12.2 Lock 2: Loss of Sync (LOSS_OF_SYNC)
The motor is commutated by detecting the zero crossing on the phase which is in Hi-Z state. If the motor is
locked, the back-EMF will disappear and MCT8317A will be not able to detect the zero crossing. If MCT8317A is
not able to detect zero crossing for LOSS_SYNC_TIMES number of times, LOSS_OF_SYNC event is
recognized and action is taken according to the MTR_LCK_MODE. LOSS_OF_SYNC lock can be enabled/
disabled by LOCK2_EN.
8.3.19.12.3 Lock3: No-Motor Fault (NO_MTR)
The MCT8317A continuously monitors the relevant phase current (low-side phase in the present phase pattern);
if the relevant phase current stays below NO_MTR_THR for a time longer than NO_MTR_DEG_TIME, a
NO_MTR event is recognized. The response to the NO_MTR event is configured through MTR_LCK_MODE .
NO_MTR lock can be enabled/disabled by LOCK3_EN.
8.3.19.13 IPD Faults
The MCT8317A uses 12-bit timers to estimate the time during the current ramp up and ramp down during IPD,
when the motor start-up is configured as IPD (MTR_STARTUP is set to 10b). During IPD, the algorithm checks
for a successful current ramp-up to IPD_CURR_THR, starting with an IPD clock of 10MHz; if unsuccessful (timer
overflow before current reaches IPD_CURR_THR), IPD is repeated with lower frequency clocks of 1MHz,
100kHz, and 10kHz sequentially. If the IPD timer overflows (current does not reach IPD_CURR_THR) with all
the four clock frequencies, then the IPD_T1_FAULT gets triggered. Similarly the algorithm check sfor a
successful current decay to zero during IPD current ramp down using all the mentioned IPD clock frequencies. If
the IPD timer overflows (current does not ramp down to zero) in all the four attempts, then the IPD_T2_FAULT
gets triggered.
IPD gives incorrect results if the next IPD pulse is commanded before the complete decay of current due to
present IPD pulse. The MCT8317A can generate a fault called IPD_FREQ_FAULT during such a scenario . The
IPD_FREQ_FAULT maybe triggerd if the IPD frequency is too high for the IPD current limit and the IPD release
mode or if the motor inductance is too high for the IPD frequency, IPD current limit and IPD release mode.
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8.4 Device Functional Modes
8.4.1 Functional Modes
8.4.1.1 Sleep Mode
In sleep mode, the MOSFETs, sense amplifiers, buck regulator, charge pump, AVDD LDO regulator and the I2C
bus are disabled. The device can be configured to enter sleep (instead of standby) mode by configuring
DEV_MODE to 1b. SPEED pin and I2C speed command determine entry and exit from sleep state as described
in 表8-2.
备注
During power-up and power-down of the device, the nFAULT pin is held low as the internal regulators
are disabled. After the regulators have been enabled, the nFAULT pin is automatically released.
8.4.1.2 Standby Mode
The device can be configured to operate as a standby device by setting DEV_MODE to 0b. In standby mode,
the charge pump, AVDD LDO, buck regulator and I2C bus are active while the motor is in stopped state waiting
for a suitable non-zero speed command. SPEED pin (analog, PWM or frequency based speed input) or I2C
speed command (I2C based speed input) determines entry and exit from standby state as described in 表8-2.
The thresholds for entering and exiting standby mode in different speed input modes are as follows,
1. Analog : VEN_SB = (ZERO_DUTY_THR x VANA_FS), VEX_SB = ((ZERO_DUTY_THR + ZERO_DUTY_HYST) x
VANA_FS
)
2. PWM : DutyEN_SB = ZERO_DUTY_THR, DutyEX_SB = (ZERO_DUTY_THR + ZERO_DUTY_HYST)
3. I2C : SPEED_CTRLEN_SB = ZERO_DUTY_THR x 32767, SPEED_CTRLEX_SB = (ZERO_DUTY_THR +
ZERO_DUTY_HYST) x 32767
4. Frequency : FreqEN_SB = ZERO_DUTY_THR x INPUT_MAX_FREQUENCY, FreqEX_SB
(ZERO_DUTY_THR + ZERO_DUTY_HYST) x INPUT_MAX_FREQUENCY
=
表8-2. Conditions to Enter or Exit Sleep or Standby Modes
SPEED
COMMAND
MODE
ENTER STANDBY
CONDITION
EXIT FROM STANDBY
CONDITION
EXIT FROM SLEEP
ENTER SLEEP CONDITION
CONDITION
VSPEED < VEN_SL for
tDET_SL_ANA
Analog
PWM
VSPEED < VEN_SB
VSPEED > VEX_SB
VSPEED > VEX_SL for tDET_ANA
DutySPEED < DutyEN_SB
DutySPEED > DutyEX_SB
VSPEED < VIL for tDET_SL_PWM VSPEED > VIH for tDET_PWM
SPEED_CTRL is set to 0b
for SLEEP_TIME and
VSPEED < VIL
SPEED_CTRL <
SPEED_CTRLEN_SB
SPEED_CTRL >
SPEED_CTRLEX_SB
I2C
VSPEED > VIH for tDET_PWM
Frequency
FreqSPEED < FreqEN_SB
FreqSPEED > FreqEX_SB
VSPEED < VIL for tDET_SL_PWM VSPEED > VIH for tDET_PWM
8.4.1.3 Fault Reset (CLR_FLT)
In the case of latched faults, the device goes into a partial shutdown state to help protect the power MOSFETs
and system. When the fault condition clears, the device can go to the operating state again by setting the
CLR_FLT to 1b.
8.5 External Interface
8.5.1 DAC outputs
MCT8317A has two 12-bit DACs which output analog voltage equivalent of digital variables on DACOUT1 and
DACOUT2 pins with resolution of 12 bits and maximum voltage is 3-V. Signals available on DACOUT pins is
useful in tracking algorithm variables in real-time and can be used for tuning speed controller or motor
acceleration time. The address for variables for DACOUT1 and DACOUT2 are configured using
DACOUT1_VAR_ADDR and DACOUT2_VAR_ADDR. DACOUT1 is available on pin 37 and DACOUT2 can be
configured on pin 36 by setting DAC_SOX_CONFIG to 00b. DACOUT2 is also available on pin 38.
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8.5.2 SOX Output
MCT8317A can provide the built-in current sense amplifiers' output on the SOX pin. SOX output is available on
pin 36 and can be configured by DAC_SOX_CONFIG.
8.5.3 Oscillator Source
MCT8317A has a built-in oscillator that is used as the clock source for all digital peripherals and timing
measurements. Default configuration for MCT8317A is to use the internal oscillator and it is sufficient to drive the
motor without need for any external crystal or clock sources.
In case MCT8317A does not meet accuracy requirements of timing measurement or speed loop, then
MCT8317A has an option to support an external clock reference.
In order to improve EMI performance, MCT8317A provides the option of modulating the clock frequency by
enabling Spread Spectrum Modulation (SSM) through SSM_CONFIG
.
8.5.3.1 External Clock Source
Speed loop accuracy of MCT8317A over wide operating temperature range can be improved by providing more
accurate optional clock reference on EXT_CLK pin as shown in 图 8-46. EXT_CLK will be used to calibrate
internal clock oscillator and match the accuracy of the external clock. External clock source can be selected by
configuring CLK_SEL to 11b and setting EXT_CLK_EN to 1b. The external clock source frequency can be
configured through EXT_CLK_CONFIG.
Internal
Oscillator
(60 MHz)
EXT_CLK
Calibrate
图8-46. External Clock Reference
备注
External clock is optional and can be used when higher clock accuracy is needed. MCT8317A will
always power up using the internal oscillator in all modes.
8.5.4 External Watchdog
MCT8317A provides an external watchdog feature - EXT_WD_EN bit should be set to 1b to enable the external
watchdog. When this feature is enabled, the device waits for a tickle (low to high transition in GPIO mode,
EXT_WD_STATUS_SET set to 1b in I2C mode) from the external watchdog input for a configured time interval; if
the time interval between two consecutive tickles is higher than the configured time, a watchdog fault is
triggered. This fault can be configured using EXT_WD_FAULT either as a report only fault or as a latched fault
with outputs in Hi-Z state. The latched fault can be cleared by writing 1b to CLR_FLT. In case, the next tickle
arrives before the configured time interval elapses, the watchdog timer is reset and it begins to wait for the next
tickle. This can be used to continuously monitor the health of an external MCU (which is the external watchdog
input) and put the MCT8317A outputs in Hi-Z in case the external MCU is in an erroneous state.
The external watchdog input is selected using EXT_WD_INPUT and can either be the EXT_WD pin or the I2C
interface . The time interval between two tickles to trigger a watchdog fault is configured by EXT_WD_FREQ;
there are 4 time (frequency) settings - 100 (10Hz), 200 (5Hz), 500 (2Hz) and 1000ms (1Hz).
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8.6 EEPROM access and I2C interface
8.6.1 EEPROM Access
MCT8317A has 1024 bits (16 rows of 64 bits each) of EEPROM, which are used to store the motor configuration
parameters. Erase operations are row-wise (all 64 bits are erased in a single erase operation), but 32-bit write
and read operations are supported. EEPROM can be written and read using the I2C serial interface but erase
cannot be performed using I2C serial interface. The shadow registers corresponding to the EEPROM are located
at addresses 0x000080-0x0000AE.
备注
MCT8317A allows EEPROM write and read operations only when the motor is not spinning.
8.6.1.1 EEPROM Write
In MCT8317A, EEPROM write procedure is as follows,
1. Write register 0x000080 (ISD_CONFIG) with ISD configuration like resync enable, reverse drive enable,
stationary detect threshold etc.,
2. Write register 0x000082 (MOTOR_STARTUP1) with motor start-up configuration like start-up method, first
cycle frequency, IPD parameters, align parameters etc.,
3. Write register 0x000084 (MOTOR_STARTUP2) with motor start-up configuration like open loop acceleration,
minimum duty cycle etc.,
4. Write register 0x000086 (CLOSED_LOOP1) with motor control configuration like closed loop acceleration,
PWM frequency, PWM modulation etc.,
5. Write register 0x000088 (CLOSED_LOOP2) with motor control configuration like FG signal parameters,
motor stop options etc.,
6. Write register 0x00008A (CLOSED_LOOP3) with motor control configuration like fast start-up and dynamic
degauss parameters including BEMF thresholds, duty cycle thresholds etc.,
7. Write register 0x00008C (CLOSED_LOOP4) with motor control configuration like fast deceleration
parameters including fast deceleration duty threshold, window, current limits etc.,
8. Write register 0x00008E (CONST_SPEED) with motor control configuration like speed loop parameters
including closed loop mode, saturation limits, Kp, Ki etc.,
9. Write register 0x000090 (CONST_PWR) with motor control configuration like input power regulation
parameters including maximum power, constant power mode, power level hysteresis, maximum speed etc.,
10. Write register 0x000092 (FAULT_CONFIG1) with fault control configuration like CBC, lock current limits and
actions, retry times etc.,
11. Write register 0x000094 (FAULT_CONFIG2) with fault control configuration like OV, UV limits and actions,
abnormal speed level, motor lock setting etc.,
12. Write registers 0x000096 and 0x000098 (150_DEG_TWO_PH_PROFILE,
150_DEG_THREE_PH_PROFILE) with PWM duty cycle configurations for 150o modulation.
13. Write registers 0x00009A and 0x00009C (TRAP_CONFIG1 and TRAP_CONFIG2) with algorithm
parameters like ISD BEMF threshold, blanking time, AVS current limits etc.,
14. Write registers 0x0000A4 and 0x0000A6 (PIN_CONFIG1 and PIN_CONFIG2) with pin configuration for DIR,
BRAKE, DACOUT1 and DACOUT2, SOX, external watchdog etc.,
15. Write register 0x0000A8 (DEVICE_CONFIG) with device configuration like device mode, external clock
enable, clock source, speed input PWM frequency range etc.,
16. Write registers 0x0000AC and 0x0000AE (GD_CONFIG1 and GD_CONFIG2) with gate driver configuration
like slew rate, CSA gain, OCP level, mode, OVP enable etc.,
17. Write 0x8A500000 into register 0x0000E6 to write the shadow register (0x000080-0x0000AE) values into the
EEPROM.
18. Wait for 100ms for the EEPROM write operation to complete
Steps 1-16 can be selectively executed based on registers/parameters that need to be modified. After all
shadow registers have been updated with the required values, step 17 should be executed to copy the contents
of the shadow registers into the EEPROM.
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8.6.1.2 EEPROM Read
In MCT8317A, EEPROM read procedure is as follows,
1. Write 0x40000000 into register 0x0000E6 to read the EEPROM data into the shadow registers
(0x000080-0x0000AE).
2. Wait for 100ms for the EEPROM read operation to complete.
3. Read the shadow register values, 1 or 2 registers at a time, using the I2C read command as explained in 节
8.6.2. Shadow register addresses are in the range of 0x000080-0x0000AE. Register address increases in
steps of 2 for 32-bit read operation (since each address is a 16-bit location).
8.6.2 I2C Serial Interface
MCT8317A interfaces with an external MCU over an I2C serial interface. MCT8317A is an I2C target to be
interfaced with a controller. External MCU can use this interface to read/write from/to any non-reserved register
in MCT8317A
备注
For reliable communication, a 100-µs delay should be used between every byte transferred over the
I2C bus.
8.6.2.1 I2C Data Word
The I2C data word format is shown in 表8-3.
表8-3. I2C Data Word Format
TARGET_ID
R/W
CONTROL WORD
DATA
CRC-8
A6 - A0
W0
CW23 - CW0
D15 / D31/ D63 - D0
C7 - C0
Target ID and R/W Bit: The first byte includes the 7-bit I2C target ID (0x00), followed by the read/write command
bit. Every packet in MCT8317A the communication protocol starts with writing a 24-bit control word and hence
the R/W bit is always 0.
24-bit Control Word: The Target Address is followed by a 24-bit control bit. The control word format is shown in
表8-4.
表8-4. 24-bit Control Word Format
OP_R/W
CRC_EN
DLEN
MEM_SEC
MEM_PAGE
MEM_ADDR
CW23
CW22
CW21- CW20
CW19 - CW16
CW15 - CW12
CW11 - CW0
Each field in the control word is explained in detail below.
OP_R/W – Read/Write: R/W bit gives information on whether this is a read operation or write operation. Bit
value 0 indicates it is a write operation. Bit value 1 indicates it is a read operation. For write operation,
MCT8317A will expect data bytes to be sent after the 24-bit control word. For read operation, MCT8317A will
expect an I2C read request with repeated start or normal start after the 24-bit control word.
CRC_EN – Cyclic Redundancy Check(CRC) Enable: MCT8317A supports CRC to verify the data integrity.
This bit controls whether the CRC feature is enabled or not.
DLEN – Data Length: DLEN field determines the length of the data that will be sent by external MCU to
MCT8317A. MCT8317A protocol supports three data lengths: 16-bit, 32-bit and 64-bit.
表8-5. Data Length Configuration
DLEN Value
00b
Data Length
16-bit
01b
32-bit
10b
64-bit
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表8-5. Data Length Configuration (continued)
DLEN Value
11b
Data Length
Reserved
MEM_SEC –Memory Section: Each memory location in MCT8317A is addressed using three separate entities
in the control word – Memory Section, Memory Page, Memory Address. Memory Section is a 4-bit field which
denotes the memory section to which the memory location belongs like RAM, ROM etc.
MEM_PAGE – Memory Page: Memory page is a 4-bit field which denotes the memory page to which the
memory location belongs.
MEM_ADDR – Memory Address: Memory address is the last 12-bits of the address. The complete 22-bit
address is constructed internally by MCT8317A using all three fields –Memory Section, Memory Page, Memory
Address. For memory locations 0x000000-0x000800, memory section is 0x0, memory page is 0x0 and memory
address is the lowest 12 bits(0x000 for 0x000000, 0x080 for 0x000080 and 0x800 for 0x000800)
Data Bytes: For a write operation to MCT8317A, the 24-bit control word is followed by data bytes. The DLEN
field in the control word should correspond with the number of bytes sent in this section.
CRC Byte: If the CRC feature is enabled in the control word, CRC byte has to be sent at the end of a write
transaction. Procedure to calculate CRC is explained in CRC Byte Calculation below.
8.6.2.2 I2C Write Operation
MCT8317A write operation over I2C involves the following sequence.
1. I2C start condition.
2. The sequence starts with I2C target start byte, made up of 7-bit target ID (0x00) to identify the MCT8317A
along with the R/W bit set to 0.
3. The start byte is followed by 24-bit control word. Bit 23 in the control word has to be 0 as it is a write
operation.
4. The 24-bit control word is then followed by the data bytes. The length of the data byte depends on the DLEN
field.
a. While sending data bytes, the LSB byte is sent first. Refer below examples for more details.
b. 16-bit/32-bit write –The data sent is written to the address mentioned in Control Word.
c. 64-bit Write –64-bit is treated as two 32-bit writes. The address mentioned in Control word is taken as
Addr 0. Addr 1 is calculating internally by MCT8317A by incrementing Addr 0 by 2. A total of 8 data
bytes are sent. The first 4 bytes (sent in LSB first way) are written to Addr 0 and the next 4 bytes are
written to Addr 1.
5. If CRC is enabled, the packet ends with a CRC byte. CRC is calculated for the entire packet (Target ID + W
bit, Control Word, Data Bytes).
6. I2C stop condition.
2 / 4 / 8 DATA BYTES
Write – without CRC
TARGET
ID [6:0]
CONTROL
WORD [23:16]
CONTROL
WORD [15:8]
CONTROL
WORD [7:0]
DATA
BYTES
DATA
BYTES
S
0
ACK
ACK
ACK
ACK
ACK
ACK
P
2 / 4 / 8 DATA BYTES
Write – with CRC
TARGET
CONTROL
WORD [23:16]
CONTROL
WORD [15:8]
CONTROL
WORD [7:0]
DATA
BYTES
DATA
S
0
ACK
ACK
ACK
ACK
ACK
ACK CRC ACK
P
ID [6:0]
BYTES
CRC includes {TARGET ID,0}, CONTROL WORD[23:0], DATA BYTES
图8-47. I2C Write Operation Sequence
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8.6.2.3 I2C Read Operation
MCT8317A read operation over I2C involves the following sequence.
1. I2C start condition.
2. The sequence starts with I2C target Start Byte.
3. The Start Byte is followed by 24-bit Control Word. Bit 23 in the control word has to be 1 as it is a read
operation.
4. The control word is followed by a repeated start or normal start.
5. MCT8317A sends the data bytes on SDA. The number of bytes sent by MCT8317A depends on the DLEN
field value in the control word.
a. While sending data bytes, the LSB byte is sent first. Refer the examples below for more details.
b. 16-bit/32-bit Read –The data from the address mentioned in Control Word is sent back.
c. 64-bit Read –64-bit is treated as two 32-bit read. The address mentioned in Control Word is taken as
Addr 0. Addr 1 is calculating internally by MCT8317A by incrementing Addr 0 by 2. A total of 8 data
bytes are sent by MCT8317A. The first 4 bytes (sent in LSB first way) are read from Addr 0 and the next
4 bytes are read from Addr 1.
d. MCT8317A takes some time to process the control word and read data from the given address. This
involves some delay. It is quite possible that the repeated start with Target ID will be NACK’d. If the I2C
read request has been NACK’d by MCT8317A, retry after few cycles. During this retry, it is not
necessary to send the entire packet along with the control word. It is sufficient to send only the start
condition with target ID and read bit.
6. If CRC is enabled, then MCT8317A sends an additional CRC byte at the end. If CRC is enabled, external
MCU I2C controller has to read this additional byte before sending the stop bit. CRC is calculated for the
entire packet (Target ID + W bit, Control Word, Target ID + R bit, Data Bytes).
7. I2C stop condition.
2 / 4 / 8 DATA BYTES
Read – without CRC
TARGET
ID [6:0]
CONTROL
WORD [23:16]
CONTROL
WORD [15:8]
CONTROL
WORD [7:0]
TARGET
ID [6:0]
DATA
BYTES
DATA
BYTES
S
0
ACK
ACK
ACK
ACK RS
1
ACK
ACK
ACK
P
Read – with CRC
TARGET
2 / 4 / 8 DATA BYTES
CONTROL
WORD [23:16]
CONTROL
WORD [15:8]
CONTROL
WORD [7:0]
TARGET
ID [6:0]
DATA
BYTES
DATA
S
0
ACK
ACK
ACK
ACK RS
1
ACK
ACK
ACK CRC ACK
P
ID [6:0]
BYTES
CRC includes {TARGET ID,0}, CONTROL WORD[23:0], {TARGET ID,1}, DATA BYTES
图8-48. I2C Read Operation Sequence
8.6.2.4 Examples of MCT8317A I2C Communication Protocol Packets
All values used in this example section are in hex format. I2C target ID used in the examples is 0x00.
Example for 32-bit Write Operation: Address – 0x00000080, Data – 0x1234ABCD, CRC Byte – 0x45
(Sample value; does not match with the actual CRC calculation)
表8-6. Example for 32-bit Write Operation Packet
Start Byte
Control Word 0
Control Word 1
Control Data Bytes
Word 2
CRC
Target
ID
I2C
Write
OP_R/ CRC_E DLEN
MEM_S MEM_P MEM_A MEM_A DB0
EC AGE DDR DDR
DB1
DB2
DB3
CRC
Byte
W
N
A6-A0
W0
CW23
CW22
CW21- CW19- CW15- CW11- CW7-
D7-D0
D7-D0
D7-D0
D7-D0
C7-C0
CW20
CW16
CW12
CW8
CW0
0x80
0x80
0x00
0x00
0x0
0x0
0x1
0x1
0x0
0x0
0x0
0xCD
0xCD
0xAB
0xAB
0x34
0x34
0x12
0x12
0x45
0x45
0x50
0x00
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Example for 64-bit Write Operation: Address - 0x00000080, Data Address 0x00000080 - Data 0x01234567,
Data Address 0x00000082 – Data 0x89ABCDEF, CRC Byte – 0x45 (Sample value; does not match with the
actual CRC calculation)
表8-7. Example for 64-bit Write Operation Packet
Start Byte
Control Word 0
Control Word 1
Control Word Data Bytes
2
CRC
Target I2C
OP_R/W CRC_EN DLEN MEM_SEC MEM_PAGE MEM_ADDR MEM_ADDR DB0 - DB7
CRC
Byte
ID
Write
A6-A0 W0
CW23
CW22
0x1
CW21- CW19-
CW20 CW16
CW15-
CW12
CW11-CW8
0x0
CW7-CW0
[D7-D0] x 8
C7-C0
0x00
0x00
0x0
0x0
0x2
0x0
0x0
0x80
0x80
0x67452301EFCDAB89
0x67452301EFCDAB89
0x45
0x45
0x60
0x00
Example for 32-bit Read Operation: Address – 0x00000080, Data – 0x1234ABCD, CRC Byte – 0x56
(Sample value; does not match with the actual CRC calculation)
表8-8. Example for 32-bit Read Operation Packet
Start Byte
Control Word 0
Control Word 1 Control Start Byte
Word 2
Byte 0 Byte 1 Byte 2 Byte 3 Byte 4
Target I2C
R/W
CRC_ DLEN MEM_ MEM_ MEM_ MEM_ Target I2C
EN SEC PAGE ADDR ADDR ID Read
DB0
DB1
DB2
DB3
CRC
Byte
ID
Write
A6-A0 W0
CW23 CW22 CW21- CW19- CW15- CW11- CW7- A6-A0 W0
D7-D0 D7-D0 D7-D0 D7-D0 C7-C0
CW20 CW16 CW12 CW8
CW0
0x80
0x80
0x00
0x00
0x0
0x1
0x1
0x1
0x0
0x0
0x0
0x00
0x01
0x1
0xCD 0xAB
0xCD 0xAB
0x34
0x34
0x12
0x12
0x56
0x56
0xD0
0x00
8.6.2.5 Internal Buffers
MCT8317A uses buffers internally to store the data received on I2C. Highest priority is given to collecting data on
the I2C Bus. There are 2 buffers (ping-pong) for I2C Rx Data and 2 buffers (ping-pong) for I2C Tx Data.
A write request from external MCU is stored in Rx Buffer 1 and then the parsing block is triggered to work on this
data in Rx Buffer 1. While MCT8317A is processing a write packet from Rx Buffer 1, if there is another new read/
write request, the entire data from the I2C bus is stored in Rx Buffer 2 and it will be processed after the current
request.
MCT8317A can accommodate a maximum of two consecutive read/write requests. If MCT8317A is busy due to
high priority interrupts, the data sent will be stored in internal buffers (Rx Buffer 1 and Rx Buffer 2). At this point,
if there is a third read/write request, the Target ID will be NACK’d as the buffers are already full.
During read operations, the read request is processed and the read data from the register is stored in the Tx
Buffer along with the CRC byte, if enabled. Now if the external MCU initiates an I2C Read (Target ID + R bit), the
data from this Tx Buffer is sent over I2C. Since there are two Tx Buffers, register data from 2 MCT8317A reads
can be buffered. Given this scenario, if there is a third read request, the control word will be stored in the Rx
Buffer 1, but it will not be processed by MCT8317A as the Tx Buffers are full.
Once a data is read from Tx Buffer, the data is no longer stored in the Tx buffer. The buffer is cleared and it
becomes available for the next data to be stored. If the read transaction was interrupted in between and if the
MCU had not read all the bytes, external MCU can initiate another I2C read (only I2C read, without any control
word information) to read all the data bytes from first.
8.6.2.6 CRC Byte Calculation
An 8-bit CCIT polynomial (x8 + x2+ x + 1) is used for CRC computation.
CRC Calculation in Write Operation: When the external MCU writes to MCT8317A, if the CRC is enabled, the
external MCU has to compute an 8-bit CRC byte and add the CRC byte at the end of the data. MCT8317A will
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compute CRC using the same polynomial internally and if there is a mismatch, the write request is discarded.
Input data for CRC calculation by external MCU for write operation are listed below:
1. Target ID + write bit.
2. Control word –3 bytes
3. Data bytes –2/4/8 bytes
CRC Calculation in Read Operation: When the external MCU reads from MCT8317A, if the CRC is enabled,
MCT8317A sends the CRC byte at the end of the data. The CRC computation in read operation involves the
start byte, control words sent by external MCU along with data bytes sent by MCT8317A. Input data for CRC
calculation by external MCU to verify the data sent by MCT8317A are listed below :
1. Target ID + write bit
2. Control word –3 bytes
3. Target ID + read bit
4. Data bytes –2/4/8 bytes
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8.7 EEPROM (Non-Volatile) Register Map
8.7.1 Algorithm_Configuration Registers
表 8-9 lists the memory-mapped registers for the Algorithm_Configuration registers. All register offset addresses
not listed in 表8-9 should be considered as reserved locations and the register contents should not be modified.
表8-9. ALGORITHM_CONFIGURATION Registers
Offset Acronym
ISD_CONFIG
Register Name
Section
80h
82h
84h
86h
88h
8Ah
8Ch
8Eh
90h
96h
98h
9Ah
9Ch
9Eh
A0h
A2h
A4h
ISD configuration
ISD_CONFIG Register (Offset = 80h) [Reset
= 00000000h]
MOTOR_STARTUP1
MOTOR_STARTUP2
CLOSED_LOOP1
CLOSED_LOOP2
CLOSED_LOOP3
CLOSED_LOOP4
CONST_SPEED
Motor start-up configuration 1
Motor start-up configuration 2
Closed loop configuration 1
Closed loop configuration 2
Closed loop configuration 3
Closed loop configuration 4
Constant speed configuration
Constant power configuration
150° Two-ph profile
MOTOR_STARTUP1 Register (Offset = 82h)
[Reset = 00000000h]
MOTOR_STARTUP2 Register (Offset = 84h)
[Reset = 00000000h]
CLOSED_LOOP1 Register (Offset = 86h)
[Reset = 00000000h]
CLOSED_LOOP2 Register (Offset = 88h)
[Reset = 00000000h]
CLOSED_LOOP3 Register (Offset = 8Ah)
[Reset = 000000A0h]
CLOSED_LOOP4 Register (Offset = 8Ch)
[Reset = 00000000h]
CONST_SPEED Register (Offset = 8Eh)
[Reset = 00000000h]
CONST_PWR
CONST_PWR Register (Offset = 90h) [Reset
= 00000000h]
150_DEG_TWO_PH_PROFILE
150_DEG_TWO_PH_PROFILE Register
(Offset = 96h) [Reset = 00000000h]
150_DEG_THREE_PH_PROFIL 150° Three-ph profile
E
150_DEG_THREE_PH_PROFILE Register
(Offset = 98h) [Reset = 00000000h]
REF_PROFILES1
REF_PROFILES2
REF_PROFILES3
REF_PROFILES4
REF_PROFILES5
REF_PROFILES6
Speed Profile Configuration1
REF_PROFILES1 Register (Offset = 9Ah)
[Reset = X]
Speed Profile Configuration2
Speed Profile Configuration3
Speed Profile Configuration4
Speed Profile Configuration5
Speed Profile Configuration6
REF_PROFILES2 Register (Offset = 9Ch)
[Reset = X]
REF_PROFILES3 Register (Offset = 9Eh)
[Reset = X]
REF_PROFILES4 Register (Offset = A0h)
[Reset = X]
REF_PROFILES5 Register (Offset = A2h)
[Reset = X]
REF_PROFILES6 Register (Offset = A4h)
[Reset = X]
Complex bit access types are encoded to fit into small table cells. 表 8-10 shows the codes that are used for
access types in this section.
表8-10. Algorithm_Configuration Access Type
Codes
Access Type
Read Type
R
Code
R
Description
Read
Write Type
W
W
Write
Reset or Default Value
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表8-10. Algorithm_Configuration Access Type
Codes (continued)
Access Type
Code
Description
-n
Value after reset or the default
value
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8.7.1.1 ISD_CONFIG Register (Offset = 80h) [Reset = 00000000h]
ISD_CONFIG is shown in 图8-49 and described in 表8-11.
Return to the Summary Table.
Register to configure initial speed detect settings
图8-49. ISD_CONFIG Register
31
30
29
28
27
26
25
24
PARITY
ISD_EN
BRAKE_EN
HIZ_EN
RVS_DR_EN
RESYNC_EN STAT_BRK_EN STAT_DETECT
_THR
R/W-0h
23
R/W-0h
22
R/W-0h
R/W-0h
R/W-0h
19
R/W-0h
R/W-0h
17
R/W-0h
21
20
18
16
STAT_DETECT_THR
R/W-0h
BRK_MODE
R/W-0h
RESERVED
R/W-0h
RESERVED
R/W-0h
BRK_TIME
R/W-0h
15
14
13
12
11
10
9
8
BRK_TIME
HIZ_TIME
R/W-0h
STARTUP_BRK
_TIME
R/W-0h
6
R/W-0h
0
7
5
4
3
2
1
STARTUP_BRK_TIME
RESYNC_MIN_THRESHOLD
R/W-0h
MTR_STARTUP
IPD_RLS_MOD
E
R/W-0h
R/W-0h
R/W-0h
表8-11. ISD_CONFIG Register Field Descriptions
Bit
31
30
Field
Type
R/W
R/W
Reset
Description
PARITY
ISD_EN
0h
Parity bit
0h
ISD enable
0h = Disable
1h = Enable
29
28
BRAKE_EN
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
Brake enable
0h = Disable
1h = Enable
HIZ_EN
Hi-Z enable
0h = Disable
1h = Enable
27
RVS_DR_EN
RESYNC_EN
STAT_BRK_EN
STAT_DETECT_THR
Reverse drive enable
0h = Disable
1h = Enable
26
Resynchronization enable
0h = Disable
1h = Enable
25
Enable or disable brake during stationary
0h = Disable
1h = Enable
24-22
Stationary BEMF detect threshold
0h = 5 mV
1h = 10 mV
2h = 15 mV
3h = 20 mV
4h = 25 mV
5h = 30 mV
6h = 50 mV
7h = 100 mV
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表8-11. ISD_CONFIG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
21
BRK_MODE
R/W
0h
Brake mode
0h = All three low-side FETs turned ON
1h = All three high-side FETs turned ON
20
RESERVED
RESERVED
BRK_TIME
R/W
R/W
R/W
0h
0h
0h
Reserved
Reserved
19-17
16-13
Brake time
0h = 10 ms
1h = 50 ms
2h = 100 ms
3h = 200 ms
4h = 300 ms
5h = 400 ms
6h = 500 ms
7h = 750 ms
8h = 1 s
9h = 2 s
Ah = 3 s
Bh = 4 s
Ch = 5 s
Dh = 7.5 s
Eh = 10 s
Fh = 15 s
12-9
HIZ_TIME
R/W
0h
Hi-Z time
0h = 10 ms
1h = 50 ms
2h = 100 ms
3h = 200 ms
4h = 300 ms
5h = 400 ms
6h = 500 ms
7h = 750 ms
8h = 1 s
9h = 2 s
Ah = 3 s
Bh = 4 s
Ch = 5 s
Dh = 7.5 s
Eh = 10 s
Fh = 15 s
8-6
STARTUP_BRK_TIME
R/W
0h
Brake time when motor is stationary
0h = 1 ms
1h = 10 ms
2h = 25 ms
3h = 50 ms
4h = 100 ms
5h = 250 ms
6h = 500 ms
7h = 1000 ms
5-3
RESYNC_MIN_THRESH R/W
OLD
0h
Minimum phase BEMF below which the motor is coasted instead of
resync
0h = computed based on MIN_DUTY
1h = 300 mV
2h = 400 mV
3h = 500 mV
4h = 600 mV
5h = 800 mV
6h = 1000 mV
7h = 1250 mV
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表8-11. ISD_CONFIG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2-1
MTR_STARTUP
R/W
0h
Motor start-up method
0h = Align
1h = Double Align
2h = IPD
3h = Slow first cycle
0
IPD_RLS_MODE
R/W
0h
IPD release mode
0h = Brake
1h = Tristate
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8.7.1.2 MOTOR_STARTUP1 Register (Offset = 82h) [Reset = 00000000h]
MOTOR_STARTUP1 is shown in 图8-50 and described in 表8-12.
Return to the Summary Table.
Register to configure motor startup settings1
图8-50. MOTOR_STARTUP1 Register
31
30
22
29
28
27
19
11
3
26
18
25
24
16
8
PARITY
R/W-0h
ALIGN_RAMP_RATE
R/W-0h
ALIGN_TIME
R/W-0h
23
21
13
5
20
17
ALIGN_TIME
R/W-0h
ALIGN_CURR_THR
R/W-0h
ALIGN_DUTY
R/W-0h
15
14
12
10
9
1
IPD_CLK_FREQ
R/W-0h
IPD_CURR_THR
R/W-0h
7
6
4
2
0
IPD_ADV_ANGLE
IPD_REPEAT
R/W-0h
SLOW_FIRST_CYC_FREQ
R/W-0h
R/W-0h
表8-12. MOTOR_STARTUP1 Register Field Descriptions
Bit
31
Field
Type
R/W
R/W
Reset
Description
PARITY
0h
Parity bit
30-27
ALIGN_RAMP_RATE
0h
Align voltage ramp rate
0h = 0.1 V/s
1h = 0.2 V/s
2h = 0.5 V/s
3h = 1 V/s
4h = 2.5 V/s
5h = 5 V/s
6h = 7.5 V/s
7h = 10 V/s
8h = 25 V/s
9h = 50 V/s
Ah = 75 V/s
Bh = 100 V/s
Ch = 250 V/s
Dh = 500 V/s
Eh = 750 V/s
Fh = 1000 V/s
26-23
ALIGN_TIME
R/W
0h
Align time
0h = 5 ms
1h = 10 ms
2h = 25 ms
3h = 50 ms
4h = 75 ms
5h = 100 ms
6h = 200 ms
7h = 400 ms
8h = 600 ms
9h = 800 ms
Ah = 1 s
Bh = 2 s
Ch = 4 s
Dh = 6 s
Eh = 8 s
Fh = 10 s
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表8-12. MOTOR_STARTUP1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
22-18
ALIGN_CURR_THR
R/W
0h
Align current threshold (Align current threshold (A) =
ALIGN_CURR_THR / CSA_GAIN)
0h = 0.0 V
1h = 0.1 V
2h = 0.2 V
3h = 0.3 V
4h = 0.4 V
5h = 0.5 V
6h = 0.6 V
7h = 0.7 V
8h = 0.8 V
9h = 0.9 V
Ah = 1.0 V
Bh = 1.1 V
Ch = 1.2 V
Dh = 1.3 V
Eh = 1.4 V
Fh = 1.5 V
10h = N/A
11h = N/A
12h = N/A
13h = N/A
14h = N/A
15h = N/A
16h = N/A
17h = N/A
18h = N/A
19h = N/A
1Ah = N/A
1Bh = N/A
1Ch = N/A
1Dh = N/A
1Eh = N/A
1Fh = N/A
17-16
15-13
ALIGN_DUTY
R/W
R/W
0h
0h
Duty cycle limit during align
0h = 10 %
1h = 25 %
2h = 50 %
3h = 100 %
IPD_CLK_FREQ
IPD clock frequency
0h = 50 Hz
1h = 100 Hz
2h = 250 Hz
3h = 500 Hz
4h = 1000 Hz
5h = 2000 Hz
6h = 5000 Hz
7h = 10000 Hz
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表8-12. MOTOR_STARTUP1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
12-8
IPD_CURR_THR
R/W
0h
IPD current threshold (IPD current threshold (A) = IPD_CURR_THR /
CSA_GAIN)
0h = 0.0 V
1h = 0.1 V
2h = 0.2 V
3h = 0.3 V
4h = 0.4 V
5h = 0.5 V
6h = 0.6 V
7h = 0.7 V
8h = 0.8 V
9h = 0.9 V
Ah = 1.0 V
Bh = 1.1 V
Ch = 1.2 V
Dh = 1.3 V
Eh = 1.4 V
Fh = 1.5 V
10h = N/A
11h = N/A
12h = N/A
13h = N/A
14h = N/A
15h = N/A
16h = N/A
17h = N/A
18h = N/A
19h = N/A
1Ah = N/A
1Bh = N/A
1Ch = N/A
1Dh = N/A
1Eh = N/A
1Fh = N/A
7-6
5-4
3-0
IPD_ADV_ANGLE
IPD_REPEAT
R/W
R/W
0h
0h
0h
IPD advance angle
0h = 0°
1h = 30°
2h = 60°
3h = 90°
Number of times IPD is executed
0h = one
1h = average of 2 times
2h = average of 3 times
3h = average of 4 times
SLOW_FIRST_CYC_FRE R/W
Q
Frequency of first cycle
0h = 0.05 Hz
1h = 0.1 Hz
2h = 0.25 Hz
3h = 0.5 Hz
4h = 1 Hz
5h = 2 Hz
6h = 3 Hz
7h = 5 Hz
8h = 10 Hz
9h = 15 Hz
Bh = 25 Hz
Ch = 50 Hz
Dh = 100 Hz
Eh = 150 Hz
Fh = 200 Hz
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8.7.1.3 MOTOR_STARTUP2 Register (Offset = 84h) [Reset = 00000000h]
MOTOR_STARTUP2 is shown in 图8-51 and described in 表8-13.
Return to the Summary Table.
Register to configure motor startup settings2
图8-51. MOTOR_STARTUP2 Register
31
30
22
29
28
27
19
11
3
26
18
10
25
17
9
24
16
PARITY
R/W-0h
OL_DUTY
R/W-0h
OL_ILIMIT
R/W-0h
23
21
13
5
20
OL_ILIMIT
R/W-0h
OL_ACC_A1
R/W-0h
OL_ACC_A2
R/W-0h
15
14
12
8
0
OL_ACC_A2
R/W-0h
OPN_CL_HANDOFF_THR
R/W-0h
7
6
4
2
1
AUTO_HANDO FIRST_CYCLE
MIN_DUTY
R/W-0h
OL_HANDOFF_CYCLES
FF
_FREQ_SEL
R/W-0h
R/W-0h
R/W-0h
表8-13. MOTOR_STARTUP2 Register Field Descriptions
Bit
31
Field
Type
R/W
R/W
Reset
Description
PARITY
0h
Parity bit
30-28
OL_DUTY
0h
Duty cycle limit during open loop
0h = 10%
1h = 15%
2h = 20%
3h = 25%
4h = 30%
5h = 40%
6h = 50%
7h = 100%
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表8-13. MOTOR_STARTUP2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
27-23
OL_ILIMIT
R/W
0h
Open loop current limit (OL current threshold (A) = OL_CURR_THR /
CSA_GAIN)
0h = 0.0 V
1h = 0.1 V
2h = 0.2 V
3h = 0.3 V
4h = 0.4 V
5h = 0.5 V
6h = 0.6 V
7h = 0.7 V
8h = 0.8 V
9h = 0.9 V
Ah = 1.0 V
Bh = 1.1 V
Ch = 1.2 V
Dh = 1.3 V
Eh = 1.4 V
Fh = 1.5 V
10h = N/A
11h = N/A
12h = N/A
13h = N/A
14h = N/A
15h = N/A
16h = N/A
17h = N/A
18h = N/A
19h = N/A
1Ah = N/A
1Bh = N/A
1Ch = N/A
1Dh = N/A
1Eh = N/A
1Fh = N/A
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表8-13. MOTOR_STARTUP2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
22-18
OL_ACC_A1
R/W
0h
Open loop acceleration A1
0h = 0.005 Hz/s
1h = 0.01 Hz/s
2h = 0.025 Hz/s
3h = 0.05 Hz/s
4h = 0.1 Hz/s
5h = 0.25 Hz/s
6h = 0.5 Hz/s
7h = 1 Hz/s
8h = 2.5 Hz/s
9h = 5 Hz/s
Ah = 7.5 Hz/s
Bh = 10 Hz/s
Ch = 12.5 Hz/s
Dh = 15 Hz/s
Eh = 20 Hz/s
Fh = 30 Hz/s
10h = 40 Hz/s
11h = 50 Hz/s
12h = 60 Hz/s
13h = 75 Hz/s
14h = 100 Hz/s
15h = 125 Hz/s
16h = 150 Hz/s
17h = 175 Hz/s
18h = 200 Hz/s
19h = 250 Hz/s
1Ah = 300 Hz/s
1Bh = 400 Hz/s
1Ch = 500 Hz/s
1Dh = 750 Hz/s
1Eh = 1000 Hz/s
1Fh = No Limit (32767) Hz/s
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表8-13. MOTOR_STARTUP2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
17-13
OL_ACC_A2
R/W
0h
Open loop acceleration A2
0h = 0.005 Hz/s2
1h = 0.01 Hz/s2
2h = 0.025 Hz/s2
3h = 0.05 Hz/s2
4h = 0.1 Hz/s2
5h = 0.25 Hz/s2
6h = 0.5 Hz/s2
7h = 1 Hz/s2
8h = 2.5 Hz/s2
9h = 5 Hz/s2
Ah = 7.5 Hz/s2
Bh = 10 Hz/s2
Ch = 12.5 Hz/s2
Dh = 15 Hz/s2
Eh = 20 Hz/s2
Fh = 30 Hz/s2
10h = 40 Hz/s2
11h = 50 Hz/s2
12h = 60 Hz/s2
13h = 75 Hz/s2
14h = 100 Hz/s2
15h = 125 Hz/s2
16h = 150 Hz/s2
17h = 175 Hz/s2
18h = 200 Hz/s2
19h = 250 Hz/s2
1Ah = 300 Hz/s2
1Bh = 400 Hz/s2
1Ch = 500 Hz/s2
1Dh = 750 Hz/s2
1Eh = 1000 Hz/s2
1Fh = No Limit (32767) Hz/s2
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表8-13. MOTOR_STARTUP2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
12-8
OPN_CL_HANDOFF_TH R/W
R
0h
Open to closed loop handoff threshold
0h = 1 Hz
1h = 4 Hz
2h = 8 Hz
3h = 12 Hz
4h = 16 Hz
5h = 20 Hz
6h = 24 Hz
7h = 28 Hz
8h = 32 Hz
9h = 36 Hz
Ah = 40 Hz
Bh = 45 Hz
Ch = 50 Hz
Dh = 55 Hz
Eh = 60 Hz
Fh = 65 Hz
10h = 70 Hz
11h = 75 Hz
12h = 80 Hz
13h = 85 Hz
14h = 90 Hz
15h = 100 Hz
16h = 150 Hz
17h = 200 Hz
18h = 250 Hz
19h = 300 Hz
1Ah = 350 Hz
1Bh = 400 Hz
1Ch = 450 Hz
1Dh = 500 Hz
1Eh = 550 Hz
1Fh = 600 Hz
7
6
AUTO_HANDOFF
R/W
0h
0h
0h
Auto handoff enable
0h = Disable Auto Handoff (and use OPN_CL_HANDOFF_THR)
1h = Enable Auto Handoff
FIRST_CYCLE_FREQ_S R/W
EL
First cycle frequency select
0h = Defined by SLOW_FIRST_CYC_FREQ
1h = 0 Hz
5-2
MIN_DUTY
R/W
Min operational duty cycle
0h = 0%
1h = 1.5 %
2h = 2 %
3h = 3 %
4h = 4 %
5h = 5 %
6h = 6 %
7h = 7 %
8h = 8 %
9h = 9 %
Ah = 10 %
Bh = 12 %
Ch = 15 %
Dh = 17.5 %
Eh = 20 %
Fh = 25 %
1-0
OL_HANDOFF_CYCLES R/W
0h
Open loop handoff cycles
0h = 3
1h = 6
2h = 12
3h = 24
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8.7.1.4 CLOSED_LOOP1 Register (Offset = 86h) [Reset = 00000000h]
CLOSED_LOOP1 is shown in 图8-52 and described in 表8-14.
Return to the Summary Table.
Register to configure close loop settings1
图8-52. CLOSED_LOOP1 Register
31
30
29
28
27
19
26
25
24
16
PARITY
R/W-0h
COMM_CONTROL
R/W-0h
CL_ACC
R/W-0h
23
22
21
13
5
20
18
17
CL_DEC_CON
FIG
CL_DEC
PWM_FREQ_OUT
R/W-0h
15
R/W-0h
12
R/W-0h
14
11
3
10
9
8
PWM_FREQ_OUT
PWM_MODUL
PWM_MODE LD_ANGLE_PO
LARITY
LD_ANGLE
R/W-0h
6
R/W-0h
R/W-0h
2
R/W-0h
1
R/W-0h
7
4
0
LD_ANGLE
R/W-0h
RESERVED
R/W-0h
表8-14. CLOSED_LOOP1 Register Field Descriptions
Bit
31
Field
Type
R/W
R/W
Reset
Description
PARITY
0h
Parity bit
30-29
COMM_CONTROL
0h
Trapezoidal commutation mode
0h = 120° Commutation
1h = Variable commutation between 120° and 150°
2h = N/A
3h = N/A
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表8-14. CLOSED_LOOP1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
28-24
CL_ACC
R/W
0h
Closed loop acceleration rate
0h = 0.005 V/s
1h = 0.01 V/s
2h = 0.025 V/s
3h = 0.05 V/s
4h = 0.1 V/s
5h = 0.25 V/s
6h = 0.5 V/s
7h = 1 V/s
8h = 2.5 V/s
9h = 5 V/s
Ah = 7.5 V/s
Bh = 10 V/s
Ch = 12.5 V/s
Dh = 15 V/s
Eh = 20 V/s
Fh = 30 V/s
10h = 40 V/s
11h = 50 V/s
12h = 60 V/s
13h = 75 V/s
14h = 100 V/s
15h = 125 V/s
16h = 150 V/s
17h = 175 V/s
18h = 200 V/s
19h = 250 V/s
1Ah = 300 V/s
1Bh = 400 V/s
1Ch = 500 V/s
1Dh = 750 V/s
1Eh = 1000 V/s
1Fh = 32767 V/s
23
CL_DEC_CONFIG
R/W
0h
Closed loop decel configuration
0h = Close loop deceleration defined by CL_DEC
1h = Close loop deceleration defined by CL_ACC
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表8-14. CLOSED_LOOP1 Register Field Descriptions (continued)
Bit
Field
CL_DEC
Type
Reset
Description
22-18
R/W
0h
Closed loop deceleration rate
0h = 0.005 V/s
1h = 0.01 V/s
2h = 0.025 V/s
3h = 0.05 V/s
4h = 0.1 V/s
5h = 0.25 V/s
6h = 0.5 V/s
7h = 1 V/s
8h = 2.5 V/s
9h = 5 V/s
Ah = 7.5 V/s
Bh = 10 V/s
Ch = 12.5 V/s
Dh = 15 V/s
Eh = 20 V/s
Fh = 30 V/s
10h = 40 V/s
11h = 50 V/s
12h = 60 V/s
13h = 75 V/s
14h = 100 V/s
15h = 125 V/s
16h = 150 V/s
17h = 175 V/s
18h = 200 V/s
19h = 250 V/s
1Ah = 300 V/s
1Bh = 400 V/s
1Ch = 500 V/s
1Dh = 750 V/s
1Eh = 1000 V/s
1Fh = 32767 V/s
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表8-14. CLOSED_LOOP1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
17-13
PWM_FREQ_OUT
R/W
0h
Output PWM switching frequency
0h = 5 kHz
1h = 6 kHz
2h = 7 kHz
3h = 8 kHz
4h = 9 kHz
5h = 10 kHz
6h = 11 kHz
7h = 12 kHz
8h = 13 kHz
9h = 14 kHz
Ah = 15 kHz
Bh = 16 kHz
Ch = 17 kHz
Dh = 18 kHz
Eh = 19 kHz
Fh = 20 kHz
10h = 25 kHz
11h = 30 kHz
12h = 35 kHz
13h = 40 kHz
14h = 45 kHz
15h = 50 kHz
16h = 55 kHz
17h = 60 kHz
18h = 65 kHz
19h = 70 kHz
1Ah = 75 kHz
1Bh = 80 kHz
1Ch = 85 kHz
1Dh = 90 kHz
1Eh = 95 kHz
1Fh = 100 kHz
12-11
PWM_MODUL
R/W
0h
PWM modulation.
0h = High-Side Modulation
1h = Low-Side Modulation
2h = Mixed Modulation
3h = N/A
10
9
PWM_MODE
R/W
R/W
0h
0h
PWM mode
0h = Single Ended Mode
1h = Complementary Mode
LD_ANGLE_POLARITY
Polarity of applied lead angle
0h = Negative
1h = Positive
8-1
0
LD_ANGLE
RESERVED
R/W
R/W
0h
0h
Lead Angle {Lead Angle (deg) = LD_ANGLE * 0.12}
Reserved
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8.7.1.5 CLOSED_LOOP2 Register (Offset = 88h) [Reset = 00000000h]
CLOSED_LOOP2 is shown in 图8-53 and described in 表8-15.
Return to the Summary Table.
Register to configure close loop settings2
图8-53. CLOSED_LOOP2 Register
31
30
29
28
20
27
26
25
24
PARITY
FG_SEL
R/W-0h
FG_DIV_FACTOR
DEAD_TIME_C
OMP
R/W-0h
23
R/W-0h
R/W-0h
16
22
21
13
5
19
18
10
2
17
FG_BEMF_THR
R/W-0h
MTR_STOP
R/W-0h
MTR_STOP_BRK_TIME
R/W-0h
15
14
12
11
9
8
MTR_STOP_BRK_TIME
R/W-0h
ACT_SPIN_BRK_THR
R/W-0h
BRAKE_DUTY_THRESHOLD
R/W-0h
7
6
4
3
1
0
AVS_EN
CBC_ILIMIT
OL_ILIMIT_CO INTEG_ZC_ME
NFIG
THOD
R/W-0h
R/W-0h
R/W-0h
R/W-0h
表8-15. CLOSED_LOOP2 Register Field Descriptions
Bit
31
Field
Type
R/W
R/W
Reset
Description
PARITY
FG_SEL
0h
Parity bit
30-29
0h
FG mode select
0h = Output FG in open loop and closed loop
1h = Output FG in only closed loop
2h = Output FG in open loop for the first try.
3h = N/A
28-25
FG_DIV_FACTOR
R/W
0h
FG division factor
0h = Divide by 3 (2-pole motor mechanical speed/3)
1h = Divide by 1 (2-pole motor mechanical speed)
2h = Divide by 2 (4-pole motor mechanical speed)
3h = Divide by 3 (6-pole motor mechanical speed)
4h = Divide by 4 (8-pole motor mechanical speed)
5h = Divide by 5 (10-pole motor mechanical speed)
6h = Divide by 6 (12-pole motor mechanical speed)
7h = Divide by 7 (14-pole motor mechanical speed)
8h = Divide by 8 (16-pole motor mechanical speed)
9h = Divide by 9 (18-pole motor mechanical speed)
Ah = Divide by 10 (20-pole motor mechanical speed)
Bh = Divide by 11 (22-pole motor mechanical speed)
Ch = Divide by 12 (24-pole motor mechanical speed)
Dh = Divide by 13 (26-pole motor mechanical speed)
Eh = Divide by 14 (28-pole motor mechanical speed)
Fh = Divide by 15 (30-pole motor mechanical speed)
24
DEAD_TIME_COMP
R/W
0h
Dead Time Compensation
0h = Disable
1h = Enable
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表8-15. CLOSED_LOOP2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
23-21
FG_BEMF_THR
R/W
0h
FG output BEMF threshold
0h = +/- 1mV
1h = +/- 2mV
2h = +/- 5mV
3h = +/- 10mV
4h = +/- 20mV
5h = +/- 30mV
6h = N/A
7h = N/A
20-18
MTR_STOP
R/W
0h
Motor stop method
0h = Hi-z
1h = Recirculation
2h = Low-side braking
3h = High-side braking
4h = Active spin down
5h = N/A
6h = N/A
7h = N/A
17-14
MTR_STOP_BRK_TIME R/W
0h
Brake time during motor stop
0h = 1 ms
1h = 2 ms
2h = 5 ms
3h = 10 ms
4h = 15 ms
5h = 25 ms
6h = 50 ms
7h = 75 ms
8h = 100 ms
9h = 250 ms
Ah = 500 ms
Bh = 1000 ms
Ch = 2500 ms
Dh = 5000 ms
Eh = 10000 ms
Fh = 15000 ms
13-11
ACT_SPIN_BRK_THR
R/W
0h
Duty cycle threshold for motor stop using active spin down, low- and
high-side braking
0h = Immediate
1h = 50 %
2h = 25 %
3h = 15 %
4h = 10 %
5h = 7.5 %
6h = 5 %
7h = 2.5 %
10-8
BRAKE_DUTY_THRESH R/W
OLD
0h
Duty cycle threshold for BRAKE pin based low-side braking
0h = Immediate
1h = 50 %
2h = 25 %
3h = 15 %
4h = 10 %
5h = 7.5 %
6h = 5 %
7h = 2.5 %
7
AVS_EN
R/W
0h
AVS enable
0h = Disable
1h = Enable
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表8-15. CLOSED_LOOP2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
6-2
CBC_ILIMIT
R/W
0h
Cycle by Cycle (CBC) current limit (CBC current limit (A) =
CBC_ILIMIT / CSA_GAIN)
0h = 0.0 V
1h = 0.1 V
2h = 0.2 V
3h = 0.3 V
4h = 0.4 V
5h = 0.5 V
6h = 0.6 V
7h = 0.7 V
8h = 0.8 V
9h = 0.9 V
Ah = 1.0 V
Bh = 1.1 V
Ch = 1.2 V
Dh = 1.3 V
Eh = 1.4 V
Fh = 1.5 V
10h = N/A
11h = N/A
12h = N/A
13h = N/A
14h = N/A
15h = N/A
16h = N/A
17h = N/A
18h = N/A
19h = N/A
1Ah = N/A
1Bh = N/A
1Ch = N/A
1Dh = N/A
1Eh = N/A
1Fh = N/A
1
0
OL_ILIMIT_CONFIG
INTEG_ZC_METHOD
R/W
R/W
0h
0h
Open loop current limit configuration
0h = Open loop current limit defined by OL_ILIMIT
1h = Open loop current limit defined by ILIMIT
Commutation method select
0h = ZC based
1h = Integration based
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8.7.1.6 CLOSED_LOOP3 Register (Offset = 8Ah) [Reset = 000000A0h]
CLOSED_LOOP3 is shown in 图8-54 and described in 表8-16.
Return to the Summary Table.
Register to configure close loop settings3
图8-54. CLOSED_LOOP3 Register
31
30
29
28
27
26
25
24
PARITY
INTEG_CYCL_THR_LOW
R/W-0h
INTEG_CYCL_THR_HIGH
R/W-0h
INTEG_DUTY_THR_LOW
R/W-0h
INTEG_DUTY_
THR_HIGH
R/W-0h
23
R/W-0h
16
22
21
20
19
18
17
INTEG_DUTY_
THR_HIGH
BEMF_THRESHOLD2
BEMF_THRES
HOLD1
R/W-0h
15
R/W-0h
R/W-0h
8
14
6
13
12
4
11
3
10
2
9
BEMF_THRESHOLD1
R/W-0h
DYN_DGS_FILT_COUNT
R/W-0h
7
5
1
0
DYN_DGS_UPPER_LIM
DYN_DGS_LOWER_LIM
DEGAUSS_MAX_WIN
DYN_DEGAUS
S_EN
R/W-2h
R/W-2h
R/W-0h
R/W-0h
表8-16. CLOSED_LOOP3 Register Field Descriptions
Bit
31
Field
Type
Reset
Description
PARITY
R/W
0h
Parity bit
30-29
INTEG_CYCL_THR_LOW R/W
0h
Number of BEMF samples per 30° below which commutation method
switches from integration to ZC
0h = 3
1h = 4
2h = 6
3h = 8
28-27
26-25
24-23
INTEG_CYCL_THR_HIG R/W
H
0h
0h
0h
Number of BEMF samples per 30° above which commutation
method switches from ZC to integration
0h = 4
1h = 6
2h = 8
3h = 10
INTEG_DUTY_THR_LOW R/W
Duty cycle below which commutation method switches from
integration to ZC
0h = 12 %
1h = 15 %
2h = 18 %
3h = 20 %
INTEG_DUTY_THR_HIG R/W
H
Duty cycle above which commutation method switches from ZC to
integration
0h = 12 %
1h = 15 %
2h = 18 %
3h = 20 %
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表8-16. CLOSED_LOOP3 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
22-17
BEMF_THRESHOLD2
R/W
0h
BEMF threshold for integration based commutation during falling
floating phase voltage
0h = 0
1h = 25
2h = 50
3h = 75
4h = 100
5h = 125
6h = 150
7h = 175
8h = 200
9h = 225
Ah = 250
Bh = 275
Ch = 300
Dh = 325
Eh = 350
Fh = 375
10h = 400
11h = 425
12h = 450
13h = 475
14h = 500
15h = 525
16h = 550
17h = 575
18h = 600
19h = 625
1Ah = 650
1Bh = 675
1Ch = 700
1Dh = 725
1Eh = 750
1Fh = 775
20h = 800
21h = 850
22h = 900
23h = 950
24h = 1000
25h = 1050
26h = 1100
27h = 1150
28h = 1200
29h = 1250
2Ah = 1300
2Bh = 1350
2Ch = 1400
2Dh = 1450
2Eh = 1500
2Fh = 1550
30h = 1600
31h = 1700
32h = 1800
33h = 1900
34h = 2000
35h = 2100
36h = 2200
37h = 2300
38h = 2400
39h = 2600
3Ah = 2800
3Bh = 3000
3Ch = 3200
3Dh = 3400
3Eh = 3600
3Fh = 3800
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表8-16. CLOSED_LOOP3 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
16-11
BEMF_THRESHOLD1
R/W
0h
BEMF threshold for integration based commutation during rising
floating phase voltage
0h = 0
1h = 25
2h = 50
3h = 75
4h = 100
5h = 125
6h = 150
7h = 175
8h = 200
9h = 225
Ah = 250
Bh = 275
Ch = 300
Dh = 325
Eh = 350
Fh = 375
10h = 400
11h = 425
12h = 450
13h = 475
14h = 500
15h = 525
16h = 550
17h = 575
18h = 600
19h = 625
1Ah = 650
1Bh = 675
1Ch = 700
1Dh = 725
1Eh = 750
1Fh = 775
20h = 800
21h = 850
22h = 900
23h = 950
24h = 1000
25h = 1050
26h = 1100
27h = 1150
28h = 1200
29h = 1250
2Ah = 1300
2Bh = 1350
2Ch = 1400
2Dh = 1450
2Eh = 1500
2Fh = 1550
30h = 1600
31h = 1700
32h = 1800
33h = 1900
34h = 2000
35h = 2100
36h = 2200
37h = 2300
38h = 2400
39h = 2600
3Ah = 2800
3Bh = 3000
3Ch = 3200
3Dh = 3400
3Eh = 3600
3Fh = 3800
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表8-16. CLOSED_LOOP3 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
10-8
DYN_DGS_FILT_COUNT R/W
0h
Number of samples needed for dynamic degauss check
0h = 3
1h = 6
2h = 9
3h = 12
4h = 15
5h = 20
6h = 30
7h = 40
7-6
5-4
3-1
DYN_DGS_UPPER_LIM R/W
DYN_DGS_LOWER_LIM R/W
2h
2h
0h
Dynamic degauss voltage upper bound
0h = (VM - 0.09) V
1h = (VM - 0.12) V
2h = (VM - 0.15) V
3h = (VM - 0.18) V
Dynamic degauss voltage lower bound
0h = 0.03 V
1h = 0.06 V
2h = 0.09 V
3h = 0.12 V
DEGAUSS_MAX_WIN
R/W
Maximum degauss window
0h = 22.5°
1h = 10°
2h = 15°
3h = 18°
4h = 30°
5h = 37.5°
6h = 45°
7h = 60°
0
DYN_DEGAUSS_EN
R/W
0h
Dynamic degauss detection
0h = Disable
1h = Enable
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8.7.1.7 CLOSED_LOOP4 Register (Offset = 8Ch) [Reset = 00000000h]
CLOSED_LOOP4 is shown in 图8-55 and described in 表8-17.
Return to the Summary Table.
Register to configure close loop settings4
图8-55. CLOSED_LOOP4 Register
31
30
29
28
27
26
25
17
24
PARITY
DYN_VOLT_SC HIGH_RES_SA AVS_LIMIT_HY
AVS_NEG_CURR_LIMIT
RESERVED
ALING_EN
R/W-0h
MP
ST
R/W-0h
23
R/W-0h
R/W-0h
R/W-0h
18
R/W-0h
16
22
21
20
19
HYST_CURR_LIM_BAND
FAST_DEC_DEG_TIME
WCOMP_BLAN
K_EN
FAST_DEC_DUTY_WIN
R/W-0h
R/W-0h
R/W-0h
11
R/W-0h
9
15
7
14
13
5
12
4
10
8
FAST_DEC_DUTY_THR
DYN_BRK_CURR_LOW_LIM
DYNAMIC_BRK
_CURR
R/W-0h
6
R/W-0h
R/W-0h
0
3
2
1
FAST_DECEL_
EN
FAST_DECEL_CURR_LIM
FAST_BRK_DELTA
R/W-0h
R/W-0h
R/W-0h
表8-17. CLOSED_LOOP4 Register Field Descriptions
Bit
31
30
Field
PARITY
Type
Reset
Description
R/W
0h
Parity bit
DYN_VOLT_SCALING_E R/W
N
0h
Dynamic Voltage Scaling Enable
0h = Disable
1h = Enable
29
28
HIGH_RES_SAMP
AVS_LIMIT_HYST
R/W
R/W
0h
0h
Sampling rate
0h = sampRate / 4
1h = sampRate / 8
AVS current hysteresis (AVS positive current limit (A) =
((AVS_LIMIT_HYST + AVS_NEG_CURR_LIMIT) * 3 /4095) /
CSA_GAIN)
0h = 20
1h = 10
30-27
27-25
RESERVED
R/W
0h
0h
Reserved
AVS_NEG_CURR_LIMIT R/W
AVS negative current limit (AVS negative current limit (A) =
(AVS_NEG_CURRENT_LIMIT * 3 /4095) / CSA_GAIN)
0h = 0
1h = -60
2h = -40
3h = -30
4h = -20
5h = -10
6h = 15
7h = 30
24
RESERVED
R/W
0h
0h
Reserved
23-22
HYST_CURR_LIM_BAND R/W
Hysteresis Band during Fast Decel( if AVS Disabled)
0h = 0
1h = 100mV
2h = 200mV
3h = 400mV
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表8-17. CLOSED_LOOP4 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
21-20
FAST_DEC_DEG_TIME
R/W
0h
Fast Decel Deglitch Time
0h = 2uS
1h = 4uS
2h = 8uS
3h = 14uS
19
WCOMP_BLANK_EN
R/W
R/W
0h
0h
Enable WCOMP blanking during fast deceleration
0h = Disable
1h = Enable
18-16
FAST_DEC_DUTY_WIN
Fast deceleration duty window
0h = 0 %
1h = 2.5 %
2h = 5 %
3h = 7.5 %
4h = 10 %
5h = 15 %
6h = 20 %
7h = 25 %
15-13
FAST_DEC_DUTY_THR R/W
0h
Fast deceleration duty threshold
0h = 100 %
1h = 95 %
2h = 90 %
3h = 85 %
4h = 80 %
5h = 75 %
6h = 70%
7h = 65 %
12-9
DYN_BRK_CURR_LOW_ R/W
LIM
0h
Fast deceleration dynamic current limit lower threshold (Deceleration
current lower threshold (A) = DYN_BRK_CURR_LOW_LIM /
CSA_GAIN)
0h = N/A
1h = 0.1V
2h = 0.2 V
3h = 0.3 V
4h = 0.4 V
5h = 0.5 V
6h = 0.6 V
7h = 0.7 V
8h = 0.8 V
9h = 0.9 V
Ah = 1 V
Bh = 1.1 V
Ch = 1.2 V
Dh = 1.3 V
Eh = 1.4 V
Fh = 1.5 V
8
7
DYNAMIC_BRK_CURR
FAST_DECEL_EN
R/W
R/W
0h
0h
Enable dynamic decrease in current limit during fast deceleration
0h = Disable
1h = Enable
Fast deceleration enable
0h = Disable
1h = Enable
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表8-17. CLOSED_LOOP4 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
6-3
FAST_DECEL_CURR_LI R/W
M
0h
Deceleration current threshold (Fast Deceleration current limit upper
threshold (A) = FAST_DECEL_CURR_LIM / CSA_GAIN)
0h = N/A
1h = 0.1V
2h = 0.2 V
3h = 0.3 V
4h = 0.4 V
5h = 0.5 V
6h = 0.6 V
7h = 0.7 V
8h = 0.8 V
9h = 0.9 V
Ah = 1 V
Bh = 1.1 V
Ch = 1.2 V
Dh = 1.3 V
Eh = 1.4 V
Fh = 1.5 V
2-0
FAST_BRK_DELTA
R/W
0h
Fast deceleration exit speed delta
0h = 0.5 %
1h = 1 %
2h = 1.5 %
3h = 2 %
4h = 2.5 %
5h = 3 %
6h = 4 %
7h = 5 %
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8.7.1.8 CONST_SPEED Register (Offset = 8Eh) [Reset = 00000000h]
CONST_SPEED is shown in 图8-56 and described in 表8-18.
Return to the Summary Table.
Register to configure Constant speed mode settings
图8-56. CONST_SPEED Register
31
30
29
21
28
20
12
27
SPD_POWER_KP
R/W-0h
26
25
24
16
8
PARITY
R/W-0h
RESERVED
R/W-0h
23
15
7
22
19
18
SPD_POWER_KI
R/W-0h
17
SPD_POWER_KP
R/W-0h
14
13
11
10
9
SPD_POWER_KI
R/W-0h
6
5
4
3
2
1
0
SPD_POWER_V_MAX
R/W-0h
SPD_POWER_V_MIN
R/W-0h
CLOSED_LOOP_MODE
R/W-0h
表8-18. CONST_SPEED Register Field Descriptions
Bit
31
Field
Type
R/W
R/W
R/W
R/W
R/W
Reset
Description
PARITY
0h
Parity bit
30
RESERVED
0h
Reserved
29-20
19-8
7-5
SPD_POWER_KP
SPD_POWER_KI
SPD_POWER_V_MAX
0h
Speed/ Power loop Kp (Kp = SPD_LOOP_KP / 10000)
Speed/ Power loop Ki (Ki = SPD_LOOP_KI / 1000000)
0h
0h
Upper saturation limit for speed/ power loop
0h = 100 %
1h = 95 %
2h = 90 %
3h = 85 %
4h = 80 %
5h = 75 %
6h = 70%
7h = 65 %
4-2
SPD_POWER_V_MIN
R/W
0h
Lower saturation limit for speed/power loop
0h = 0 %
1h = 2.5 %
2h = 5 %
3h = 7.5 %
4h = 10 %
5h = 15 %
6h = 20 %
7h = 25 %
1-0
CLOSED_LOOP_MODE R/W
0h
Closed loop mode
0h = Disabled
1h = Speed Loop
2h = Power Loop
3h = Reserved
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8.7.1.9 CONST_PWR Register (Offset = 90h) [Reset = 00000000h]
CONST_PWR is shown in 图8-57 and described in 表8-19.
Return to the Summary Table.
Register to configure Constant power mode settings
图8-57. CONST_PWR Register
31
30
22
14
6
29
21
13
5
28
20
12
4
27
26
18
10
2
25
17
9
24
16
8
PARITY
R/W-0h
MAX_SPEED
R/W-0h
23
19
MAX_SPEED
R/W-0h
15
11
MAX_SPEED
R/W-0h
MAX_POWER
R/W-0h
7
3
1
0
MAX_POWER
R/W-0h
CONST_POWER_LIMIT_HYST
R/W-0h
CONST_POWER_MODE
R/W-0h
表8-19. CONST_PWR Register Field Descriptions
Bit
31
Field
PARITY
Type
R/W
R/W
R/W
Reset
Description
0h
Parity bit
30-15
14-4
3-2
MAX_SPEED
MAX_POWER
0h
Maximum Speed (Maximum Speed (Hz) = MAX_SPEED / 16)
Maximum power (Maximum power (W) = MAX_POWER / 4)
0h
CONST_POWER_LIMIT_ R/W
HYST
0h
Hysteresis for input power regulation
0h = 5 %
1h = 7.5 %
2h = 10 %
3h = 12.5 %
1-0
CONST_POWER_MODE R/W
0h
Input power regulation mode
0h = Voltage Control mode
1h = Closed Loop Power Control
2h = Power Limit Control
3h = Reserved
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8.7.1.10 150_DEG_TWO_PH_PROFILE Register (Offset = 96h) [Reset = 00000000h]
150_DEG_TWO_PH_PROFILE is shown in 图8-58 and described in 表8-20.
Return to the Summary Table.
Register to configure 150 degree modulation TWO phase duty
图8-58. 150_DEG_TWO_PH_PROFILE Register
31
30
29
28
27
19
26
25
24
PARITY
TWOPH_STEP0
TWOPH_STEP1
TWOPH_STEP
2
R/W-0h
23
R/W-0h
21
R/W-0h
18
R/W-0h
16
22
20
17
TWOPH_STEP2
R/W-0h
TWOPH_STEP3
R/W-0h
TWOPH_STEP4
R/W-0h
15
14
13
5
12
11
10
2
9
8
TWOPH_STEP5
R/W-0h
TWOPH_STEP6
R/W-0h
TWOPH_STEP7
R/W-0h
7
6
4
3
1
0
TWOPH_STEP
7
RESERVED
R/W-0h
R/W-0h
表8-20. 150_DEG_TWO_PH_PROFILE Register Field Descriptions
Bit
31
Field
Type
R/W
R/W
Reset
Description
PARITY
0h
Parity bit
30-28
TWOPH_STEP0
0h
150° modulation , Two ph - step duty - 0
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
27-25
TWOPH_STEP1
R/W
0h
150° modulation , Two ph - step duty - 1
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
24-22
TWOPH_STEP2
R/W
0h
150° modulation, Two ph - step duty - 2
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
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表8-20. 150_DEG_TWO_PH_PROFILE Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
21-19
TWOPH_STEP3
R/W
0h
150° modulation, Two ph - step duty - 3
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
18-16
15-13
12-10
9-7
TWOPH_STEP4
TWOPH_STEP5
TWOPH_STEP6
TWOPH_STEP7
RESERVED
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
150° modulation, Two ph - step duty - 4
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
150° modulation, Two ph - step duty - 5
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
150° modulation, Two ph - step duty - 6
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
150° modulation, Two ph - step duty - 7
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
6-0
Reserved
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8.7.1.11 150_DEG_THREE_PH_PROFILE Register (Offset = 98h) [Reset = 00000000h]
150_DEG_THREE_PH_PROFILE is shown in 图8-59 and described in 表8-21.
Return to the Summary Table.
Register to configure 150 degree modulation Three phase duty
图8-59. 150_DEG_THREE_PH_PROFILE Register
31
30
29
28
27
26
25
24
PARITY
THREEPH_STEP0
THREEPH_STEP1
THREEPH_ST
EP2
R/W-0h
23
R/W-0h
21
R/W-0h
18
R/W-0h
16
22
20
19
11
17
THREEPH_STEP2
R/W-0h
THREEPH_STEP3
R/W-0h
THREEPH_STEP4
R/W-0h
15
14
13
5
12
10
9
8
THREEPH_STEP5
R/W-0h
THREEPH_STEP6
R/W-0h
THREEPH_STEP7
R/W-0h
7
6
4
3
2
1
0
THREEPH_ST
EP7
LEAD_ANGLE_150DEG_ADV
RESERVED
R/W-0h
R/W-0h
R/W-0h
表8-21. 150_DEG_THREE_PH_PROFILE Register Field Descriptions
Bit
31
Field
Type
R/W
R/W
Reset
Description
PARITY
0h
Parity bit
30-28
THREEPH_STEP0
0h
150° modulation, Three ph - step duty - 0
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
27-25
THREEPH_STEP1
R/W
0h
150° modulation, Three ph - step duty - 1
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
24-22
THREEPH_STEP2
R/W
0h
150° modulation, Three ph - step duty - 2
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
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表8-21. 150_DEG_THREE_PH_PROFILE Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
21-19
THREEPH_STEP3
R/W
0h
150° modulation, Three ph - step duty - 3
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
18-16
15-13
12-10
9-7
THREEPH_STEP4
THREEPH_STEP5
THREEPH_STEP6
THREEPH_STEP7
R/W
R/W
R/W
R/W
0h
0h
0h
0h
150° modulation, Three ph - step duty - 4
0h = 0.0 %
1h = 0.5 %
2h = 0.75 %
3h = 0.8375 %
4h = 0.875 %
5h = 0.9375 %
6h = 0.975 %
7h = 0.99 %
150° modulation, Three ph - step duty - 5
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
150° modulation, Three ph - step duty - 6
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
150° modulation, Three ph - step duty - 7
0h = 0%
1h = 50 %
2h = 75 %
3h = 83.75 %
4h = 87.5 %
5h = 93.75 %
6h = 97.5 %
7h = 99 %
6-5
4-0
LEAD_ANGLE_150DEG_ R/W
ADV
0h
0h
Angle advance for 150° modulation
0h = 0°
1h = 5°
2h = 10°
3h = 15°
RESERVED
R/W
Reserved
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8.7.1.12 REF_PROFILES1 Register (Offset = 9Ah) [Reset = X]
REF_PROFILES1 is shown in 图8-60 and described in 表8-22.
Return to the Summary Table.
Register to configure speed profile1
图8-60. REF_PROFILES1 Register
31
30
29
28
20
12
4
27
19
11
3
26
25
24
16
8
PARITY
R/W-0h
REF_PROFILE_CONFIG
R/W-0h
DUTY_ON1
R/W-X
23
15
7
22
21
13
5
18
17
9
DUTY_ON1
R/W-X
DUTY_OFF1
R/W-X
14
10
DUTY_OFF1
R/W-X
DUTY_CLAMP1
R/W-X
6
2
1
0
DUTY_CLAMP1
R/W-X
DUTY_A
R/W-X
表8-22. REF_PROFILES1 Register Field Descriptions
Bit
31
Field
PARITY
Type
Reset
Description
R/W
0h
Parity bit
30-29
REF_PROFILE_CONFIG R/W
0h
Reference Profile Configuration
0h = Duty Control Mode
1h = Linear Mode
2h = Staircase Mode
3h = Forward Reverse Mode
28-21
20-13
12-5
4-0
DUTY_ON1
DUTY_OFF1
DUTY_CLAMP1
DUTY_A
R/W
R/W
R/W
R/W
X
X
X
X
Duty_ON1 Configuration Turn On Duty Cycle (%) =
{(DUTY_ON1/255)*100}
Duty_OFF1 Configuration Turn Off Duty Cycle (%) =
{(DUTY_OFF1/255)*100}
Duty_CLAMP1 Configuration Duty Cycle for clamping speed (%) =
{(DUTY_CLAMP1/255)*100}
5 MSB bits for Duty Cycle A Duty Cycle A (%) = {(DUTY_A/
255)*100}
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8.7.1.13 REF_PROFILES2 Register (Offset = 9Ch) [Reset = X]
REF_PROFILES2 is shown in 图8-61 and described in 表8-23.
Return to the Summary Table.
Register to configure speed profile2
图8-61. REF_PROFILES2 Register
31
30
22
14
6
29
28
20
12
4
27
19
11
3
26
18
10
2
25
17
9
24
16
8
PARITY
R/W-0h
DUTY_A
R/W-X
DUTY_B
R/W-X
23
15
7
21
13
5
DUTY_B
R/W-X
DUTY_C
R/W-X
DUTY_C
R/W-X
DUTY_D
R/W-X
1
0
DUTY_D
R/W-X
DUTY_E
R/W-0h
表8-23. REF_PROFILES2 Register Field Descriptions
Bit
31
Field
Type
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0h
X
Description
PARITY
DUTY_A
DUTY_B
DUTY_C
DUTY_D
DUTY_E
Parity bit
30-28
27-20
19-12
11-4
3-0
3 LSB bits for Duty Cycle A Duty Cycle A (%) = {(DUTY_A/255)*100}
Duty_B Configuration Duty Cycle B (%) = {(DUTY_B/255)*100}
Duty_C Configuration Duty Cycle C (%) = {(DUTY_C/255)*100}
Duty_D Configuration Duty Cycle D (%) = {(DUTY_D/255)*100}
X
X
X
0h
4 MSB bits for Duty Cycle E Duty Cycle E (%) = {(DUTY_E/
255)*100}
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8.7.1.14 REF_PROFILES3 Register (Offset = 9Eh) [Reset = X]
REF_PROFILES3 is shown in 图8-62 and described in 表8-24.
Return to the Summary Table.
Register to configure speed profile3
图8-62. REF_PROFILES3 Register
31
30
22
14
6
29
21
28
27
26
18
10
2
25
24
16
8
PARITY
R/W-0h
DUTY_E
R/W-X
DUTY_ON2
R/W-X
23
15
7
20
12
4
19
11
3
17
DUTY_ON2
R/W-X
DUTY_OFF2
R/W-X
13
9
DUTY_OFF2
R/W-X
DUTY_CLAMP2
R/W-X
5
1
0
DUTY_CLAMP2
R/W-X
STEP_HYST_BAND
0h
RESERVED
R/W-0h
表8-24. REF_PROFILES3 Register Field Descriptions
Bit
31
Field
Type
R/W
R/W
R/W
Reset
Description
PARITY
DUTY_E
0h
X
Parity bit
30-27
26-19
4 LSB bits for Duty Cycle E Duty Cycle E (%) = {(DUTY_E/255)*100}
DUTY_ON2
X
Duty_ON2 Configuration Turn On Duty Cycle (%) =
{(DUTY_ON2/255)*100}
18-11
10-3
2-1
DUTY_OFF2
R/W
R/W
X
Duty_OFF2 Configuration Turn Off Duty Cycle (%) =
{(DUTY_OFF2/255)*100}
DUTY_CLAMP2
STEP_HYST_BAND
X
Duty_CLAMP2 Configuration Duty Cycle for clamping speed (%) =
{(DUTY_CLAMP1/255)*100}
0h
Hysteresis band used for Step changes
0h = 0%
1h = 2%
2h = 4%
3h = 6%
0
RESERVED
R/W
0h
Reserved
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8.7.1.15 REF_PROFILES4 Register (Offset = A0h) [Reset = X]
REF_PROFILES4 is shown in 图8-63 and described in 表8-25.
Return to the Summary Table.
Register to configure speed profile4
图8-63. REF_PROFILES4 Register
31
30
22
14
6
29
21
13
5
28
27
26
18
10
2
25
17
9
24
16
8
PARITY
R/W-0h
REF_OFF1
R/W-X
23
20
12
4
19
REF_OFF1
R/W-X
REF_CLAMP1
R/W-X
15
11
REF_CLAMP1
R/W-X
REF_A
R/W-X
7
3
1
0
REF_A
R/W-X
REF_B
R/W-X
表8-25. REF_PROFILES4 Register Field Descriptions
Bit
31
Field
PARITY
Type
R/W
R/W
Reset
Description
0h
Parity bit
30-23
REF_OFF1
X
Turn off Ref Configuration Turn off Reference % =
{(REF_OFF1/255)*100}
22-15
REF_CLAMP1
R/W
X
Ref Clamp 1 Configuration Clamp REF % =
{(REF_CLAMP1/255)*100}
14-7
6-0
REF_A
REF_B
R/W
R/W
X
X
Ref A configuration Ref A % = {(REF_A/255)*100}
7 MSB of REF_B configuration REF B% = {(REF_B/255)*100}
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8.7.1.16 REF_PROFILES5 Register (Offset = A2h) [Reset = X]
REF_PROFILES5 is shown in 图8-64 and described in 表8-26.
Return to the Summary Table.
Register to configure speed profile5
图8-64. REF_PROFILES5 Register
31
30
29
21
13
5
28
27
26
18
10
2
25
24
16
8
PARITY
R/W-0h
REF_B
R/W-X
REF_C
R/W-X
23
15
7
22
14
6
20
12
4
19
11
3
17
9
REF_C
R/W-X
REF_D
R/W-X
REF_D
R/W-X
REF_E
R/W-X
1
0
REF_E
R/W-X
RESERVED
R/W-0h
表8-26. REF_PROFILES5 Register Field Descriptions
Bit
31
Field
Type
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0h
X
Description
PARITY
REF_B
REF_C
REF_D
REF_E
Parity bit
30
1 LSB of REF_B configuration REF B% = {(REF_B/255)*100}
REF C configuration REF C % = {(REF_A/255)*100}
REF D configuration REF D % = {(REF_D/255)*100}
REF E Configuration REF E% = {(REF_E/255)*100}
Reserved
29-22
21-14
13-6
5-0
X
X
X
RESERVED
0h
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8.7.1.17 REF_PROFILES6 Register (Offset = A4h) [Reset = X]
REF_PROFILES6 is shown in 图8-65 and described in 表8-27.
Return to the Summary Table.
Register to configure speed profile6
图8-65. REF_PROFILES6 Register
31
30
22
14
6
29
21
13
5
28
27
26
18
10
2
25
17
9
24
16
8
PARITY
R/W-0h
REF_OFF2
R/W-X
23
20
12
4
19
REF_OFF2
R/W-X
REF_CLAMP2
R/W-X
15
11
REF_CLAMP2
R/W-X
RESERVED
R/W-X
7
3
1
0
RESERVED
R/W-X
表8-27. REF_PROFILES6 Register Field Descriptions
Bit
31
Field
PARITY
Type
R/W
R/W
R/W
Reset
Description
0h
X
Parity bit
30-23
22-15
REF_OFF2
Turn off REF Configuration Turn off REF % = {(REF_OFF2/255)*100}
REF_CLAMP2
X
Clamp REF Configuration Clamp REF % =
{(REF_CLAMP2/255)*100}
14-0
RESERVED
R/W
X
Reserved
8.7.2 Fault_Configuration Registers
表8-28 lists the memory-mapped registers for the Fault_Configuration registers. All register offset addresses not
listed in 表8-28 should be considered as reserved locations and the register contents should not be modified.
表8-28. FAULT_CONFIGURATION Registers
Offset Acronym
Register Name
Section
92h
FAULT_CONFIG1
Fault configuration 1
FAULT_CONFIG1 Register (Offset = 92h)
[Reset = 00000000h]
94h
FAULT_CONFIG2
Fault configuration 2
FAULT_CONFIG2 Register (Offset = 94h)
[Reset = 00000000h]
Complex bit access types are encoded to fit into small table cells. 表 8-29 shows the codes that are used for
access types in this section.
表8-29. Fault_Configuration Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
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表8-29. Fault_Configuration Access Type Codes
(continued)
Access Type
Code
Description
-n
Value after reset or the default
value
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8.7.2.1 FAULT_CONFIG1 Register (Offset = 92h) [Reset = 00000000h]
FAULT_CONFIG1 is shown in 图8-66 and described in 表8-30.
Return to the Summary Table.
Register to configure fault settings1
图8-66. FAULT_CONFIG1 Register
31
30
22
14
29
28
20
12
27
19
11
26
25
24
16
8
PARITY
R/W-0h
NO_MTR_DEG_TIME
R/W-0h
CBC_ILIMIT_MODE
R/W-0h
23
21
18
17
LOCK_ILIMIT
R/W-0h
LOCK_ILIMIT_MODE
R/W-0h
15
13
10
9
LOCK_ILIMIT_
MODE
LOCK_ILIMIT_DEG
CBC_RETRY_PWM_CYC
R/W-0h
R/W-0h
R/W-0h
7
6
5
4
3
2
1
0
RESERVED
R/W-0h
MTR_LCK_MODE
R/W-0h
LCK_RETRY
R/W-0h
表8-30. FAULT_CONFIG1 Register Field Descriptions
Bit
31
Field
PARITY
NO_MTR_DEG_TIME
Type
R/W
R/W
Reset
Description
0h
Parity bit
30-28
0h
No motor detect deglitch time
0h = 1 ms
1h = 10 ms
2h = 25 ms
3h = 50 ms
4h = 100 ms
5h = 250 ms
6h = 500 ms
7h = 1000 ms
27-24
CBC_ILIMIT_MODE
R/W
0h
Cycle by cycle current limit
0h = Automatic recovery next PWM cycle; nFAULT active; driver is in
recirculation mode
1h = Automatic recovery next PWM cycle; nFAULT inactive; driver is
in recirculation mode
2h = Automatic recovery if VSOX < ILIMIT; nFAULT active; driver is
in recirculation mode (Only available with high-side modulation)
3h = Automatic recovery if VSOX < ILIMIT; nFAULT inactive; driver is
in recirculation mode (Only available with high-side modulation)
4h = Automatic recovery after CBC_RETRY_PWM_CYC; nFAULT
active; driver is in recirculation mode
5h = Automatic recovery after CBC_RETRY_PWM_CYC; nFAULT
inactive; driver is in recirculation mode
6h = VSOX > ILIMIT is report only but no action is taken
7h = Cycle by Cycle limit is disabled
8h = Cycle by Cycle limit is disabled
9h = Cycle by Cycle limit is disabled
Ah = Cycle by Cycle limit is disabled
Bh = Cycle by Cycle limit is disabled
Ch = Cycle by Cycle limit is disabled
Dh = Cycle by Cycle limit is disabled
Eh = Cycle by Cycle limit is disabled
Fh = Cycle by Cycle limit is disabled
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表8-30. FAULT_CONFIG1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
23-19
LOCK_ILIMIT
R/W
0h
Lock detection current limit (Lock detection current limit (A) =
LOCK_ILIMIT / CSA_GAIN)
0h = 0.0 V
1h = 0.1 V
2h = 0.2 V
3h = 0.3 V
4h = 0.4 V
5h = 0.5 V
6h = 0.6 V
7h = 0.7 V
8h = 0.8 V
9h = 0.9 V
Ah = 1.0 V
Bh = 1.1 V
Ch = 1.2 V
Dh = 1.3 V
Eh = 1.4 V
Fh = 1.5 V
10h = N/A
11h = N/A
12h = N/A
13h = N/A
14h = N/A
15h = N/A
16h = N/A
17h = N/A
18h = N/A
19h = N/A
1Ah = N/A
1Bh = N/A
1Ch = N/A
1Dh = N/A
1Eh = N/A
1Fh = N/A
18-15
LOCK_ILIMIT_MODE
R/W
0h
Lock detection current limit mode
0h = Ilimit lock detection causes latched fault; nFAULT active; Gate
driver is tristated
1h = Ilimit lock detection causes latched fault; nFAULT active; Gate
driver is in recirculation mode
2h = Ilimit lock detection causes latched fault; nFAULT active; Gate
driver is in high-side brake mode (All high-side FETs are turned ON)
3h = Ilimit lock detection causes latched fault; nFAULT active; Gate
driver is in low-side brake mode (All low-side FETs are turned ON)
4h = Automatic recovery after tLCK_RETRY; Gate driver is tristated
5h = Automatic recovery after tLCK_RETRY; Gate driver is in
recirculation mode
6h = Automatic recovery after tLCK_RETRY; Gate driver is in high-
side brake mode (All high-side FETs are turned ON)
7h = Automatic recovery after tLCK_RETRY; Gate driver is in low-
side brake mode (All low-side FETs are turned ON)
8h = Ilimit lock detection is in report only but no action is taken
9h = Ilimit lock detection is disabled
Ah = Ilimit lock detection is disabled
Bh = Ilimit lock detection is disabled
Ch = Ilimit lock detection is disabled
Dh = Ilimit lock detection is disabled
Eh = Ilimit lock detection is disabled
Fh = Ilimit lock detection is disabled
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表8-30. FAULT_CONFIG1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
14-11
LOCK_ILIMIT_DEG
R/W
0h
Lock detection current limit deglitch time
0h = 1 ms
1h = 2 ms
2h = 5 ms
3h = 10 ms
4h = 25 ms
5h = 50 ms
6h = 75 ms
7h = 100 ms
8h = 250 ms
9h = 500 ms
Ah = 1 s
Bh = 2.5 s
Ch = 5 s
Dh = 10 s
Eh = 25 s
Fh = 50 s
10-8
CBC_RETRY_PWM_CYC R/W
0h
Number of PWM cycles for CBC current limit to retry
0h = 0
1h = 1
2h = 2
3h = 3
4h = 4
5h = 5
6h = 6
7h = 7
7
RESERVED
R/W
R/W
0h
0h
Reserved
6-3
MTR_LCK_MODE
Motor lock mode
0h = Motor lock detection causes latched fault; nFAULT active; Gate
driver is tristated
1h = Motor lock detection causes latched fault; nFAULT active; Gate
driver is in recirculation mode
2h = Motor lock detection causes latched fault; nFAULT active; Gate
driver is in high-side brake mode (All high-side FETs are turned ON)
3h = Motor lock detection causes latched fault; nFAULT active; Gate
driver is in low-side brake mode (All low-side FETs are turned ON)
4h = Automatic recovery after tLCK_RETRY; Gate driver is tristated
5h = Automatic recovery after tLCK_RETRY; Gate driver is in
recirculation mode
6h = Automatic recovery after tLCK_RETRY; Gate driver is in high-
side brake mode (All high-side FETs are turned ON)
7h = Automatic recovery after tLCK_RETRY; Gate driver is in low-
side brake mode (All low-side FETs are turned ON)
8h = Motor lock detection is in report only but no action is taken
9h = Motor lock detection is disabled
Bh = Motor lock detection is disabled
Ch = Motor lock detection is disabled
Dh = Motor lock detection is disabled
Eh = Motor lock detection is disabled
Fh = Motor lock detection is disabled
2-0
LCK_RETRY
R/W
0h
Lock retry time
0h = 100 ms
1h = 500 ms
2h = 1000 ms
3h = 2000 ms
4h = 3000 ms
5h = 5000 ms
6h = 7500 ms
7h = 10000 ms
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8.7.2.2 FAULT_CONFIG2 Register (Offset = 94h) [Reset = 00000000h]
FAULT_CONFIG2 is shown in 图8-67 and described in 表8-31.
Return to the Summary Table.
Register to configure fault settings2
图8-67. FAULT_CONFIG2 Register
31
30
29
28
27
26
25
24
16
PARITY
ABN_SPD_EN LOSS_OF_SYN NO_MOTOR_E
LOCK_ABN_SPEED
C_EN
N
R/W-0h
23
R/W-0h
R/W-0h
R/W-0h
R/W-0h
22
21
20
12
4
19
18
10
2
17
LOSS_SYNC_TIMES
NO_MTR_THR
MAX_VM_MOD MAX_VM_MOT
E
OR
R/W-0h
14
R/W-0h
R/W-0h
R/W-0h
15
13
11
9
8
MAX_VM_MOTOR
MIN_VM_MOD
E
MIN_VM_MOTOR
AUTO_RETRY_TIMES
R/W-0h
R/W-0h
R/W-0h
3
R/W-0h
7
6
5
1
0
AUTO_RETRY_
TIMES
LOCK_MIN_SPEED
ABN_LOCK_SPD_RATIO
ZERO_DUTY_THR
R/W-0h
R/W-0h
R/W-0h
R/W-0h
表8-31. FAULT_CONFIG2 Register Field Descriptions
Bit
31
30
Field
PARITY
Type
R/W
R/W
Reset
Description
0h
Parity bit
ABN_SPD_EN
0h
Abnormal Speed Enable
0h = Disable
1h = Enable
29
28
LOSS_OF_SYNC_EN
NO_MOTOR_EN
LOCK_ABN_SPEED
R/W
R/W
R/W
0h
0h
0h
Loss of Sync Enable
0h = Disable
1h = Enable
No Motor Enable
0h = Disable
1h = Enable
27-24
Abnormal speed lock threshold
0h = 250 Hz
1h = 500 Hz
2h = 750 Hz
3h = 1000 Hz
4h = 1250 Hz
5h = 1500 Hz
6h = 1750 Hz
7h = 2000 Hz
8h = 2250 Hz
9h = 2500 Hz
Ah = 2750 Hz
Bh = 3000 Hz
Ch = 3250 Hz
Dh = 3500 Hz
Eh = 3750 Hz
Fh = 4000 Hz
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表8-31. FAULT_CONFIG2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
23-21
LOSS_SYNC_TIMES
R/W
0h
Number of times sync lost for loss of sync lock fault
0h = Trigger after losing sync 2 times
1h = Trigger after losing sync 3 times
2h = Trigger after losing sync 4 times
3h = Trigger after losing sync 5 times
4h = Trigger after losing sync 6 times
5h = Trigger after losing sync 7 times
6h = Trigger after losing sync 8 times
7h = Trigger after losing sync 9 times
20-18
NO_MTR_THR
R/W
0h
No motor lock current threshold (No motor lock current threshold (A)
= NO_MTR_THR / CSA_GAIN)
0h = 0.005 V
1h = 0.0075 V
2h = 0.010 V
3h = 0.0125 V
4h = 0.020 V
5h = 0.025 V
6h = 0.030 V
7h = 0.04 V
17
MAX_VM_MODE
MAX_VM_MOTOR
R/W
R/W
0h
0h
0h = Latch on Overvoltage
1h = Automatic clear if voltage in bounds
16-14
Maximum voltage for running motor
0h = No Limit
1h = 10.0 V
2h = 12.0 V
3h = 14.0 V
4h = 16.0 V
5h = 18.0 V
6h = 19.0 V
7h = 20.0 V
13
MIN_VM_MODE
MIN_VM_MOTOR
R/W
R/W
0h
0h
0h = Latch on Undervoltage
1h = Automatic clear if voltage in bounds
12-10
Minimum voltage for running motor
0h = No Limit
1h = 5.0 V
2h = 6.0 V
3h = 7.0 V
4h = 8.0 V
5h = 9.0 V
6h = 10.0 V
7h = 12.0 V
9-7
AUTO_RETRY_TIMES
R/W
0h
Number of automatic retry attempts
0h = No Limit
1h = 2
2h = 3
3h = 5
4h = 7
5h = 10
6h = 15
7h = 20
6-4
LOCK_MIN_SPEED
R/W
0h
Speed below which lock fault is triggered
0h = 0.5 Hz
1h = 1 Hz
2h = 2 Hz
3h = 3 Hz
4h = 5 Hz
5h = 10 Hz
6h = 15 Hz
7h = 25 Hz
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表8-31. FAULT_CONFIG2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3-2
ABN_LOCK_SPD_RATIO R/W
0h
Ratio of electrical speed between two consecutive cycles above
which abnormal speed lock fault is triggered
0h = 2
1h = 4
2h = 6
3h = 8
1-0
ZERO_DUTY_THR
R/W
0h
Duty cycle below which target speed is zero
0h = 0%
1h = 1%
2h = 2.0%
3h = 2.5%
8.7.3 Hardware_Configuration Registers
表 8-32 lists the memory-mapped registers for the Hardware_Configuration registers. All register offset
addresses not listed in 表 8-32 should be considered as reserved locations and the register contents should not
be modified.
表8-32. HARDWARE_CONFIGURATION Registers
Offset Acronym
Register Name
Section
A6h
A8h
AAh
PIN_CONFIG1
Hardware pin configuration
PIN_CONFIG1 Register (Offset = A6h)
[Reset = 00000000h]
PIN_CONFIG2
Hardware pin configuration
Peripheral configuration
PIN_CONFIG2 Register (Offset = A8h)
[Reset = 00000000h]
DEVICE_CONFIG
DEVICE_CONFIG Register (Offset = AAh)
[Reset = 00002000h]
Complex bit access types are encoded to fit into small table cells. 表 8-33 shows the codes that are used for
access types in this section.
表8-33. Hardware_Configuration Access Type
Codes
Access Type
Read Type
R
Code
R
Description
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
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8.7.3.1 PIN_CONFIG1 Register (Offset = A6h) [Reset = 00000000h]
PIN_CONFIG1 is shown in 图8-68 and described in 表8-34.
Return to the Summary Table.
Register to configure hardware pins
图8-68. PIN_CONFIG1 Register
31
30
22
14
6
29
28
20
12
27
26
18
10
2
25
24
16
8
PARITY
R/W-0h
DACOUT1_VAR_ADDR
R/W-0h
23
15
7
21
19
17
DACOUT1_VAR_ADDR
R/W-0h
DACOUT2_VAR_ADDR
R/W-0h
13
11
9
DACOUT2_VAR_ADDR
R/W-0h
5
4
3
1
0
DACOUT2_VA
R_ADDR
BRAKE_INPUT
DIR_INPUT
R/W-0h
SPD_CTRL_MODE
Alarm_Pin
R/W-0h
R/W-0h
R/W-0h
R/W-0h
表8-34. PIN_CONFIG1 Register Field Descriptions
Bit
31
Field
PARITY
Type
R/W
R/W
R/W
R/W
Reset
Description
0h
Parity bit
30-19
18-7
6-5
DACOUT1_VAR_ADDR
DACOUT2_VAR_ADDR
BRAKE_INPUT
0h
12-bit address of variable to be monitored on Pin 33
12-bit address of variable to be monitored on Pin 34
0h
0h
Brake input configuration on Pin 31
0h = Hardware Pin BRAKE
1h = Overwrite Hardware pin with Active Brake
2h = Overwrite Hardware pin with brake functionality disabled
3h = N/A
4-3
2-1
0
DIR_INPUT
R/W
R/W
R/W
0h
0h
0h
Direction input configuration on Pin 28
0h = Hardware Pin DIR
1h = Overwrite Hardware pin with clockwise rotation OUTA-OUTB-
OUTC
3h = N/A
SPD_CTRL_MODE
Alarm_Pin
Speed input configuration on Pin 24
0h = Analog mode speed Input
1h = PWM Mode Speed Input
2h = I2C Speed Input mode
3h = Frequency based speed Input mode
Alarm Pin GPIO configuration on Pin 35
0h = Disabled (Hi-Z)
1h = Enabled
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8.7.3.2 PIN_CONFIG2 Register (Offset = A8h) [Reset = 00000000h]
PIN_CONFIG2 is shown in 图8-69 and described in 表8-35.
Return to the Summary Table.
Register to configure hardware pins
图8-69. PIN_CONFIG2 Register
31
30
29
28
27
26
18
25
24
16
PARITY
R/W-0h
DAC_SOX_CONFIG
R/W-0h
SLEEP_TIME
R/W-0h
I2C_TARGET_ADDR
R/W-0h
23
22
21
20
19
17
I2C_TARGET_ADDR
DAC_OUT_EN EXT_WD_EN EXT_WD_INPU EXT_WD_FAUL
T
T
R/W-0h
R/W-0h
11
R/W-0h
10
R/W-0h
R/W-0h
15
14
13
12
9
8
EXT_WD_FREQ
FG_CONFIG
R/W-0h
FG_PIN_FAULT_CONFIG
R/W-0h
FG_PIN_STOP_CONFIG
R/W-0h
TBLANK
R/W-0h
R/W-0h
7
6
5
4
3
2
1
0
TBLANK
R/W-0h
TPWDTH
R/W-0h
ZERO_DUTY_HYST
R/W-0h
表8-35. PIN_CONFIG2 Register Field Descriptions
Bit
Field
Type
R/W
R/W
Reset
Description
31
PARITY
0h
Parity bit
30-29
DAC_SOX_CONFIG
0h
DAC/SOx Pin 32 Configuration
0h = DACOUT2
1h = SOA
2h = SOB
3h = SOC
28-27
SLEEP_TIME
R/W
0h
Sleep Time
0h = Check low for 50 µs
1h = Check low for 200 µs
2h = Check low for 20 ms
3h = Check low for 200 ms
26-20
19
I2C_TARGET_ADDR
DAC_OUT_EN
R/W
R/W
0h
0h
I2C target address
Enable DAC Outputs
0h = Disable
1h = Enable
18
17
EXT_WD_EN
R/W
R/W
R/W
R/W
0h
0h
0h
0h
Enable external watchdog on pin29
0h = Disable
1h = Enable
EXT_WD_INPUT
EXT_WD_FAULT
EXT_WD_FREQ
External watchdog source
0h = I2C
1h = GPIO
16
External watchdog fault mode
0h = Report only
1h = Latched fault with Hi-Z outputs
15-14
External watchdog frequency
0h = 10Hz
1h = 5Hz
2h = 2Hz
3h = 1Hz
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表8-35. PIN_CONFIG2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
13
FG_CONFIG
R/W
0h
Fault on FG Pin Configuration
0h = FG active till BEMF drops below BEMF threshold defined by
FG_BEMF_THR
1h = FG toggle as long as motor is actively driven
12-11
10-9
8-5
FG_PIN_FAULT_CONFIG R/W
FG_PIN_STOP_CONFIG R/W
0h
0h
0h
Fault on FG Pin Configuration
0h = FG continues to toggle till motor stops
1h = FG in Hi-Z state, pulled up externally
2h = FG pulled Low
3h = N/A
FG upon Motor Stop Configuration
0h = FG continues to toggle till motor stops
1h = FG in Hi-Z state, pulled up externally
2h = FG pulled Low
3h = N/A
TBLANK
R/W
Blanking time after PWM edge
0h = 0 µs
1h = 1 µs
2h = 2 µs
3h = 3 µs
4h = 4 µs
5h = 5 µs
6h = 6 µs
7h = 7 µs
8h = 8 µs
9h = 9 µs
Ah = 10 µs
Bh = 11 µs
Ch = 12 µs
Dh = 13 µs
Eh = 14 µs
Fh = 15 µs
4-2
TPWDTH
R/W
0h
Comparator deglitch time
0h = 0 µs
1h = 1 µs
2h = 2 µs
3h = 3 µs
4h = 4 µs
5h = 5 µs
6h = 6 µs
7h = 7 µs
1-0
ZERO_DUTY_HYST
R/W
0h
Duty cycle hysteresis to exit standby
0h = 0 %
1h = 1 %
2h = 2 %
3h = 3 %
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8.7.3.3 DEVICE_CONFIG Register (Offset = AAh) [Reset = 00002000h]
DEVICE_CONFIG is shown in 图8-70 and described in 表8-36.
Return to the Summary Table.
Register to peripheral1
图8-70. DEVICE_CONFIG Register
31
30
22
29
21
13
28
27
26
18
10
25
24
16
8
PARITY
R/W-0h
INPUT_MAX_FREQUENCY
R/W-0h
23
20
19
17
9
INPUT_MAX_FREQUENCY
R/W-0h
15
14
12
11
RESERVED
SSM_CONFIG
RESERVED
R/W-2h
DEV_MODE SPD_PWM_RA
NGE_SELECT
CLK_SEL
R/W-0h
R/W-0h
R/W-0h
6
R/W-0h
3
R/W-0h
2
7
5
4
1
0
EXT_CLK_EN
R/W-0h
EXT_CLK_CONFIG
R/W-0h
DIG_DEAD_TIME
R/W-0h
表8-36. DEVICE_CONFIG Register Field Descriptions
Bit
31
Field
PARITY
Type
Reset
Description
R/W
0h
Parity bit
30-16
INPUT_MAX_FREQUENC R/W
Y
0h
Maximum frequency (in Hz) for frequency based speed input
15
14
RESERVED
R/W
R/W
0h
0h
Reserved
SSM_CONFIG
SSM enable
0h = Enable
1h = Disable
13-12
11
RESERVED
DEV_MODE
R/W
R/W
2h
0h
Reserved
Device mode select
0h = Standby mode
1h = Sleep mode
10
SPD_PWM_RANGE_SEL R/W
ECT
0h
0h
PWM frequency range select
0h = 325 Hz to 100 kHz speed PWM input
1h = 10 Hz to 325 Hz speed PWM input
9-8
CLK_SEL
R/W
Clock source
0h = Internal Oscillator
1h = N/A
2h = N/A
3h = External Clock input
7
EXT_CLK_EN
R/W
R/W
0h
0h
External clock enable
0h = Disable
1h = Enable
6-4
EXT_CLK_CONFIG
External clock frequency
0h = 8 kHz
1h = 16 kHz
2h = 32 kHz
3h = 64 kHz
4h = 128 kHz
5h = 256 kHz
6h = 512 kHz
7h = 1024 kHz
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表8-36. DEVICE_CONFIG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3-0
DIG_DEAD_TIME
R/W
0h
Dead time added by digital controller to gate input signals
0h = 0ns
1h = 50ns
2h = 100ns
3h = 150ns
4h = 200ns
5h = 250ns
6h = 300ns
7h = 350ns
8h = 400ns
9h = 450ns
Ah = 500ns
Bh = 600ns
Ch = 700ns
Dh = 800ns
Eh = 900ns
Fh = 1000ns
8.7.4 Gate_Driver_Configuration Registers
表 8-37 lists the memory-mapped registers for the Gate_Driver_Configuration registers. All register offset
addresses not listed in 表 8-37 should be considered as reserved locations and the register contents should not
be modified.
表8-37. GATE_DRIVER_CONFIGURATION Registers
Offset Acronym
Register Name
Section
ACh
GD_CONFIG1
Gate driver configuration 1
GD_CONFIG1 Register (Offset = ACh)
[Reset = 00000000h]
AEh
GD_CONFIG2
Gate driver configuration 2
GD_CONFIG2 Register (Offset = AEh)
[Reset = 00000000h]
Complex bit access types are encoded to fit into small table cells. 表 8-38 shows the codes that are used for
access types in this section.
表8-38. Gate_Driver_Configuration Access Type
Codes
Access Type
Read Type
R
Code
R
Description
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
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8.7.4.1 GD_CONFIG1 Register (Offset = ACh) [Reset = 00000000h]
GD_CONFIG1 is shown in 图8-71 and described in 表8-39.
Return to the Summary Table.
Register to configure gated driver settings1
图8-71. GD_CONFIG1 Register
31
30
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
24
16
8
PARITY
R/W-0h
RESERVED
R/W-0h
RESERVED
R/W-0h
RESERVED
R/W-0h
OCP_MODE
R/W-0h
23
22
17
OCP_MODE
R/W-0h
RESERVED
R/W-0h
OCP_DEG
R/W-0h
OCP_TBLANK
R/W-0h
TRETRY
R/W-0h
15
14
9
RESERVED
R/W-0h
DLY_TARGET
R/W-0h
DLYCMP_EN
R/W-0h
SLEW_RATE
R/W-0h
7
6
1
0
SLEW_RATE
R/W-0h
CSA_GAIN
R/W-0h
RESERVED
R/W-0h
表8-39. GD_CONFIG1 Register Field Descriptions
Bit
31
Field
PARITY
Type
R/W
R/W
R/W
R/W
R/W
Reset
Description
0h
Parity bit
30
RESERVED
RESERVED
RESERVED
OCP_MODE
0h
Reserved
Reserved
Reserved
OCP MODE
29-28
27-26
25-23
0h
0h
0h
0h = Report on nFAULT, latch into status register, predriver Hi-Z,
auto recover with retry time
1h = Reserved
2h = Report on nFAULT, latch into status register, predriver Hi-Z, no
auto recovery, wait for CLR_FLT
3h = Report on nFAULT, latch into status register, no action on
predriver
4h = Reserved
5h = Reserved
6h = Reserved
7h = Disabled
22
RESERVED
OCP_DEG
R/W
R/W
0h
0h
Reserved
21-20
OCP Deglitch time
0h = 0.3 µs
1h = 0.7 µs
2h = 1 µs
3h = 1.2 µs
19-18
17-16
15-14
OCP_TBLANK
TRETRY
R/W
R/W
R/W
0h
0h
0h
OCP Blanking Time
0h = 0.3 µs
1h = 0.6 µs
2h = 1 µs
3h = 1.2 µs
Retry Time
0h = 0.5 s
1h = 1 s
2h = 2 s
3h = 5 s
RESERVED
Reserved
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表8-39. GD_CONFIG1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
13-10
DLY_TARGET
R/W
0h
Delay Target Value = 200ns * Value
0h = 0
1h = 200ns
2h = 400ns
3h = 600ns
4h = 800ns
5h = 1000ns
6h = 1200ns
7h = 1400ns
8h = 1600ns
9h = 1800ns
Ah = 2000ns
Bh = 2200ns
Ch = 2400ns
Dh = 2600ns
Eh = 2800ns
Fh = 3000ns
9
DLYCMP_EN
SLEW_RATE
R/W
R/W
0h
0h
Delay Compensation Enabled
0h = Disabled
1h = Enabled
8-7
Slew Rate
0h = 25V/µs
1h = 50V/µs
2h = 125V/µs
3h = 200V/µs
6-5
4-0
CSA_GAIN
RESERVED
R/W
R/W
0h
0h
Current Sense Amplifier (CSA) Gain
0h = 0.25V/A
1h = 0.5V/A
2h = 1V/A
3h = 2V/A
Reserved
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8.7.4.2 GD_CONFIG2 Register (Offset = AEh) [Reset = 00000000h]
GD_CONFIG2 is shown in 图8-72 and described in 表8-40.
Return to the Summary Table.
Register to configure gated driver settings2
图8-72. GD_CONFIG2 Register
31
30
22
14
6
29
21
13
5
28
20
12
4
27
26
18
10
2
25
24
16
8
PARITY
R/W-0h
RESERVED
R/W-0h
23
15
7
19
17
9
RESERVED
R/W-0h
11
3
RESERVED
R/W-0h
1
0
RESERVED
R/W-0h
表8-40. GD_CONFIG2 Register Field Descriptions
Bit
31
Field
Type
R/W
R/W
Reset
Description
PARITY
0h
Parity bit
30-0
RESERVED
0h
Reserved
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8.8 RAM (Volatile) Register Map
8.8.1 Fault_Status Registers
表 8-41 lists the memory-mapped registers for the Fault_Status registers. All register offset addresses not listed
in 表8-41 should be considered as reserved locations and the register contents should not be modified.
表8-41. FAULT_STATUS Registers
Offset Acronym
Register Name
Section
E0h
GATE_DRIVER_FAULT_STATUS Fault Status Register
CONTROLLER_FAULT_STATUS Fault Status Register
GATE_DRIVER_FAULT_STATUS Register
(Offset = E0h) [Reset = 00000000h]
E2h
CONTROLLER_FAULT_STATUS Register
(Offset = E2h) [Reset = 00000000h]
Complex bit access types are encoded to fit into small table cells. 表 8-42 shows the codes that are used for
access types in this section.
表8-42. Fault_Status Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Reset or Default Value
-n
Value after reset or the default
value
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8.8.1.1 GATE_DRIVER_FAULT_STATUS Register (Offset = E0h) [Reset = 00000000h]
GATE_DRIVER_FAULT_STATUS is shown in 图8-73 and described in 表8-43.
Return to the Summary Table.
Status of various faults
图8-73. GATE_DRIVER_FAULT_STATUS Register
31
30
22
29
28
27
26
25
24
16
DRIVER_FAUL
T
RESERVED
R-0h
23
R-0h
19
21
20
18
17
RESERVED
R-0h
15
14
13
12
11
10
9
8
RESERVED
R-0h
OCP
R-0h
RESET
R-0h
SYSFLT
R-0h
OVP
R-0h
CP_UV
R-0h
VM_UV
R-0h
RESERVED
R-0h
7
6
5
4
3
2
1
0
OTW
R-0h
OTS
R-0h
RESERVED
R-0h
SPI_FLT
R-0h
AVDD_UV
R-0h
VINAVDD_UV
R-0h
AVDD_OCP
R-0h
表8-43. GATE_DRIVER_FAULT_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
31
DRIVER_FAULT
R
0h
Logic OR of driver fault registers
0h = No Gate Driver fault condition is detected
1h = Gate Driver fault condition is detected
30-15
14
RESERVED
OCP
R
R
0h
0h
Reserved
Over current protection
0h = No overcurrent condition is detected
1h = Overcurrent condition is detected
13
12
11
10
9
RESET
SYSFLT
OVP
R
R
R
R
R
0h
0h
0h
0h
0h
Power On Reset
0h = Powerup condition is detected
1h = Powerup condition is cleared
System Fault
0h = No system fault is detected
1h = system fault is detected
Over voltage protection
0h = No overvoltage condition is detected on VM
1h = Overvoltage condition is detected on VM
CP_UV
VM_UV
Charge pump undervoltage
0h = No undervoltage condition is detected on CP
1h = Undervoltage condition is detected on CP
VM undervoltage
0h = No undervoltage condition is detected on VM
1h = Undervoltage condition is detected on VM
8
7
RESERVED
OTW
R
R
0h
0h
Reserved
Over temperature warning
0h = No overtemperature warning is detected
1h = Overtemperature warning is detected
6
OTS
R
R
0h
0h
Over temperature shutdown
0h = No overtemperature shutdown is detected
1h = Overtemperature shutdown is detected
5-4
RESERVED
Reserved
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表8-43. GATE_DRIVER_FAULT_STATUS Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3
SPI_FLT
R
0h
SPI faults
0h = No SPI fault is detected
1h = SPI fault is detected
2
1
0
AVDD_UV
R
R
R
0h
0h
0h
AVDD undervoltage
0h = No undervoltage condition is detected on AVDD
1h = Undervoltage condition is detected on AVDD
VINAVDD_UV
AVDD_OCP
VINAVDD undervoltage
0h = No undervoltage condition is detected on VIN_AVDD
1h = Undervoltage condition is detected on VIN_AVDD
AVDD OCP fault
0h = No overcurrent condition is detected on AVDD LDO
1h = Overcurrent condition is detected on AVDD LDO
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8.8.1.2 CONTROLLER_FAULT_STATUS Register (Offset = E2h) [Reset = 00000000h]
CONTROLLER_FAULT_STATUS is shown in 图8-74 and described in 表8-44.
Return to the Summary Table.
Status of various faults
图8-74. CONTROLLER_FAULT_STATUS Register
31
30
29
28
27
26
25
24
16
CONTROLLER
_FAULT
RESERVED
IPD_FREQ_FA IPD_T1_FAULT IPD_T2_FAULT
ULT
RESERVED
R-0h
23
R-0h
22
R-0h
R-0h
R-0h
R-0h
17
21
20
19
18
ABN_SPEED LOSS_OF_SYN
C
NO_MTR
MTR_LCK
CBC_ILIMIT
LOCK_ILIMIT MTR_UNDER_ MTR_OVER_V
VOLTAGE
OLTAGE
R-0h
15
R-0h
14
R-0h
13
R-0h
12
R-0h
R-0h
10
R-0h
R-0h
11
9
8
EXT_WD_TIME
OUT
RESERVED
R-0h
7
R-0h
3
6
5
4
2
1
0
RESERVED
R-0h
STL_EN
R-0h
STL_STATUS
R-0h
APP_RESET
R-0h
表8-44. CONTROLLER_FAULT_STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
31
CONTROLLER_FAULT
R
0h
Logic OR of controller fault registers
0h = No controller fault condition is detected
1h = Controller fault condition is detected
30
29
RESERVED
R
R
0h
0h
Reserved
IPD_FREQ_FAULT
Indicates IPD frequency fault
0h = No IPD frequency fault detected
1h = IPD frequency fault detected
28
27
IPD_T1_FAULT
IPD_T2_FAULT
R
R
0h
0h
Indicates IPD T1 fault
0h = No IPD T1 fault detected
1h = IPD T1 fault detected
Indicates IPD T2 fault
0h = No IPD T2 fault detected
1h = IPD T2 fault detected
26-24
23
RESERVED
ABN_SPEED
R
R
0h
0h
Reserved
Indicates abnormal speed motor lock condition
0h = No abnormal speed fault detected
1h = Abnormal Speed fault detected
22
21
20
19
LOSS_OF_SYNC
NO_MTR
R
R
R
R
0h
0h
0h
0h
Indicates sync lost motor lock condition
0h = No sync lost fault detected
1h = Sync lost fault detected
Indicates no motor fault
0h = No motor fault not detected
1h = No motor fault detected
MTR_LCK
Indicates when one of the motor lock is triggered
0h = Motor lock fault not detected
1h = Motor lock fault detected
CBC_ILIMIT
Indicates CBC current limit fault
0h = No CBC fault detected
1h = CBC fault detected
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表8-44. CONTROLLER_FAULT_STATUS Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
18
LOCK_ILIMIT
R
0h
Indicates lock detection current limit fault
0h = No lock current limit fault detected
1h = Lock current limit fault detected
17
16
15
MTR_UNDER_VOLTAGE
MTR_OVER_VOLTAGE
EXT_WD_TIMEOUT
R
R
R
0h
0h
0h
Indicates motor undervoltage fault
0h = No motor undervoltage detected
1h = Motor undervoltage detected
Indicates motor overvoltage fault
0h = No motor overvoltage detected
1h = Motor overvoltage detected
Indicates external watchdog timeout fault
0h = No external watchdog timeout fault detected
1h = External watchdog timeout fault detected
14-3
2
RESERVED
STL_EN
R
R
0h
0h
Reserved
Indicates STL is enabled in EEPROM
0h = STL Disable
1h = STL Enable
1
0
STL_STATUS
APP_RESET
R
R
0h
0h
Indicates STL success criteria Pass = 1b; Fail = 0b
0h = STL Fail
1h = STL Pass
App reset
0h = App Reset Fail
1h = App Reset Successful
8.8.2 System_Status Registers
表 8-45 lists the memory-mapped registers for the System_Status registers. All register offset addresses not
listed in 表8-45 should be considered as reserved locations and the register contents should not be modified.
表8-45. SYSTEM_STATUS Registers
Offset Acronym
Register Name
Section
E4h
EAh
ECh
SYS_STATUS1
System Status Register1
SYS_STATUS1 Register (Offset = E4h)
[Reset = 00000000h]
SYS_STATUS2
SYS_STATUS3
System Status Register2
System Status Register3
SYS_STATUS2 Register (Offset = EAh)
[Reset = 00000000h]
SYS_STATUS3 Register (Offset = ECh)
[Reset = 00000000h]
Complex bit access types are encoded to fit into small table cells. 表 8-46 shows the codes that are used for
access types in this section.
表8-46. System_Status Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Reset or Default Value
-n
Value after reset or the default
value
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8.8.2.1 SYS_STATUS1 Register (Offset = E4h) [Reset = 00000000h]
SYS_STATUS1 is shown in 图8-75 and described in 表8-47.
Return to the Summary Table.
Status of various system and motor parameters
图8-75. SYS_STATUS1 Register
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
25
24
16
8
VOLT_MAG
R-0h
17
9
VOLT_MAG
R-0h
SPEED_CMD
R-0h
1
0
SPEED_CMD
I2C_ENTRY_S
TATUS
R-0h
R-0h
表8-47. SYS_STATUS1 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-16
15-1
VOLT_MAG
R
0h
Applied DC input voltage (/10 to get DC input voltage in V)
SPEED_CMD
R
0h
Decoded speed command in PWM/Analog/Freq. mode
(SPEED_CMD (%) = SPEED_CMD/32767 * 100%)
0
I2C_ENTRY_STATUS
R
0h
Indicates if I2C entry has happened
0h = I2C mode not entered through pin sequence
1h = I2C mode entered through pin sequence
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8.8.2.2 SYS_STATUS2 Register (Offset = EAh) [Reset = 00000000h]
SYS_STATUS2 is shown in 图8-76 and described in 表8-48.
Return to the Summary Table.
Status of various system and motor parameters
图8-76. SYS_STATUS2 Register
31
23
15
7
30
22
14
6
29
21
13
5
28
20
12
27
19
11
26
18
10
2
25
17
24
STATE
R-0h
RESERVED
R-0h
16
RESERVED
R-0h
STL_FAULT
R-0h
RESERVED
R-0h
9
8
MOTOR_SPEED
R-0h
4
3
1
0
MOTOR_SPEED
R-0h
表8-48. SYS_STATUS2 Register Field Descriptions
Bit
Field
Type
Reset
Description
31-28
STATE
R
0h
Current status of state machine; 4-bit value indicating status of state
machine
0h = SYSTEM_IDLE
1h = MOTOR_START
2h = MOTOR_RUN
3h = SYSTEM_INIT
4h = MOTOR_IPD
5h = MOTOR_ALIGN
6h = MOTOR_IDLE
7h = MOTOR_STOP
8h = FAULT
9h = MOTOR_DIRECTION
Ah = HALL_ALIGN
Ch = MOTOR_CALIBRATE
Dh = MOTOR_DESCEL
Eh = MOTOR_BRAKE
Fh = N/A
27-18
17
RESERVED
STL_FAULT
R
R
0h
0h
Reserved
STL fault status
0h = Pass
1h = Fail
16
RESERVED
R
R
0h
0h
Reserved
15-0
MOTOR_SPEED
Speed output (/10 to get motor electrical speed in Hz)
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8.8.2.3 SYS_STATUS3 Register (Offset = ECh) [Reset = 00000000h]
SYS_STATUS3 is shown in 图8-77 and described in 表8-49.
Return to the Summary Table.
Status of various system and motor parameters
图8-77. SYS_STATUS3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DC_BUS_CURR
R-0h
DC_BATT_POW
R-0h
表8-49. SYS_STATUS3 Register Field Descriptions
Bit
Field
Type
Reset
Description
DC bus current (/256 to get DC bus current in A)
Battery (input) power (/64 to get battery power in W)
31-16
15-0
DC_BUS_CURR
DC_BATT_POW
R
0h
R
0h
8.8.3 Algo_Control Registers
表 8-50 lists the memory-mapped registers for the Algo_Control registers. All register offset addresses not listed
in 表8-50 should be considered as reserved locations and the register contents should not be modified.
表8-50. ALGO_CONTROL Registers
Offset Acronym
E6h ALGO_CTRL1
Register Name
Section
Algorithm Control Parameters
ALGO_CTRL1 Register (Offset = E6h) [Reset
= 00000000h]
Complex bit access types are encoded to fit into small table cells. 表 8-51 shows the codes that are used for
access types in this section.
表8-51. Algo_Control Access Type Codes
Access Type
Write Type
W
Code
Description
W
Write
Reset or Default Value
-n
Value after reset or the default
value
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8.8.3.1 ALGO_CTRL1 Register (Offset = E6h) [Reset = 00000000h]
ALGO_CTRL1 is shown in 图8-78 and described in 表8-52.
Return to the Summary Table.
Algorithm Control Parameters
图8-78. ALGO_CTRL1 Register
31
30
29
28
27
26
25
24
EEPROM_WRT EEPROM_REA
D
CLR_FLT
CLR_FLT_RET
RY_COUNT
EEPROM_WRITE_ACCESS_KEY
W-0h
W-0h
23
W-0h
22
W-0h
21
W-0h
20
19
11
3
18
10
2
17
16
8
EEPROM_WRITE_ACCESS_KEY
W-0h
RESERVED
W-0h
15
7
14
13
12
9
RESERVED
W-0h
6
5
4
1
0
RESERVED
EXT_WD_STAT
US_SET
W-0h
W-0h
表8-52. ALGO_CTRL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
31
EEPROM_WRT
EEPROM_READ
CLR_FLT
W
0h
Write the configuration to EEPROM
1h = Write to the EEPROM registers from shadow registers
30
29
W
W
W
W
0h
0h
0h
0h
Read the default configuration from EEPROM
1h = Read the EEPROM registers to shadow registers
Clears all faults
1h = Clear all the driver and controller faults
28
CLR_FLT_RETRY_COUN
T
Clears fault retry count
1h = clear the lock fault retry counts
27-20
EEPROM_WRITE_ACCE
SS_KEY
EEPROM write access key; 8-bit key to unlock the EEPROM write
command
19-1
0
RESERVED
W
W
0h
0h
Reserved
EXT_WD_STATUS_SET
Watchdog status to be set by external MCU in I2C watchdog mode
0h = Reset automatically
1h = To set the EXT_WD_STATUS_SET
8.8.4 Device_Control Registers
表 8-53 lists the memory-mapped registers for the Device_Control registers. All register offset addresses not
listed in 表8-53 should be considered as reserved locations and the register contents should not be modified.
表8-53. DEVICE_CONTROL Registers
Offset Acronym
E8h DEVICE_CTRL
Register Name
Section
Device Control Parameters
DEVICE_CTRL Register (Offset = E8h)
[Reset = 00000000h]
Complex bit access types are encoded to fit into small table cells. 表 8-54 shows the codes that are used for
access types in this section.
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表8-54. Device_Control Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
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8.8.4.1 DEVICE_CTRL Register (Offset = E8h) [Reset = 00000000h]
DEVICE_CTRL is shown in 图8-79 and described in 表8-55.
Return to the Summary Table.
Device Control Parameters
图8-79. DEVICE_CTRL Register
31
30
22
14
6
29
21
13
5
28
20
12
4
27
26
18
10
2
25
17
9
24
16
8
RESERVED
W-0h
SPEED_CTRL
W-0h
23
19
SPEED_CTRL
W-0h
15
11
OVERRIDE
W-0h
RESERVED
R-0h
7
3
1
0
RESERVED
R-0h
表8-55. DEVICE_CTRL Register Field Descriptions
Bit
31
Field
Type
Reset
Description
RESERVED
W
0h
Reserved
30-16
SPEED_CTRL
W
0h
Digital speed command (SPEED_CTRL (%) = SPEED_CTRL/32767
* 100%)
15
OVERRIDE
RESERVED
W
R
0h
0h
Speed input select for I2C vs speed pin
0h = SPEED_CMD using Analog/Freq/PWM mode
1h = SPEED_CMD using SPD_CTRL[14:0]
14-0
Reserved
8.8.5 Algorithm_Variables Registers
表8-56 lists the memory-mapped registers for the Algorithm_Variables registers. All register offset addresses not
listed in 表8-56 should be considered as reserved locations and the register contents should not be modified.
表8-56. ALGORITHM_VARIABLES Registers
Offset Acronym
Register Name
Section
40Ch
512h
522h
5CEh
714h
INPUT_DUTY
Input Duty Cycle
INPUT_DUTY Register (Offset = 40Ch)
[Reset = 00000000h]
CURRENT_DUTY
SET_DUTY
Current Duty Cycle
Set Duty Cycle
CURRENT_DUTY Register (Offset = 512h)
[Reset = 00000000h]
SET_DUTY Register (Offset = 522h) [Reset =
00000000h]
MOTOR_SPEED_PU
DC_BUS_POWER_PU
Motor Speed in PU
DC Bus Power in PU
MOTOR_SPEED_PU Register (Offset =
5CEh) [Reset = 00000000h]
DC_BUS_POWER_PU Register (Offset =
714h) [Reset = 00000000h]
Complex bit access types are encoded to fit into small table cells. 表 8-57 shows the codes that are used for
access types in this section.
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表8-57. Algorithm_Variables Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Reset or Default Value
-n
Value after reset or the default
value
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8.8.5.1 INPUT_DUTY Register (Offset = 40Ch) [Reset = 00000000h]
INPUT_DUTY is shown in 图8-80 and described in 表8-58.
Return to the Summary Table.
Input duty cycle
图8-80. INPUT_DUTY Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
INPUT_DUTY
R-0h
表8-58. INPUT_DUTY Register Field Descriptions
Bit
Field
Type
Reset
Description
31-0
INPUT_DUTY
R
0h
32-bit value indicating the duty cycle that the user commands Input
duty cycle (in %) = (Input Duty Cycle / 230) * 100
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8.8.5.2 CURRENT_DUTY Register (Offset = 512h) [Reset = 00000000h]
CURRENT_DUTY is shown in 图8-81 and described in 表8-59.
Return to the Summary Table.
Current duty cycle
图8-81. CURRENT_DUTY Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
CURRENT_DUTY
R-0h
表8-59. CURRENT_DUTY Register Field Descriptions
Bit
Field
Type
Reset
Description
31-0
CURRENT_DUTY
R
0h
32-bit value indicating the duty cycle that is currently being applied.
Current duty cycle (in %) = (Current Duty Cycle / 230) * 100
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8.8.5.3 SET_DUTY Register (Offset = 522h) [Reset = 00000000h]
SET_DUTY is shown in 图8-82 and described in 表8-60.
Return to the Summary Table.
Target duty cycle
图8-82. SET_DUTY Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
SET_DUTY
R-0h
表8-60. SET_DUTY Register Field Descriptions
Bit
Field
Type
Reset
Description
31-0
SET_DUTY
R
0h
32-bit value indicating the duty cycle that the FW wants. Set duty
cycle (in %) = (Set Duty Cycle / 230) * 100
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8.8.5.4 MOTOR_SPEED_PU Register (Offset = 5CEh) [Reset = 00000000h]
MOTOR_SPEED_PU is shown in 图8-83 and described in 表8-61.
Return to the Summary Table.
Motor speed in PU
图8-83. MOTOR_SPEED_PU Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
MOTOR_SPEED_PU
R-0h
表8-61. MOTOR_SPEED_PU Register Field Descriptions
Bit
Field
Type
Reset
Description
31-0
MOTOR_SPEED_PU
R
0h
32-bit value indicating the speed of the motor. Motor speed (in Hz) =
(Motor Speed in PU / 230) * (MAX_SPEED / 16)
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8.8.5.5 DC_BUS_POWER_PU Register (Offset = 714h) [Reset = 00000000h]
DC_BUS_POWER_PU is shown in 图8-84 and described in 表8-62.
Return to the Summary Table.
DC bus power in PU
图8-84. DC_BUS_POWER_PU Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DC_BUS_POWER_PU
R-0h
表8-62. DC_BUS_POWER_PU Register Field Descriptions
Bit
Field
Type
Reset
Description
31-0
DC_BUS_POWER_PU
R
0h
32-bit value indicating the power drawn by the motor. DC Bus Power
(in W) = (DC Bus Power in PU / 230) * (MAX_POWER / 4)
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The MCT8317A device is used in sensorless 3-phase BLDC motor control. The driver provides a high
performance, high-reliability, flexible solution for robotic vacuum, fuel pumps, automotive fans and blowers,
medical CPAP blowers etc., The following section shows a common application of the MCT8317A device.
9.2 Typical Applications
图9-1 shows the typical schematic of MCT8317A.
VVM
+
47 nF
1 µF
0.1 µF
>10 µF
CPH
CPL CP
VM
VIN_AVDD
SPEED/WAKE (PWM/Analog/Freq)
AVDD
CAVDD
1 µF
1 µF
AGND
BRAKE
DIR
DVDD
AGND
CDVDD
EXT_CLK
EXT_WD
Optional
Control
Interface
ALARM
MCT8317A
DACOUT1
DACOUT2
SOX
AVDD or EXT SUPPLY
RFG
RnFAULT
OUTA
OUTB
FG
nFAULT
AVDD or EXT SUPPLY
RSDA RSCL
OUTC
PGND
Optional
Serial
Interface
SDA
I2C
SCL
图9-1. Example Application Schematic
表9-1 lists the recommended values of the external components for MCT8317A.
表9-1. MCT8317A External Components
COMPONENTS
PIN 1
PIN 2
RECOMMENDED
X5R or X7R, 0.1-µF, TI recommends a capacitor
voltage rating at least twice the normal operating
voltage of the device
CVM1
VM
PGND
≥10-µF, TI recommends a capacitor voltage rating at
least twice the normal operating voltage of the device
CVM2
VM
PGND
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表9-1. MCT8317A External Components (continued)
COMPONENTS
PIN 1
PIN 2
RECOMMENDED
CCP
CP
VM
X5R or X7R, 16-V, 1-µF capacitor
X5R or X7R, 47-nF, TI recommends a capacitor
voltage rating at least twice the normal operating
voltage of the pin
CFLY
CPH
CPL
X5R or X7R, 1-µF, ≥6.3-V. In order for AVDD to
accurately regulate output voltage, capacitor should
have effective capacitance between 0.7-µF to 1.3-µF
at 3.3-V across operating temperature.
CAVDD
AVDD
AGND
X5R or X7R, 1-µF, ≥4-V. In order for DVDD to
accurately regulate output voltage, capacitor should
have effective capacitance between 0.6-µF to 1.3-µF
at 1.5-V across operating temperature.
CDVDD
AVDD
AGND
RFG
RnFAULT
RSDA
1.8 to 5-V Supply
1.8 to 5-V Supply
1.8 to 3.3-V Supply
1.8 to 3.3-V Supply
FG
nFAULT
SDA
5.1-kΩ, Pull-up resistor
5.1-kΩ, Pull-up resistor
5.1-kΩ, Pull-up resistor
5.1-kΩ, Pull-up resistor
RSCL
SCL
Recommended application range for MCT8317A is shown in 表9-2.
表9-2. Recommended Application Range
Parameter
Min
Max
Unit
V
Motor voltage
4.5
35
Motor electrical speed
Peak motor phase current
-
-
3000
8
Hz
A
Default EEPROM configuration for MCT8317A is listed in 表 9-3. Default values are chosen for reliable motor
start-up and closed loop operation. Refer to MCT8317A tuning guide which provides step by step procedure to
tune a 3-phase BLDC motor in closed loop, conform to use-case and explore features in the device.
表9-3. Recommended Default Values
Address Name
Address
Recommended Value
0x6EC4C100
0x2EA610E4
0x1221109C
0x0C321200
0x024224B0
0x4CCC03E0
0x000CE944
0x00A00510
0x5DC04C84
0x60F43025
0x7F87A009
0x0548A186
0x3A840000
0x6ADB44A6
0x392DFF80
0x2D720600
0x08000000
0x7FFF0000
0x00000000
ISD_CONFIG
0x00000080
0x00000082
0x00000084
0x00000086
0x00000088
0x0000008A
0x0000008C
0x0000008E
0x00000090
0x00000092
0x00000094
0x0000009A
0x0000009C
0x00000096
0x00000098
0x000000A4
0x000000A6
0x000000A8
0x000000AA
MOTOR_STARTUP1
MOTOR_STARTUP2
CLOSED_LOOP1
CLOSED_LOOP2
CLOSED_LOOP3
CLOSED_LOOP4
CONST_SPEED
CONST_PWR
FAULT_CONFIG1
FAULT_CONFIG2
TRAP_CONFIG1
TRAP_CONFIG2
150_DEG_TWO_PH_PROFILE
150_DEG_THREE_PH_PROFILE
PIN_CONFIG1
PIN_CONFIG2
DEVICE_CONFIG
PERIPH_CONFIG
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表9-3. Recommended Default Values (continued)
GD_CONFIG1
GD_CONFIG2
0x000000AC
0x1C440000
0x000000AE
0x00000000
Once the device EEPROM is programmed with the desired configuration, device can be operated stand-alone
and I2C serial interface is not required anymore. Speed can be commanded using SPEED pin.
Below are the two essential parameters that are required to spin the motor in closed loop.
1. Maximum motor speed.
2. Cycle by cycle (CBC) current limit.
9.2.1 Application curves
9.2.1.1 Motor startup
图9-2 shows the phase current waveforms of various startup methods in MCT8317A such as align, double align,
IPD and slow first cycle.
图9-2. Motor phase current waveforms of all startup methods
9.2.1.2 120o and variable commutation
In 120° commutation scheme, each motor phase is driven for 120° and Hi-Z for 60° within each half electrical
cycle, resulting in six different commutation states for a motor. 图 9-3 shows the phase current and current
waveform FFT in 120° commutation mode. In variable commutation scheme, MCT8317A device switches
dynamically between 120° and 150° trapezoidal commutation depending on motor speed. The device operates
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in 150° mode at lower speeds and moves to 120° mode at higher speeds. 图 9-4 shows the phase current and
current waveform FFT in 150° commutation.
Phase current
FFT
图9-3. Phase current and FFT - 120 ocommutation
Phase current
FFT
图9-4. Phase current and FFT - 150ocommutation
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9.2.1.3 Faster startup time
Startup time is the time taken for the motor to reach the target speed from zero speed. Faster startup time can
be achieved in MCT8317A by tuning motor startup, open loop and closed loop settings. 图9-5 shows FG, phase
current and motor electrical speed waveform. Motor takes 50 ms to reach target speed from zero speed.
FG
Phase current
Speed
图9-5. Phase current, FG and motor speed - Faster startup time
9.2.1.4 Setting the BEMF threshold
The BEMF_THRESHOLD1 and BEMF_THRESHOLD2 values used for commutation instant detection in
MCT8317A can be computed from the motor phase voltage waveforms during coasting. For example, consider
the three-phase voltage waveforms of a BLDC motor while coasting as in 图 9-6. The motor phase voltage
during coasting is the motor back-EMF.
图9-6. Motor phase voltage during coasting
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In 图 9-6, one floating phase voltage interval is denoted by the vertical markers on channel 3. The Vpeak (peak-
peak back-EMF) on channel 3 is 208-mV and Tc (commutation interval) is 2.22-ms as denoted by the horizontal
and vertical markers on channel 3. The digital equivalent counts for Vpeak and Tc are calculated as follows.
In MCT8317A, a 3-V analog input corresponds to 4095 counts(12-bit) and phase voltage is scaled down by 10x
factor before ADC input; therfore, Vpeak of 208-mV corresponds to an ADC input of 20.8mV, which in turn
equals 29 ADC counts. Assuming the PWM switching frequency is 25-kHz, one back-EMF sample is available
every 40-μs. So, in a time interval of 2.22-ms, a total of 55 back-EMF samples are integrated. Therefore, the
BEMF_THRESHOLD1 or BEMF_THRESHOLD2 value calculated is (½) * (29/2) * (55/2) = 199. Hence, in this
example, BEMF_THRESHOLD1 and BEMF_THRESHOLD2 are set to 8h (corresponding to 200 which is the
closest value to 199) for commutation instant detection using back-EMF integration method during fast start-up.
The exact speed at which the Vpeak and Tc values are measured to calculate the BEMF_THRESHOLD1 and
BEMF_THRESHOLD2 values is not critical (as long as there is sufficient resolution in digital counts) since the
product (Vpeak * Tc) is, largely, a constant for a given BLDC motor.
9.2.1.5 Maximum speed
图9-7 shows phase current, phase voltage and FG of a motor that spins at maximum electrical speed of 3 kHz.
Phase current
Phase voltage
FG
图9-7. Phase current, Phase voltage and FG at Maximum speed
9.2.1.6 Faster deceleration
MCT8317A has features to decelerate the motor quickly. 图 9-8 shows phase current and motor electrical speed
waveform when the motor decelerates from 100% duty cycle to 10% duty cycle. Time taken for the motor to
decelerate from 100% duty cycle to 10% duty cycle when fast deceleration is disabled is around 10 seconds. 图
9-9 shows phase current and motor electrical speed waveform when the motor decelerates from 100% duty
cycle to 10% duty cycle. Time taken for the motor to decelerate from 100% duty cycle to 10% duty cycle when
fast deceleration is enabled is around 1.5 seconds.
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备注
Please note that when fast deceleration is enabled and anti-voltage surge (AVS) is disabled, there
might be voltage spikes seen in supply voltage. Enable AVS to protect the power supply from voltage
overshoots during motor deceleration.
Phase current
Speed
图9-8. Phase current and motor speed - Faster deceleration disabled
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Phase current
Speed
图9-9. Phase current and motor speed -Faster deceleration enabled
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10 Power Supply Recommendations
10.1 Bulk Capacitance
Having an appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors, including:
• The highest current required by the motor system
• The capacitance and current capability of the power supply
• The amount of parasitic inductance between the power supply and motor system
• The acceptable voltage ripple
• The type of motor used (brushed DC, brushless DC, stepper)
• The motor braking method
The inductance between the power supply and the motor drive system limits the rate at which current can
change from the power supply. If the local bulk capacitance is too small, the system responds to excessive
current demands or dumps from the motor with a change in VM voltage. When adequate bulk capacitance is
used, the VM voltage remains stable and high current can be quickly supplied.
The data sheet generally provides a recommended value, but system-level testing is required to determine the
appropriate bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
+
Motor Driver
œ
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
图10-1. Example Setup of Motor Drive System With External Power Supply
The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.
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11 Layout
11.1 Layout Guidelines
The bulk capacitor should be placed to minimize the distance of the high-current path through the motor driver
device. The connecting metal trace widths should be as wide as possible, and numerous vias should be used
when connecting PCB layers. These practices minimize parasitic inductance and allow the bulk capacitor to
deliver high current.
Small-value capacitors should be ceramic, and placed closely to device pins.
The high-current device outputs should use wide metal traces.
To reduce noise coupling and EMI interference from large transient currents into small-current signal paths,
grounding should be partitioned between PGND and AGND. TI recommends connecting all non-power stage
circuitry (including the thermal pad) to AGND to reduce parasitic effects and improve power dissipation from the
device. Optionally, GND_BK can be split. Ensure grounds are connected through net-ties or wide resistors to
reduce voltage offsets and maintain gate driver performance.
The device thermal pad should be soldered to the PCB top-layer ground plane. Multiple vias should be used to
connect to a large bottom-layer ground plane. The use of large metal planes and multiple vias helps dissipate
the I2 × RDS(on) heat that is generated in the device.
To improve thermal performance, maximize the ground area that is connected to the thermal pad ground across
all possible layers of the PCB. Using thick copper pours can lower the junction-to-air thermal resistance and
improve thermal dissipation from the die surface.
Separate the SW_BK and FB_BK traces with ground separation to reduce buck switching from coupling as noise
into the buck outer feedback loop. Widen the FB_BK trace as much as possible to allow for faster load switching.
图11-1 shows a layout example for the MCT8317A. Also, for layout example, refer to MCT8317A EVM.
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11.2 Layout Example
图11-1. Recommended Layout Example
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11.3 Thermal Considerations
The MCT8317A has over temperature shutdown (OTS) as previously described. A die temperature in excess of
145°C (minimally) disables the device until the temperature drops to a safe level.
Any tendency of the device to enter over temperature shutdown is an indication of excessive power dissipation,
insufficient heatsinking, or too high an ambient temperature.
11.3.1 Power Dissipation
The power dissipated in the output FET resistance (RDS(on)) dominates power dissipation in MCT8317A.
At start-up and fault conditions, the FET current is much higher than normal operating FET current; remember to
take these peak currents and their duration into consideration.
The total device power dissipation is the power dissipated in each of the three half-bridges added together along
with standby power, LDO and buck regulator losses.
The maximum amount of power that the device can dissipate depends on ambient temperature and heatsinking.
Note that RDS(on) increases with temperature, so as the device heats, the power dissipation increases. Take this
into consideration when sizing the heatsink.
A summary of equations for calculating each loss is shown below in 表11-1.
表11-1. Power Losses for MCT8317A
Loss type
MCT8317A
Pstandby = VM x IVM_TA
Standby power
LDO
PLDO = (VVIN_AVDD-VAVDD) x IAVDD
PCON = 2 x (IRMS(trap))2 x Rds,on(TA)
PSW = IPK(trap) x VPK(trap) x trise/fall x fPWM
Pdiode = IPK(trap) x Vdiode x tdead x fPWM
FET conduction
FET switching
Diode
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12 Device and Documentation Support
12.1 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.2 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.3 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.4 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most-
current data available for the designated device. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
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13.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
MCT8317A0IREER
WQFN
REE
36
3000
330.0
16.4
5.25
7.25
1.45
8.0
16.0
Q1
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
MCT8317A0IREER
Package Type
Package Drawing Pins
REE 36
SPQ
Length (mm) Width (mm)
367.0 367.0
Height (mm)
WQFN
3000
38.0
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MCT8317A
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PACKAGE OUTLINE
REE0036A
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
3
0
0
PLASTIC QUAD FLATPACK - NO LEAD
4.1
3.9
B
A
PIN 1 INDEX AREA
5.1
4.9
C
0.8 MAX
SEATING PLANE
0.08
0.05
0.00
2X 2.8
2.8
2.6
(0.1) TYP
11
18
4X (0.41)
32X 0.4
10
19
2X
3.6
SYMM
3.8
3.6
1
28
0.25
0.15
36X
29
36
PIN 1 ID
0.1
C A B
SYMM
0.5
0.3
0.05
36X
4226725/A 04/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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MCT8317A
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EXAMPLE BOARD LAYOUT
REE0036A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(3.8)
2X (2.8)
(2.7)
29
36
36X (0.6)
32X (0.2)
1
28
32X (0.4)
(4.8)
37
SYMM
(3.7)
2X (3.6)
2X (0.625)
2X (0.975)
10
19
(R0.05) TYP
11
(
0.2) TYP
18
2X (1.1)
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4226725/A 04/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
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MCT8317A
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EXAMPLE STENCIL DESIGN
REE0036A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(3.8)
2X (2.8)
6X (1.19)
36
29
36X (0.6)
1
28
36X (0.2)
6X
(1.05)
32X (0.4)
2X (3.6)
SYMM
(4.8)
2X (1.25)
10
19
(R0.05)
TYP
11
2X (0.7)
18
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
75% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4226725/A 04/2021
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
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3-Feb-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PMCT8317A0IREER
ACTIVE
WQFN
REE
36
5000
TBD
Call TI
Call TI
-40 to 125
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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