MSP430FG6626IPZ [TI]
具有 128KB 闪存、10KB SRAM、16 位 Σ-Δ ADC、双通道 DAC、DMA、2 个运算放大器和 160 段 LCD 的 25MHz MCU | PZ | 100 | -40 to 85;型号: | MSP430FG6626IPZ |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有 128KB 闪存、10KB SRAM、16 位 Σ-Δ ADC、双通道 DAC、DMA、2 个运算放大器和 160 段 LCD 的 25MHz MCU | PZ | 100 | -40 to 85 时钟 放大器 CD 静态存储器 运算放大器 外围集成电路 装置 闪存 |
文件: | 总186页 (文件大小:5140K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MSP430FG6626, MSP430FG6625
MSP430FG6426, MSP430FG6425
SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
MSP430FG662x, MSP430FG642x Mixed-Signal Microcontrollers
•
Enhanced UART with automatic baud-rate
detection
1 Features
•
Low supply voltage range:
3.6 V down to 1.8 V
•
•
IrDA encoder and decoder
Synchronous SPI
•
High-performance integrated signal chain
– Continuous-time sigma-delta 16-bit analog-to-
digital converter (ADC) with internal reference
with 10 external analog inputs, 6 single-ended
and 4 selectable as differential or single-ended
– Dual operational amplifiers
– Quad low-impedance ground switches
– Voltage comparator
Dual 12-bit digital-to-analog converters (DACs)
with synchronization
Integrated LCD driver with contrast control for up
to 160 segments
MSP430FG662x: Full-speed universal serial bus
(USB)
– Integrated USB-PHY
– Integrated 3.3-V and 1.8-V USB power system
– Integrated USB-PLL
– Eight input and eight output endpoints
Ultra-low power consumption
– USCI_B0 and USCI_B1
•
•
I2C
Synchronous SPI
•
•
•
RTC with calibration logic for time offset correction,
operation in LPM 3.5
16-bit RISC architecture, extended memory, up to
20-MHz system clock
Flexible power-management system
– Fully integrated LDO with programmable
regulated core supply voltage
– Supply voltage supervision, monitoring, and
brownout
•
•
•
•
Unified clock system
– FLL control loop for frequency stabilization
– Low-power low-frequency internal clock source
(VLO)
– Low-frequency trimmed internal reference
source (REFO)
•
– 32-kHz crystals (XT1)
– Active mode (AM),
– High-frequency crystals up to 32 MHz (XT2)
Separate voltage supply for backup subsystem
– 32-kHz low-frequency oscillator (XT1)
– RTC
– Backup memory (8 bytes)
Development tools and software (also see Tools
and Software)
– MSP-TS430PZ100AUSB 100-pin target
development board
– MSP430Ware™ code examples
Wake up from standby mode in 3 µs (typical)
Serial onboard programming, no external
programming voltage needed
all system clocks active:
250 µA/MHz at 8 MHz, 3.0 V, flash program
execution (typical)
•
•
– Standby mode (LPM3):
watchdog with crystal, and supply supervisor
operational, full RAM retention, fast wakeup:
3.2 µA at 2.2 V, 3.4 µA at 3.0 V (typical)
– Shutdown RTC mode (LPM3.5):
shutdown mode, active RTC with crystal:
0.9 µA at 3.0 V (typical)
– Shutdown mode (LPM4.5):
0.2 µA at 3.0 V (typical)
Intelligent digital peripherals
•
•
•
•
•
Available in 100-pin LQFP and 113-pin Microstar
Junior™ BGA packages
Device Comparison summarizes the available
family members
– Two 16-bit timers with three capture/compare
registers each
– One 16-bit timer with five capture/compare
registers
– One 16-bit timer with seven capture/compare
registers
– 6-channel internal DMA
– Hardware multiplier supports 32-bit operations
Four universal serial communication interfaces
(USCIs)
2 Applications
•
•
•
•
•
•
Analog sensor systems
Digital sensor systems
Hand-held meters
Medical diagnostic meters
Hand-held industrial testers
Measurement equipment
•
– USCI_A0 and USCI_A1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430FG6626, MSP430FG6625
MSP430FG6426, MSP430FG6425
SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
www.ti.com
3 Description
The Texas Instruments MSP430FG662x and MSP430FG642x microcontrollers (MCUs) are part of the
MSP430TM Metrology and Monitoring portfolio. The architecture and integrated peripherals, combined with five
extensive low-power modes, are optimized to achieve extended battery life in portable and battery-powered
measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant
generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows the
devices to wake up from low-power modes to active mode in less than 5 µs.
The MSP430FG662x MCUs are targeted at small signal-monitoring applications and include a 16-bit sigma-delta
ADC, dual low-power operational amplifiers, dual 12-bit DACs, voltage comparator, four USCIs (two USCI_A
modules and two USCI_B modules), four 16-bit timers, a hardware multiplier, a DMA module, an RTC module,
an LCD driver with integrated contrast control for up to 160 segments, integrated full-speed USB, an auxiliary
supply system, up to 128KB flash, 10KB SRAM and 73 I/O pins in 100‑pin devices and 113‑pin devices.
The MSP430FG642x MCUs are targeted at small-signal monitoring applications and include a 16-bit sigma-delta
ADC, dual low-power operational amplifiers, dual 12-bit DACs, voltage comparator, four USCIs (two USCI_A
modules and two USCI_B modules), four 16-bit timers, a hardware multiplier, a DMA module, an RTC module,
an LCD driver with integrated contrast control for up to 160 segments, an auxiliary supply system, up to 128KB
of flash, 10KB of SRAM, and 73 I/O pins in 100‑pin devices and 113‑pin devices.
Typical applications for these microcontrollers include small signal-monitoring applications such as handheld test
and measurement equipment, field transmitters, and blood glucose meters. These microcontrollers can reduce
overall system cost through high analog integration and enable long battery life by low-power operation.
The MSP430FG662x and MSP430FG642x MCUs are supported by an extensive hardware and software
ecosystem with reference designs and code examples to get your design started quickly. Development kits
include the MSP-TS430PZ100AUSB 100-pin target development board. TI also provides free MSP430Ware™
software, which is available as a component of Code Composer Studio™ IDE desktop and cloud versions within
TI Resource Explorer. The MSP430 MCUs are also supported by extensive online collateral, training, and online
support through the TI E2E™ support forums.
For complete module descriptions, see the MSP430F5xx and MSP430F6xx Family User's Guide.
Device Information
PART NUMBER(1)
MSP430FG6626IPZ
PACKAGE
BODY SIZE(2)
14 mm × 14 mm
7 mm × 7 mm
7 mm × 7 mm
PZ (100)
MSP430FG6626IZCA
nFBGA (113)
MSP430FG6626IZQW(3)
MicroStar Junior™ BGA (113)
(1) For the most current part, package, and ordering information for all available devices, see the
Package Option Addendum in Section 12, or see the TI website at www.ti.com.
(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 12.
(3) All orderable part numbers in the ZQW (MicroStar Junior BGA) package have been changed to a
status of Last Time Buy. Visit the Product life cycle page for details on this status.
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MSP430FG6626, MSP430FG6625
MSP430FG6426, MSP430FG6425
SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
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4 Functional Block Diagrams
Figure 4-1 shows the functional block diagram for the MSP430FG6626 and MSP430FG6625 devices.
PA
PB
PC
PD
XIN XOUT
DVCC DVSS
AVCC AVSS
RST/NMI
VCORE
NR
P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x
P9.x
DP, DM, PUR
XT2IN
8KB
RAM
I/O Ports
P1, P2
2×8 I/Os
Interrupt
Capability
I/O Ports
P3, P4
2×8 I/Os
Interrupt
Capability
I/O Ports
P5, P6
1×7 I/Os
1×8 I/Os
I/O Ports
P7, P8
1×6 I/Os
1×8 I/Os
I/O Ports
P9
1×8 I/Os
USCI0,1
USB
ACLK
SYS
Power
Management
Unified
Clock
System
128KB
64KB
Ax: UART,
IrDA, SPI
Full-Speed
XT2OUT
Watchdog
SMCLK
+2KB RAM
USB Buffer
P2 Port
Mapping
Controller
LDO
SVM, SVS
Brownout
PE
1×8 I/Os
Bx: SPI, I2C
Flash
MCLK
+8B Backup
RAM
PA
1×16 I/Os
PB
1×16 I/Os
PC
1×15 I/Os
PD
1×14 I/Os
CPUXV2
and
DMA
Working
Registers
6 Channel
EEM
(L: 8+2)
CTSD16
Sigma-Delta
ADC
Operational
Amplifiers
OA0, OA1
Reference
TA1 and
TA2
RTC_B
TA0
TB0
DAC12_A
LCD_B
JTAG,
SBW
Interface
1.5 V,
2.0 V,
2.5 V
Timer_A
5 CC
Registers
Timer_B
7 CC
Registers
Comp_B
12 bit
2 channels
voltage out
MPY32
CRC16
2 Timer_A
each with
3 CC
14 inputs
(6 SE ext,
4 SE/diff ext,
4 int)
160
Segments
Quad
Ground
Switches
Battery
Backup
System
Port PJ
Registers
1.16 V
VREFBG
Figure 4-1. Functional Block Diagram – MSP430FG6626, MSP430FG6625
Figure 4-2 shows the functional block diagram for the MSP430FG6426 and MSP430FG6425 devices.
PU.0,
PU.1
PA
PB
PC
PD
XIN XOUT
DVCC DVSS
AVCC AVSS
RST/NMI
VCORE
NR
LDOO LDOI
P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x
P9.x
XT2IN
I/O Ports
P1, P2
2×8 I/Os
Interrupt
Capability
I/O Ports
P3, P4
2×8 I/Os
Interrupt
Capability
I/O Ports
P5, P6
1×7 I/Os
1×8 I/Os
I/O Ports
P7, P8
1×6 I/Os
1×8 I/Os
I/O Ports
P9
1×8 I/Os
USCI0,1
PU Port
LDO
ACLK
SYS
Power
Management
Unified
Clock
System
128KB
64KB
10KB
RAM
Ax: UART,
IrDA, SPI
XT2OUT
Watchdog
SMCLK
P2 Port
Mapping
Controller
LDO
SVM, SVS
Brownout
+8B Backup
RAM
PE
1×8 I/Os
Bx: SPI, I2C
Flash
MCLK
PA
1×16 I/Os
PB
1×16 I/Os
PC
1×15 I/Os
PD
1×14 I/Os
CPUXV2
and
DMA
Working
Registers
6 Channel
EEM
(L: 8+2)
CTSD16
Sigma-Delta
ADC
Reference
Operational
Amplifiers
OA0, OA1
LCD_B
TA1 and
TA2
RTC_B
DAC12_A
TA0
TB0
1.5 V,
2.0 V,
2.5 V
JTAG,
SBW
Interface
160
Segments
12 bit
2 channels
voltage out
Comp_B
MPY32
CRC16
2 Timer_A
each with
3 CC
Timer_A
5 CC
Registers
Timer_B
7 CC
Registers
14 inputs
(6 SE ext,
4 SE/dif ext,
4 int)
Quad
Ground
Switches
Battery
Backup
System
Port PJ
Registers
1.16 V
VREFBG
Figure 4-2. Functional Block Diagram – MSP430FG6426, MSP430FG6425
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MSP430FG6426, MSP430FG6425
SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................2
4 Functional Block Diagrams............................................ 3
5 Revision History.............................................................. 5
6 Device Comparison.........................................................6
6.1 Related Products........................................................ 7
7 Terminal Configuration and Functions..........................8
7.1 Pin Diagrams.............................................................. 8
7.2 Pin Attributes.............................................................11
7.3 Signal Descriptions................................................... 18
7.4 Pin Multiplexing.........................................................25
7.5 Buffer Type................................................................25
7.6 Connection of Unused Pins...................................... 26
8 Specifications................................................................ 27
8.1 Absolute Maximum Ratings ..................................... 27
8.2 ESD Ratings............................................................. 27
8.3 Recommended Operating Conditions.......................27
8.4 Active Mode Supply Current Into VCC Excluding
9.5 Interrupt Vector Addresses....................................... 79
9.6 USB BSL...................................................................80
9.7 UART BSL................................................................ 80
9.8 JTAG Operation........................................................ 81
9.9 Flash Memory........................................................... 81
9.10 RAM........................................................................81
9.11 Backup RAM........................................................... 82
9.12 Peripherals..............................................................82
9.13 Input/Output Diagrams............................................96
9.14 Device Descriptors................................................136
9.15 Memory.................................................................136
9.16 Identification..........................................................152
10 Applications, Implementation, and Layout............. 153
10.1 Device Connection and Layout Fundamentals..... 153
10.2 Peripheral- and Interface-Specific Design
Information................................................................ 157
11 Device and Documentation Support........................168
11.1 Getting Started......................................................168
11.2 Device Nomenclature............................................168
11.3 Tools and Software................................................170
11.4 Documentation Support........................................ 172
11.5 Related Links........................................................ 173
11.6 Support Resources............................................... 173
11.7 Trademarks........................................................... 173
11.8 Electrostatic Discharge Caution............................173
11.9 Export Control Notice............................................173
11.10 Glossary..............................................................174
12 Mechanical, Packaging, and Orderable
External Current.......................................................... 29
8.5 Low-Power Mode Supply Currents (Into VCC
)
Excluding External Current..........................................30
8.6 Low-Power Mode With LCD Supply Currents
(Into VCC) Excluding External Current.........................31
8.7 Thermal Resistance Characteristics ........................ 32
8.8 Timing and Switching Characteristics....................... 32
9 Detailed Description......................................................76
9.1 Overview...................................................................76
9.2 CPU.......................................................................... 76
9.3 Instruction Set...........................................................77
9.4 Operating Modes...................................................... 78
Information.................................................................. 175
12.1 Packaging Information.......................................... 175
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5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from revision A to revision B
Changes from September 27, 2018 to September 11, 2020
Page
•
•
•
•
•
•
Updated the numbering for sections, tables, figures, and cross-references throughout the document..............1
Updated Section 1, Features .............................................................................................................................1
Added nFBGA package (ZCA) information throughout document......................................................................2
Added note about status change for all orderable part numbers in the ZQW package in Device Information .. 2
Updated Section 3, Description ......................................................................................................................... 2
Corrected the signal name and description (changed DVCC to AVCC) on pin 16 (or H1, G2) in Table 7-2,
Signal Descriptions ..........................................................................................................................................18
Changed the MAX value of the IERASE and IMERASE, IBANK parameters in Section 8.8.19.1, Flash Memory ... 75
•
Changes from initial release to revision A
Changes from May 22, 2015 to September 26, 2018
Page
•
•
•
Added Section 6.1, Related Products ................................................................................................................7
Added typical conditions statements at the beginning of Section 8, Specifications .........................................27
Updated notes (1) and (2) and added note (3) in Section 8.8.4.1, Wake-up Times From Low-Power Modes
and Reset ........................................................................................................................................................ 37
Removed duplicate symbol and removed note (5) on Ri(VREFBG), Ri(VeREF+) parameter in Section 8.8.13.4, 12-
Bit DAC, Reference Input Specifications ......................................................................................................... 64
Added "CBPWRMD = 00 or 01" to Test Conditions of the first row of the tEN_CMP parameter; Added second
row for tEN_CMP with Test Conditions of "CBPWRMD = 10" and MAX value of 100 µs in Section 8.8.16.1,
Comparator_B ................................................................................................................................................. 70
Added Section 8.8.18, LDO-PWR (LDO Power System) ................................................................................ 74
Throughout document, changed all instances of "bootstrap loader" to "bootloader"........................................85
Changed decoupling capacitor recommendation from "one 10 µF and one 100 nF" to "one 1 µF and one
100 nF" for consistency with Section 10.1.1 ..................................................................................................157
Changed decoupling capacitor recommendation from "one 10 µF and one 100 nF" to "one 1 µF and one
100 nF" for consistency with Section 10.1.1 ..................................................................................................158
Changed decoupling capacitor recommendation from "one 10 µF and one 100 nF" to "one 1 µF and one
100 nF" for consistency with Section 10.1.1 ..................................................................................................161
Added Section 10.2.5, DAC12 Peripheral ..................................................................................................... 165
Added Section 10.2.6, USB Module .............................................................................................................. 166
Added Section 10.2.7, LDO Module .............................................................................................................. 167
Replaced former section Development Tools Support with Section 11.3, Tools and Software ......................170
Changed format and added content to Section 11.4, Documentation Support ..............................................172
•
•
•
•
•
•
•
•
•
•
•
•
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6 Device Comparison
Table 6-1 summarizes the available family members.
Table 6-1. Device Comparison
USCI_A:
FLASH
(KB)
SRAM
(KB)(3)
USCI_B:
SPI, I2C
CTSD16
(Ch)(6)
DAC12_A
(Ch)
Comp_B
(channels)
DEVICE(1) (2)
MSP430FG6626
MSP430FG6625
MSP430FG6426
MSP430FG6425
Timer_A(4) Timer_B(5) UART, IrDA,
SPI
OA
2
USB
I/Os
73
PACKAGE
100 PZ,
113 ZCA
113 ZQW
10 ext,
5 int
128
64
8 + 2
8 + 2
10
5, 3, 3
5, 3, 3
5, 3, 3
5, 3, 3
7
7
7
7
2
2
2
2
2
2
2
2
2
2
2
2
12
12
12
12
1
1
0
0
100 PZ,
113 ZCA
113 ZQW
10 ext,
5 int
2
73
100 PZ,
113 ZCA
113 ZQW
10 ext,
5 int
128
64
2
73
100 PZ,
113 ZCA
113 ZQW
10 ext,
5 int
10
2
73
(1) For the most current package and ordering information, see the Package Option Addendum in Section 12, or see the TI website at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging.
(3) The additional 2KB of USB SRAM that is listed can be used as general-purpose SRAM when USB is not in use.
(4) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output
generators, respectively.
(5) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM output generators available. For example, a
number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output
generators, respectively.
(6) ADC inputs consist of a mix of single ended and differential. See the pinning for available input pairs and types.
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6.1 Related Products
For information about other devices in this family of products or related products, see the following links.
Products for TI microcontrollers
TI's low-power and high-performance MCUs, with wired and wireless connectivity options, are optimized for a
broad range of applications.
Products for MSP430 ultra-low-power microcontrollers
One platform. One ecosystem. Endless possibilities. Enabling the connected world with innovations in ultra-low-
power microcontrollers with advanced peripherals for precise sensing and measurement.
Companion products for MSP430FG6626
Review products that are frequently purchased or used with this product.
Reference designs for MSP430FG6626
Find reference designs that leverage the best in TI technology to solve your system-level challenges.
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7 Terminal Configuration and Functions
7.1 Pin Diagrams
Figure 7-1 shows the pinout for the MSP430FG6626 and MSP430FG6625 devices in the 100-pin PZ package.
P6.4/CB4/AD0+/OA0O
P6.5/CB5/AD0-/OA0IN0
P6.6/CB6/AD1+/G0SW0
P6.7/CB7/AD1-/G0SW1
P7.4/CB8/AD2+/OA1O
P7.5/CB9/AD2-/OA1IN0
P7.6/CB10/AD3+/G1SW0
P7.7/CB11/AD3-/G1SW1
P5.0/VREFBG/VeREF+
P5.1/A4/DAC0
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P9.7/S0
2
P9.6/S1
3
P9.5/S2
4
P9.4/S3
5
P9.3/S4
6
P9.2/S5
7
P9.1/S6
8
P9.0/S7
9
P8.7/S8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P8.6/UCB1SOMI/UCB1SCL/S9
P8.5/UCB1SIMO/UCB1SDA/S10
DVCC2
P5.6/A5/DAC1
NR
MSP430FG6626
MSP430FG6625
DVSS2
AVSS1
XOUT
XIN
P8.4/UCB1CLK/UCA1STE/S11
P8.3/UCA1RXD/UCA1SOMI/S12
P8.2/UCA1TXD/UCA1SIMO/S13
P8.1/UCB1STE/UCA1CLK/S14
P8.0/TB0CLK/S15
P4.7/TB0OUTH/SVMOUT/S16
P4.6/TB0.6/S17
P4.5/TB0.5/S18
P4.4/TB0.4/S19
P4.3/TB0.3/S20
P4.2/TB0.2/S21
P4.1/TB0.1/S22
AVCC
CPCAP
P2.0/P2MAP0/DAC0
P2.1/P2MAP1/DAC1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4/R03
P2.5/P2MAP5
P2.6/P2MAP6/LCDREF/R13
P2.7/P2MAP7/R23
CAUTION: LCDCAP/R33 must be connected to DVSS if not used.
Figure 7-1. 100-Pin PZ Package (Top View), MSP430FG6626IPZ, MSP430FG6625IPZ
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Figure 7-2 shows the pinout for the MSP430FG6426 and MSP430FG6425 devices in the 100-pin PZ package.
P6.4/CB4/AD0+/OA0O
P6.5/CB5/AD0-/OA0IN0
P6.6/CB6/AD1+/G0SW0
P6.7/CB7/AD1-/G0SW1
P7.4/CB8/AD2+/OA1O
P7.5/CB9/AD2-/OA1IN0
P7.6/CB10/AD3+/G1SW0
P7.7/CB11/AD3-/G1SW1
P5.0/VREFBG/VeREF+
P5.1/A4/DAC0
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P9.7/S0
2
P9.6/S1
3
P9.5/S2
4
P9.4/S3
5
P9.3/S4
6
P9.2/S5
7
P9.1/S6
8
P9.0/S7
9
P8.7/S8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P8.6/UCB1SOMI/UCB1SCL/S9
P8.5/UCB1SIMO/UCB1SDA/S10
DVCC2
P5.6/A5/DAC1
NR
MSP430FG6426
MSP430FG6425
DVSS2
AVSS1
XOUT
XIN
P8.4/UCB1CLK/UCA1STE/S11
P8.3/UCA1RXD/UCA1SOMI/S12
P8.2/UCA1TXD/UCA1SIMO/S13
P8.1/UCB1STE/UCA1CLK/S14
P8.0/TB0CLK/S15
P4.7/TB0OUTH/SVMOUT/S16
P4.6/TB0.6/S17
P4.5/TB0.5/S18
P4.4/TB0.4/S19
P4.3/TB0.3/S20
P4.2/TB0.2/S21
P4.1/TB0.1/S22
AVCC
CPCAP
P2.0/P2MAP0/DAC0
P2.1/P2MAP1/DAC1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4/R03
P2.5/P2MAP5
P2.6/P2MAP6/LCDREF/R13
P2.7/P2MAP7/R23
A. CAUTION: LCDCAP/R33 must be connected to DVSS if not used.
Figure 7-2. 100-Pin PZ Package (Top View), MSP430FG6426IPZ, MSP430FG6425IPZ
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Figure 7-3 shows the pinout for the 113-pin ZCA or ZQW package.
A1
B1
C1
D1
E1
F1
G1
H1
J1
A2
B2
C2
D2
E2
F2
G2
H2
J2
A3
B3
C3
A4
B4
A5
B5
A6
B6
A7
B7
A8
B8
A9
B9
A10
B10
A11
B11
C11
D11
E11
F11
G11
H11
J11
A12
B12
C12
D12
E12
F12
G12
H12
J12
D4
E4
F4
G4
H4
J4
D5
E5
F5
G5
H5
J5
D6
E6
D7
E7
D8
E8
F8
G8
H8
J8
D9
E9
F9
G9
H9
J9
H6
J6
H7
J7
K1
L1
K2
L2
K11
L11
M11
K12
L12
M12
L3
L4
L5
L6
L7
L8
L9
L10
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
NOTE: For terminal assignments, see Section 7.3.
Figure 7-3. 113-Pin ZCA or ZQW Package (Top View), MSP430FG6626IZCA, MSP430FG6625IZCA,
MSP430FG6426IZCA, MSP430FG6425IZCA, MSP430FG6626IZQW, MSP430FG6625IZQW,
MSP430FG6426IZQW, MSP430FG6425IZQW
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7.2 Pin Attributes
Table 7-1 describes the attributes of the pins.
Table 7-1. Pin Attributes
PIN NO.
ZCA, ZQW
POWER
RESET STATE
SIGNAL NAME (1) (2)
SIGNAL TYPE (3) BUFFER TYPE (4)
SOURCE(5)
AFTER BOR (6) (7)
PZ
P6.4
I/O
LVCMOS
Analog
Analog
Analog
LVCMOS
Analog
Analog
Analog
LVCMOS
Analog
Analog
Analog
LVCMOS
Analog
Analog
Analog
LVCMOS
Analog
Analog
Analog
LVCMOS
Analog
Analog
Analog
LVCMOS
Analog
Analog
Analog
LVCMOS
Analog
Analog
Analog
LVCMOS
Analog
Analog
LVCMOS
Analog
Analog
LVCMOS
Analog
Analog
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
N/A
OFF
N/A
N/A
N/A
OFF
N/A
N/A
N/A
OFF
N/A
N/A
N/A
OFF
N/A
N/A
N/A
OFF
N/A
N/A
N/A
OFF
N/A
N/A
N/A
OFF
N/A
N/A
N/A
OFF
N/A
N/A
N/A
OFF
N/A
N/A
OFF
N/A
N/A
OFF
N/A
N/A
CB4
I
1
A1
B2
B1
C3
C2
C1
D4
D2
AD0+
OA0O
P6.5
I
O
I/O
CB5
I
2
3
4
5
6
7
8
AD0-
OA0IN0
P6.6
I
I
I/O
CB6
I
AD1+
G0SW0
P6.7
I
I
I/O
CB7
I
AD1-
G0SW1
P7.4
I
I
I/O
CB8
I
AD2+
OA1O
P7.5
I
O
I/O
CB9
I
AD2-
OA1IN0
P7.6
I
I
I/O
CB10
AD3+
G1SW0
P7.7
I
I
I
I/O
I
CB11
AD3-
G1SW1
P5.0
I
I
I/O
O
I
9
D1
E4
E2
VREFBG
VeREF+
P5.1
I/O
I
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
10
11
A4
DAC0
P5.6
O
I/O
I
A5
DAC1
O
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Table 7-1. Pin Attributes (continued)
PIN NO.
ZCA, ZQW
POWER
RESET STATE
SIGNAL NAME (1) (2)
SIGNAL TYPE (3) BUFFER TYPE (4)
SOURCE(5)
AFTER BOR (6) (7)
PZ
12
13
14
15
16
17
E1
F2
NR
I
Analog
Power
N/A
N/A
N/A
N/A
N/A
N/A
N/A
OFF
N/A
N/A
OFF
N/A
N/A
OFF
N/A
OFF
N/A
OFF
N/A
N/A
OFF
N/A
OFF
N/A
N/A
N/A
OFF
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
OFF
N/A
N/A
OFF
N/A
N/A
OFF
N/A
N/A
OFF
AVSS1
XOUT
XIN
P
N/A
F1
O
Analog
N/A
G1
I
Analog
N/A
H1, G2
G4
AVCC
CPCAP
P2.0
P
Power
N/A
I/O
I/O
I/O
O
Analog
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
N/A
LVCMOS
LVCMOS
Analog
18
19
H2
J1
P2MAP0
DAC0
P2.1
I/O
I/O
O
LVCMOS
LVCMOS
Analog
P2MAP1
DAC1
P2.2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
20
21
H4
J2
P2MAP2
P2.3
P2MAP3
P2.4
22
23
K1
K2
P2MAP4
R03
P2.5
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
P2MAP5
P2.6
P2MAP6
LCDREF
R13
24
L2
I/O
I/O
I/O
I/O
P
Analog
DVCC
DVCC
DVCC
DVCC
N/A
P2.7
LVCMOS
LVCMOS
Analog
25
L3
P2MAP7
R23
26
27
28
L1
M1
M2
DVCC1
DVSS1
VCORE
LCDCAP
R33
Power
P
Power
N/A
P
Power
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
I/O
I/O
O
Analog
29
30
M3
J4
Analog
COM0
P5.3
Analog
I/O
O
LVCMOS
Analog
31
32
L4
COM1
S42
O
Analog
P5.4
I/O
O
LVCMOS
LVCMOS
Analog
M4
COM2
S41
O
P5.5
I/O
I/O
O
LVCMOS
LVCMOS
Analog
33
34
J5
L5
COM3
S40
P1.0
I/O
LVCMOS
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Table 7-1. Pin Attributes (continued)
PIN NO.
POWER
RESET STATE
SIGNAL NAME (1) (2)
SIGNAL TYPE (3) BUFFER TYPE (4)
SOURCE(5)
AFTER BOR (6) (7)
PZ
ZCA, ZQW
TA0CLK
ACLK
S39
I
LVCMOS
LVCMOS
Analog
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
N/A
N/A
N/A
OFF
N/A
N/A
N/A
OFF
N/A
N/A
N/A
OFF
N/A
N/A
OFF
N/A
N/A
OFF
N/A
N/A
OFF
N/A
N/A
OFF
N/A
N/A
OFF
N/A
N/A
N/A
OFF
N/A
N/A
OFF
N/A
N/A
OFF
N/A
N/A
OFF
N/A
N/A
N/A
OFF
O
O
P1.1
I/O
I/O
O
LVCMOS
LVCMOS
LVCMOS
Analog
TA0.0
BSLTX
S38
35
36
M5
J6
O
P1.2
I/O
I/O
I
LVCMOS
LVCMOS
LVCMOS
Analog
TA0.1
BSLRX
S37
O
P1.3
I/O
I/O
O
LVCMOS
LVCMOS
Analog
37
38
39
40
41
H6
M6
L6
TA0.2
S36
P1.4
I/O
I/O
O
LVCMOS
LVCMOS
Analog
TA0.3
S35
P1.5
I/O
I/O
O
LVCMOS
LVCMOS
Analog
TA0.4
S34
P1.6
I/O
I/O
O
LVCMOS
LVCMOS
Analog
J7
TA0.1
S33
P1.7
I/O
I/O
O
LVCMOS
LVCMOS
Analog
M7
TA0.2
S32
P3.0
I/O
I
LVCMOS
LVCMOS
LVCMOS
Analog
TA1CLK
CBOUT
S31
42
L7
O
O
P3.1
I/O
I/O
O
LVCMOS
LVCMOS
Analog
43
44
45
H7
M8
L8
TA1.0
S30
P3.2
I/O
I/O
O
LVCMOS
LVCMOS
Analog
TA1.1
S29
P3.3
I/O
I/O
O
LVCMOS
LVCMOS
Analog
TA1.2
S28
P3.4
I/O
I
LVCMOS
LVCMOS
LVCMOS
Analog
TA2CLK
SMCLK
S27
46
47
J8
O
O
M9
P3.5
I/O
LVCMOS
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www.ti.com
Table 7-1. Pin Attributes (continued)
PIN NO.
ZCA, ZQW
POWER
RESET STATE
SIGNAL NAME (1) (2)
SIGNAL TYPE (3) BUFFER TYPE (4)
SOURCE(5)
AFTER BOR (6) (7)
PZ
TA2.0
I/O
O
LVCMOS
Analog
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
N/A
N/A
OFF
N/A
N/A
OFF
N/A
N/A
OFF
N/A
N/A
OFF
N/A
N/A
OFF
N/A
N/A
OFF
N/A
N/A
OFF
N/A
N/A
OFF
N/A
N/A
OFF
N/A
N/A
OFF
N/A
N/A
N/A
OFF
N/A
N/A
OFF
N/A
N/A
N/A
OFF
N/A
N/A
N/A
S26
P3.6
I/O
I/O
O
LVCMOS
LVCMOS
Analog
48
49
50
51
52
53
54
55
56
L9
M10
J9
TA2.1
S25
P3.7
I/O
I/O
O
LVCMOS
LVCMOS
Analog
TA2.2
S24
P4.0
I/O
I/O
O
LVCMOS
LVCMOS
Analog
TB0.0
S23
P4.1
I/O
I/O
O
LVCMOS
LVCMOS
Analog
M11
L10
M12
L12
L11
K11
TB0.1
S22
P4.2
I/O
I/O
O
LVCMOS
LVCMOS
Analog
TB0.2
S21
P4.3
I/O
I/O
O
LVCMOS
LVCMOS
Analog
TB0.3
S20
P4.4
I/O
I/O
O
LVCMOS
LVCMOS
Analog
TB0.4
S19
P4.5
I/O
I/O
O
LVCMOS
LVCMOS
Analog
TB0.5
S18
P4.6
I/O
I/O
O
LVCMOS
LVCMOS
Analog
TB0.6
S17
P4.7
I/O
I
LVCMOS
LVCMOS
LVCMOS
Analog
TB0OUTH
SVMOUT
S16
57
58
59
K12
J11
J12
O
O
P8.0
I/O
I
LVCMOS
LVCMOS
Analog
TB0CLK
S15
O
P8.1
I/O
I/O
I/O
O
LVCMOS
LVCMOS
LVCMOS
Analog
UCB1STE
UCA1CLK
S14
P8.2
I/O
O
LVCMOS
LVCMOS
LVCMOS
Analog
UCA1TXD
UCA1SIMO
S13
60
H11
I/O
O
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www.ti.com
Table 7-1. Pin Attributes (continued)
PIN NO.
POWER
RESET STATE
SIGNAL NAME (1) (2)
SIGNAL TYPE (3) BUFFER TYPE (4)
SOURCE(5)
AFTER BOR (6) (7)
PZ
ZCA, ZQW
P8.3
I/O
I
LVCMOS
LVCMOS
LVCMOS
Analog
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
N/A
OFF
N/A
N/A
N/A
OFF
N/A
N/A
N/A
N/A
N/A
OFF
N/A
N/A
N/A
OFF
N/A
N/A
N/A
OFF
N/A
OFF
N/A
OFF
N/A
OFF
N/A
OFF
N/A
OFF
N/A
OFF
N/A
OFF
N/A
OFF
N/A
N/A
HiZ
UCA1RXD
UCA1SOMI
S12
61
H12
I/O
O
P8.4
I/O
I/O
I/O
O
LVCMOS
LVCMOS
LVCMOS
Analog
UCB1CLK
UCA1STE
S11
62
G11
63
64
G12
F12
DVSS2
DVCC2
P8.5
P
Power
P
Power
N/A
I/O
I/O
I/O
O
LVCMOS
LVCMOS
LVCMOS
Analog
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
N/A
UCB1SIMO
UCB1SDA
S10
65
66
F11
G9
P8.6
I/O
I/O
I/O
O
LVCMOS
LVCMOS
LVCMOS
Analog
UCB1SOMI
UCB1SCL
S9
P8.7
I/O
O
LVCMOS
Analog
67
68
69
70
71
72
73
74
E12
E11
F9
S8
P9.0
I/O
O
LVCMOS
Analog
S7
P9.1
I/O
O
LVCMOS
Analog
S6
P9.2
I/O
O
LVCMOS
Analog
D12
D11
E9
S5
P9.3
I/O
O
LVCMOS
Analog
S4
P9.4
I/O
O
LVCMOS
Analog
S3
P9.5
I/O
O
LVCMOS
Analog
C12
C11
S2
P9.6
I/O
O
LVCMOS
Analog
S1
P9.7
I/O
O
LVCMOS
Analog
75
76
77
D9
B11, B12
A12
S0
VSSU
PU.0
P
Power
I/O
I/O
HVCMOS
HVCMOS
VBUS
VBUS
DP
N/A
HVCMOS/open-
drain
PUR (FG662x only)
I/O
VBUS
HiZ
78
79
B10
A11
NC (FG642x only)
I/O
I/O
I/O
N/A
N/A
N/A
HiZ
N/A
PU.1
DM
HVCMOS
HVCMOS
VBUS
VBUS
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www.ti.com
Table 7-1. Pin Attributes (continued)
PIN NO.
ZCA, ZQW
POWER
RESET STATE
SIGNAL NAME (1) (2)
SIGNAL TYPE (3) BUFFER TYPE (4)
SOURCE(5)
AFTER BOR (6) (7)
PZ
VBUS
I
I
Power
Analog
Power
N/A
External
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
OFF
N/A
OFF
N/A
N/A
N/A
OFF
N/A
N/A
N/A
N/A
80
A10
A9
LDOI
VUSB
O
O
O
–
81
LDOO
Analog
Power
VBUS
N/A
V18 (FG662x only)
NC (FG642x only)
AVSS2
82
83
84
B9
A8
B8
N/A
N/A
P
Power
N/A
P7.2
I/O
I
LVCMOS
Analog
LVCMOS
Analog
Analog
Power
DVCC
DVCC
DVCC
DVCC
N/A
XT2IN
P7.3
I/O
O
I/O
P
85
B7
XT2OUT
VBAK
86
87
A7
D8
VBAT
N/A
P5.7
I/O
I
LVCMOS
LVCMOS
LVCMOS
Power
DVCC
DVCC
DVCC
N/A
88
D7
DMAE0
RTCCLK
DVCC3
DVSS3
O
P
89
90
A6
A5
P
Power
N/A
No Emu: PD
Emu: PD
TEST
I
LVCMOS
DVCC
91
92
B6
B5
SBWTCK
PJ.0
I
LVCMOS
LVCMOS
DVCC
DVCC
N/A
I/O
OFF
No Emu: OFF
Emu: DRIVE0
TDO
PJ.1
TDI
O
I/O
I
LVCMOS
LVCMOS
LVCMOS
DVCC
DVCC
DVCC
OFF
No Emu: OFF
Emu: PU
93
A4
No Emu: OFF
Emu: OFF
TCLK
PJ.2
TMS
PJ.3
TCK
I
I/O
I
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
DVCC
DVCC
DVCC
DVCC
DVCC
OFF
94
95
E7
D6
No Emu: OFF
Emu: PU
I/O
I
OFF
No Emu: OFF
Emu: PU
RST
NMI
I/O
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Analog
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
PU
N/A
PU
96
97
A3
B4
I
SBWTDIO
P6.0
CB0
A0
I/O
I/O
OFF
N/A
N/A
OFF
N/A
N/A
OFF
N/A
I
I
Analog
P6.1
CB1
A1
I/O
LVCMOS
Analog
98
99
B3
A2
I
I
Analog
P6.2
CB2
I/O
I
LVCMOS
Analog
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Table 7-1. Pin Attributes (continued)
PIN NO.
POWER
RESET STATE
SIGNAL NAME (1) (2)
SIGNAL TYPE (3) BUFFER TYPE (4)
SOURCE(5)
AFTER BOR (6) (7)
PZ
ZCA, ZQW
A2
I
Analog
Analog
LVCMOS
Analog
Analog
Analog
DVCC
DVCC
DVCC
DVCC
DVCC
DVCC
N/A
N/A
OFF
N/A
N/A
N/A
OA0IP0
P6.3
CB3
I
I/O
I
I
I
100
N/A
D5
A3
OA1IP0
E5, E6, E8,
F4, F5, F8,
G5, G8, H5,
H8, H9
Reserved
-
–
–
–
(1) For each multiplexed pin, the signal that is listed first in this table is the reset default.
(2) To determine the pin mux encodings for each pin, refer to Section 9.13.
(3) Signal Types: I = Input, O = Output, I/O = Input or Output, P = power
(4) Buffer Types: LVCMOS, HVCMOS, Analog, or Power (see Table 7-3 for details).
(5) The power source shown in this table is the I/O power source, which may differ from the module power source.
(6) Reset States:
OFF = High-impedance input with pullup or pulldown disabled (if available)
HiZ = High-impedance (neither input nor output)
PD = High-impedance input with pulldown enabled
PU = High-impedance input with pullup enabled
DRIVE0 = Drive output low
DRIVE1 = Drive output high
N/A = Not applicable
(7) For Debug pins: Emu = with emulator attached at reset, No Emu = without emulator attached at reset
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7.3 Signal Descriptions
Table 7-2 describes the signals for all device variants and package options.
Table 7-2. Signal Descriptions
PIN NO.
SIGNAL
NAME
PIN
FUNCTION
DESCRIPTION
TYPE(1)
ZCA,
ZQW
PZ
A0
A1
A2
A3
A4
A5
97
98
99
100
10
11
1
B4
B3
A2
D5
E4
E2
A1
B2
B1
C3
C2
C1
D4
D2
D1
J6
I
I
ADC analog single ended input A0
ADC analog single ended input A1
I
ADC analog single ended input A2
I
ADC analog single ended input A3
I
ADC analog single ended input A4
I
ADC analog single ended input A5
AD0+
AD0-
I
ADC positive analog differential input AD0+
ADC negative analog differential input AD0-
ADC positive analog differential input AD1+
ADC negative analog differential input AD1-
ADC positive analog differential input AD2+
ADC negative analog differential input AD2-
ADC positive analog differential input AD3+
ADC negative analog differential input AD3-
Input for an external reference voltage to the ADC and DAC
BSL receive input
ADC
2
I
AD1+
AD1-
3
I
4
I
AD2+
AD2-
5
I
6
I
AD3+
AD3-
7
I
8
I
VeREF+
BSLRX
BSLTX
9
I
36
35
I
BSL
M5
O
BSL transmit output
Capacitor for backup subsystem. Do not load this pin externally. For
capacitor values, see CBAK in Section 8.3.
VBAK
VBAT
86
87
A7
D8
I/O
P
Backup
Backup or secondary supply voltage. If backup voltage is not supplied,
connect to DVCC externally.
Charge Pump CPCAP
ACLK
17
34
88
46
15
14
84
85
97
98
99
100
1
G4
L5
I/O
O
O
O
I
Capacitor for op amp and CTSD16 rail-to-rail charge pump
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
RTCCLK output
RTCCLK
D7
J8
SMCLK
SMCLK output
Clock
XIN
G1
F1
B8
B7
B4
B3
A2
D5
A1
B2
B1
C3
C2
C1
D4
D2
L7
Input terminal for crystal oscillator XT1
Output terminal of crystal oscillator XT1
Input terminal for crystal oscillator XT2
Output terminal of crystal oscillator XT2
Comparator_B input CB0
XOUT
XT2IN
XT2OUT
CB0
O
I
O
I
CB1
I
Comparator_B input CB1
CB2
I
Comparator_B input CB2
CB3
I
Comparator_B input CB3
CB4
I
Comparator_B input CB4
CB5
2
I
Comparator_B input CB5
Comparator
CB6
3
I
Comparator_B input CB6
CB7
4
I
Comparator_B input CB7
CB8
5
I
Comparator_B input CB8
CB9
6
I
Comparator_B input CB9
CB10
CB11
CBOUT
7
I
Comparator_B input CB10
8
I
Comparator_B input CB11
42
O
Comparator_B output
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FUNCTION
SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
Table 7-2. Signal Descriptions (continued)
PIN NO.
SIGNAL
NAME
PIN
DESCRIPTION
TYPE(1)
ZCA,
ZQW
PZ
10
18
E4
H2
DAC0
O
O
DAC output channel 0
DAC output channel 1
DAC
DMA
11
19
E2
J1
DAC1
DMAE0
SBWTCK
TCK
88
91
95
93
93
92
91
94
96
34
35
36
37
38
39
40
41
D7
B6
D6
A4
A4
B5
B6
E7
A3
L5
I
DMA external trigger input
Spy-Bi-Wire input clock
Test clock
I
I
TCLK
TDI
I
Test clock input
I
Test data input
Debug
TDO
O
Test data output
TEST
TMS
I
Test mode pin; selects digital I/O on JTAG pins
Test mode select
I
SBWTDIO
P1.0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Spy-Bi-Wire data input/output
General-purpose digital I/O with port interrupt
General-purpose digital I/O with port interrupt
General-purpose digital I/O with port interrupt
General-purpose digital I/O with port interrupt
General-purpose digital I/O with port interrupt
General-purpose digital I/O with port interrupt
General-purpose digital I/O with port interrupt
General-purpose digital I/O with port interrupt
P1.1
M5
J6
P1.2
P1.3
H6
M6
L6
P1.4
P1.5
P1.6
J7
P1.7
M7
General-purpose digital I/O with port interrupt and mappable secondary
function
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
18
19
20
21
22
23
24
25
H2
J1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O with port interrupt and mappable secondary
function
General-purpose digital I/O with port interrupt and mappable secondary
function
H4
J2
General-purpose digital I/O with port interrupt and mappable secondary
function
GPIO
General-purpose digital I/O with port interrupt and mappable secondary
function
K1
K2
L2
L3
General-purpose digital I/O with port interrupt and mappable secondary
function
General-purpose digital I/O with port interrupt and mappable secondary
function
General-purpose digital I/O with port interrupt and mappable secondary
function
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
42
43
44
45
46
47
48
49
50
L7
H7
M8
L8
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O with port interrupt
General-purpose digital I/O with port interrupt
General-purpose digital I/O with port interrupt
General-purpose digital I/O with port interrupt
General-purpose digital I/O with port interrupt
General-purpose digital I/O with port interrupt
General-purpose digital I/O with port interrupt
General-purpose digital I/O with port interrupt
General-purpose digital I/O with port interrupt
J8
M9
L9
M10
J9
GPIO
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Table 7-2. Signal Descriptions (continued)
PIN NO.
SIGNAL
NAME
PIN
FUNCTION
DESCRIPTION
TYPE(1)
ZCA,
PZ
ZQW
M11
L10
M12
L12
L11
K11
K12
D1
P4.1
51
52
53
54
55
56
57
9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
General-purpose digital I/O with port interrupt
General-purpose digital I/O with port interrupt
General-purpose digital I/O with port interrupt
General-purpose digital I/O with port interrupt
General-purpose digital I/O with port interrupt
General-purpose digital I/O with port interrupt
General-purpose digital I/O with port interrupt
General-purpose digital I/O
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
P5.0
P5.1
P5.3
P5.4
P5.5
P5.6
P5.7
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7
P8.0
P8.1
P8.2
P8.3
P8.4
P8.5
P8.6
P8.7
P9.0
P9.1
P9.2
P9.3
P9.4
P9.5
P9.6
P9.7
10
31
32
33
11
88
97
98
99
100
1
E4
General-purpose digital I/O
L4
General-purpose digital I/O
M4
J5
General-purpose digital I/O
General-purpose digital I/O
E2
General-purpose digital I/O
D7
General-purpose digital I/O
B4
General-purpose digital I/O
B3
General-purpose digital I/O
A2
General-purpose digital I/O
D5
General-purpose digital I/O
A1
General-purpose digital I/O
2
B2
General-purpose digital I/O
3
B1
General-purpose digital I/O
4
C3
General-purpose digital I/O
84
85
5
B8
General-purpose digital I/O
B7
General-purpose digital I/O
C2
General-purpose digital I/O
6
C1
General-purpose digital I/O
7
D4
General-purpose digital I/O
8
D2
General-purpose digital I/O
58
59
60
61
62
65
66
67
68
69
70
71
72
73
74
75
J11
J12
H11
H12
G11
F11
G9
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
E12
E11
F9
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
D12
D11
E9
General-purpose digital I/O
General-purpose digital I/O
GPIO
General-purpose digital I/O
C12
C11
D9
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
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FUNCTION
SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
Table 7-2. Signal Descriptions (continued)
PIN NO.
SIGNAL
NAME
PIN
DESCRIPTION
TYPE(1)
ZCA,
ZQW
PZ
PJ.0
92
93
94
95
B5
A4
E7
D6
I/O
I/O
I/O
I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
General-purpose digital I/O
PJ.1
PJ.2
PJ.3
General-purpose digital I/O - controlled by USB control register (FG662x
devices) or PU control register
PU.0
77
79
3
A12
A11
B1
I/O
General-purpose digital I/O - controlled by USB control register (FG662x
devices) or PU control register
PU.1
I/O
Analog switch to AVSS. Internally connected to ADC positive analog
differential input AD1+.
G0SW0
G0SW1
G1SW0
G1SW1
I
I
I
I
Analog switch to AVSS. Internally connected to ADC negative analog
differential input AD1-.
4
C3
Ground Switch
Analog switch to AVSS. Internally connected to ADC positive analog
differential input AD3+.
7
D4
Analog switch to AVSS. Internally connected to ADC negative analog
differential input AD3-.
8
D2
UCB1SCL
UCB1SDA
COM0
66
65
30
31
32
33
G9
F11
J4
I/O
I/O
O
USCI_B1 I2C clock
I2C
USCI_B1 I2C data
LCD common output COM0 for LCD backplane
LCD common output COM1 for LCD backplane
LCD common output COM2 for LCD backplane
LCD common output COM3 for LCD backplane
COM1
L4
O
COM2
M4
J5
O
COM3
I/O
LCD capacitor connection
CAUTION: LCDCAP/R33 must be connected to DVSS if not used.
LCDCAP
29
M3
I/O
LCDREF
R03
24
22
24
25
L2
K1
L2
L3
I
External reference voltage input for regulated LCD voltage
Input/output port of lowest analog LCD voltage (V5)
I/O
I/O
I/O
R13
Input/output port of third most positive analog LCD voltage (V3 or V4)
Input/output port of second most positive analog LCD voltage (V2)
LCD
R23
Input/output port of most positive analog LCD voltage (V1)
CAUTION: LCDCAP/R33 must be connected to DVSS if not used.
R33
29
M3
I/O
S0
75
74
73
72
71
70
69
68
67
66
65
62
61
60
59
58
D9
C11
C12
E9
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
LCD segment output S0
LCD segment output S1
LCD segment output S2
LCD segment output S3
LCD segment output S4
LCD segment output S5
LCD segment output S6
LCD segment output S7
LCD segment output S8
LCD segment output S9
LCD segment output S10
LCD segment output S11
LCD segment output S12
LCD segment output S13
LCD segment output S14
LCD segment output S15
S1
S2
S3
S4
D11
D12
F9
S5
S6
S7
E11
E12
G9
S8
S9
S10
S11
S12
S13
S14
S15
F11
G11
H12
H11
J12
J11
LCD
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Table 7-2. Signal Descriptions (continued)
PIN NO.
SIGNAL
NAME
PIN
FUNCTION
DESCRIPTION
TYPE(1)
ZCA,
PZ
ZQW
K12
K11
L11
L12
M12
L10
M11
J9
S16
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
LCD segment output S16
LCD segment output S17
LCD segment output S18
LCD segment output S19
LCD segment output S20
LCD segment output S21
LCD segment output S22
LCD segment output S23
LCD segment output S24
LCD segment output S25
LCD segment output S26
LCD segment output S27
LCD segment output S28
LCD segment output S29
LCD segment output S30
LCD segment output S31
LCD segment output S32
LCD segment output S33
LCD segment output S34
LCD segment output S35
LCD segment output S36
LCD segment output S37
LCD segment output S38
LCD segment output S39
LCD segment output S40
LCD segment output S41
LCD segment output S42
S17
S18
S19
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
S37
S38
S39
S40
S41
S42
M10
L9
M9
J8
L8
M8
H7
L7
M7
J7
L6
M6
H6
J6
M5
L5
J5
M4
L4
Default mapping: USCI_B0 SPI slave transmit enable; USCI_A0 clock
input/output
P2MAP0
18
H2
I/O
Mapping Options: See Table 9-8
Default mapping: USCI_B0 SPI slave in/master out; USCI_B0 I2C data
Mapping Options: See Table 9-8
P2MAP1
P2MAP2
19
20
J1
I/O
I/O
Default mapping: USCI_B0 SPI slave out/master in; USCI_B0 I2C clock
Mapping Options: See Table 9-8
H4
Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave
transmit enable
Mapping Options: See Table 9-8
P2MAP3
P2MAP4
P2MAP5
21
22
23
J2
K1
K2
I/O
I/O
I/O
Mappable
Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in/
master out
Mapping Options: See Table 9-8
Default mapping: USCI_A0 UART receive data; USCI_A0 slave out/
master in
Mapping Options: See Table 9-8
Default mapping: no secondary function
Mapping Options: See Table 9-8
P2MAP6
P2MAP7
24
25
L2
L3
I/O
I/O
Default mapping: no secondary function
Mapping Options: See Table 9-8
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FUNCTION
SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
Table 7-2. Signal Descriptions (continued)
PIN NO.
SIGNAL
NAME
PIN
DESCRIPTION
TYPE(1)
ZCA,
ZQW
PZ
12
6
Noise
Reduction
NR
E1
C1
I
I
Noise reduction. Connect pin to analog ground.
OA1 negative input internally connected to ADC negative analog
differential input AD2-
OA1IN0
OA0 negative input internally connected to ADC negative analog
differential input AD0-
OA0IN0
OA0IP0
OA0O
2
99
1
B2
A2
A1
D5
C2
I
I
OA0 positive input internally connected to ADC analog input A2
Op Amp
OA0 output internally connected to ADC positive analog differential input
AD0+
O
I
OA1IP0
OA1O
100
5
OA1 positive input internally connected to ADC analog input A3
OA1 output internally connected to ADC positive analog differential input
AD2+
O
AVSS1
AVSS2
AVCC
13
83
16
26
64
89
27
63
90
80
81
F2
A8
P
P
P
P
P
P
P
P
P
I
Analog ground supply
Analog ground supply
H1, G2
L1
Analog power supply
DVCC1
DVCC2
DVCC3
DVSS1
DVSS2
DVSS3
LDOI
Digital power supply
F12
A6
Digital power supply
Digital power supply
Power
M1
Digital ground supply
G12
A5
Digital ground supply
Digital ground supply
A10
A9
LDO input (not available on FG662x devices)
LDO output (not available on FG662x devices)
LDOO
O
Regulated core power supply (internal use only, no external current
loading)
VCORE(2)
VREFBG
NC
28
9
M2
D1
O
O
REF
Output of reference voltage to the ADC and DAC
Not connected (not available on FG662x devices)
78
82
B10
B9
I/O
E5, E6,
E8, F4,
F5, F8,
G5, G8,
H5, H8,
H9
Reserved
Reserved. Internally connected to DVSS. TI recommends external
connection to ground (DVSS).
Reserved
–
–
UCA1CLK
UCA1SIMO
UCA1SOMI
UCA1STE
UCB1CLK
UCB1SIMO
UCB1SOMI
UCB1STE
NMI
59
60
61
62
62
65
66
59
96
96
57
35
36
J12
H11
H12
G11
G11
F11
G9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
USCI_A1 clock input/output
USCI_A1 SPI slave in/master out
USCI_A1 SPI slave out/master in
USCI_A1 SPI slave transmit enable
USCI_B1 clock input/output
SPI
USCI_B1 SPI slave in/master out
USCI_B1 SPI slave out/master in
USCI_B1 SPI slave transmit enable
Nonmaskable interrupt input
J12
A3
System
RST
A3
I/O
O
Reset input (active low)(3)
SVMOUT
TA0.0
K12
M5
SVM output
I/O
I/O
Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output
Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output
Timer_A
TA0.1
J6
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Table 7-2. Signal Descriptions (continued)
PIN NO.
SIGNAL
NAME
PIN
FUNCTION
DESCRIPTION
TYPE(1)
ZCA,
PZ
ZQW
J7
40
37
41
38
39
34
43
44
45
42
47
48
49
46
50
51
52
53
54
55
56
58
57
59
61
60
79
77
I/O
I/O
I/O
I/O
I/O
I
Timer TA0 CCR1 capture: CCI1B input, compare: Out1 output
Timer TA0 CCR2 capture: CCI2A input, compare: Out2 output
Timer TA0 CCR2 capture: CCI2B input, compare: Out2 output
Timer TA0 CCR3 capture: CCI3A input compare: Out3 output
Timer TA0 CCR4 capture: CCI4A input, compare: Out4 output
Timer TA0 clock signal TACLK input
H6
TA0.2
M7
M6
L6
TA0.3
TA0.4
TA0CLK
TA1.0
L5
H7
I/O
I/O
I/O
I
Timer TA1 capture CCR0: CCI0A input, compare: Out0 output
Timer TA1 capture CCR1: CCI1A input, compare: Out1 output
Timer TA1 capture CCR2: CCI2A input, compare: Out2 output
Timer TA1 clock input
TA1.1
M8
L8
TA1.2
TA1CLK
TA2.0
L7
M9
L9
I/O
I/O
I/O
I
Timer TA2 capture CCR0: CCI0A input, compare: Out0 output
Timer TA2 capture CCR1: CCI1A input, compare: Out1 output
Timer TA2 capture CCR2: CCI2A input, compare: Out2 output
Timer TA2 clock input
TA2.1
TA2.2
M10
J8
TA2CLK
TB0.0
J9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
Timer TB0 capture CCR0: CCI0A input, compare: Out0 output
Timer TB0 capture CCR1: CCI1A input, compare: Out1 output
Timer TB0 capture CCR2: CCI2A input, compare: Out2 output
Timer TB0 capture CCR3: CCI3A input, compare: Out3 output
Timer TB0 capture CCR4: CCI4A input, compare: Out4 output
Timer TB0 capture CCR5: CCI5A input, compare: Out5 output
Timer TB0 capture CCR6: CCI6A input, compare: Out6 output
Timer TB0 clock input
TB0.1
M11
L10
M12
L12
L11
K11
J11
K12
J12
H12
H11
A11
A12
TB0.2
TB0.3
Timer_B
TB0.4
TB0.5
TB0.6
TB0CLK
TB0OUTH
UCA1CLK
UCA1RXD
UCA1TXD
DM
I
Timer TB0: switch all PWM outputs to high impedance
USCI_A1 clock input/output
I/O
I
UART
USCI_A1 UART receive data
O
USCI_A1 UART transmit data
I/O
I/O
USB data terminal DM (not available on FG6426 and FG6425 devices)
USB data terminal DP (not available on FG6426 and FG6425 devices)
DP
USB pullup resistor pin (open drain). The voltage level at the PUR pin is
used to invoke the default USB BSL.
Recommended 1-MΩ resistor to ground. See Section 9.6 for more
information.
PUR
78
B10
I/O
Not available on FG6426 and FG6425 devices.
USB
(FG662x only)
USB regulated power (internal use only, no external current loading) (not
available on FG6426 and FG6425 devices)
V18
82
80
B9
O
I
USB LDO input (connect to USB power source) (not available on FG6426
and FG6425 devices)
VBUS
A10
B11
B12
VSSU
VUSB
76
81
P
USB PHY ground supply
A9
O
USB LDO output (not available on FG6426 and FG6425 devices)
(1) I = input, O = output, I/O = input or output, P = power
(2) VCORE is for internal use only. No external current loading is possible. VCORE must be connected to the recommended capacitor
value, CVCORE
(3) When this pin is configured as reset, the internal pullup resistor is enabled by default.
.
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7.4 Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for example, if the
device is in test mode). For details of the settings for each pin and schematics of the multiplexed ports, see
Section 9.13.
7.5 Buffer Type
Table 7-3 describes the buffer types that are referenced in Table 7-1.
Table 7-3. Buffer Type
NOMINAL
OUTPUT DRIVE
STRENGTH
(mA)
BUFFER TYPE
(STANDARD)
NOMINAL
VOLTAGE
PU OR PD
STRENGTH
(µA)
OTHER
CHARACTERISTICS
HYSTERESIS
PU OR PD
N/A
See analog modules in
Section 8, Specifications for
details
Analog(2)
HVCMOS
3.0 V
5.0 V
N
Y
N/A
N/A
N/A
See Section
8.8.5.7, Typical
Characteristics –
Outputs
N/A
See Section
8.8.5.7, Typical
Characteristics –
Outputs
See Section
8.8.5, General-
Purpose I/Os
LVCMOS
3.0 V
Y(1)
Programmable
SVS enables hysteresis on
DVCC
Power (DVCC)(3)
Power (AVCC)(3)
3.0 V
3.0 V
0 V
N
N
N
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Power (DVSS
and AVSS)(3)
(1) Only for input pins
(2) This is a switch, not a buffer.
(3) This is supply input, not a buffer.
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7.6 Connection of Unused Pins
Table 7-4 lists the correct termination of all unused pins.
Table 7-4. Connection of Unused Pins
(1)PIN
POTENTIAL
DVCC
COMMENT
AVCC
AVSS
DVSS
Open
DVSS
DVSS
Open
Open
CPCAP
LCDCAP
LDOI
For devices where the charge pump is not used (no rail-to-rail OA and no rail-to-rail CTSD16).
For devices with LDO-PWR module when not being used in the application.
For devices with LDO-PWR module when not being used in the application.
LDOO
NC
PJ.0/TDO
PJ.1/TDI
PJ.2/TMS
PJ.3/TCK
The JTAG pins are shared with general-purpose I/O function (PJ.x). If not being used, these must
be switched to port function, output direction (PJDIR.n = 1). When used as JTAG pins, these pins
must remain open.
Open
PU.0/DP
PU.1/DM
Open
DVSS
Open
For USB devices only when USB module is not being used in the application
For USB devices only when USB module is not being used in the application
PUR(3)
Switched to port function, output direction (PxDIR.n = 1). Px.y represents port x and bit y of port x
(for example, P1.0, P1.1, P2.2, PJ.0, PJ.1)
Px.y
RST/NMI
Reserved
TEST
DVCC or VCC
DVSS
47-kΩ pullup or internal pullup selected with 10-nF (2.2 nF) pulldown(2)
Open
This pin always has an internal pulldown enabled.
V18
Open
For USB devices only when USB module is not being used in the application
For devices where no separate battery backup supply is used in the system. Set bit BAKDIS = 1.
For devices where no separate battery backup supply is used in the system. Set bit BAKDIS = 1.
For USB devices only when USB module is not being used in the application
For USB devices only when USB module is not being used in the application
VBAK
Open
VBAT
DVCC
VBUS, VSSU
VUSB
DVSS
Open
For dedicated XIN pins only. XIN pins with shared GPIO functions must be programmed to GPIO
and follow Px.y recommendations.
XIN
DVSS
Open
DVSS
Open
For dedicated XOUT pins only. XOUT pins with shared GPIO functions must be programmed to
GPIO and follow Px.y recommendations.
XOUT
XT2IN
XT2OUT
For dedicated XT2IN pins only. XT2IN pins with shared GPIO functions must be programmed to
GPIO and follow Px.y recommendations.
For dedicated XT2OUT pins only. XT2OUT pins with shared GPIO functions must be programmed
to GPIO and follow Px.y recommendations.
(1) Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.y unused pin connection
guidelines.
(2) The pulldown capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire
JTAG mode with TI tools such as FET interfaces or GANG programmers.
(3) The default USB BSL evaluates the state of the PUR pin after a BOR reset. If it is pulled high externally, then the BSL is invoked.
Therefore, unless invoking the BSL, it is important to keep PUR pulled low after a BOR reset, even if BSL or USB is never used. TI
recommends a 1-MΩ resistor to ground.
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8 Specifications
All graphs in this section are for typical conditions, unless otherwise noted.
Typical (TYP) values are specified at VCC = 3.3 V and TA = 25°C, unless otherwise noted.
8.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
4.1
UNIT
V
Voltage applied at VCC to VSS
–0.3
–0.3
Voltage applied to any pin (excluding VCORE, VBUS, V18, LDOI) (2)
VCC + 0.3
±2
V
Diode current at any device pin
mA
°C
(3)
Storage temperature, Tstg
–55
150
Maximum junction temperature, TJ
95
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
8.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD) Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as
±250 V may actually have higher performance.
8.3 Recommended Operating Conditions
Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MIN
1.8
2.0
2.2
2.4
1.8
2.0
2.2
2.4
2.2
2.4
NOM
MAX UNIT
PMMCOREV = 0
3.6
Supply voltage during program execution and flash
PMMCOREV = 0, 1
PMMCOREV = 0, 1, 2
PMMCOREV = 0, 1, 2, 3
PMMCOREV = 0
3.6
V
3.6
VCC
programming (AVCC = DVCC1 = DVCC2 = DVCC3 =
(1) (2) (3)
DVCC = VCC
)
3.6
3.6
3.6
PMMCOREV = 0, 1
PMMCOREV = 0, 1, 2
PMMCOREV = 0, 1, 2, 3
PMMCOREV = 2
Supply voltage during USB operation, USB PLL disabled
(USB_EN = 1, UPLLEN = 0)
3.6
V
3.6
(2)
VCC,USB
3.6
3.6
V
Supply voltage during USB operation, USB PLL enabled
(4) (USB_EN = 1, UPLLEN = 1)
PMMCOREV = 2, 3
VSS
Supply voltage (AVSS1 = AVSS2 = AVSS3 = DVSS1 = DVSS2 = DVSS3 = VSS
)
0
TA = 0°C to 85°C
TA = –40°C to 85°C
TA = –40°C to 85°C
I version
1.55
1.70
1.20
–40
–40
1
3.6
V
VBAT,RTC
Backup-supply voltage with RTC operational
3.6
VBAT,MEM
TA
Backup-supply voltage with backup memory retained
Operating free-air temperature
3.6
85
85
10
V
°C
°C
nF
TJ
Operating junction temperature
I version
CBAK
Capacitance at pin VBAK
4.7
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8.3 Recommended Operating Conditions (continued)
Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MIN
NOM
MAX UNIT
CVCORE
CDVCC
CVCORE
Capacitor at VCORE(5)
470
nF
/
Capacitor ratio of DVCC to VCORE
10
0
PMMCOREV = 0,
1.8 V ≤ VCC ≤ 3.6 V
(default condition)
8.0
PMMCOREV = 1,
2 V ≤ VCC ≤ 3.6 V
Processor frequency (maximum MCLK frequency) (6) (7)
(see Figure 8-1)
0
0
12.0
MHz
fSYSTEM
PMMCOREV = 2,
2.2 V ≤ VCC ≤ 3.6 V
16.0
20.0
PMMCOREV = 3,
2.4 V ≤ VCC ≤ 3.6 V
0
fSYSTEM_USB Minimum processor frequency for USB operation
USB_wait Wait state cycles during USB operation
1.5
MHz
16
cycles
(1) TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
(2) Some modules may have reduced recommended ranges of operation.
(3) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the threshold parameters in Section
8.8.6.2 for the exact values and further details.
(4) USB operation with USB PLL enabled requires PMMCOREV ≥ 2 for proper operation.
(5) A capacitor tolerance of ±20% is required.
(6) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the
specified maximum frequency.
(7) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
25
20
3
16
2, 3
2
12
8
1, 2
1, 2, 3
1
0
0, 1
0, 1, 2
0, 1, 2, 3
0
1.8
2.0
2.2
2.4
3.6
Supply Voltage - V
NOTE: The numbers within the fields denote the supported PMMCOREVx settings.
Figure 8-1. Frequency vs Supply Voltage
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8.4 Active Mode Supply Current Into VCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted)(1) (2) (3)
FREQUENCY (fDCO = fMCLK = fSMCLK
8 MHz 12 MHz
TYP MAX
)
EXECUTION
MEMORY
PARAMETER
VCC
PMMCOREV
1 MHz
20 MHz
UNIT
TYP
MAX
TYP
MAX
TYP
MAX
0
1
2
3
0
1
2
3
0.31
0.35
0.37
0.4
0.36
2.0
2.3
2.5
2.7
1.1
1.3
1.5
1.6
2.4
3.4
3.8
4.0
4.0
IAM, Flash
Flash
RAM
3 V
mA
6.6
0.2
0.23
1.2
0.22
0.24
0.26
1.9
2.2
2.4
2.1
IAM, RAM
3 V
mA
3.9
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external
load capacitance are chosen to closely match the required 12.5 pF.
(3) Characterized with program executing typical data processing. FG6626 and FG6625 USB disabled (VUSBEN = 0, SLDOEN = 0).
FG6426 and FG6425 LDO disabled (LDOEN = 0).
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF = SMCLKOFF = 0.
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8.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
TEMPERATURE (TA)
PARAMETER
VCC
PMMCOREV
–40°C
TYP MAX
72
25°C
60°C
TYP MAX
81
85°C
UNIT
TYP MAX
TYP MAX
2.2 V
3 V
0
3
0
3
0
1
2
0
1
2
3
0
1
2
3
0
1
2
3
77
92
87
105
9.9
11
87
104
12
98
117
17
ILPM0,1MHz Low-power mode 0(3) (9)
µA
µA
86
97
2.2 V
3 V
6.9
7.5
8.5
3.2
3.6
4.0
3.4
3.8
4.2
4.2
1.5
1.6
1.8
1.8
0.9
1.0
1.1
1.1
8.5
ILPM2
Low-power mode 2(4) (9)
7.9
9.7
14
20
2.8
3.7
4.2
7.6
8.2
8.8
7.9
8.5
9.0
9.1
5.8
6.1
6.5
6.5
5.4
5.6
5.9
6.0
13.5
2.2 V
3.1
4.6
3.5
5.1
Low-power mode 3,
crystal mode(5) (9)
ILPM3,XT1LF
3.0
4.0
4.4
14
µA
3.3
4.9
3 V
3.7
5.3
3.7
4.8
2.1
5.3
16
1.2
2.4
12.5
Low-power mode 3,
VLO mode, Watchdog
enabled(6) (9)
1.4
2.6
ILPM3,
3 V
3 V
µA
µA
VLO,WDT
1.6
2.8
1.6
2.6
1.8
2.9
14
0.6
1.9
11.5
0.7
2.0
ILPM4
Low-power mode 4(7) (9)
0.8
2.2
0.8
2.1
2.2
13
Low-power mode 3.5
(LPM3.5) current with
active RTC into primary
ILPM3.5,
3 V
3 V
0.2
0.7
0.7
0.9
1.7
µA
µA
RTC,VCC
(10)
supply pin DVCC
Low-power mode 3.5
(LPM3.5) current with
active RTC into backup
supply pin VBAT(11)
ILPM3.5,
1.2
RTC,VBAT
Total low-power mode 3.5
(LPM3.5) current with
active RTC(12)
ILPM3.5,
3 V
3 V
0.8
0.9
0.2
1.0
1.6
0.8
2.9
1.9
µA
µA
RTC,TOT
Low-power mode 4.5
(LPM4.5)(8)
ILPM4.5
0.12
0.6
0.32
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external
load capacitance are chosen to closely match the required 9 pF.
(3) Current for watchdog timer clocked by SMCLK included. ACLK = low-frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz
FG6626 and FG6625 USB disabled (VUSBEN = 0, SLDOEN = 0). FG6426 and FG6425 LDO disabled (LDOEN = 0).
(4) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low-frequency crystal operation
(XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2), fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz; DCO
setting = 1 MHz operation, DCO bias generator enabled.
FG6626 and FG6625 USB disabled (VUSBEN = 0, SLDOEN = 0). FG6426 and FG6425 LDO disabled (LDOEN = 0).
(5) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low-frequency crystal operation
(XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
FG6626 and FG6625 USB disabled (VUSBEN = 0, SLDOEN = 0). FG6426 and FG6425 LDO disabled (LDOEN = 0).
(6) Current for watchdog timer clocked by VLO included.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = fMCLK = fSMCLK = fDCO = 0 MHz
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FG6626 and FG6625 USB disabled (VUSBEN = 0, SLDOEN = 0). FG6426 and FG6425 LDO disabled (LDOEN = 0).
(7) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
FG6626 and FG6625 USB disabled (VUSBEN = 0, SLDOEN = 0). FG6426 and FG6425 LDO disabled (LDOEN = 0).
(8) Internal regulator disabled. No data retention.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5), fDCO = fACLK = fMCLK = fSMCLK = 0 MHz
(9) Current for brownout included. Low-side supervisor and monitors disabled (SVSL, SVML). High-side supervisor and monitor disabled
(SVSH, SVMH). RAM retention enabled.
(10) VVBAT = VCC – 0.2 V, fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active
(11) VVBAT = VCC – 0.2 V, fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active, no
current drawn on VBAK
(12) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, PMMREGOFF = 1, RTC in backup domain active, no current drawn on VBAK
8.6 Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
TEMPERATURE (TA)
PARAMETER
VCC
PMMCOREV
–40°C
TYP MAX
25°C
TYP
60°C
TYP
85°C
TYP
UNIT
MAX
MAX
MAX
0
1
2
3
0
1
2
3
0
1
2
0
1
2
3
3.7
4.1
4.5
4.5
4.2
4.7
5.1
5.0
4.3
4.7
4.9
5.5
5.9
6.3
6.5
6.0
6.6
7.1
7.0
9.0
9.6
15.0
Low-power mode 3
ILPM3, LCD, (LPM3) current, LCD 4-
3 V
µA
ext. bias
mux mode, external
5.1
10.2
10.4
9.6
biasing(1) (2)
5.2
5.8
5.4
18.0
17.0
4.8
Low-power mode 3
(LPM3) current, LCD 4-
mux mode, internal
biasing, charge pump
disabled(1) (3)
5.4
10.4
11.0
11.0
ILPM3, LCD,
int. bias
3 V
2.2 V
3 V
µA
µA
µA
5.8
5.7
6.4
19.0
6.4
6.77
7.13
6.53
7.0
Low-power mode 3
(LPM3) current, LCD 4-
mux mode, internal
biasing, charge pump
enabled(1) (4)
ILPM3
LCD,CP
7.43
7.6
(1) Current for watchdog timer clocked by ACLK and RTC clocked by LFXT1 (32768 Hz) included. ACLK = low-frequency crystal operation
(XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3), fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
Current for brownout included. Low-side supervisor (SVSL) and low-side monitor (SVML) disabled. High-side supervisor (SVSH) and
high-side monitor (SVMH) disabled. RAM retention enabled.
(2) LCDMx = 11 (4-mux mode), LCDREXT = 1, LCDEXTBIAS = 1 (external biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump
disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Current through external resistors not included (voltage levels are supplied by test equipment).
Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.
(3) LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 0 (charge pump
disabled), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.
(4) LCDMx = 11 (4-mux mode), LCDREXT = 0, LCDEXTBIAS = 0 (internal biasing), LCD2B = 0 (1/3 bias), LCDCPEN = 1 (charge pump
enabled), VLCDx = 1000 (VLCD = 3 V, typical), LCDSSEL = 0, LCDPREx = 101, LCDDIVx = 00011 (fLCD = 32768 Hz / 32 / 4 = 256 Hz)
Even segments S0, S2,... = 0, odd segments S1, S3,... = 1. No LCD panel load.
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8.7 Thermal Resistance Characteristics
PARAMETER
Junction-to-ambient thermal resistance, still air (1)
VALUE
122
108
83
UNIT
QFP (PZ)
θJA
°C/W
BGA (ZQW)
QFP (PZ)
θJC(TOP)
Junction-to-case (top) thermal resistance (2)
Junction-to-board thermal resistance (3)
°C/W
°C/W
BGA (ZQW)
QFP (PZ)
72
98
θJB
BGA (ZQW)
76
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board,
as specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
8.8 Timing and Switching Characteristics
8.8.1 Power Supply Sequencing
TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up, power
down, and device operation, the voltage difference between AVCC and DVCC must not exceed the limits
specified in Absolute Maximum Ratings. Exceeding the specified limits may cause malfunction of the device
including erroneous writes to RAM and flash.
Section 8.8.1.1 lists the device reset requirements.
8.8.1.1 Brownout and Device Reset Power Ramp Requirements
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
| dDVCC/dt | < 3 V/s
| dDVCC/dt | < 3 V/s
MIN
TYP
MAX UNIT
V(DVCC_BOR_IT–)
V(DVCC_BOR_IT+)
V(DVCC_BOR_hys)
BORH on voltage, DVCC falling level
BORH off voltage, DVCC rising level
BORH hysteresis
1.47
1.55
250
V
V
0.80
60
1.30
mV
8.8.2 Reset Timing
Section 8.8.2.1 lists the reset input timing.
8.8.2.1 Reset Input
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TYP UNIT
tRESET
Pulse duration required at RST/NMI pin to accept a reset
2
µs
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8.8.3 Clock Specifications
Section 8.8.3.1 lists the characteristics of XT1 in low-frequency mode.
8.8.3.1 Crystal Oscillator, XT1, Low-Frequency Mode
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1
0.075
Differential XT1 oscillator crystal
current consumption from lowest
drive setting, LF mode
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 2
ΔIDVCC,LF
3 V
0.170
0.290
32768
µA
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3
XT1 oscillator crystal frequency,
LF mode
fXT1,LF0
XTS = 0, XT1BYPASS = 0
Hz
XT1 oscillator logic-level square-
wave input frequency, LF mode
fXT1,LF,SW
XTS = 0, XT1BYPASS = 1(2) (3)
10 32.768
210
50 kHz
XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
fXT1,LF = 32768 Hz, CL,eff = 6 pF
Oscillation allowance for
LF crystals(4)
OALF
kΩ
XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 1,
fXT1,LF = 32768 Hz, CL,eff = 12 pF
300
XTS = 0, XCAPx = 0(6)
XTS = 0, XCAPx = 1
XTS = 0, XCAPx = 2
XTS = 0, XCAPx = 3
1
5.5
Integrated effective load
capacitance, LF mode(5)
CL,eff
pF
8.5
12.0
XTS = 0, Measured at ACLK,
fXT1,LF = 32768 Hz
Duty cycle, LF mode
30%
10
70%
Oscillator fault frequency,
LF mode(7)
fFault,LF
XTS = 0(8)
10000
Hz
ms
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 0,
CL,eff = 6 pF
1000
500
tSTART,LF
Start-up time, LF mode
3 V
fOSC = 32768 Hz, XTS = 0,
XT1BYPASS = 0, XT1DRIVEx = 3,
CL,eff = 12 pF
(1) To improve EMI on the XT1 oscillator, observe the following guidelines.
•
•
•
•
•
•
Keep the trace between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) When XT1BYPASS is set, XT1 circuit is automatically powered down. Input signal is a digital square wave with parametrics defined in
the Schmitt-trigger Inputs section of this data sheet.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
XT1DRIVEx settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
•
•
•
•
For XT1DRIVEx = 0, CL,eff ≤ 6 pF
For XT1DRIVEx = 1, 6 pF ≤ CL,eff ≤ 9 pF
For XT1DRIVEx = 2, 6 pF ≤ CL,eff ≤ 10 pF
For XT1DRIVEx = 3, CL,ef f ≥ 6 pF
(5) Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, verify
the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the
specification of the used crystal.
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(6) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies between the MIN and MAX specifications might set the flag.
(8) Measured with logic-level input frequency but also applies to operation with crystals.
Section 8.8.3.2 lists the characteristics of XT2.
8.8.3.2 Crystal Oscillator, XT2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fOSC = 4 MHz, XT2OFF = 0, TA = 25°C,
XT2BYPASS = 0, XT2DRIVEx = 0
200
fOSC = 12 MHz, XT2OFF = 0, TA = 25°C,
XT2BYPASS = 0, XT2DRIVEx = 1
260
325
450
XT2 oscillator crystal current
consumption
IDVCC,XT2
3 V
µA
fOSC = 20 MHz, XT2OFF = 0, TA = 25°C,
XT2BYPASS = 0, XT2DRIVEx = 2
fOSC = 32 MHz, XT2OFF = 0, TA = 25°C,
XT2BYPASS = 0, XT2DRIVEx = 3
XT2 oscillator crystal frequency,
mode 0
fXT2,HF0
fXT2,HF1
fXT2,HF2
fXT2,HF3
fXT2,HF,SW
XT2DRIVEx = 0, XT2BYPASS = 0(3)
XT2DRIVEx = 1, XT2BYPASS = 0(3)
XT2DRIVEx = 2, XT2BYPASS = 0(3)
XT2DRIVEx = 3, XT2BYPASS = 0(3)
XT2BYPASS = 1(3) (4)
4
8
8
MHz
XT2 oscillator crystal frequency,
mode 1
16 MHz
24 MHz
32 MHz
32 MHz
XT2 oscillator crystal frequency,
mode 2
16
24
0.7
XT2 oscillator crystal frequency,
mode 3
XT2 oscillator logic-level square-
wave input frequency
XT2DRIVEx = 0, XT2BYPASS = 0,
fXT2,HF0 = 6 MHz, CL,eff = 15 pF
450
320
200
200
XT2DRIVEx = 1, XT2BYPASS = 0,
fXT2,HF1 = 12 MHz, CL,eff = 15 pF
Oscillation allowance for
HF crystals(5)
OAHF
Ω
XT2DRIVEx = 2, XT2BYPASS = 0,
fXT2,HF2 = 20 MHz, CL,eff = 15 pF
XT2DRIVEx = 3, XT2BYPASS = 0,
fXT2,HF3 = 32 MHz, CL,eff = 15 pF
fOSC = 6 MHz,
XT2BYPASS = 0, XT2DRIVEx = 0,
TA = 25°C, CL,eff = 15 pF
0.5
0.3
tSTART,HF
Start-up time
3 V
ms
pF
fOSC = 20 MHz,
XT2BYPASS = 0, XT2DRIVEx = 3,
TA = 25°C, CL,eff = 15 pF
Integrated effective load
CL,eff
1
capacitance, HF mode(6) (1)
Duty cycle
Measured at ACLK, fXT2,HF2 = 20 MHz
XT2BYPASS = 1(8)
40%
30
50%
60%
300 kHz
fFault,HF
Oscillator fault frequency(7)
(1) Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
(2) To improve EMI on the XT2 oscillator, observe the following guidelines.
•
•
•
•
•
•
Keep the traces between the device and the crystal as short as possible.
Design a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XT2IN and XT2OUT.
Avoid running PCB traces underneath or adjacent to the XT2IN and XT2OUT pins.
Use assembly materials and processes that avoid any parasitic load on the oscillator XT2IN and XT2OUT pins.
If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) When XT2BYPASS is set, the XT2 circuit is automatically powered down.
(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals.
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(6) Includes parasitic bond and package capacitance (approximately 2 pF per pin). Because the PCB adds additional capacitance, verify
the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the
specification of the used crystal.
(7) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies between the MIN and MAX specifications might set the flag.
(8) Measured with logic-level input frequency but also applies to operation with crystals.
Section 8.8.3.3 lists the characteristics of the VLO.
8.8.3.3 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VLO frequency
VLO frequency temperature drift
TEST CONDITIONS
VCC
MIN
TYP
9.4
0.5
4
MAX UNIT
14 kHz
%/°C
fVLO
Measured at ACLK
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
1.8 V to 3.6 V
6
dfVLO/dT
Measured at ACLK(1)
Measured at ACLK(2)
Measured at ACLK
dfVLO/dVCC VLO frequency supply voltage drift
Duty cycle
%/V
40%
50%
60%
(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
Section 8.8.3.4 lists the characteristics of the REFO.
8.8.3.4 Internal Reference, Low-Frequency Oscillator (REFO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
REFO oscillator current
consumption
IREFO
TA = 25°C
1.8 V to 3.6 V
3
µA
Hz
REFO frequency calibrated
Measured at ACLK
Full temperature range
TA = 25°C
1.8 V to 3.6 V
1.8 V to 3.6 V
3 V
32768
fREFO
±3.5%
REFO absolute tolerance
calibrated
±1.5%
dfREFO/dT
REFO frequency temperature drift Measured at ACLK(1)
1.8 V to 3.6 V
0.01
1.0
%/°C
%/V
REFO frequency supply voltage
Measured at ACLK(2)
drift
dfREFO/dVCC
1.8 V to 3.6 V
Duty cycle
Measured at ACLK
40%/60% duty cycle
1.8 V to 3.6 V
1.8 V to 3.6 V
40%
50%
25
60%
tSTART
REFO start-up time
µs
(1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
(2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
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Section 8.8.3.5 lists the characteristics of the DCO frequency.
8.8.3.5 DCO Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DCORSELx = 0, DCOx = 0, MODx = 0
DCORSELx = 0, DCOx = 31, MODx = 0
DCORSELx = 1, DCOx = 0, MODx = 0
DCORSELx = 1, DCOx = 31, MODx = 0
DCORSELx = 2, DCOx = 0, MODx = 0
DCORSELx = 2, DCOx = 31, MODx = 0
DCORSELx = 3, DCOx = 0, MODx = 0
DCORSELx = 3, DCOx = 31, MODx = 0
DCORSELx = 4, DCOx = 0, MODx = 0
DCORSELx = 4, DCOx = 31, MODx = 0
DCORSELx = 5, DCOx = 0, MODx = 0
DCORSELx = 5, DCOx = 31, MODx = 0
DCORSELx = 6, DCOx = 0, MODx = 0
DCORSELx = 6, DCOx = 31, MODx = 0
DCORSELx = 7, DCOx = 0, MODx = 0
DCORSELx = 7, DCOx = 31, MODx = 0
MIN
0.07
0.70
0.15
1.47
0.32
3.17
0.64
6.07
1.3
TYP
MAX UNIT
0.20 MHz
1.70 MHz
0.36 MHz
3.45 MHz
0.75 MHz
7.38 MHz
1.51 MHz
14.0 MHz
3.2 MHz
fDCO(0,0)
fDCO(0,31)
fDCO(1,0)
fDCO(1,31)
fDCO(2,0)
fDCO(2,31)
fDCO(3,0)
fDCO(3,31)
fDCO(4,0)
fDCO(4,31)
fDCO(5,0)
fDCO(5,31)
fDCO(6,0)
fDCO(6,31)
fDCO(7,0)
fDCO(7,31)
DCO frequency (0, 0)(1)
DCO frequency (0, 31)(1)
DCO frequency (1, 0)(1)
DCO frequency (1, 31)(1)
DCO frequency (2, 0)(1)
DCO frequency (2, 31)(1)
DCO frequency (3, 0)(1)
DCO frequency (3, 31)(1)
DCO frequency (4, 0)(1)
DCO frequency (4, 31)(1)
DCO frequency (5, 0)(1)
DCO frequency (5, 31)(1)
DCO frequency (6, 0)(1)
DCO frequency (6, 31)(1)
DCO frequency (7, 0)(1)
DCO frequency (7, 31)(1)
12.3
2.5
28.2 MHz
6.0 MHz
23.7
4.6
54.1 MHz
10.7 MHz
88.0 MHz
19.6 MHz
135 MHz
39.0
8.5
60
Frequency step between range
DCORSEL and DCORSEL + 1
SDCORSEL
SDCO
SRSEL = fDCO(DCORSEL+1,DCO)/fDCO(DCORSEL,DCO)
1.2
2.3 ratio
Frequency step between tap
DCO and DCO + 1
SDCO = fDCO(DCORSEL,DCO+1)/fDCO(DCORSEL,DCO)
Measured at SMCLK
1.02
40%
1.12 ratio
Duty cycle
50%
0.1
60%
%/°C
%/V
dfDCO/dT
DCO frequency temperature drift fDCO = 1 MHz,
DCO frequency voltage drift fDCO = 1 MHz
dfDCO/dVCC
1.9
(1) When selecting the proper DCO frequency range (DCORSELx), the target DCO frequency, fDCO, should be set to reside within the
range of fDCO(n, 0),MAX ≤ fDCO ≤ fDCO(n, 31),MIN, where fDCO(n, 0),MAX represents the maximum frequency specified for the DCO frequency,
range n, tap 0 (DCOx = 0) and fDCO(n,31),MIN represents the minimum frequency specified for the DCO frequency, range n, tap 31
(DCOx = 31). This ensures that the target DCO frequency resides within the range selected. It should also be noted that if the actual
fDCO frequency for the selected range causes the FLL or the application to select tap 0 or 31, the DCO fault flag is set to report that the
selected range is at its minimum or maximum tap setting.
100
VCC = 3.0 V
TA = 25°C
10
DCOx = 31
1
DCOx = 0
0.1
0
1
2
3
4
5
6
7
DCORSEL
Figure 8-2. Typical DCO Frequency
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8.8.4 Wake-up Characteristics
Section 8.8.4.1 lists the characteristics of the wake-up times.
8.8.4.1 Wake-up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
fMCLK ≥ 4 MHz
3
6.5
Wake-up time from LPM2,
LPM3, or LPM4 to active
mode(1)
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 1
tWAKE-UP-FAST
µs
1 MHz < fMCLK
4 MHz
<
4
8.0
Wake-up time from LPM2,
LPM3, or LPM4 to active
mode(2) (3)
PMMCOREV = SVSMLRRL = n
(where n = 0, 1, 2, or 3),
SVSLFP = 0
tWAKE-UP-SLOW
150
165
µs
Wake-up time from LPM3.5
or LPM4.5 to active mode(4)
tWAKE-UP-LPM5
tWAKE-UP-RESET
2
2
3
3
ms
ms
Wake-up time from RST or
BOR event to active mode(4)
(1) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the
performance mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-FAST is possible with SVSL and SVML in
full performance mode or disabled. For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode
Selection section in the Power Management Module and Supply Voltage Supervisor chapter of the MSP430F5xx and MSP430F6xx
Family User's Guide.
(2) This value represents the time from the wake-up event to the first active edge of MCLK. The wake-up time depends on the
performance mode of the low-side supervisor (SVSL) and low-side monitor (SVML). tWAKE-UP-SLOW is set with SVSL and SVML in
normal mode (low current mode). For specific register settings, see the Low-Side SVS and SVM Control and Performance Mode
Selection section in the Power Management Module and Supply Voltage Supervisor chapter of the MSP430F5xx and MSP430F6xx
Family User's Guide.
(3) The wake-up times from LPM0 and LPM1 to AM are not specified. They are proportional to MCLK cycle time but are not affected by
the performance mode settings as for LPM2, LPM3, and LPM4.
(4) This value represents the time from the wake-up event to the reset vector execution.
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8.8.5 General-Purpose I/Os
Section 8.8.5.1 lists the characteristics of the Schmitt-trigger inputs.
8.8.5.1 Schmitt-Trigger Inputs – General-Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
1.8 V
3 V
MIN
0.80
1.50
0.45
0.75
0.3
TYP
MAX UNIT
1.40
V
2.10
VIT+
VIT–
Vhys
Positive-going input threshold voltage
1.8 V
3 V
1.00
V
1.65
Negative-going input threshold voltage
1.8 V
3 V
0.8
V
1.0
Input voltage hysteresis (VIT+ – VIT–
)
0.4
For pullup: VIN = VSS
For pulldown: VIN = VCC
RPull
CI
Pullup or pulldown resistor
Input capacitance
20
35
5
50
kΩ
pF
VIN = VSS or VCC
(1) The same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).
Section 8.8.5.2 lists the characteristics of P1, P2, P3, and P4 .
8.8.5.2 Inputs – Ports P1, P2, P3, and P4
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
Port P1, P2, P3, P4: P1.x to P4.x,
External trigger pulse duration to set interrupt flag
t(int)
External interrupt timing(2)
2.2 V, 3 V
20
ns
(1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
(2) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals
shorter than t(int)
.
Section 8.8.5.3 lists the leakage current of the GPIOs.
8.8.5.3 Leakage Current – General-Purpose I/O
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
See (1) (2)
VCC
MIN
MAX UNIT
Ilkg(Px.x)
High-impedance leakage current
1.8 V, 3 V
±50 nA
(1) The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is
disabled.
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Section 8.8.5.4 lists the output characteristics of the GPIOs.
8.8.5.4 Outputs – General-Purpose I/O (Full Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I(OHmax) = –3 mA(1)
VCC
MIN
VCC – 0.25
VCC – 0.60
VCC – 0.25
VCC – 0.60
MAX UNIT
VCC
1.8 V
I(OHmax) = –10 mA(2)
I(OHmax) = –5 mA(1)
I(OHmax) = –15 mA(2)
I(OLmax) = 3 mA(1)
I(OLmax) = 10 mA(2)
I(OLmax) = 5 mA(1)
I(OLmax) = 15 mA(2)
VCC
VOH
High-level output voltage
V
VCC
3 V
1.8 V
3 V
VCC
VSS VSS + 0.25
VSS VSS + 0.60
VSS VSS + 0.25
VSS VSS + 0.60
VOL
Low-level output voltage
V
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage
drop specified.
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage
drop specified.
Section 8.8.5.5 lists the output characteristics of the GPIOs.
8.8.5.5 Outputs – General-Purpose I/O (Reduced Drive Strength)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(3)
PARAMETER
TEST CONDITIONS
I(OHmax) = –1 mA(1)
VCC
MIN
VCC – 0.25
VCC – 0.60
VCC – 0.25
VCC – 0.60
MAX UNIT
VCC
1.8 V
I(OHmax) = –3 mA(2)
I(OHmax) = –2 mA(1)
I(OHmax) = –6 mA(2)
I(OLmax) = 1 mA(1)
I(OLmax) = 3 mA(2)
I(OLmax) = 2 mA(1)
I(OLmax) = 6 mA(2)
VCC
VOH
High-level output voltage
V
VCC
3 V
1.8 V
3 V
VCC
VSS VSS + 0.25
VSS VSS + 0.60
VSS VSS + 0.25
VSS VSS + 0.60
VOL
Low-level output voltage
V
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage
drop specified.
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage
drop specified.
(3) Selecting reduced drive strength may reduce EMI.
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Section 8.8.5.6 lists the frequency characteristics of the GPIOs.
8.8.5.6 Output Frequency – Ports P1, P2 and P3
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX UNIT
VCC = 1.8 V
PMMCOREVx = 0
8
Port output frequency
(with load)
P3.4/TA2CLK/SMCLK/S27
fPx.y
MHz
20
CL = 20 pF, RL = 1 kΩ(1) or 3.2 kΩ(2) (3)
VCC = 3 V
PMMCOREVx = 3
VCC = 1.8 V
PMMCOREVx = 0
P1.0/TA0CLK/ACLK/S39
P3.4/TA2CLK/SMCLK/S27
P2.0/P2MAP0 (P2MAP0 = PM_MCLK )
CL = 20 pF(3)
8
fPort_CLK
Clock output frequency
MHz
20
VCC = 3 V
PMMCOREVx = 3
(1) Full drive strength of port: A resistive divider with 2 × 0.5 kΩ between VCC and VSS is used as load. The output is connected to the
center tap of the divider.
(2) Reduced drive strength of port: A resistive divider with 2 × 1.6 kΩ between VCC and VSS is used as load. The output is connected to
the center tap of the divider.
(3) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
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8.8.5.7 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
25.0
20.0
15.0
10.0
5.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
TA = 25°C
TA = 85°C
TA = 25°C
TA = 85°C
0.0
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOL – Low-Level Output Voltage – V
VOL – Low-Level Output Voltage – V
VCC = 1.8 V
P3.2
VCC = 3.0 V
P3.2
Figure 8-4. Typical Low-Level Output Current vs
Low-Level Output Voltage
Figure 8-3. Typical Low-Level Output Current vs
Low-Level Output Voltage
0.0
0.0
−1.0
−2.0
−3.0
−4.0
−5.0
−10.0
−15.0
TA = 85°C
TA = 25°C
−5.0
−6.0
−7.0
−8.0
TA = 85°C
−20.0
TA = 25°C
−25.0
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOH – High-Level Output Voltage – V
VOH – High-Level Output Voltage – V
VCC = 1.8 V
P3.2
VCC = 3.0 V
P3.2
Figure 8-6. Typical High-Level Output Current Vs
High-Level Output Voltage
Figure 8-5. Typical High-Level Output Current Vs
High-Level Output Voltage
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8.8.5.8 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
60.0
24
TA = 25°C
55.0
TA = 25°C
TA = 85°C
50.0
45.0
40.0
35.0
30.0
25.0
20.0
15.0
10.0
5.0
20
16
12
8
TA = 85°C
4
0
0.0
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOL – Low-Level Output Voltage – V
VOL – Low-Level Output Voltage – V
VCC = 1.8 V
P3.2
VCC = 3.0 V
P3.2
Figure 8-8. Typical Low-Level Output Current vs
Low-Level Output Voltage
Figure 8-7. Typical Low-Level Output Current vs
Low-Level Output Voltage
0.0
−5.0
0
−10.0
−15.0
−20.0
−25.0
−30.0
−35.0
−40.0
−4
−8
−12
TA = 85°C
−16
−45.0
TA = 85°C
−50.0
−55.0
TA = 25°C
−60.0
TA = 25°C
−20
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
VOH – High-Level Output Voltage – V
VOH – High-Level Output Voltage – V
VCC = 3.0 V
P3.2
VCC = 1.8 V
P3.2
Figure 8-9. Typical High-Level Output Current vs
High-level Output Voltage
Figure 8-10. Typical High-Level Output Current vs
High-level Output Voltage
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8.8.6 PMM
Section 8.8.6.1 lists the characteristics of the PMM core voltage.
8.8.6.1 PMM, Core Voltage
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Core voltage, active mode,
PMMCOREV = 3
VCORE3(AM)
VCORE2(AM)
VCORE1(AM)
VCORE0(AM)
VCORE3(LPM)
VCORE2(LPM)
VCORE1(LPM)
VCORE0(LPM)
2.4 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 21 mA
1.90
V
Core voltage, active mode,
PMMCOREV = 2
2.2 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 21 mA
2 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 17 mA
1.8 V ≤ DVCC ≤ 3.6 V, 0 mA ≤ I(VCORE) ≤ 13 mA
2.4 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA
2.2 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA
2 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA
1.8 V ≤ DVCC ≤ 3.6 V, 0 µA ≤ I(VCORE) ≤ 30 µA
1.80
1.60
1.40
1.94
1.84
1.64
1.44
V
V
V
V
V
V
V
Core voltage, active mode,
PMMCOREV = 1
Core voltage, active mode,
PMMCOREV = 0
Core voltage, low-current mode,
PMMCOREV = 3
Core voltage, low-current mode,
PMMCOREV = 2
Core voltage, low-current mode,
PMMCOREV = 1
Core voltage, low-current mode,
PMMCOREV = 0
Section 8.8.6.2 lists the characteristics of the SVS high side.
8.8.6.2 PMM, SVS High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SVSHE = 0, DVCC = 3.6 V
0
nA
I(SVSH)
SVS current consumption
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 0
SVSHE = 1, DVCC = 3.6 V, SVSHFP = 1
SVSHE = 1, SVSHRVL = 0
200
2.0
µA
1.59
1.79
1.98
2.10
1.62
1.88
2.07
2.20
2.32
2.56
2.85
2.85
1.64
1.84
2.04
2.16
1.74
1.94
2.14
2.26
2.40
2.70
3.00
3.00
2.5
1.69
SVSHE = 1, SVSHRVL = 1
1.91
V
V(SVSH_IT–) SVSH on voltage level(1)
SVSHE = 1, SVSHRVL = 2
2.11
SVSHE = 1, SVSHRVL = 3
2.23
1.81
2.01
2.21
SVSHE = 1, SVSMHRRL = 0
SVSHE = 1, SVSMHRRL = 1
SVSHE = 1, SVSMHRRL = 2
SVSHE = 1, SVSMHRRL = 3
2.33
V
V(SVSH_IT+) SVSH off voltage level(1)
SVSHE = 1, SVSMHRRL = 4
2.48
SVSHE = 1, SVSMHRRL = 5
2.84
3.15
3.15
SVSHE = 1, SVSMHRRL = 6
SVSHE = 1, SVSMHRRL = 7
SVSHE = 1, dVDVCC/dt = 10 mV/µs, SVSHFP = 1
SVSHE = 1, dVDVCC/dt = 1 mV/µs, SVSHFP = 0
SVSHE = 0→1, SVSHFP = 1
SVSHE = 0→1, SVSHFP = 0
tpd(SVSH)
SVSH propagation delay
µs
µs
20
12.5
100
t(SVSH)
SVSH on or off delay time
DVCC rise time
dVDVCC/dt
0
1000
V/s
(1) The SVSH settings available depend on the VCORE (PMMCOREV) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the MSP430F5xx and MSP430F6xx Family User's Guide on recommended settings and use.
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Section 8.8.6.3 lists the characteristics of the SVM high side.
8.8.6.3 PMM, SVM High Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SVMHE = 0, DVCC = 3.6 V
0
nA
I(SVMH)
SVMH current consumption
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 0
SVMHE = 1, DVCC = 3.6 V, SVMHFP = 1
SVMHE = 1, SVSMHRRL = 0
200
2.0
µA
1.86
1.65
1.85
2.02
2.18
2.32
2.56
2.85
2.85
1.74
1.94
2.14
2.26
2.40
2.70
3.00
3.00
3.75
2.5
SVMHE = 1, SVSMHRRL = 1
2.02
SVMHE = 1, SVSMHRRL = 2
2.22
SVMHE = 1, SVSMHRRL = 3
2.35
V(SVMH)
SVMH on or off voltage level(1)
SVMHE = 1, SVSMHRRL = 4
2.48
2.84
3.15
3.15
V
SVMHE = 1, SVSMHRRL = 5
SVMHE = 1, SVSMHRRL = 6
SVMHE = 1, SVSMHRRL = 7
SVMHE = 1, SVMHOVPE = 1
SVMHE = 1, dVDVCC/dt = 10 mV/µs, SVMHFP = 1
SVMHE = 1, dVDVCC/dt = 1 mV/µs, SVMHFP = 0
SVMHE = 0→1, SVSMFP = 1
tpd(SVMH) SVMH propagation delay
µs
µs
20
12.5
100
t(SVMH)
SVMH on or off delay time
SVMHE = 0→1, SVMHFP = 0
(1) The SVMH settings available depend on the VCORE (PMMCOREV) setting. See the Power Management Module and Supply Voltage
Supervisor chapter in the MSP430F5xx and MSP430F6xx Family User's Guide on recommended settings and use.
Section 8.8.6.4 lists the characteristics of the SVS low side.
8.8.6.4 PMM, SVS Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SVSLE = 0, PMMCOREV = 2
0
nA
µA
µs
I(SVSL)
SVSL current consumption
SVSLE = 1, PMMCOREV = 2, SVSLFP = 0
SVSLE = 1, PMMCOREV = 2, SVSLFP = 1
SVSLE = 1, dVCORE/dt = 10 mV/µs, SVSLFP = 1
SVSLE = 1, dVCORE/dt = 1 mV/µs, SVSLFP = 0
SVSLE = 0→1, SVSLFP = 1
200
2.0
2.5
20
tpd(SVSL) SVSL propagation delay
12.5
100
t(SVSL)
SVSL on or off delay time
µs
SVSLE = 0→1, SVSLFP = 0
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Section 8.8.6.5 lists the characteristics of the SVM low side.
8.8.6.5 PMM, SVM Low Side
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
SVMLE = 0, PMMCOREV = 2
0
nA
µA
µs
I(SVML)
SVML current consumption
SVMLE = 1, PMMCOREV = 2, SVMLFP = 0
SVMLE = 1, PMMCOREV = 2, SVMLFP = 1
SVMLE = 1, dVCORE/dt = 10 mV/µs, SVMLFP = 1
SVMLE = 1, dVCORE/dt = 1 mV/µs, SVMLFP = 0
SVMLE = 0→1, SVMLFP = 1
200
2.0
2.5
20
tpd(SVML) SVML propagation delay
12.5
100
t(SVML)
SVML on or off delay time
µs
SVMLE = 0→1, SVMLFP = 0
8.8.7 Timers
Section 8.8.7.1 lists the characteristics of Timer_A.
8.8.7.1 Timer_A, Timers TA0, TA1, and TA2
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
Internal: SMCLK or ACLK,
External: TACLK,
fTA
Timer_A input clock frequency
1.8 V, 3 V
20 MHz
Duty cycle = 50% ±10%
All capture inputs, minimum pulse
duration required for capture
tTA,cap Timer_A capture timing
1.8 V, 3 V
20
ns
Section 8.8.7.2 lists the characteristics of Timer_B.
8.8.7.2 Timer_B, Timer TB0
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
Internal: SMCLK or ACLK,
External: TBCLK,
fTB
Timer_B input clock frequency
1.8 V, 3 V
20 MHz
Duty cycle = 50% ±10%
All capture inputs, minimum pulse
duration required for capture
tTB,cap Timer_B capture timing
1.8 V, 3 V
20
ns
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8.8.8 Battery Backup
Section 8.8.8.1 lists the characteristics of the battery backup.
8.8.8.1 Battery Backup
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
0.43
MAX UNIT
TA = –40°C
VBAT = 1.7 V,
DVCC not connected,
RTC running
TA = 25°C
TA = 60°C
TA = 85°C
TA = –40°C
TA = 25°C
TA = 60°C
TA = 85°C
TA = –40°C
TA = 25°C
TA = 60°C
TA = 85°C
General
0.52
0.58
0.66
0.50
Current into VBAT terminal in VBAT = 2.2 V,
0.59
IVBAT
case no primary battery is
connected.
DVCC not connected,
RTC running
µA
0.64
0.72
0.68
VBAT = 3 V,
DVCC not connected,
RTC running
0.75
0.79
0.86
VSVSH_IT-
SVSHRL = 0
SVSHRL = 1
SVSHRL = 2
SVSHRL = 3
1.59
1.79
1.98
2.10
1.69
Switch-over level (VCC to
VBAT)
VSWITCH
CVCC = 4.7 µF
1.91
2.11
2.23
V
ON-resistance of switch
between VBAT and VBAK
RON_VBAT
VBAT = 1.8 V
0 V
0.35
1
kΩ
1.8 V
3 V
0.6
1.0
1.2
2.7
±5%
±5%
±5%
2.9
VBAT to ADC:
VBAT divided,
VBAT3 = VBAT /3
VBAT3
V
V
3.6 V
VCHVx
Charger end voltage
CHVx = 2
2.65
CHCx = 1
CHCx = 2
CHCx = 3
5.2
RCHARGE
Charge limiting resistor
10.2
20
kΩ
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8.8.9 USCI
Section 8.8.9.1 lists the characteristics of the USCI in UART mode.
8.8.9.1 USCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
Internal: SMCLK or ACLK,
External: UCLK,
fUSCI
USCI input clock frequency
fSYSTEM MHz
Duty cycle = 50% ±10%
fBITCLK BITCLK clock frequency (equals baud rate in MBaud)
tτ
UART receive deglitch time(1)
1
600
600
MHz
ns
2.2 V
3 V
50
50
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
Section 8.8.9.2 lists the characteristics of the USCI in SPI master mode.
8.8.9.2 USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
(see Figure 8-11 and Figure 8-12)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
fUSCI
USCI input clock frequency
SMCLK, ACLK, duty cycle = 50% ±10%
fSYSTEM MHz
1.8 V
3 V
55
38
30
25
0
PMMCOREV = 0
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
tSU,MI
SOMI input data setup time
SOMI input data hold time
SIMO output data valid time(2)
SIMO output data hold time(3)
ns
2.4 V
3 V
1.8 V
3 V
0
tHD,MI
ns
2.4 V
3 V
0
0
1.8 V
3 V
20
UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 0
18
ns
16
tVALID,MO
2.4 V
3 V
UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 3
15
1.8 V
3 V
–10
–8
CL = 20 pF, PMMCOREV = 0
CL = 20 pF, PMMCOREV = 3
tHD,MO
ns
2.4 V
3 V
–10
–8
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)
)
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams
in Figure 8-11 and Figure 8-12.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure
8-11 and Figure 8-12.
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1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLO/HI
tLO/HI
tSU,MI
tHD,MI
SOMI
SIMO
tHD,MO
tVALID,MO
Figure 8-11. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLO/HI
tLO/HI
tHD,MI
tSU,MI
SOMI
SIMO
tHD,MO
tVALID,MO
Figure 8-12. SPI Master Mode, CKPH = 1
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Section 8.8.9.3 lists the characteristics of the USCI in SPI slave mode.
8.8.9.3 USCI (SPI Slave Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
(see Figure 8-13 and Figure 8-14)
PARAMETER
TEST CONDITIONS
VCC
1.8 V
3 V
MIN
11
8
MAX UNIT
PMMCOREV = 0
tSTE,LEAD
tSTE,LAG
tSTE,ACC
tSTE,DIS
tSU,SI
STE lead time, STE low to clock
ns
2.4 V
3 V
7
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
PMMCOREV = 0
PMMCOREV = 3
6
1.8 V
3 V
3
3
STE lag time, Last clock to STE high
ns
2.4 V
3 V
3
3
1.8 V
3 V
66
50
ns
36
STE access time, STE low to SOMI data out
2.4 V
3 V
30
30
1.8 V
3 V
30
ns
30
STE disable time, STE high to SOMI high
impedance
2.4 V
3 V
30
1.8 V
3 V
5
5
2
2
5
5
5
5
SIMO input data setup time
SIMO input data hold time
SOMI output data valid time(2)
SOMI output data hold time(3)
ns
2.4 V
3 V
1.8 V
3 V
tHD,SI
ns
2.4 V
3 V
1.8 V
3 V
76
UCLK edge to SOMI valid,
CL = 20 pF, PMMCOREV = 0
60
ns
44
tVALID,SO
2.4 V
3 V
UCLK edge to SOMI valid,
CL = 20 pF, PMMCOREV = 3
40
1.8 V
3 V
12
12
12
12
CL = 20 pF, PMMCOREV = 0
CL = 20 pF, PMMCOREV = 3
tHD,SO
ns
2.4 V
3 V
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)
)
For the master parameters tSU,MI(Master) and tVALID,MO(Master), see the SPI parameters of the attached master.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams
in Figure 8-13 and Figure 8-14.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure
8-13 and Figure 8-14.
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tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tSU,SI
tLO/HI
tLO/HI
tHD,SI
SIMO
SOMI
tHD,SO
tVALID,SO
tSTE,ACC
tSTE,DIS
Figure 8-13. SPI Slave Mode, CKPH = 0
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL = 0
CKPL = 1
UCLK
tLO/HI
tLO/HI
tHD,SI
tSU,SI
SIMO
SOMI
tHD,MO
tVALID,SO
tSTE,ACC
tSTE,DIS
Figure 8-14. SPI Slave Mode, CKPH = 1
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Section 8.8.9.4 lists the characteristics of the USCI in I2C mode.
8.8.9.4 USCI (I2C Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see
Figure 8-15)
PARAMETER
TEST CONDITIONS
VCC
MIN
MAX UNIT
Internal: SMCLK or ACLK,
External: UCLK,
fUSCI
USCI input clock frequency
fSYSTEM MHz
Duty cycle = 50% ±10%
fSCL
SCL clock frequency
2.2 V, 3 V
2.2 V, 3 V
0
4.0
0.6
4.7
0.6
0
400 kHz
µs
fSCL ≤ 100 kHz
fSCL > 100 kHz
fSCL ≤ 100 kHz
fSCL > 100 kHz
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
2.2 V, 3 V
µs
tHD,DAT
tSU,DAT
Data hold time
Data setup time
2.2 V, 3 V
2.2 V, 3 V
ns
ns
250
4.0
0.6
50
fSCL ≤ 100 kHz
fSCL > 100 kHz
tSU,STO
Setup time for STOP
2.2 V, 3 V
µs
2.2 V
3 V
600
ns
600
tSP
Pulse duration of spikes suppressed by input filter
50
tHD,STA
tSU,STA
tHD,STA
tBUF
SDA
SCL
tLOW
tHIGH
tSP
tSU,DAT
tSU,STO
tHD,DAT
Figure 8-15. I2C Mode Timing
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8.8.10 LCD Controller
Section 8.8.10.1 lists the operating conditions of the LCD controller.
8.8.10.1 LCD_B Operating Conditions
PARAMETER
CONDITIONS
MIN
NOM
MAX UNIT
VCC,LCD_B,
Supply voltage range, charge
pump enabled, VLCD ≤ 3.6 V
LCDCPEN = 1, 0000 < VLCDx ≤ 1111
(charge pump enabled, VLCD ≤ 3.6 V)
2.2
3.6
3.6
3.6
3.6
V
V
V
V
CP en,3.6
VCC,LCD_B,
Supply voltage range, charge
pump enabled, VLCD ≤ 3.3 V
LCDCPEN = 1, 0000 < VLCDx ≤ 1100
(charge pump enabled, VLCD ≤ 3.3 V)
2.0
2.4
2.4
CP en,3.3
Supply voltage range, internal
biasing, charge pump disabled
VCC,LCD_B, int. bias
LCDCPEN = 0, VLCDEXT = 0
LCDCPEN = 0, VLCDEXT = 0
Supply voltage range, external
biasing, charge pump disabled
VCC,LCD_B, ext. bias
Supply voltage range, external
LCD voltage, internal or external
biasing, charge pump disabled
VCC,LCD_B,
LCDCPEN = 0, VLCDEXT = 1
LCDCPEN = 0, VLCDEXT = 1
2.0
2.4
3.6
3.6
V
V
VLCDEXT
External LCD voltage at LCDCAP/
R33, internal or external biasing,
charge pump disabled
VLCDCAP/R33
Capacitor on LCDCAP when
charge pump enabled
LCDCPEN = 1, VLCDx > 0000
(charge pump enabled)
CLCDCAP
fFrame
4.7
32
10
µF
Hz
fLCD = 2 × mux × fFRAME
(mux = 1 (static), 2, 3, 4)
LCD frame frequency range
0
100
fACLK,in
CPanel
ACLK input frequency range
Panel capacitance
30
40 kHz
100-Hz frame frequency
10000
pF
V
VCC
+
VR33
Analog input voltage at R33
Analog input voltage at R23
LCDCPEN = 0, VLCDEXT = 1
2.4
VR13
VR03
0.2
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0
VR03 + 2/3 ×
VR23,1/3bias
VR13,1/3bias
VR13,1/2bias
VR03
VR33
V
V
(VR33 – VR03
VR03 + 1/3 ×
(VR33 – VR03
VR03 + 1/2 ×
(VR33 – VR03
)
Analog input voltage at R13 with
1/3 biasing
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 0
VR23
VR33
)
Analog input voltage at R13 with
1/2 biasing
LCDREXT = 1, LCDEXTBIAS = 1,
LCD2B = 1
VR03
VSS
2.4
V
V
V
)
Analog input voltage at R03
R0EXT = 1
Voltage difference between VLCD
and R03
VCC
+ 0.2
VLCD-VR03
LCDCPEN = 0, R0EXT = 1
External LCD reference voltage
applied at LCDREF/R13
VLCDREF/R13
VLCDREFx = 01
0.8
1.2
1.5
V
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Section 8.8.10.2 lists the characteristics of the LCD controller.
8.8.10.2 LCD_B, Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
VCC
MAX UNIT
VLCDx = 0000, VLCDEXT = 0
LCDCPEN = 1, VLCDx = 0001
LCDCPEN = 1, VLCDx = 0010
LCDCPEN = 1, VLCDx = 0011
LCDCPEN = 1, VLCDx = 0100
LCDCPEN = 1, VLCDx = 0101
LCDCPEN = 1, VLCDx = 0110
LCDCPEN = 1, VLCDx = 0111
LCDCPEN = 1, VLCDx = 1000
LCDCPEN = 1, VLCDx = 1001
LCDCPEN = 1, VLCDx = 1010
LCDCPEN = 1, VLCDx = 1011
LCDCPEN = 1, VLCDx = 1100
LCDCPEN = 1, VLCDx = 1101
LCDCPEN = 1, VLCDx = 1110
LCDCPEN = 1, VLCDx = 1111
2.4 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2 V to 3.6 V
2.2 V to 3.6 V
2.2 V to 3.6 V
2.2 V to 3.6 V
2.60
2.66
2.72
2.79
2.85
2.92
2.98
3.05
3.10
3.17
3.24
3.30
3.36
3.42
3.48
VLCD
LCD voltage
V
3.6
Peak supply currents due to
charge pump activities
ICC,Peak,CP
LCDCPEN = 1, VLCDx = 1111
2.2 V
2.2 V
400
100
µA
CLCD = 4.7 µF,
LCDCPEN = 0→1,
VLCDx = 1111
Time to charge CLCD when
discharged
tLCD,CP,on
500
ms
Maximum charge pump load
current
ICP,Load
LCDCPEN = 1, VLCDx = 1111
2.2 V
2.2 V
2.2 V
50
µA
kΩ
kΩ
LCD driver output impedance, LCDCPEN = 1, VLCDx = 1000,
segment lines ILOAD = ±10 µA
RLCD,Seg
RLCD,COM
10
10
LCD driver output impedance, LCDCPEN = 1, VLCDx = 1000,
common lines ILOAD = ±10 µA
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8.8.11 CTSD16
Note
The delta-sigma analog-to-digital converter uses the CTSD16. The CTSD16 is proceeded by a unity-
gain buffer stage following the channel muxing as shown in Figure 9-2. See Section 8.8.14.1 for the
electrical characteristics of the PGA buffer stages.
Section 8.8.11.1 lists the operating conditions of the CTSD16.
8.8.11.1 CTSD16, Power Supply and Operating Conditions
PARAMETER
TEST CONDITIONS
AVSS = DVSS = 0 V
VCC
MIN
TYP
MAX UNIT
VCC
Supply voltage range
2.2
3.6
V
Analog plus digital supply
current per converter
(reference current not
included)
GAIN: 1, 2, 4, 8, 16
3 V
3 V
190(1)
CTSD16OSRx = 256,
CTSD16RRI = 0
ICTSD16
µA
GAIN: 1, 16
300(1)
This is requested when CTSD16 is converting, or
CTSD16RRIBURST = 0, or when OA is in rail-to-
rail input mode (OARRI = 1), or when OA charge
pump is on. The current should only be counted
once even if both OA and CTSD16 are requesting
the clock.
CTSD16 clock current
consumption
ICTSD16CLK
3 V
205
240
µA
(1) See Table 8-1 to calculate total current from CTSD16 for different use cases.
Table 8-1 explains how to compute the total current, ITOTAL, when the CTSD, along with associated modules, are
used. See Section 8.8.14.2 for a similar table for the OA. A "yes" means it must be included in computing ITOTAL
.
Here is an example current calculation for CTS16D in rail-to-rail input mode (CTSD16RRI = 1) using the internal
reference (CTSD16REFS = 1) and OA0 and OA1 enabled in rail-to-rail input modes, OARRI = 1.
As an example, assume that the application uses the CTS16D in rail-to-rail input mode (CTSD16RRI = 1) with
the internal reference (CTSD16REFS = 1) and OA0 and OA1 are enabled in rail-to-rail input modes, OARRI = 1.
The total current, ITOTAL, would be computed as follows:
ITOTAL = ICTSD16 + ICTSD16CLK+ ICP + IREFBG + 2 × IOA
(1)
Table 8-1. CTSD16, Current Calculation
USE CASE
DETAILS
(1)
(2)
(3)
(4)
USE CASE NAME
CTSD16
CTSD16 rail-to-rail inputs CTSD16RRI = 1
ICTSD16
ICTSD16CLK
ICP
no
yes
IREFBG
IREF
yes
yes
yes if CTSD16REFS = 1
no if CTSD16REFS = 0
yes
yes
yes if CTSD16REFS = 1
no if CTSD16REFS = 0
yes
yes
(1) Count this only once no matter how many modules use it. OA can also use this when rail-to-rail input is selected.
(2) Count this only once no matter how many modules use it. OA also uses this. This current is listed in Section 8.8.14.1.
(3) Count this only once no matter how many modules use it. DAC can use this as well as internal reference when it is available externally,
REFOUT = 1. This current is listed in Section 8.8.12.1.
(4) Count this only once no matter how many modules use it. This current is listed in Section 8.8.14.1. If IREFBG is used that includes IREF
current.
Section 8.8.11.2 lists the characteristics of the CTSD16 external voltage reference.
8.8.11.2 CTSD16, External Voltage Reference
PARAMETER
Input voltage range
Input current
TEST CONDITIONS
CTSD16REFS = 0
CTSD16REFS = 0
VCC
3 V
3 V
MIN
TYP
MAX UNIT
VVeREF+
IVeREF+
1.0
1.2
1.5
50
V
nA
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Section 8.8.11.3 lists the characteristics of the CTSD16 input range.
8.8.11.3 CTSD16, Input Range
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Differential full-scale input
voltage range
VID,FSR
VI,FSR
VID = VI,A+ – VI,A–
–VR/Gain
+VR/Gain
V
V
Single-ended full-scale input
voltage range
VID = VI,A+ – VR
negative input is tied to VR
VR – VR/
Gain
VR + VR/
Gain
CTSD16GAINx = 1
±928
±464
±232
±116
±58
CTSD16GAINx = 2
CTSD16REFS = 1 CTSD16GAINx = 4
CTSD16GAINx = 8
Differential input voltage range
for specified performance(2)
VID
mV
CTSD16GAINx = 16
VR
(0.8 × VR/
Gain)
–
VR +
(0.8 × VR/
Gain)
Single-ended input voltage
range for specified performance
VI
ZI
V
Input impedance
(pin Ax or ADx+ or ADx- to
AVSS)
CTSD16GAINx = 1, 16
CTSD16GAINx = 1, 16
3 V
3 V
20
35
MΩ
Differential input impedance
(pin ADx+ to pin ADx-)
ZID
VI
MΩ
V
Absolute input voltage range
AVSS
AVSS
VCC
VCC
Common-mode input voltage
range
VIC
V
(1) All parameters pertain to each CTSD16 input.
(2) The full-scale range is defined by VFSR+ = +VR/GAIN and VFSR- = -VR/GAIN; FSR = VFSR+ - VFSR- = 2xVR/GAIN. If VR is sourced
externally, the analog input range should not exceed 80% of VFSR+ or VFSR-; that is, VID = 0.8 VFSR- to 0.8 VFSR+. If VR is sourced
internally, the given VID ranges apply.
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Section 8.8.11.4 lists the performance characteristics of the CTSD16.
8.8.11.4 CTSD16, Performance
CTSD16OSRx = 256, CTSD164REFS = 1 (see Figure 8-16, Figure 8-17, and Figure 8-18)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
fM
Modulator clock
1.024
MHz
CTSD16GAINx = 1, input ADx+ and
ADx- (differential)
84
87
86
85
82
77
83
82
78
72
66
CTSD16GAINx = 2, input ADx+ and
ADx- (differential)
Signal-to-noise +
distortion ratio for
differential inputs
CTSD16GAINx = 4, input ADx+ and
ADx- (differential)
SINAD
fIN = 50 Hz(1)
3 V
dB
CTSD16GAINx = 8, input ADx+ and
ADx- (differential)
CTSD16GAINx = 16, input ADx+ and
ADx- (differential)
CTSD16GAINx = 1, input Ax (single-
ended)
CTSD16GAINx = 2, input Ax (single-
ended)
Signal-to-noise +
distortion ratio for
single-ended input
CTSD16GAINx = 4, input Ax (single-
ended)
SINAD
fIN = 50 Hz(1)
3 V
dB
CTSD16GAINx = 8, input Ax (single-
ended)
CTSD16GAINx = 16, input Ax (single-
ended)
CTSD16GAINx = 1
CTSD16GAINx = 2
CTSD16GAINx = 4
CTSD16GAINx = 8
CTSD16GAINx = 16
1
2
G
Nominal gain
Gain error
3 V
4
8
16
CTSD16GAINx: 1, 8, or 16 with external reference (1.2
V)
EG
3 V
3 V
–1%
+1%
Gain error
temperature
coefficient, internal
reference
ppm/
ΔEG/ΔT
CTSD16GAINx: 1, 8, or 16
3
50
°C
Gain error
temperature
coefficient, external
reference
CTSD16GAIN: 1, 8, or 16 with external reference
(1.2 V)
ppm/
ΔEG/ΔT
3 V
4
15
°C
ΔEG/ ΔVCC Gain error vs VCC
CTSD16GAINx: 1, 8, or 16
CTSD16GAINx = 1
0.02
%/V
±4.1
mV
EOS
Offset error
3 V
3 V
CTSD16GAINx = 16
±3.4
Offset error
temperature
coefficient
ppm
±10 FSR/
°C
ΔEOS/ΔT
CTSD16GAINx = 1, 16
CTSD16GAINx = 1, 16
±1
11
ΔEOS/
ΔVCC
Offset error vs VCC
3 V
3 V
µV/V
dB
CTSD16GAINx = 1, VID = 928 mV, fIN = 50 Hz
CTSD16GAINx = 16, VID = 58 mV, fIN = 50 Hz
78
80
CMRR,
50Hz
Common-mode
rejection ratio at 50 Hz
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8.8.11.4 CTSD16, Performance (continued)
CTSD16OSRx = 256, CTSD164REFS = 1 (see Figure 8-16, Figure 8-17, and Figure 8-18)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
CTSD16GAINx: 1, VCC = 3 V ±50 mV × sin(2π × fVcc
t), fVcc = 50 Hz,
Inputs grounded (no analog signal applied)
×
×
95
CTSD16GAINx: 8, VCC = 3 V ±50 mV × sin(2π × fVcc
t), fVcc = 50 Hz,
Inputs grounded (no analog signal applied)
AC power supply
rejection ratio
AC PSRR
DC PSRR
105
105
dB
CTSD16GAINx: 16, VCC = 3 V ±50 mV × sin(2π × fVcc
t), fVcc = 50 Hz,
×
Inputs grounded (no analog signal applied)
CTSD16GAINx: (1, 8, 16), VCC = 2.2 V to 3.6 V, (PSRR
[dB] = –20 log(dVout/dVcc) with dVout observed as
change in the digital conversion result; assumed to be
dominated by reference)
DC power supply
rejection ratio
90
dB
(1) The following voltages were applied to the CTSD16 inputs:
VI,A+(t) = 0 V + VPP/2 × sin(2π × fIN × t)
VI,A–(t) = 0 V – VPP/2 × sin(2π × fIN × t)
resulting in a differential voltage of VID = VIN,A+(t) – VIN,A-(t) = VPP × sin(2π × fIN × t) with VPP being selected as the maximum value
allowed for a given range (according to CTSD16 input range).
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0
-0.2
-0.4
-0.6
-0.8
-1
3
2.5
2
1.5
1
0.5
Gain = 1
-1.2
Gain = 16
-1.4
-40
0
0.25
0.55
0.85
1.2
1.5
1.8
2.1
2.4
2.7
-20
0
20
40
60
80
100
Common-Mode Voltage (V)
Temperature (°C)
A.
A.
Gain = 1
OSR = 256
DIfferential Signal = 300
Average of four typical devices
Figure 8-17. CTSD16 Typical Offset Voltage vs
Common-Mode Voltage
Figure 8-16. CTSD16 Offset Voltage vs
Temperature
90
85
80
75
70
65
60
55
50
10
100
1000
OSR
CTSD16REFS = 1 CTSD16GAINx = 1
Figure 8-18. SINAD Performance vs OSR
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Section 8.8.11.5 lists the characteristics of the built-in Vcc sense.
8.8.11.5 Built-in Vcc Sense
PARAMETER
AVCC divider
TEST CONDITIONS
MIN
TYP
MAX UNIT
0.95 ×
(AVCC / 2)
1.05 ×
V
VCC,sense
CTSD16ON = 1, CTSD16INCH = 0111
AVCC / 2
(AVCC / 2)
Section 8.8.11.6 lists the characteristics of the temperature sensor.
8.8.11.6 Temperature Sensor
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
CTSD16ON = 1, CTSD16INCH = 110,
VCC = 3 V, TA = 30°C
Vsensor Temperature sensor output voltage(1) (2)
800
mV
CTSD16ON = 1, CTSD16INCH = 110,
TA = 85°C
Isensor Temperature sensor quiescent current consumption
2
uA
(1) The temperature sensor offset can be as much as ±30°C. TI recommends a single-point calibration to minimize the offset error of the
built-in temperature sensor.
(2) The device descriptor structure contains calibration values for 30°C ±3°C and 85°C ±3°C for each of the available reference voltage
levels. The sensor voltage can be computed as VSENSE = TCSENSOR * (Temperature, °C) + VSENSOR, where TCSENSOR and VSENSOR
can be computed from the calibration values for higher accuracy.
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8.8.12 REF
Section 8.8.12.1 lists the characteristics of the REF and REFBG built-in reference.
8.8.12.1 REF and REFBG, Built-In Reference
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Operating supply current into AVCC
terminal(1)
IREFBG
VREFBG
IREF
VCC = 3.0 V, REFON = 1 and REFOUT = 1
110
130
1.174
20
µA
V
VCC = 3.0 V,
VeREF+ ≤ 1.5 V if used
Bandgap output voltage calibrated
1.146
1.16
15
Operating supply current into AVCC
terminal(1)
VCC = 3.0 V, REFON = 1
µA
REFVSEL = {2} for 2.5 V, REFON = 1
REFVSEL = {1} for 2.0 V, REFON = 1
REFVSEL = {0} for 1.5 V, REFON = 1
DAC12SREFx = 0, REFVSEL = {0} for 1.5 V
DAC12SREFx = 0, REFVSEL = {1} for 2 V
DAC12SREFx = 0, REFVSEL = {2} for 2.5 V
VCC = 2.2 V to 3.6 V, TA = 25°C
2.5
2.0
1.5
±1%
±1%
±1%
Positive built-in reference voltage
output
VREF
V
V
2.2
2.3
2.8
AVCC minimum voltage, Positive
built-in reference active
AVCC(min)
PSRR_DC Power supply rejection ratio (DC)
PSRR_AC Power supply rejection ratio (AC)
50
µV/V
VCC = 2.2 V to 3.6 V, TA = 25°C,
f = 1 kHz, ΔVpp = 100 mV
1.5
mV/V
Bandgap reference temperature
TCREF+
IVREF+ = 0 A
15
50 ppm/°C
coefficient(2)
Settling time of VREFBG reference
AVCC = AVCC (min) through AVCC(max)
REFON = 0 → 1
,
tSETTLE
120
µs
voltage(3)
CVREFBG
ILOAD
Capacitance at VREFBG terminal
VREFBG maximum load current
See (4)
1
1
nF
REFOUT = REFON = 1
I(VREF+) = +1 mA or –1 mA,
AVCC = AVCC (min)
REFON = REFOUT = 1
mA
Load-current regulation, VREFBG
terminal(5)
IL(VREFBG)
,
3.5 mV/mA
(1) The internal reference current is supplied from terminal AVCC. Consumption is independent of the CTSD16ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
(2) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C)/(85°C – (–40°C)).
(3) The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB.
(4) There is no capacitance required on VREFBG if the reference voltage is not used externally. However, TI recommends a capacitance
close to the maximum value to reduce any reference voltage noise.
(5) Contribution only due to the reference and buffer including package. This does not include resistance due to PCB traces or other
external factors.
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8.8.13 DAC
Section 8.8.13.1 lists the supply specifications of the DAC.
8.8.13.1 12-Bit DAC, Supply Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
AVCC
Analog supply voltage
AVCC = DVCC, AVSS = DVSS = 0 V
2.2
3.6
V
DAC12AMPx = 2, DAC12IR = 0,
DAC12OG = 1,
DAC12_xDAT = 0800h,
VeREF+ = VREFBG = 1.16 V
3 V
65
110
DAC12AMPx = 2, DAC12IR = 1,
DAC12_xDAT = 0800h,
VeREF+ = AVCC
125
250
750
70
165
350
IDD
Supply current, single DAC channel(1) (2)
µA
DAC12AMPx = 5, DAC12IR = 1,
DAC12_xDAT = 0800h,
VeREF+ = AVCC
2.2 V to
3.6 V
DAC12AMPx = 7, DAC12IR = 1,
DAC12_xDAT = 0800h,
VeREF+ = AVCC
1100
DAC12_xDAT = 800h,
VeREF+ = 1.16 V or 1.5 V,
ΔAVCC = 100 mV
2.2 V to
3.6 V
PSRR Power supply rejection ratio(3) (4)
dB
DAC12_xDAT = 800h,
VeREF+ = 1.16 V or 2.5 V
ΔAVCC = 100 mV
3 V
70
(1) No load at the output pin, DAC12_0 or DAC12_1, assuming that the control bits for the shared pins are set properly.
(2) Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input
specifications Section 8.8.13.4.
(3) PSRR = 20 log (ΔAVCC / ΔVDAC12_xOUT
(4) The internal reference is not used.
)
DAC VOUT
VR+
DAC Output
RLoad = ¥
Ideal transfer
function
AVCC
2
Offset Error
Positive
Gain Error
CLoad = 100 pF
Negative
DAC Code
Figure 8-19. Linearity Test Load Conditions, Gain and Offset Definition
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Section 8.8.13.2 lists the linearity specifications of the DAC.
8.8.13.2 12-Bit DAC, Linearity Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see
Figure 8-19)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Resolution
12-bit monotonic
12
bits
VeREF+ = 1.16 V, DAC12AMPx = 7, DAC12IR = 1
VeREF+ = 2.5 V, DAC12AMPx = 7, DAC12IR = 1
VeREF+ = 1.16 V, DAC12AMPx = 7, DAC12IR = 1
VeREF+ = 2.5 V, DAC12AMPx = 7, DAC12IR = 1
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
±2
±2
±4
INL
Integral nonlinearity(1)
LSB
±4
±0.4
±0.4
±1
Differential
DNL
LSB
±1
nonlinearity(1)
VeREF+ = 1.16 V,
DAC12AMPx = 7,
DAC12IR = 1
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
±21
Without calibration(1) (2)
VeREF+ = 2.5 V,
DAC12AMPx = 7,
DAC12IR = 1
±21
mV
EO
Offset voltage
VeREF+ = 1.16 V,
DAC12AMPx = 7,
±1.5
DAC12IR = 1
With calibration(1) (2)
VeREF+ = 2.5 V,
DAC12AMPx = 7,
DAC12IR = 1
2.2 V, 3 V
2.2 V, 3 V
±1.5
Offset error temperature
coefficient(1)
dE(O)/dT
With calibration
±10
10
µV/°C
VeREF+ = 1.16 V
VeREF+ = 2.5 V
2.2 V, 3 V
2.2 V, 3 V
±2.5
%FSR
±2.5
EG
Gain error
ppm of
FSR/
°C
Gain temperature
coefficient(1)
dE(G)/dT
2.2 V, 3 V
2.2 V, 3 V
DAC12AMPx = 2
165
Time for offset
calibration(3)
tOffset_Cal
DAC12AMPx = 3, 5
DAC12AMPx = 4, 6, 7
66
ms
16.5
(1) Parameters calculated from the best-fit curve from 0x0F to 0xFFF. The best-fit curve method is used to deliver coefficients "a" and "b"
of the first-order equation: y = a + bx. VDAC12_xOUT = EO + (1 + EG) × (VeREF+/4095) × DAC12_xDAT, DAC12IR = 1.
(2) The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON
(3) The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with
DAC12AMPx = {0, 1}. TI recommends configuring the DAC12 module before initiating calibration. Port activity during calibration may
affect accuracy and is not recommended.
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Section 8.8.13.3 lists the output specifications of the DAC.
8.8.13.3 12-Bit DAC, Output Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
No load, VeREF+ = AVCC
,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
0
0.005
No load, VeREF+ = AVCC
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
,
AVCC
0.05
–
AVCC
Output voltage
range(1) (see Figure
8-20)
VO
2.2 V, 3.6 V
V
RLoad = 3 kΩ, VeREF+ = AVCC
,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
0
0.1
RLoad = 3 kΩ, VeREF+ = AVCC
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
,
AVCC
0.13
–
AVCC
Maximum DAC12
load capacitance
CL(DAC12)
2.2 V, 3.6 V
2.2 V, 3.6 V
100
pF
DAC12AMPx = 2, DAC12_xDAT = 0FFFh,
VO/P(DAC12) > AVCC – 0.3
–1
Maximum DAC12
load current
IL(DAC12)
mA
DAC12AMPx = 2, DAC12_xDAT = 0h,
VO/P(DAC12) < 0.3 V
1
250
250
6
RLoad = 3 kΩ, VO/P(DAC12) < 0.3 V,
DAC12AMPx = 2, DAC12_xDAT = 0h
150
150
Output resistance
(see Figure 8-20)
RLoad = 3 kΩ, VO/P(DAC12) > AVCC – 0.3 V,
DAC12_xDAT = 0FFFh
RO/P(DAC12)
2.2 V, 3.6 V
Ω
RLoad = 3 kΩ,
0.3 V ≤ VO/P(DAC12) ≤ AVCC – 0.3 V
(1) Data is valid after the offset calibration of the output amplifier.
RO/P(DAC12_x)
Max
RLoad
ILoad
AVCC
DAC12
2
CLoad = 100 pF
O/P(DAC12_x)
Min
0.3
AVCC – 0.3 V
VOUT
AVCC
Figure 8-20. DAC12_x Output Resistance Tests
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Section 8.8.13.4 lists the reference input specificaitons of the DAC.
8.8.13.4 12-Bit DAC, Reference Input Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DAC12IR = 0(1) (2)
VCC
MIN
TYP
MAX UNIT
AVCC / 3 AVCC + 0.2
AVCC AVCC + 0.2
Reference input voltage
range
VeREF+
2.2 V to 3.6 V
V
DAC12IR = 1(3) (4)
DAC12_0 DAC12IR =
DAC12_1 DAC12IR = 0
20
MΩ
DAC12_0 DAC12IR = 1,
DAC12_1 DAC12IR = 0
52
52
Ri(VREFBG), Reference input
Ri(VeREF+) resistance
DAC12_0 DAC12IR = 0,
DAC12_1 DAC12IR = 1
2.2 V, 3 V
kΩ
DAC12_0 DAC12IR =
DAC12_1 DAC12IR = 1,
DAC12_0 DAC12SREFx =
DAC12_1 DAC12SREFx(5)
26
(1) For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).
(2) The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / [3 × (1 + EG)].
(3) For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).
(4) The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / (1 + EG).
(5) When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel
and reduce the reference input resistance.
Section 8.8.13.5 and Section 8.8.13.6 list the dynamic specifications of the DAC.
8.8.13.5 12-Bit DAC, Dynamic Specifications
VREF = VCC, DAC12IR = 1 (see Figure 8-21 and Figure 8-22), over recommended ranges of supply voltage and
operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
DAC12AMPx = 0 → {2, 3, 4}
60
120
DAC12_xDAT = 800h,
ErrorV(O) < ±0.5 LSB(1)
(see Figure 8-21)
tON
DAC12 on time
DAC12AMPx = 0 → {5, 6}
DAC12AMPx = 0 → 7
DAC12AMPx = 2
2.2 V, 3 V
15
30
12
µs
µs
µs
6
100
40
200
80
DAC12_xDAT =
80h → F7Fh → 80h
tS(FS)
tS(C-C)
SR
Settling time, full scale
DAC12AMPx = 3, 5
DAC12AMPx = 4, 6, 7
DAC12AMPx = 2
2.2 V, 3 V
2.2 V, 3 V
15
30
5
DAC12_xDAT =
3F8h → 408h → 3F8h,
BF8h → C08h → BF8h
Settling time, code to
code
DAC12AMPx = 3, 5
DAC12AMPx = 4, 6, 7
DAC12AMPx = 2
2
1
0.05
0.35
1.50
0.35
1.10
5.20
DAC12_xDAT =
Slew rate
DAC12AMPx = 3, 5
DAC12AMPx = 4, 6, 7
2.2 V, 3 V
2.2 V, 3 V
V/µs
nV-s
80h → F7Fh → 80h(2)
DAC12_xDAT =
800h → 7FFh → 800h
Glitch energy
DAC12AMPx = 7
35
(1) RLoad and CLoad connected to AVSS (not AVCC/2) in Figure 8-21.
(2) Slew rate applies to output voltage steps ≥ 200 mV.
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Conversion 1
Conversion 2
1/2 LꢀS
Conversion 3
VOUT
DAC Output
Glitch
Energy
RLoad = 3 kW
ILoad
AVCC
2
1/2 LꢀS
CLoad = 100 pF
RO/P(DAC12.x)
tsettleLH
tsettleHL
Figure 8-21. Settling Time and Glitch Energy Testing
Conversion 1
Conversion 2
Conversion 3
VOUT
90%
90%
10%
10%
tSRLH
tSRHL
Figure 8-22. Slew Rate Testing
8.8.13.6 12-Bit DAC, Dynamic Specifications (Continued)
over recommended ranges of supply voltage and TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
40
3-dB bandwidth,
VDC = 1.5 V,
VAC = 0.1 VPP
(see Figure 8-23)
DAC12AMPx = {5, 6}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
BW–3dB
2.2 V, 3 V
180
550
kHz
DAC12AMPx = 7, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
DAC12_0DAT = 800h, No load,
DAC12_1DAT = 80h ↔ F7Fh, RLoad = 3 kΩ,
fDAC12_1OUT = 10 kHz at 50/50 duty cycle
–80
–80
Channel-to-channel crosstalk(1)
(see Figure 8-24)
2.2 V, 3 V
dB
DAC12_0DAT = 80h ↔ F7Fh, RLoad = 3 kΩ,
DAC12_1DAT = 800h, No load,
fDAC12_0OUT = 10 kHz at 50/50 duty cycle
(1) RLoad = 3 kΩ, CLoad = 100 pF
RLoad = 3 kW
ILoad
VeREF+
AVCC
2
DAC12_x
DACx
AC
DC
CLoad = 100 pF
Figure 8-23. Test Conditions for 3-dB Bandwidth Specification
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RLoad
ILoad
AVCC
2
DAC12_xDA
T
080h
080h
F7Fh
080h
F7Fh
DAC12_0
DAC0
VOUT
CLoad = 100 pF
RLoad
VREF+
VDAC12_yOUT
ILoad
VDAC12_xOUT
AVCC
2
DAC12_1
1/fToggle
DAC1
CLoad = 100 pF
Figure 8-24. Crosstalk Test Conditions
8.8.14 Operational Amplifier
Section 8.8.14.1 lists the characteristics of the OA.
8.8.14.1 Operational Amplifier, OA0, OA1, PGA Buffers
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
VCC
Analog supply voltage AVCC = DVCC, AVSS = DVSS = 0 V
2.2
20
3.6
24
V
External charge pump
CCPCAP
Required when charge pump is enabled
capacitor to AVSS.
22
1.6
nF
mA
μA
Charge pump peak
OARRI = 0h to 1h, ICP_LOAD = 0 μA
current
ICP_PEAK
ICP
Charge pump average
OARRI = 1h, ICP_LOAD = 100 μA
current
570(1)
710(1)
OARRI = 0h to 1h, ICP_LOAD = 0 μA,
Charge pump enable
time fast
AFE biases previously enabled and settled
which can be done with REFON=1 or other
modules requesting REFON.
tCP_EN_fast
50
75
μs
μs
OARRI = 0h to 1h, ICP_LOAD = 0 μA,
Includes AFE bias settling
Charge pump enable
time slow
tCP_EN_slow
Supply current, per
opamp
IO = 0 mA,
OARRI = 0h (charge pump disabled)
IOA
105(1)
±2
130(1)
μA
mV
VOS
Input offset voltage
Noninverting, unity gain
Noninverting, unity gain
Input offset voltage
temperature drift
dVOS/dT
±1
μV/°C
Input offset voltage
voltage drift
dVOS/dV
Cin
Noninverting, unity gain
±3
μV/V
Differential
4
6
pF
pF
Input capacitance
Common mode
Power supply rejection Noninverting, unity gain,
PSRR_DC
50
μV/V
V
ratio, DC
VINP = positive input of OA = 1 V
OARRI = 0h,
0.1
0.1
VCC - 1.0
VCC - 0.1
Noninverting, unity gain
Common mode
voltage range(2)
VCM
OARRI = 1h,
V
Noninverting, unity gain
Common mode
rejection ratio, DC
CMRR_DC
Over common-mode voltage range
110
dB
f = 100 Hz, OARRI = 0h or 1h
f = 50 kHz, OARRI = 0h or 1h
3.0 V
3.0 V
90
25
Input voltage noise
density
en
nV/√Hz
dB
Open-loop voltage
gain, DC
AOL
95
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over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
Gain-bandwidth
product
GBW
SR
CL = 100 pF, OAM = 1h
800
kHz
Noninverting, unity gain,
CL = 100 pF, OAM = 1h
Slew rate
0.4
5.3
5
V/μs
μs
Noninverting, unity gain,
2.0-V step, 0.1%, OAM = 1h
tSETTLE
VO
Settling time
3.0 V
Voltage output swing
from rail
–250 μA ≤ IO ≤ 250 μA,
Noninverting, unity gain (OAM = 1h)
55
7
mV
Noninverting, unity gain,
OAM = 0h transition to 1h,
AFE biases previously enabled and settled
which can be done with REFON = 1 or other
modules requesting REFON(3)
tEN_FAST
Enable time fast
3
μs
Noninverting,unity gain,
OARRI = 0h transition to 1h,
OAM = 0h transition to 1h,
Includes AFE bias and charge pump
settling(3)
tEN_SLOW
Enable time slow
Disable time
190
0.4
225
μs
μs
tDIS
(1) See Section 8.8.14.2 to calculate total current from OA for different use cases.
(2) The common-mode input range is measured with the OA in a unity-gain source-follower configuration. The input signal is swept from 0
V to VCC, and the output of the OA is monitored. The minimum and maximum values represent when the input and output differ more
than 10 mV, not including the offset, VOS
.
(3) The AFE bias is used by several modules including the OA charge pump, OA, and CTSD16. Any of these modules will request the
AFE bias when enabled. The AFE bias is generated by the REF module, so enabling the REF module also enables the AFE bias.
Section 8.8.14.2 explains how to compute the total current, ITOTAL, when the OA and associated modules are
used. See Table 8-1 for a similar table for the CTSD16. A "yes" means it must be included in computing ITOTAL
.
As an example, assume that the application uses the CTS16D in rail-to-rail input mode (CTSD16RRI = 1) with
the internal reference (CTSD16REFS = 1) and OA0 and OA1 are enabled in rail-to-rail input modes, OARRI = 1.
The total current, ITOTAL, would be computed as follows:
ITOTAL = ICTSD16 + ICTSD16CLK+ ICP + IREFBG + 2 × IOA
700
650
600
550
500
450
400
350
300
250
200
150
100
160
140
120
100
80
60
40
20
0
50
0
0
0.5
1
1.5
2
2.5
Offset Voltage Drift (µV/°C)
3
3.5
4
4.5
0.4
0.6
0.8
1
1.2
1.5
1.6
1.8
2
2.2
2.4
2.6
Offset Voltage (mV)
Figure 8-26. OA Offset Voltage Drift Sample
Production Distribution
Figure 8-25. OA Offset Voltage Sample Production
Distribution
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8.8.14.2 OA, Current Calculation
(1)
(2)
(3)
USE CASE NAME
USE CASE DETAILS
IOA
yes
yes
ICTSD16CLK
no
ICP
no
IREF
OA
OARRI = 0
OARRI = 1
yes
yes
OA with rail-to-rail input
yes
yes
(CTSD16SC = 0) AND
(CTSD16RRI = 1) AND
(CTSD16RRIBURST = 0) OR
((OARRI = 1 (for any OA))
AND (OAM = 0))
Rail-to-rail input up, module off
no
yes
yes
yes
(1) Count this current only once no matter how many modules use it. CTSD16 and the charge pump also use this. This current is listed in
Section 8.8.11.1.
(2) Count this current only once no matter how many modules use it. CTSD16 also uses this when rail-to-rail inputs are selected.
(3) Count this current only once no matter how many modules use it. This current is listed in Section 8.8.14.1. If IREFBG is used, that
includes the IREF current.
8.8.15 Switches
Section 8.8.15.1 lists the characteristics of the ground switches.
8.8.15.1 Ground Switches (GSW0A, GSW0B, GSW1A, GSW1B)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VCC
ILKG
Supply voltage
2.2
3.6
V
TA = 0°C to 60°C
±0.25
Input leakage(1)
nA
TA = –40°C to 85°C
±50
100
IIN
Input current switch to AVSS
0
µA
Ω
IIN = 100 µA,
TA = –40°C to 85°C
RON
Switch ON resistance with switch closed
9.5
18.5
TA = –40°C to 85°C,
Input signal frequency < 100 Hz
ROFF
Switch OFF resistance with switch open
100
MΩ
µs
tON/OFF Enable or disable time
TA = –40°C to 85°C
0.25
(1) Ground switches are shared with general-purpose I/Os. This leakage includes all leakage seen at the device pin, not only leakage
caused by the switch itself.
4
DVCC = 2.2 V
DVCC = 3 V
DVCC = 3.6 V
3.5
3
2.5
2
1.5
1
0.5
0
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85
Temperature (°C)
Average of three typical devices
Figure 8-27. Ground Switch Input Leakage Current vs Temperature
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Section 8.8.15.2 lists the characteristics of the OA switches.
8.8.15.2 Operational Amplifier Switches
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VCC
ILKG
Supply voltage
2.2
3.6
V
TA = 0°C to 60°C
±0.25
Input leakage(1)
nA
TA = –40°C to 85°C
±50
100
IIN
Input current through switch
0
µA
kΩ
IIN = 100 µA,
TA = –40°C to 85°C
RON
Switch ON resistance with switch closed(2)
1
TA = –40°C to 85°C,
Input signal frequency < 100 Hz
ROFF
Switch OFF resistance with switch open
100
MΩ
µs
tON/OFF Enable or disable time
TA = –40°C to 85°C
0.45
(1) This leakage includes all leakage seen at the device pin, not only leakage caused by the switch itself. It assumes a total of five
switches present and a shared digital I/O.
(2) The resistance varies with input voltage range. This resistance represents the peak resistance at the worst case input range (see
Figure 8-29).
0.30
0.25
0.20
0.15
0.10
0.05
0.00
-0.05
1400
1200
1000
800
600
400
200
0
DVCC = 2.2 V
DVCC = 2.3 V
DVCC = 3 V
DVCC = 3.6 V
TA = –40°C
TA = 25°C
TA = 85°C
0.2
0.6
1.0
1.4
1.8
2.2
2.6
3.0
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Temperature (°C)
Common-Mode Voltage (V)
Average of three typical devices
Average of three typical devices
Figure 8-28. OA Switch Input Leakage Current vs
Temperature
Figure 8-29. OA Switch RON vs Common-Mode
Voltage
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8.8.16 Comparator
Section 8.8.16.1 lists the characteristics of the comparator.
8.8.16.1 Comparator_B
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
VCC
Supply voltage
1.8
3.6
40
50
65
V
1.8 V
2.2 V
3 V
CBPWRMD = 00, CBON = 1,
CBRSx = 00
30
40
Comparator operating supply
IAVCC_COMP current into AVCC, Excludes
reference resistor ladder
µA
CBPWRMD = 01, CBON = 1,
CBRSx = 00
2.2 V, 3 V
2.2 V, 3 V
10
30
CBPWRMD = 10, CBON = 1,
CBRSx = 00
0.5
1.3
Quiescent current of resistor
ladder into AVCC, Includes
REF module current
CBREFACC = 1, CBREFLx = 01,
CBRSx = 10, REFON = 0, CBON = 0
IAVCC_REF
2.2 V, 3 V
10
22
µA
VIC
Common mode input range
0
–20
–10
VCC – 1
20
V
CBPWRMD = 00
VOFFSET
CIN
Input offset voltage
mV
CBPWRMD = 01 or 10
10
Input capacitance
5
3
pF
kΩ
On (switch closed)
4
RSIN
Series input resistance
Off (switch open)
50
MΩ
CBPWRMD = 00, CBF = 0
CBPWRMD = 01, CBF = 0
CBPWRMD = 10, CBF = 0
450
600
50
ns
µs
Propagation delay, response
time
tPD
CBPWRMD = 00, CBON = 1, CBF = 1,
CBFDLY = 00
0.35
0.6
1.0
1.8
0.6
1.0
1.8
3.4
1
1.5
1.8
3.4
6.5
2
CBPWRMD = 00, CBON = 1, CBF = 1,
CBFDLY = 01
Propagation delay with filter
active
tPD,filter
µs
CBPWRMD = 00, CBON = 1, CBF = 1,
CBFDLY = 10
CBPWRMD = 00, CBON = 1, CBF = 1,
CBFDLY = 11
CBON = 0 → 1,
CBPWRMD = 00 or 01
tEN_CMP
Comparator enable time
µs
µs
CBON = 0 → 1,
CBPWRMD = 10
100
1.5
tEN_REF
Resistor reference enable time CBON = 0 → 1
1.0
Temperature coefficient of
VCB_REF
ppm/
°C
TCCB_REF
50
VIN ×
VIN ×
VIN ×
Reference voltage for a given VIN = reference into resistor ladder,
VCB_REF
(n + 0.5) / (n + 1) / (n + 1.5) /
32 32 32
V
tap
n = 0 to 31
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8.8.17 USB
Section 8.8.17.1 lists the characteristics of PU.0 and PU.1.
8.8.17.1 Ports PU.0 and PU.1
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VUSB = 3.3 V ±10%, IOH = –25 mA
VUSB = 3.3 V ±10%, IOL = 25 mA
VUSB = 3.3 V ±10%
MIN
MAX
UNIT
VOH High-level output voltage (see Figure 8-31)
VOL Low-level output voltage (see Figure 8-30)
2.4
V
V
V
V
0.4
VIH
VIL
High-level input voltage (see Figure 8-32)
Low-level input voltage (see Figure 8-32)
2.0
VUSB = 3.3 V ±10%
0.8
90
80
70
60
50
40
30
20
10
VCC = 3.0 V
TA = 25ºC
VCC = 3.0 V
TA = 85ºC
VCC = 1.8 V
TA = 25ºC
VCC = 1.8 V
TA = 85ºC
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
V
OL - Low-Level Output Voltage - V
Figure 8-30. Ports PU.0, PU.1 Typical Low-Level Output Characteristics
0
-10
-20
-30
VCC = 1.8 V
TA = 85ºC
-40
-50
VCC = 3.0 V
TA = 85ºC
-60
-70
-80
-90
VCC = 1.8 V
TA = 25ºC
VCC = 3.0 V
TA = 25ºC
0.5
1
1.5
2
2.5
3
VOH - High-Level Output Voltage - V
Figure 8-31. Ports PU.0, PU.1 Typical High-Level Output Characteristics
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2.0
TA = 25°C, 85°C
1.8
VIT+, postive-going input threshold
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
VIT–, negative-going input threshold
0.0
1.8
2.2
2.6
3
3.4
VUSB Supply Voltage, VUSB - V
Figure 8-32. Ports PU.0, PU.1 Typical Input Threshold Characteristics
Section 8.8.17.2 and Section 8.8.17.3 list the characteristics of the DP and DM ports.
8.8.17.2 USB Output Ports DP and DM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
D+, D– single ended
D+, D– single ended
D+, D– impedance
Rise time
TEST CONDITIONS
MIN
2.8
0
MAX UNIT
VOH
USB 2.0 load conditions
USB 2.0 load conditions
3.6
0.3
44
V
V
VOL
Z(DRV)
tRISE
tFALL
Including external series resistor of 27 Ω
28
4
Ω
Full speed, differential, CL = 50 pF, 10%/90%, Rpu on D+
Full speed, differential, CL = 50 pF, 10%/90%, Rpu on D+
20
ns
ns
Fall time
4
20
8.8.17.3 USB Input Ports DP and DM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
MIN
MAX UNIT
V(CM)
Z(IN)
VCRS
VIL
Differential input common mode range
Input impedance
0.8
2.5
V
kΩ
V
300
1.3
Crossover voltage
2.0
Static SE input logic low level
Static SE input logic high level
Differential input voltage
0.8
V
VIH
2.0
0.2
V
VDI
V
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Section 8.8.17.4 lists the characteristics of the USB power system.
8.8.17.4 USB-PWR (USB Power System)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VLAUNCH VBUS detection threshold
3.75
5.5
V
V
VBUS
VUSB
V18
USB bus voltage
Normal operation
3.76
USB LDO output voltage
Internal USB voltage(1)
3.3
1.8
±9%
V
V
IUSB_EXT Maximum external current from VUSB terminal(2)
IDET
USB LDO current overload detection(3)
ISUSPEND Operating supply current into VBUS terminal(4)
USB LDO is on
12
100
250
mA
mA
µA
µF
nF
nF
60
USB LDO is on, USB PLL disabled
CBUS
CUSB
C18
VBUS terminal recommended capacitance
VUSB terminal recommended capacitance
V18 terminal recommended capacitance
4.7
220
220
Within 2%,
recommended capacitances
tENABLE
RPUR
Settling time VUSB and V18
2
ms
Ω
Pullup resistance of PUR terminal
70
110
150
(1) This voltage is for internal use only. No external DC loading should be applied.
(2) This represents additional current that can be supplied to the application from the VUSB terminal beyond the needs of the USB
operation.
(3) A current overload is detected when the total current supplied from the USB LDO, including IUSB_EXT, exceeds this value.
(4) Does not include current contribution of Rpu and Rpd as outlined in the USB specification.
Section 8.8.17.5 lists the characteristics of the USB PLL.
8.8.17.5 USB-PLL (USB Phase-Locked Loop)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
MIN
TYP
MAX UNIT
IPLL
Operating supply current
PLL frequency
7
mA
MHz
MHz
ms
fPLL
48
fUPD
tLOCK
tJitter
PLL reference frequency
PLL lock time
1.5
3
2
PLL jitter
1000
ps
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8.8.18 LDO-PWR (LDO Power System)
Section 8.8.18.1 lists the characteristics of the LDP power system.
8.8.18.1 LDO-PWR (LDO Power System)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
LDO input detection threshold
LDO input voltage
TEST CONDITIONS
MIN
TYP
MAX UNIT
VLAUNCH
VLDOI
3.75
5.5
V
V
V
3.76
VLDO
LDO output voltage
3.3
±9%
LDOO terminal input voltage with LDO
disabled
VLDO_EXT
ILDOO
LDO disabled
1.8
60
3.6
V
Maximum external current from LDOO
terminal
LDO is on
20
mA
IDET
LDO current overload detection (1)
LDOI terminal recommended capacitance
LDOO terminal recommended capacitance
Settling time VLDO
100
mA
µF
nF
CLDOI
CLDOO
tENABLE
4.7
220
Within 2%, recommended capacitances
2
ms
(1) A current overload will be detected when the total current supplied from the LDO exceeds this value.
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8.8.19 Flash
Section 8.8.19.1 lists the characteristics of the flash memory.
8.8.19.1 Flash Memory
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TJ
MIN
TYP
MAX UNIT
DVCC(PGM/ERASE) Program and erase supply voltage
1.8
3.6
5
V
mA
IPGM
Average supply current from DVCC during program
3
6
6
IERASE
Average supply current from DVCC during erase
Average supply current from DVCC during mass erase or bank erase
Cumulative program time(1)
15
15
16
mA
IMERASE, IBANK
tCPT
mA
ms
Program and erase endurance
104
100
64
105
cycles
years
µs
tRetention
tWord
Data retention duration
25°C
Word or byte program time(2)
85
65
tBlock, 0
Block program time for first byte or word(2)
49
µs
Block program time for each additional byte or word, except for last byte or
word(2)
tBlock, 1–(N–1)
37
49
µs
tBlock, N
Block program time for last byte or word(2)
55
23
73
32
µs
tSeg Erase
Erase time for segment, mass erase, and bank erase when available(2)
ms
MCLK frequency in marginal read mode
(FCTL4.MGR0 = 1 or FCTL4.MGR1 = 1)
fMCLK,MGR
0
1
MHz
(1) The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming
methods: individual word or byte write and block write modes.
(2) These values are hardwired into the state machine of the flash controller.
8.8.20 Debug and Emulation
Section 8.8.20.1 lists the characteristics of the JTAG and SBW interface.
8.8.20.1 JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
MIN
TYP
MAX UNIT
fSBW
Spy-Bi-Wire input frequency
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
0
20 MHz
tSBW,Low
tSBW, En
tSBW,Rst
Spy-Bi-Wire low clock pulse duration
0.025
15
1
µs
µs
Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)(1)
Spy-Bi-Wire return to normal operation time
15
0
100
5
µs
2.2 V
3 V
MHz
fTCK
TCK input frequency (4-wire JTAG)(2)
Internal pulldown resistance on TEST
0
10 MHz
80 kΩ
Rinternal
2.2 V, 3 V
45
60
(1) Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
(2) fTCK may be restricted to meet the timing requirements of the module selected.
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9 Detailed Description
9.1 Overview
The MSP430FG6626 and MSP430FG6625 are microcontroller configurations with a high-performance 16-bit
ADC, dual 12-bit DACs, dual low-power operational amplifiers, a comparator (COMPB), two USCIs, USB 2.0, a
hardware multiplier (MPY32), DMA, four 16-bit timers, an RTC module with alarm capabilities, an LCD driver,
and up to 73 I/O pins.
The MSP430FG6426 and MSP430FG6425 are microcontroller configurations with a high-performance 16-bit
ADC, dual 12-bit DACs, dual low-power operational amplifiers, a comparator (COMPB), two USCIs, a 3.3-V
LDO, a hardware multiplier (MPY32), DMA, four 16-bit timers, an RTC module with alarm capabilities, an LCD
driver, and up to 73 I/O pins.
9.2 CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations,
other than program-flow instructions, are performed as register operations in conjunction with seven addressing
modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register
operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are
general-purpose registers (see Figure 9-1).
Peripherals are connected to the CPU using data, address, and control buses. Peripherals can be managed with
all instructions.
Program Counter
PC/R0
SP/R1
SR/CG1/R2
CG2/R3
R4
Stack Pointer
Status Register
Constant Generator
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
General-Purpose Register
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
Figure 9-1. Integrated CPU Registers
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9.3 Instruction Set
The instruction set consists of the original 51 instructions with three formats and seven address modes and
additional instructions for the expanded address range. Each instruction can operate on word and byte data.
Table 9-1 lists examples of the three types of instruction formats, and Table 9-2 lists the address modes.
Table 9-1. Instruction Word Formats
INSTRUCTION WORD FORMAT
Dual operands, source and destination
Single operands, destination only
EXAMPLE
ADD R4,R5
CALL R8
JNE
OPERATION
R4 + R5 → R5
PC → (TOS), R8 → PC
Jump-on-equal bit = 0
Relative jump, unconditional or conditional
Table 9-2. Address Mode Descriptions
ADDRESS MODE
Register
S(1)
✓
D(1)
✓
SYNTAX
EXAMPLE
OPERATION
MOV Rs,Rd
MOV R10,R11
R10 → R11
Indexed
✓
✓
MOV X(Rn),Y(Rm)
MOV EDE,TONI
MOV &MEM, &TCDAT
MOV @Rn,Y(Rm)
MOV 2(R5),6(R6)
M(2+R5) → M(6+R6)
M(EDE) → M(TONI)
M(MEM) → M(TCDAT)
M(R10) → M(Tab+R6)
Symbolic (PC relative)
Absolute
✓
✓
✓
✓
Indirect
✓
MOV @R10,Tab(R6)
MOV @R10+,R11
MOV #45,TONI
M(R10) → R11
R10 + 2 → R10
Indirect auto-increment
Immediate
✓
✓
MOV @Rn+,Rm
MOV #X,TONI
#45 → M(TONI)
(1) S = source, D = destination
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9.4 Operating Modes
The devices have one active mode and seven software-selectable low-power modes of operation. An interrupt
event can wake up the device from any of the low-power modes, service the request, and restore back to the
low-power mode on return from the interrupt program.
Software can configure the following operating modes:
•
Active mode (AM)
– All clocks are active
•
Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active, MCLK is disabled
– FLL loop control remains active
Low-power mode 1 (LPM1)
•
•
– CPU is disabled
– FLL loop control is disabled
– ACLK and SMCLK remain active, MCLK is disabled
Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO remains enabled
– ACLK remains active
•
•
Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO is disabled
– ACLK remains active
Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK, FLL loop control, and DCOCLK are disabled
– DC generator of the DCO is disabled
– Crystal oscillator is stopped
– Complete data retention
•
•
Low-power mode 3.5 (LPM3.5)
– Internal regulator disabled
– No data retention
– RTC enabled and clocked by low-frequency oscillator
– Wake-up input from RST/NMI, RTC_B, P1, P2, P3, and P4
Low-power mode 4.5 (LPM4.5)
– Internal regulator disabled
– No data retention
– Wake-up input from RST/NMI, P1, P2, P3, and P4
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9.5 Interrupt Vector Addresses
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see Table
9-3). The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 9-3. Interrupt Sources, Flags, and Vectors
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
System Reset
Power-up, External reset
Watchdog time-out, key violation
Flash memory key violation
WDTIFG, KEYV (SYSRSTIV)(1) (3)
Reset
0FFFEh
0FFFCh
0FFFAh
63, highest
System NMI
PMM
Vacant memory access
JTAG mailbox
SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,
VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG,
JMBOUTIFG (SYSSNIV)(1)
(Non)maskable
(Non)maskable
62
61
User NMI
NMI
Oscillator fault
NMIIFG, OFIFG, ACCVIFG, BUSIFG (SYSUNIV)
(1) (3)
Flash memory access violation
Comp_B
Comparator B interrupt flags (CBIV)(1) (2)
TB0CCR0 CCIFG0(2)
Maskable
Maskable
0FFF8h
0FFF6h
60
59
Timer TB0
TB0CCR1 CCIFG1 to TB0CCR6 CCIFG6,
TB0IFG (TBIV)(1) (2)
Timer TB0
Maskable
0FFF4h
58
Watchdog interval timer mode
USCI_A0 receive or transmit
USCI_B0 receive or transmit
CTSD16
WDTIFG
Maskable
Maskable
Maskable
Maskable
Maskable
0FFF2h
0FFF0h
0FFEEh
0FFECh
0FFEAh
57
56
55
54
53
UCA0RXIFG, UCA0TXIFG (UCA0IV)(1) (2)
UCB0RXIFG, UCB0TXIFG (UCB0IV)(1) (2)
CTSD16IFG0, CTSD16OVIFG0(1) (2)
TA0CCR0 CCIFG0(2)
Timer TA0
TA0CCR1 CCIFG1 to TA0CCR4 CCIFG4,
TA0IFG (TA0IV)(1) (2)
Timer TA0
Maskable
Maskable
0FFE8h
0FFE6h
52
51
USB_UBM(5)
LDO-PWR (6)
USB interrupts (USBIV)(1) (2)
LDOOFFIG, LDOONIFG, LDOOVLIFG
DMA0IFG, DMA1IFG, DMA2IFG, DMA3IFG,
DMA4IFG, DMA5IFG (DMAIV)(1) (2)
DMA
Maskable
Maskable
Maskable
0FFE4h
0FFE2h
0FFE0h
50
49
48
Timer TA1
Timer TA1
TA1CCR0 CCIFG0(2)
TA1CCR1 CCIFG1 to TA1CCR2 CCIFG2,
TA1IFG (TA1IV)(1) (2)
I/O Port P1
USCI_A1 receive or transmit
USCI_B1 receive or transmit
I/O port P2
P1IFG.0 to P1IFG.7 (P1IV)(1) (2)
UCA1RXIFG, UCA1TXIFG (UCA1IV)(1) (2)
UCB1RXIFG, UCB1TXIFG (UCB1IV)(1) (2)
P2IFG.0 to P2IFG.7 (P2IV)(1) (2)
Maskable
Maskable
Maskable
Maskable
Maskable
0FFDEh
0FFDCh
0FFDAh
0FFD8h
0FFD6h
47
46
45
44
43
LCD_B
LCD_B Interrupt Flags (LCDBIV)(1)
RTCRDYIFG, RTCTEVIFG, RTCAIFG,
RTC_B
Maskable
0FFD4h
42
RT0PSIFG, RT1PSIFG, RTCOFIFG (RTCIV)(1) (2)
DAC12_A
Timer TA2
DAC12_0IFG, DAC12_1IFG(1) (2)
TA2CCR0 CCIFG0(2)
Maskable
Maskable
0FFD2h
0FFD0h
41
40
TA2CCR1 CCIFG1 to TA2CCR2 CCIFG2,
TA2IFG (TA2IV)(1) (2)
Timer TA2
Maskable
0FFCEh
39
I/O port P3
I/O port P4
P3IFG.0 to P3IFG.7 (P3IV)(1) (2)
P4IFG.0 to P4IFG.7 (P4IV)(1) (2)
Maskable
Maskable
0FFCCh
0FFCAh
0FFC8h
⋮
38
37
36
⋮
Reserved
Reserved(4)
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Table 9-3. Interrupt Sources, Flags, and Vectors (continued)
SYSTEM
INTERRUPT
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
PRIORITY
0FF80h
0, lowest
(1) Multiple source flags
(2) Interrupt flags are in the module.
(3) A reset is generated if the CPU tries to fetch instructions from within peripheral space or vacant memory space.
(Non)maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable bit cannot disable it.
(4) Reserved interrupt vectors at addresses are not used in this device and can be used for regular program code if necessary. To
maintain compatibility with other devices, TI recommends reserving these locations.
(5) Only on devices with peripheral module USB (MSP430FG6626 and MSP430FG6625)
(6) Only on devices with peripheral module LDO-PWR (MSP430FG6426 and MSP430FG6425)
9.6 USB BSL
The devices MSP430FG6626 and MSP430FG6625 are preprogrammed with the USB BSL. Use of the USB BSL
requires external access to six pins (see Table 9-4). In addition to these pins, the application must support
external components necessary for normal USB operation; for example, the proper crystal on XT2IN and
XT2OUT, proper decoupling, and so on. For additional information, see the MSP430™ Flash Device Bootloader
(BSL) User's Guide.
Table 9-4. USB BSL Pin Requirements and Functions
DEVICE SIGNAL
RST/NMI/SBWTDIO
PU.0/DP
BSL FUNCTION
Entry sequence signal
USB data terminal DP
USB data terminal DM
USB pullup resistor terminal
USB bus power supply
USB ground supply
PU.1/DM
PUR
VBUS
VSSU
Note
The default USB BSL evaluates the logic level of the PUR pin after a BOR reset. If it is pulled high
externally, then the BSL is invoked. Therefore, unless the application is invoking the BSL, it is
important to keep PUR pulled low after a BOR reset, even if BSL or USB is never used. TI
recommends applying a 1-MΩ resistor to ground.
9.7 UART BSL
Devices without a USB module (MSP430FG642x) come preprogrammed with the UART BSL. A UART BSL is
also available for devices with the USB module (MSP430FG662x), and it can be programmed by the user into
the BSL memory by replacing the preprogrammed factory-supplied USB BSL. Use of the UART BSL requires
external access to six pins (see Table 9-5). For additional information, see the MSP430™ Flash Device
Bootloader (BSL) User's Guide.
Table 9-5. UART BSL Pin Requirements and Functions
DEVICE SIGNAL
BSL FUNCTION
Entry sequence signal
Entry sequence signal
Data transmit
RST/NMI/SBWTDIO
TEST/SBWTCK
P1.1
P1.2
VCC
VSS
Data receive
Power supply
Ground supply
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9.8 JTAG Operation
9.8.1 JTAG Standard Interface
The MSP430 family supports the standard JTAG interface, which requires four signals for sending and receiving
data. The JTAG signals are shared with general-purpose I/Os. The TEST/SBWTCK pin is used to enable the
JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430
development tools and device programmers. Table 9-6 lists the JTAG pin requirements. For further details on
interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide. For a
complete description of the features of the JTAG interface and its implementation, see MSP430 Programming
With the JTAG Interface.
Table 9-6. JTAG Pin Requirements and Functions
DEVICE SIGNAL
DIRECTION
FUNCTION
JTAG clock input
JTAG state control
JTAG data input, TCLK input
JTAG data output
Enable JTAG pins
External reset
PJ.3/TCK
IN
IN
PJ.2/TMS
PJ.1/TDI/TCLK
PJ.0/TDO
IN
OUT
IN
TEST/SBWTCK
RST/NMI/SBWTDIO
VCC
IN
Power supply
VSS
Ground supply
9.8.2 Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the two-wire Spy-Bi-Wire interface. Spy-
Bi-Wire can be used to interface with MSP430 development tools and device programmers. Table 9-7 lists the
Spy-Bi-Wire interface pin requirements. For further details on interfacing to development tools and device
programmers, see the MSP430 Hardware Tools User's Guide. For a complete description of the features of the
JTAG interface and its implementation, see MSP430 Programming With the JTAG interface.
Table 9-7. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
TEST/SBWTCK
RST/NMI/SBWTDIO
VCC
DIRECTION
FUNCTION
Spy-Bi-Wire clock input
Spy-Bi-Wire data input/output
Power supply
IN
IN, OUT
VSS
Ground supply
9.9 Flash Memory
The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the
flash memory include:
•
Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also
called information memory.
•
•
•
Segment A can be locked separately.
9.10 RAM
The RAM is made up of n sectors. Each sector can be completely powered down to save leakage; however, all
data is lost. Features of the RAM include:
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•
•
•
•
RAM has n sectors. The size of a sector can be found in Section 9.15.
Each sector 0 to n can be complete disabled; however, data retention is lost.
Each sector 0 to n automatically enters low-power retention mode when possible.
For devices that contain USB memory, the USB memory can be used as normal RAM if USB is not required.
9.11 Backup RAM
The backup RAM provides a limited number of bytes of RAM that are retained during LPMx.5 and during
operation from a backup supply if the Battery Backup System module is implemented.
There are 8 bytes of backup RAM. It can be word-wise accessed through the control registers BAKMEM0,
BAKMEM1, BAKMEM2, and BAKMEM3.
9.12 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. The peripherals can be
managed using all instructions. For complete module descriptions, see the MSP430F5xx and MSP430F6xx
Family User's Guide.
9.12.1 Digital I/O
Up to nine 8-bit I/O ports are implemented: P1 through P9 are complete except P5.2, and port PJ contains four
individual I/O ports.
•
•
•
•
•
•
•
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Programmable pullup or pulldown on all ports.
Programmable drive strength on all ports.
Edge-selectable interrupt input capability for all the eight bits of ports P1, P2, P3, and P4.
Read and write access to port-control registers is supported by all instructions.
Ports can be accessed byte-wise (P1 through P9) or word-wise (P1 through P8) in pairs (PA through PD).
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9.12.2 Port Mapping Controller
The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P2 (see
Table 9-8).
Table 9-8. Port Mapping Mnemonics and Functions
VALUE
PxMAPy MNEMONIC
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
0
PM_NONE
None
DVSS
Comparator_B output
PM_CBOUT
–
1
2
3
PM_TB0CLK
Timer TB0 clock input
–
Reserved
–
Reserved
PM_DMAE0
DMAE0 Input
–
PM_SVMOUT
PM_TB0OUTH
PM_TB0CCR0B
PM_TB0CCR1B
PM_TB0CCR2B
PM_TB0CCR3B
PM_TB0CCR4B
PM_TB0CCR5B
PM_TB0CCR6B
PM_UCA0RXD
PM_UCA0SOMI
PM_UCA0TXD
PM_UCA0SIMO
PM_UCA0CLK
PM_UCB0STE
PM_UCB0SOMI
PM_UCB0SCL
PM_UCB0SIMO
PM_UCB0SDA
PM_UCB0CLK
PM_UCA0STE
PM_MCLK
–
SVM output
Timer TB0 high impedance input TB0OUTH
Timer TB0 CCR0 capture input CCI0B
Timer TB0 CCR1 capture input CCI1B
Timer TB0 CCR2 capture input CCI2B
Timer TB0 CCR3 capture input CCI3B
Timer TB0 CCR4 capture input CCI4B
Timer TB0 CCR5 capture input CCI5B
Timer TB0 CCR6 capture input CCI6B
–
4
5
Timer TB0: TB0.0 compare output Out0
Timer TB0: TB0.1 compare output Out1
Timer TB0: TB0.2 compare output Out2
Timer TB0: TB0.3 compare output Out3
Timer TB0: TB0.4 compare output Out4
Timer TB0: TB0.5 compare output Out5
Timer TB0: TB0.6 compare output Out6
6
7
8
9
10
USCI_A0 UART RXD (Direction controlled by USCI – input)
11
12
13
14
15
16
USCI_A0 SPI slave out master in (direction controlled by USCI)
USCI_A0 UART TXD (Direction controlled by USCI – output)
USCI_A0 SPI slave in master out (direction controlled by USCI)
USCI_A0 clock input/output (direction controlled by USCI)
USCI_B0 SPI slave transmit enable (direction controlled by USCI – input)
USCI_B0 SPI slave out master in (direction controlled by USCI)
USCI_B0 I2C clock (open drain and direction controlled by USCI)
USCI_B0 SPI slave in master out (direction controlled by USCI)
USCI_B0 I2C data (open drain and direction controlled by USCI)
USCI_B0 clock input/output (direction controlled by USCI)
USCI_A0 SPI slave transmit enable (direction controlled by USCI – input)
17
–
MCLK
DVSS
18-30
Reserved
None
Disables the output driver and the input Schmitt-trigger to prevent parasitic cross currents when
applying analog signals.
31 (0FFh)(1)
PM_ANALOG
(1) The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are 5 bits wide, and the upper bits are ignored,
which results in a read value of 31.
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Table 9-9 lists the default settings for all pins that support port mapping.
Table 9-9. Default Mapping
PxMAPy
MNEMONIC
PIN
INPUT PIN FUNCTION
OUTPUT PIN FUNCTION
PM_UCB0STE,
PM_UCA0CLK
USCI_B0 SPI slave transmit enable (direction controlled by USCI – input),
USCI_A0 clock input/output (direction controlled by USCI)
P2.0/P2MAP0
P2.1/P2MAP1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4
P2.5/P2MAP5/R23
PM_UCB0SIMO,
PM_UCB0SDA
USCI_B0 SPI slave in master out (direction controlled by USCI),
USCI_B0 I2C data (open drain and direction controlled by USCI)
PM_UCB0SOMI,
PM_UCB0SCL
USCI_B0 SPI slave out master in (direction controlled by USCI),
USCI_B0 I2C clock (open drain and direction controlled by USCI)
PM_UCB0CLK,
PM_UCA0STE
USCI_B0 clock input/output (direction controlled by USCI),
USCI_A0 SPI slave transmit enable (direction controlled by USCI – input)
PM_UCA0TXD,
PM_UCA0SIMO
USCI_A0 UART TXD (direction controlled by USCI – output),
USCI_A0 SPI slave in master out (direction controlled by USCI)
PM_UCA0RXD,
PM_UCA0SOMI
USCI_A0 UART RXD (direction controlled by USCI – input),
USCI_A0 SPI slave out master in (direction controlled by USCI)
P2.6/P2MAP6/R03
PM_NONE
PM_NONE
-
-
DVSS
DVSS
P2.7/P2MAP7/LCDREF/R13
9.12.3 Oscillator and System Clock
The clock system in the MSP430FG662x and MSP430FG642x devices are supported by the Unified Clock
System (UCS) module that includes support for a 32-kHz watch crystal oscillator (in XT1 LF mode; XT1 HF
mode is not supported), an internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-
frequency oscillator (REFO), an integrated internal digitally controlled oscillator (DCO), and a high-frequency
crystal oscillator XT2. The UCS module is designed to meet the requirements of both low system cost and low
power consumption. The UCS module features digital frequency locked loop (FLL) hardware that, in conjunction
with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency.
The internal DCO provides a fast turnon clock source and stabilizes in 3 µs (typical). The UCS module provides
the following clock signals:
•
Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (XT1), a high-frequency crystal (XT2), the
internal low-frequency oscillator (VLO), the trimmed low-frequency oscillator (REFO), or the internal digitally-
controlled oscillator (DCO).
•
•
•
Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources available to
ACLK.
Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourced by
same sources available to ACLK.
ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, ACLK/8, ACLK/16, ACLK/32.
9.12.4 Power Management Module (PMM)
The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains
programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor
(SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit
provides the proper internal reset signal to the device during power on and power off. The SVS and SVM
circuitry detect if the supply voltage drops below a user-selectable level and supports both supply voltage
supervision (the device is automatically reset) and supply voltage monitoring (the device is not automatically
reset). SVS and SVM circuitry is available on the primary supply and the core supply.
9.12.5 Hardware Multiplier (MPY32)
The multiplication operation is supported by a dedicated peripheral module. The module performs operations
with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication as well as signed
and unsigned multiply-and-accumulate operations.
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9.12.6 Real-Time Clock (RTC_B)
The RTC_B module can be configured for real-time clock (RTC) or calendar mode providing seconds, minutes,
hours, day of week, day of month, month, and year. Calendar mode integrates an internal calendar which
compensates for months with less than 31 days and includes leap year correction. The RTC_B also supports
flexible alarm functions and offset-calibration hardware. The implementation on this device supports operation in
LPM3.5 mode and operation from a backup supply.
9.12.7 Watchdog Timer (WDT_A)
The primary function of the WDT_A module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be configured as an interval timer and can generate interrupts at selected time
intervals.
9.12.8 System Module (SYS)
The SYS module handles many of the system functions within the device. These include power-on reset and
power-up clear handling, NMI source selection and management, reset interrupt vector generators, bootloader
entry mechanisms, and configuration management (device descriptors). SYS also includes a data exchange
mechanism through JTAG called a JTAG mailbox that can be used in the application. Table 9-10 lists the SYS
module interrupt vector registers.
Table 9-10. System Module Interrupt Vector Registers
INTERRUPT VECTOR REGISTER
INTERRUPT EVENT
No interrupt pending
Brownout (BOR)
RST/NMI (BOR)
PMMSWBOR (BOR)
LPM3.5 or LPM4.5 wake up (BOR)
Security violation (BOR)
SVSL (POR)
WORD ADDRESS
OFFSET
00h
PRIORITY
02h
Highest
04h
06h
08h
0Ah
0Ch
0Eh
10h
SVSH (POR)
SVML_OVP (POR)
SVMH_OVP (POR)
PMMSWPOR (POR)
WDT time-out (PUC)
WDT key violation (PUC)
KEYV flash key violation (PUC)
Reserved
SYSRSTIV, System Reset
019Eh
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
Peripheral area fetch (PUC)
PMM key violation (PUC)
Reserved
22h to 3Eh
00h
Lowest
Highest
No interrupt pending
SVMLIFG
02h
SVMHIFG
04h
DLYLIFG
06h
SYSSNIV, System NMI
DLYHIFG
019Ch
08h
VMAIFG
0Ah
0Ch
0Eh
10h
JMBINIFG
JMBOUTIFG
SVMLVLRIFG
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Table 9-10. System Module Interrupt Vector Registers (continued)
INTERRUPT VECTOR REGISTER
INTERRUPT EVENT
SVMHVLRIFG
Reserved
WORD ADDRESS
OFFSET
PRIORITY
Lowest
12h
14h to 1Eh
00h
No interrupt pending
NMIFG
02h
Highest
OFIFG
04h
SYSUNIV, User NMI
019Ah
0198h
ACCVIFG
06h
BUSIFG
08h
Reserved
0Ah to 1Eh
00h
Lowest
No interrupt pending
USB wait state time-out
Reserved
SYSBERRIV, Bus Error
02h
Highest
Lowest
04h to 1Eh
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9.12.9 DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU intervention.
For example, the DMA controller can be used to move data from the ADC conversion memory to RAM. Using
the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system
power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or
from a peripheral.
The USB timestamp generator also uses the channel 0, 1, and 2 DMA trigger assignments (see Table 9-11). The
USB timestamp generator is available only on devices with the USB module (MSP430FG662x).
Table 9-11. DMA Trigger Assignments
CHANNEL
TRIGGER(1)
0
1
2
3
4
5
0
DMAREQ
1
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2CCR0 CCIFG
TA2CCR2 CCIFG
TBCCR0 CCIFG
TBCCR2 CCIFG
Reserved
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
UCA0RXIFG
UCA0TXIFG
UCB0RXIFG
UCB0TXIFG
UCA1RXIFG
UCA1TXIFG
UCB1RXIFG
UCB1TXIFG
CTSD16IFG0
DAC12_0IFG
DAC12_1IFG
USB FNRXD(2)
USB ready(2)
MPY ready
DMA5IFG
DMA0IFG
DMA1IFG
DMA2IFG
DMAE0
DMA3IFG
DMA4IFG
(1) Reserved DMA triggers may be used by other devices in the family. Reserved DMA triggers do not cause any DMA trigger event when
selected.
(2) Only on devices with peripheral module USB (MSP430FG662x), otherwise reserved (MSP430FG642x).
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9.12.10 Universal Serial Communication Interface (USCI)
The USCI modules are used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3- or 4-pin) and I2C, and asynchronous communication protocols such as
UART, enhanced UART with automatic baudrate detection, and IrDA. Each USCI module contains two portions,
A and B.
The USCI_An module provides support for SPI (3- or 4-pin), UART, enhanced UART, or IrDA.
The USCI_Bn module provides support for SPI (3- or 4-pin) or I2C.
The MSP430FG662x and MSP430FG642x include two complete USCI modules (n = 0 to 1).
9.12.11 Timer TA0
Timer TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. TA0 supports multiple
capture/compares, PWM outputs, and interval timing (see Table 9-12). It also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 9-12. Timer TA0 Signal Connections
INPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
OUTPUT PIN NUMBER
MODULE
BLOCK
PZ
ZCA, ZQW
PZ
ZCA, ZQW
34-P1.0
L5-P1.0
TA0CLK
ACLK
SMCLK
TA0CLK
TA0.0
DVSS
TACLK
ACLK
SMCLK
TACLK
CCI0A
CCI0B
GND
Timer
CCR0
CCR1
CCR2
CCR3
CCR4
NA
TA0
TA1
TA2
TA3
TA4
NA
34-P1.0
35-P1.1
L5-P1.0
M5-P1.1
35-P1.1
M5-P1.1
TA0.0
TA0.1
TA0.2
TA0.3
TA0.4
DVSS
DVCC
TA0.1
TA0.1
DVSS
VCC
36-P1.2
40-P1.6
J6-P1.2
J7-P1.6
CCI1A
CCI1B
GND
36-P1.2
40-P1.6
J6-P1.2
J7-P1.6
DVCC
TA0.2
TA0.2
DVSS
VCC
37-P1.3
41-P1.7
H6-P1.3
M7-P1.7
CCI2A
CCI2B
GND
37-P1.3
41-P1.7
H6-P1.3
M7-P1.7
DVCC
TA0.3
DVSS
VCC
38-P1.4
39-P1.5
M6-P1.4
L6-P1.5
CCI3A
CCI3B
GND
38-P1.4
39-P1.5
M6-P1.4
L6-P1.5
DVSS
DVCC
TA0.4
DVSS
VCC
CCI4A
CCI4B
GND
DVSS
DVCC
VCC
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9.12.12 Timer TA1
Timer TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA1 supports multiple
capture/compares, PWM outputs, and interval timing (see Table 9-13). It also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 9-13. Timer TA1 Signal Connections
INPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
OUTPUT PIN NUMBER
MODULE
BLOCK
PZ
ZCA, ZQW
PZ
ZCA, ZQW
42-P3.0
L7-P3.0
TA1CLK
ACLK
TACLK
ACLK
SMCLK
TACLK
CCI0A
CCI0B
GND
Timer
CCR0
NA
NA
SMCLK
TA1CLK
TA1.0
42-P3.0
43-P3.1
L7-P3.0
H7-P3.1
43-P3.1
44-P3.2
H7-P3.1
M8-P3.2
DVSS
TA0
TA1.0
DVSS
DVCC
VCC
44-P3.2
45-P3.3
M8-P3.2
L8-P3.3
TA1.1
CCI1A
DAC12_A
DAC12_0, DAC12_1
(internal)
CBOUT
(internal)
CCI1B
CCR1
CCR2
TA1
TA2
TA1.1
TA1.2
DVSS
DVCC
TA1.2
GND
VCC
CCI2A
45-P3.3
L8-P3.3
ACLK
(internal)
CCI2B
DVSS
DVCC
GND
VCC
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9.12.13 Timer TA2
Timer TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA2 supports multiple
capture/compares, PWM outputs, and interval timing (see Table 9-14). It also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 9-14. Timer TA2 Signal Connections
INPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
OUTPUT PIN NUMBER
MODULE
BLOCK
PZ
ZCA, ZQW
PZ
ZCA, ZQW
46-P3.4
J8-P3.4
TA2CLK
ACLK
TACLK
ACLK
SMCLK
TACLK
CCI0A
CCI0B
GND
Timer
CCR0
NA
NA
SMCLK
TA2CLK
TA2.0
46-P3.4
47-P3.5
J8-P3.4
M9-P3.5
47-P3.5
48-P3.6
M9-P3.5
L9-P3.6
DVSS
TA0
TA2.0
DVSS
DVCC
VCC
48-P3.6
49-P3.7
L9-P3.6
TA2.1
CCI1A
CBOUT
(internal)
CCI1B
CCR1
CCR2
TA1
TA2
TA2.1
TA2.2
DVSS
DVCC
TA2.2
GND
VCC
M10-P3.7
CCI2A
49-P3.7
M10-P3.7
ACLK
(internal)
CCI2B
DVSS
DVCC
GND
VCC
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9.12.14 Timer TB0
Timer TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. TB0 supports multiple
capture/compares, PWM outputs, and interval timing (see Table 9-15). It also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Table 9-15. Timer TB0 Signal Connections
INPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
OUTPUT PIN NUMBER
MODULE
BLOCK
PZ
ZCA, ZQW
PZ
ZCA, ZQW
58-P8.0
J11-P8.0
TB0CLK
TB0CLK
P2MAPx(1)
P2MAPx(1)
ACLK
ACLK
Timer
NA
NA
SMCLK
SMCLK
58-P8.0
J11-P8.0
TB0CLK
TB0CLK
P2MAPx(1)
P2MAPx(1)
50-P4.0
J9-P4.0
TB0.0
TB0.0
DVSS
DVCC
TB0.1
TB0.1
DVSS
DVCC
TB0.2
TB0.2
CCI0A
CCI0B
GND
50-P4.0
J9-P4.0
P2MAPx(1)
P2MAPx(1)
P2MAPx(1)
P2MAPx(1)
CCR0
CCR1
TB0
TB1
TB0.0
TB0.1
VCC
51-P4.1
M11-P4.1
CCI1A
CCI1B
GND
51-P4.1
M11-P4.1
P2MAPx(1)
P2MAPx(1)
P2MAPx(1)
P2MAPx(1)
VCC
52-P4.2
L10-P4.2
CCI2A
CCI2B
52-P4.2
L10-P4.2
P2MAPx(1)
P2MAPx(1)
P2MAPx(1)
P2MAPx(1)
DAC12_A
DAC12_0, DAC12_1
(internal)
CCR2
TB2
TB0.2
DVSS
GND
DVCC
TB0.3
TB0.3
DVSS
DVCC
TB0.4
TB0.4
DVSS
DVCC
TB0.5
TB0.5
DVSS
DVCC
TB0.6
TB0.6
DVSS
DVCC
VCC
CCI3A
CCI3B
GND
53-P4.3
M12-P4.3
53-P4.3
M12-P4.3
P2MAPx(1)
P2MAPx(1)
P2MAPx(1)
P2MAPx(1)
CCR3
CCR4
CCR5
CCR6
TB3
TB4
TB5
TB6
TB0.3
TB0.4
TB0.5
TB0.6
VCC
54-P4.4
L12-P4.4
CCI4A
CCI4B
GND
54-P4.4
L12-P4.4
P2MAPx(1)
P2MAPx(1)
P2MAPx(1)
P2MAPx(1)
VCC
55-P4.5
L11-P4.5
CCI5A
CCI5B
GND
55-P4.5
L11-P4.5
P2MAPx(1)
P2MAPx(1)
P2MAPx(1)
P2MAPx(1)
VCC
56-P4.6
K11-P4.6
CCI6A
CCI6B
GND
56-P4.6
K11-P4.6
P2MAPx(1)
P2MAPx(1)
P2MAPx(1)
P2MAPx(1)
VCC
(1) Timer functions are selectable by the port mapping controller.
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9.12.15 Comparator_B
The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions,
battery voltage supervision, and monitoring of external analog signals.
9.12.16 Signal Chain
All devices include all the building blocks to construct a complete signal chain. These blocks include two digital-
to-analog converter (DAC) channels, two integrated operational amplifiers (OAs), a sigma-delta analog-to-digital
converter (CTSD16), and low-ohmic switches (GSW). Figure 9-2 shows the various signal chain blocks and their
interconnections in the overall system.
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NR
Device Boundary
P5.0/VREFBG/VeREF+
CTSD16
P6.0/CB0/A0
P6.1/CB1/A1
P6.2/CB2/A2/OA0IP0
P6.3/CB3/A3/OA1IP0
P5.1/A4/DAC0
A0
A1
A2
A3
A4
A5
P5.6/A5/DAC1
Temp
Sense
REFON
A6
A7
A8
+
OR
CTSD16REFS AND CTD16SC
AVCC
Sense
BUF
Request to
shared reference
-
VBAT
Sense
Bandgap voltage
from shared reference
~1.16 V nominal
+
-
+
AD0+
AD0-
Delta
Sigma
PGA
+
AD1+
AD1-
-
BUF
-
AD2+
AD2-
AD3+
AD3-
VREFBG/VeREF+
AD4+
AD4-
AD4+
AD4-
DAC0
VREFBG/VeREF+
P6.2/CB2/A2/OA0IP0
OA0
PSW
4
DAC12_A
PSW0
PSW1
PSW2
PSW3
DAC12_0
12 bit
DAC12AMP>0 & !DAC12OPS
OAM
DAC12AMP>0 & DAC12OPS
+
NSW
P6.4/CB4/AD0+/OA0O
5
NSW0
P2.0/P2MAP0/DAC0
-
NSW1
NSW2
NSW3
NSW4
P5.1/A4/DAC0
P5.6/A5/DAC1
P6.5/CB5/AD0-/OA0IN0
P6.6/CB6/AD1+/G0SW0
P6.7/CB7/AD1-/G0SW1
GSW0
GSW1
PSW
OA1
4
PSW0
DAC12_1
12 bit
PSW1
PSW2
PSW3
DAC12AMP>0 & !DAC12OPS
OAM
DAC12AMP>0 & DAC12OPS
+
NSW
P7.4/CB8/AD2+/OA1O
5
NSW0
P2.1/P2MAP1/DAC1
P6.3/CB3/A3/OA1IP0
-
NSW1
NSW2
NSW3
NSW4
P7.5/CB9/AD2-/OA1IN0
P7.6/CB10/AD3+/G1SW0
P7.7/CB11/AD3-/G1SW1
GSW0
GSW1
Device Boundary
A. See the MSP430F5xx and MSP430F6xx Family User's Guide for additional module details.
Figure 9-2. Signal Chain
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9.12.16.1 CTSD16
The CTSD16 module integrates a single sigma-delta ADC with ten external inputs and four internal inputs. The
converter is designed with a fully differential analog input pair and a programmable gain amplifier input stage.
The converter is based on second-order over-sampling sigma-delta modulators and digital decimation filters. The
decimation filters are comb type filters with selectable oversampling ratios of up to 256.
The CTSD16 is proceeded by an analog multiplexer which is used for channel selection, followed by a unity gain
buffer stage useful when sampling high impedance sensors.
The CTSD16 can use as its reference the internal bandgap voltage from the REF module or an external
reference at the VeREF+ pin.
9.12.16.2 DAC12_A
The DAC12_A module is a 12-bit R-ladder voltage-output DAC. The DAC12_A can be used in 8-bit or 12-bit
mode, and can be used in conjunction with the DMA controller. When multiple DAC12_A modules are present,
they may be grouped together for synchronous operation. Two complete channels are available, DAC12_0 and
DAC12_1.
9.12.16.3 Operational Amplifiers (OA)
The device integrates two low-power operational amplifiers. The operational amplifiers can perform signal
conditioning of low-level analog signals before conversion by the ADC. Each operational amplifier can be
individually controlled by software.
9.12.16.4 Ground Switches (GSW)
The device integrates four low-ohmic switches to ground that are individually controllable in software. These can
switch in and out various components in the measurement system.
9.12.17 REF Voltage Reference
The reference module (REF) generates all of the critical reference voltages that can be used by the various
analog peripherals in the device.
9.12.18 CRC16
The CRC16 module produces a signature based on a sequence of entered data values and can be used for data
checking purposes. The CRC16 module signature is based on the CRC-CCITT standard.
9.12.19 LCD_B
The LCD_B driver generates the segment and common signals that are required to drive a liquid crystal display
(LCD). The LCD_B controller has dedicated data memories to hold segment drive information. Common and
segment signals are generated as defined by the mode. Static, 2-mux, 3-mux, and 4-mux LCDs are supported.
The module can provide a LCD voltage independent of the supply voltage with its integrated charge pump. It is
possible to control the level of the LCD voltage, and thus contrast, by software. The module also provides an
automatic blinking capability for individual segments.
9.12.20 USB Universal Serial Bus
The USB module is a fully integrated USB interface that is compliant with the USB 2.0 specification. The module
supports full-speed operation of control, interrupt, and bulk transfers. The module includes an integrated LDO,
PHY, and PLL. The PLL is highly flexible and can support a wide range of input clock frequencies. USB RAM,
when not used for USB communication, can be used by the system.
The USB module is only available on the MSP430FG662x devices.
9.12.21 LDO and PU Port
The integrated 3.3-V power system incorporates an integrated 3.3-V LDO regulator that allows the entire
MSP430 microcontroller to be powered from nominal 5-V LDOI when it is made available for the system.
Alternatively, the power system can supply power only to other components within the system, or it can be
unused altogether.
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The Port U pins (PU.0 and PU.1) function as general-purpose high-current I/O pins. These pins must be
configured together as either both inputs or both outputs. Port U is supplied by the LDOO rail. If the 3.3-V LDO is
not used in the system (disabled), the LDOO pin can be supplied externally.
The LDO-PWR module (LDO and PU port) is available only on the MSP430FG6426 and MSP430FG6425
devices.
9.12.22 Embedded Emulation Module (EEM) (L Version)
The EEM supports real-time in-system debugging. The L version of the EEM has the following features:
•
•
•
•
•
•
•
Eight hardware triggers or breakpoints on memory access.
Two hardware triggers or breakpoints on CPU register write access.
Up to ten hardware triggers can be combined to form complex triggers or breakpoints.
Two cycle counters
Sequencer
State storage
Clock control on module level
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9.13 Input/Output Diagrams
9.13.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
Figure 9-3 shows the port diagram. Table 9-16 summarizes the selection of the port function.
Pad Logic
S32...S39
LCDS32...LCDS39
P1REN.x
DVSS
DVCC
0
1
1
P1DIR.x
0
1
Direction
0: Input
1: Output
P1OUT.x
0
1
Module X OUT
P1.0/TA0CLK/ACLK/S39
P1.1/TA0.0/S38
P1.2/TA0.1/S37
P1.3/TA0.2/S36
P1.4/TA0.3/S35
P1.5/TA0.4/S34
P1.6/TA0.1/S33
P1.7/TA0.2/S32
P1DS.x
0: Low drive
1: High drive
P1SEL.x
P1IN.x
Bus
Keeper
EN
D
Module X IN
P1IRQ.x
P1IE.x
EN
Q
P1IFG.x
Set
P1SEL.x
P1IES.x
Interrupt
Edge
Select
Figure 9-3. Port P1 (P1.0 to P1.7) Diagram
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Table 9-16. Port P1 (P1.0 to P1.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P1.x)
x
FUNCTION
LCDS32 to
LCDS39
P1DIR.x
P1SEL.x
P1.0 (I/O)
Timer TA0.TA0CLK
ACLK
I: 0; O: 1
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
P1.0/TA0CLK/ACLK/S39
P1.1/TA0.0/S38
P1.2/TA0.1/S37
P1.3/TA0.2/S36
P1.4/TA0.3/S35
P1.5/TA0.4/S34
P1.6/TA0.1/S33
0
1
S39
X
P1.1 (I/O)
I: 0; O: 1
Timer TA0.CCI0A capture input
Timer TA0.0 output
S38
0
1
2
3
4
5
6
7
1
X
P1.2 (I/O)
I: 0; O: 1
Timer TA0.CCI1A capture input
Timer TA0.1 output
S37
0
1
X
P1.3 (I/O)
I: 0; O: 1
Timer TA0.CCI2A capture input
Timer TA0.2 output
S36
0
1
X
P1.4 (I/O)
I: 0; O: 1
Timer TA0.CCI3A capture input
Timer TA0.3 output
S35
0
1
X
P1.5 (I/O)
I: 0; O: 1
Timer TA0.CCI4A capture input
Timer TA0.4 output
S34
0
1
X
P1.6 (I/O)
I: 0; O: 1
Timer TA0.CCI1B capture input
Timer TA0.1 output
S33
0
1
X
P1.7 (I/O)
I: 0; O: 1
Timer TA0.CCI2B capture input
Timer TA0.2 output
S32
0
1
X
P1.7/TA0.2/S32
(1) X= don't care
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9.13.2 Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
Figure 9-4 shows the port diagram. Table 9-17 summarizes the selection of the port function.
0
Pad Logic
Dvss
1
2
0 if DAC12AMPx=0
1 if DAC12AMPx=1
2 if DAC12AMPx>1
From DAC12_A
to LCD_B
from LCD_B
P2REN.x
DVSS
DVCC
0
1
1
P2DIR.x
P2OUT.x
0
1
Direction
0: Input
1: Output
0
1
From Port Mapping
DAC12AMPx>0
P2.0/P2MAP0/DAC0
DAC12OPS
P2DS.x
0: Low drive
1: High drive
P2.1/P2MAP1/DAC1
P2.2/P2MAP2
P2.3/P2MAP3
P2.4/P2MAP4/R03
P2.5/P2MAP5
P2SEL.x
P2IN.x
P2.6/P2MAP6/LCDREF/R13
P2.7/P2MAP7/R23
From Port Mapping
EN
D
To Port Mapping
P2IRQ.x
P2IE.x
EN
Q
P2IFG.x
Set
P2SEL.x
P2IES.x
Interrupt
Edge
Select
Figure 9-4. Port P2 (P2.0 to P2.7) Diagram
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Table 9-17. Port P2 (P2.0 to P2.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P2.x)
x
FUNCTION
P2DIR.x
P2SEL.x
P2MAPx
DAC12OPS
DAC12AMPx
P2.0 (I/O)
I: 0; O: 1
0
1
X
X
0
Mapped secondary digital
function
P2.0/P2MAP0/DAC0
P2.1/P2MAP1/DAC1
0
X
≤ 19
= 31
0
DAC0
X
X
0
1
>1
0
P2.1 (I/O)
I: 0; O: 1
X
Mapped secondary digital
function
1
X
1
≤ 19
= 31
X
0
DAC1
X
X
0
1
>1
0
P2.2 (I/O)
I: 0; O: 1
X
P2.2/P2MAP2
P2.3/P2MAP3
2
3
Mapped secondary digital
function
X
I: 0; O: 1
X
1
0
1
0
1
≤ 19
≤ 19
X
X
X
X
X
0
0
0
0
0
P2.3 (I/O)
Mapped secondary digital
function
P2.4 (I/O)
I: 0; O: 1
X
Mapped secondary digital
function
P2.4/P2MAP4/R03
P2.5/P2MAP5
4
5
6
≤ 19
= 31
R03
X
1
0
X
X
0
0
P2.5 (I/O
I: 0; O: 1
Mapped secondary digital
function
X
I: 0; O: 1
X
1
0
1
≤ 19
X
X
X
0
0
0
P2.6 (I/O)
Mapped secondary digital
function
P2.6/P2MAP6/LCDREF/R13
≤ 19
= 31
LCDREF/R13
P2.7 (I/O)
X
1
0
X
X
0
0
I: 0; O: 1
Mapped secondary digital
function
P2.7/P2MAP7/R23
7
X
X
1
1
≤ 19
= 31
X
X
0
0
R23
(1) X= Don't care
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9.13.3 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
Figure 9-5 shows the port diagram. Table 9-18 summarizes the selection of the port function.
Pad Logic
S24...S31
LCDS24...LCDS31
P3REN.x
DVSS
DVCC
0
1
1
P3DIR.x
0
1
Direction
0: Input
1: Output
P3OUT.x
0
1
Module X OUT
P3.0/TA1CLK/CBOUT/S31
P3.1/TA1.0/S30
P3.2/TA1.1/S29
P3DS.x
0: Low drive
1: High drive
P3SEL.x
P3IN.x
P3.3/TA1.2/S28
P3.4/TA2CLK/SMCLK/S27
P3.5/TA2.0/S26
P3.6/TA2.1/S25
Bus
Keeper
EN
D
P3.7/TA2.2/S24
Module X IN
P3IRQ.x
P3IE.x
EN
Q
P3IFG.x
Set
P3SEL.x
P3IES.x
Interrupt
Edge
Select
Figure 9-5. Port P3 (P3.0 to P3.7) Diagram
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Table 9-18. Port P3 (P3.0 to P3.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P3.x)
x
FUNCTION
LCDS24 to
LCDS31
P3DIR.x
P3SEL.x
P3.0 (I/O)
Timer TA1.TA1CLK
CBOUT
I: 0; O: 1
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
1
1
0
0
0
1
0
P3.0/TA1CLK/CBOUT/S31
P3.1/TA1.0/S30
0
1
S31
X
P3.1 (I/O)
I: 0; O: 1
Timer TA1.CCI0A capture input
0
1
2
3
4
5
6
7
Timer TA1.0 output
1
S30
X
P3.2 (I/O)
I: 0; O: 1
Timer TA1.CCI1A capture input
0
P3.2/TA1.1/S29
Timer TA1.1 output
1
S29
X
P3.3 (I/O)
I: 0; O: 1
Timer TA1.CCI2A capture input
0
P3.3/TA1.2/S28
Timer TA1.2 output
1
S28
X
P3.4 (I/O)
I: 0; O: 1
Timer TA2.TA2CLK
0
P3.4/TA2CLK/SMCLK/S27
P3.5/TA2.0/S26
SMCLK
1
S27
X
P3.5 (I/O)
I: 0; O: 1
Timer TA2.CCI0A capture input
Timer TA2.0 output
S26
0
1
X
P3.6 (I/O)
I: 0; O: 1
Timer TA2.CCI1A capture input
Timer TA2.1 output
S25
0
P3.6/TA2.1/S25
1
X
P3.7 (I/O)
I: 0; O: 1
Timer TA2.CCI2A capture input
Timer TA2.2 output
S24
0
1
X
P3.7/TA2.2/S24
(1) X= don't care
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9.13.4 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
Figure 9-6 shows the port diagram. Table 9-19 summarizes the selection of the port function.
Pad Logic
S16...S23
LCDS16...LCDS23
P4REN.x
DVSS
DVCC
0
1
1
P4DIR.x
0
1
Direction
0: Input
1: Output
P4OUT.x
0
1
Module X OUT
P4.0/TB0.0/S23
P4.1/TB0.1/S22
P4.2/TB0.2/S21
P4.3/TB0.3/S20
P4.4/TB0.4/S19
P4.5/TB0.5/S18
P4.6/TB0.6/S17
P4DS.x
0: Low drive
1: High drive
P4SEL.x
P4IN.x
Bus
Keeper
EN
D
P4.7/TB0OUTH/SVMOUT/S16
Module X IN
P4IRQ.x
P4IE.x
EN
Q
P4IFG.x
Set
P4SEL.x
P4IES.x
Interrupt
Edge
Select
Figure 9-6. Port P4 (P4.0 to P4.7) Diagram
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Table 9-19. Port P4 (P4.0 to P4.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P4.x)
x
FUNCTION
LCDS16 to
LCDS23
P4DIR.x
P4SEL.x
P4.0 (I/O)
I: 0; O: 1
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
1
1
X
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
Timer TB0.CCI0A capture input
Timer TB0.0 output(2)
S23
0
P4.0/TB0.0/S23
P4.1/TB0.1/S22
P4.2/TB0.2/S21
P4.3/TB0.3/S20
P4.4/TB0.4/S19
P4.5/TB0.5/S18
P4.6/TB0.6/S17
0
1
X
P4.1 (I/O)
I: 0; O: 1
Timer TB0.CCI1A capture input
Timer TB0.1 output(2)
S22
0
1
2
3
4
5
6
7
1
X
P4.2 (I/O)
I: 0; O: 1
Timer TB0.CCI2A capture input
Timer TB0.2 output(2)
S21
0
1
X
P4.3 (I/O)
I: 0; O: 1
Timer TB0.CCI3A capture input
Timer TB0.3 output(2)
S20
0
1
X
P4.4 (I/O)
I: 0; O: 1
Timer TB0.CCI4A capture input
Timer TB0.4 output(2)
S19
0
1
X
P4.5 (I/O)
I: 0; O: 1
Timer TB0.CCI5A capture input
Timer TB0.5 output(2)
S18
0
1
X
P4.6 (I/O)
I: 0; O: 1
Timer TB0.CCI6A capture input
Timer TB0.6 output(2)
S17
0
1
X
P4.7 (I/O)
I: 0; O: 1
Timer TB0.TB0OUTH
SVMOUT
0
1
X
P4.7/TB0OUTH/ SVMOUT/S16
(1) X= don't care
S16
(2) Setting TB0OUTH causes all Timer_B configured outputs to be set to high impedance.
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9.13.5 Port P5 (P5.0) Input/Output With Schmitt Trigger
Figure 9-7 shows the port diagram. Table 9-20 summarizes the selection of the port function.
Pad Logic
To/From
Reference
P5REN.x
DVSS
DVCC
0
1
1
P5DIR.x
0
1
P5OUT.x
0
1
Module X OUT
P5.0/VREFBG/VeREF+
P5DS.x
0: Low drive
1: High drive
P5SEL.x
P5IN.x
Bus
Keeper
EN
D
Module X IN
Figure 9-7. Port P5 (P5.0) Diagram
Table 9-20. Port P5 (P5.0) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P5.x)
x
FUNCTION
P5DIR.x
P5SEL.x
REFOUT
REFON(5)
CTSD16REFS(6)
P5.0 (I/O)(2)
I: 0; O: 1
0
1
1
X
0
1
X
X
1
X
0
1
P5.0/VREFBG/VeREF+
0
VeREF+(3)
VREFBG(4)
X
X
(1) X = Don't care
(2) Default condition
(3) Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. An external voltage can be applied to VeREF+ and used as the reference for the CTSD16 or DAC.
(4) Setting the P5SEL.0 bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals. The internal reference voltage signal, VREFBG, is available at the pin.
(5) If a module is requesting a reference then REFON need not be set to 1 for VREFBG to be selected on P5.0.
(6) If CTSD16 is active, this bit must be set as shown in the table. Otherwise if set to 1, it will force VREFBG to be selected regardless of
REFOUT setting and if P5SEL.x is set to 0 it will cause possible contention on the I/O.
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9.13.6 Port P5 (P5.1 and P5.6) Input/Output With Schmitt Trigger
Figure 9-8 shows the port diagram. Table 9-21 summarizes the selection of the port function.
0
Pad Logic
Dvss
1
2
0 if DAC12AMPx=0
1 if DAC12AMPx=1
2 if DAC12AMPx>1
From DAC12_A
To ADC
INCHx = y
DAC12AMPx>0
DAC12OPS
P5REN.x
DVSS
DVCC
0
1
1
P5DIR.x
P5OUT.x
P5.1/A4/DAC0
P5.6/A5/DAC1
P5DS.x
0: Low drive
1: High drive
P5SEL.x
P5IN.x
Bus
Keeper
Figure 9-8. Port P5 (P5.1 and P5.6) Diagram
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Table 9-21. Port P5 (P5.1 and P5.6) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P6.x)
x
FUNCTION
P5DIR.x
P5SEL.x
DAC12OPS
DAC12AMPx
P5.1(I/O)
A4(2) (3)
DAC0
I: 0; O: 1
0
1
X
0
1
X
X
X
0
0
0
P5.1/A4/DAC0
1
X
X
>1
0
P5.6(I/O)
A5(2) (3)
DAC1
I: 0; O: 1
X
X
0
P5.6/A5/DAC1
1
X
X
0
>1
(1) X = Don't care
(2) Setting the P5SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals.
(3) The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
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9.13.7 Port P5 (P5.3 to P5.5, P5.7) Input/Output With Schmitt Trigger
Figure 9-9 shows the port diagram. Table 9-22 summarizes the selection of the port function.
Pad Logic
S40...S42
LCDS40...LCDS42
P5REN.x
DVSS
DVCC
0
1
1
P5DIR.x
0
1
Direction
0: Input
1: Output
P5OUT.x
0
1
Module X OUT
P5.3/COM1/S42
P5.4/COM2/S41
P5.5/COM3/S40
P5.7/DMAE0/RTCCLK
P5DS.x
0: Low drive
1: High drive
P5SEL.x
P5IN.x
Bus
Keeper
EN
D
Module X IN
Figure 9-9. Port P5 (P5.3 to P5.5 and P5.7) Diagram
Table 9-22. Port P5 (P5.3 to P5.5, P5.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P5.x)
x
FUNCTION
LCDS40 to
LCDS42
P5DIR.x
P5SEL.x
P5.3 (I/O)
COM1
I: 0; O: 1
0
1
0
0
1
0
0
1
0
0
1
1
0
X
P5.3/COM1/S42
3
X
S42
X
1
P5.4 (I/O)
COM2
I: 0; O: 1
0
P5.4/COM2/S41
4
5
7
X
X
S41
X
1
P5.5 (I/O)
COM3
I: 0; O: 1
0
P5.5/COM3/S40
X
X
S40
X
1
P5.7 (I/O)
DMAE0
RTCCLK
I: 0; O: 1
na
na
na
P5.7/DMAE0/RTCCLK
0
1
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9.13.8 Port P6 (P6.0 to P6.1) Input/Output With Schmitt Trigger
Figure 9-10 shows the port diagram. Table 9-23 summarizes the selection of the port function.
Pad Logic
To ADC
INCHx = y
To Comparator_B
From Comparator_B
CBPD.x
P6REN.x
DVSS
DVCC
0
1
1
P6DIR.x
P6OUT.x
P6.0/CB0/A0
P6.1/CB1/A1
P6DS.x
0: Low drive
1: High drive
P6SEL.x
P6IN.x
Bus
Keeper
Figure 9-10. Port P6 (P6.0 to P6.1) Diagram
Table 9-23. Port P6 (P6.0 to P6.1) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P6.x)
x
FUNCTION
P6DIR.x
I: 0; O: 1
P6SEL.x
CBPD.x
P6.0 (I/O)
CB0
0
X
1
0
X
1
0
1
X
0
1
X
P6.0/CB0/A0
0
X
A0(2) (3)
P6.1 (I/O)
CB1
X
I: 0; O: 1
P6.1/CB1/A1
1
X
X
A1(2) (3)
(1) X= Don't care
(2) Setting the P6SEL.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when applying
analog signals.
(3) The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
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9.13.9 Port P6 (P6.2 and P6.3) Input/Output With Schmitt Trigger
Figure 9-11 shows the port diagram. Table 9-24 summarizes the selection of the port function.
Pad Logic
To ADC
INCHx = y
To Comparator_B
From Comparator_B
CBPD.x
P6REN.x
DVSS
DVCC
0
1
1
P6DIR.x
P6OUT.x
P6.2/CB2/A2/OA0IP0
P6.3/CB3/A3/OA1IP1
P6DS.x
0: Low drive
1: High drive
P6SEL.x
P6IN.x
Bus
Keeper
+
OAx
-
Figure 9-11. Port P6 (P6.2 and P6.3) Diagram
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Table 9-24. Port P6 (P6.2 and P6.3) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P6.x)
x
FUNCTION
P6DIR.x
P6SEL.x(3)
CBPD.x(3)
P6.2 (I/O)
CB2
I: 0; O: 1
0
X
1
1
0
X
1
1
0
1
X
P6.2/CB2/A2/OA0IP0
2
A2 (2)
X
X
X
0
OA0IP0(3)
P6.2 (I/O)
CB3
X
I: 0; O: 1
X
X
X
1
P6.3/CB3/A3/OA1IP0
(1) X = Don't care
3
A3 (3)
X
X
OA1IP0(3)
(2) The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
(3) Setting the P6SEL.x bit or CBPD.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
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9.13.10 Port P6 (P6.4) Input/Output With Schmitt Trigger
Figure 9-12 shows the port diagram. Table 9-25 summarizes the selection of the port function.
Pad Logic
To ADC
INCHx = y
To Comparator_B
From Comparator_B
CBPD.x
OAMx
P6REN.x
DVSS
DVCC
0
1
1
P6DIR.x
P6OUT.x
P6.4/CB4/AD0+/OA0O
P6DS.x
0: Low drive
1: High drive
P6SEL.x
P6IN.x
Bus
Keeper
+
OA0
-
Figure 9-12. Port P6 (P6.4) Diagram
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Table 9-25. Port P6 (P6.4) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P6.x)
P6.4/CB4/AD0+/OA0O
(1) X = Don't care
x
FUNCTION
P6DIR.x
P6SEL.x(3)
CBPD.x(3)
OAMx
0(4)
P6.4 (I/O)
CB4
I: 0; O: 1
0
X
1
0
1
X
X
X
0(4)
4
AD0+ (2)
OA0O
X
X
0(4)
X
= 1(4)
(2) The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
(3) Setting the P6SEL.x bit, the CBPD.x bit, or the OAMx bit disables the output driver and the input Schmitt trigger to prevent parasitic
cross currents when applying analog signals.
(4) Setting OAMx = 0 disables the operational amplifier and its output is high impedance. Setting OAMx = 1 enables the operational
amplifier output. Because the operational amplifier output is shared with the ADC channel, selection of the respective ADC channel
allows for direct measurement of the output voltage of the amplifier.
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9.13.11 Port P6 (P6.5) Input/Output With Schmitt Trigger
Figure 9-13 shows the port diagram. Table 9-26 summarizes the selection of the port function.
Pad Logic
To ADC
INCHx = y
To Comparator_B
From Comparator_B
CBPD.x
P6REN.x
DVSS
DVCC
0
1
1
P6DIR.x
P6OUT.x
P6.5/CB5/AD0-/OA0IN0
P6DS.x
0: Low drive
1: High drive
P6SEL.x
P6IN.x
Bus
Keeper
+
OA0
-
Figure 9-13. Port P6 (P6.5) Diagram
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Table 9-26. Port P6 (P6.5) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P6.x)
P6.5/CB5/AD0-/OA0IN0
(1) X = Don't care
x
FUNCTION
P6DIR.x
P6SEL.x(3)
CBPD.x(3)
P6.5 (I/O)
CB5
I: 0; O: 1
0
X
1
1
0
1
X
X
X
5
AD0- (2)
OA0IN0(3)
X
X
(2) The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
(3) Setting the P6SEL.x bit or CBPD.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents when
applying analog signals.
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9.13.12 Port P6 (P6.6) Input/Output With Schmitt Trigger
Figure 9-14 shows the port diagram. Table 9-27 summarizes the selection of the port function.
Pad Logic
To ADC
INCHx = y
To Comparator_B
From Comparator_B
CBPD.x
GSW0
P6REN.x
DVSS
DVCC
0
1
1
P6DIR.x
P6OUT.x
P6.6/CB6/AD1+/G0SW0
P6DS.x
0: Low drive
1: High drive
P6SEL.x
P6IN.x
Bus
Keeper
+
OA0
-
GSW0
GSW1
to P6.7
Figure 9-14. Port P6 (P6.6) Diagram
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Table 9-27. Port P6 (P6.6) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P6.x)
P6.6/CB6/AD1+/G0SW0
(1) X = Don't care
x
FUNCTION
P6DIR.x
P6SEL.x(3)
CBPD.x(3)
GSW0(3)
P6.6 (I/O)
CB6
I: 0; O: 1
0
X
1
0
1
0
0
0
1
X
X
X
6
AD1+ (2)
G0SW0(4)
X
X
X
(2) The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
(3) Setting the P6SEL.x bit, the CBPD.x bit, or the GSW0 bit disables the output driver and the input Schmitt trigger to prevent parasitic
cross currents when applying analog signals.
(4) Setting GSW0 = 1 closes the switch and forces the pin to be switched to ground. All switches are independent of each other, so
different settings can impose different voltages on the pin. Application must ensure there are no conflicts.
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9.13.13 Port P6 (P6.7) Input/Output With Schmitt Trigger
Figure 9-15 shows the port diagram. Table 9-28 summarizes the selection of the port function.
Pad Logic
To ADC
INCHx = y
To Comparator_B
From Comparator_B
CBPD.x
GSW1
P6REN.x
DVSS
DVCC
0
1
1
P6DIR.x
P6OUT.x
P6.7/CB7/AD1-/G0SW1
P6DS.x
0: Low drive
1: High drive
P6SEL.x
P6IN.x
Bus
Keeper
+
OA0
-
GSW0
to P6.6
GSW1
Figure 9-15. Port P6 (P6.7) Diagram
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Table 9-28. Port P6 (P6.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P6.x)
P6.7/CB7/AD1-/G0SW1
(1) X = Don't care
x
FUNCTION
P6DIR.x
P6SEL.x(3)
CBPD.x(3)
GSW1(3)
P6.7 (I/O)
CB7
I: 0; O: 1
0
X
1
0
1
0
0
0
1
X
X
X
7
AD1- (2)
G0SW1(3)
X
X
X
(2) The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
(3) Setting GSW1 = 1 closes the switch and forces the pin to be switched to ground. All switches are independent of each other, so
different settings can impose different voltages on the pin. Application must ensure there are no conflicts.
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9.13.14 Port P7 (P7.2 and P7.3) Input/Output With Schmitt Trigger
Figure 9-16 and Figure 9-17 show the port diagrams. Table 9-29 summarizes the selection of the port function.
Pad Logic
To XT2
P7REN.2
DVSS
DVCC
0
1
1
P7DIR.2
P7OUT.2
0
1
P7.2/XT2IN
P7DS.2
0: Low drive
1: High drive
P7SEL.2
P7IN.2
Bus
Keeper
Figure 9-16. Port P7 (P7.2) Diagram
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Pad Logic
To XT2
P7REN.3
DVSS
DVCC
0
1
1
P7DIR.3
0
1
P7OUT.3
P7SEL.2
P7.3/XT2OUT
P7DS.3
0: Low drive
1: High drive
XT2BYPASS
P7SEL.3
P7IN.3
Bus
Keeper
Figure 9-17. Port P7 (P7.3) Diagram
Table 9-29. Port P7 (P7.2 and P7.3) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P7.x)
x
FUNCTION
P7DIR.x
P7SEL.2
P7SEL.3
XT2BYPASS
P7.2 (I/O)
I: 0; O: 1
0
1
1
0
1
1
X
X
X
X
X
X
X
0
1
X
0
1
P7.2/XT2IN
2
XT2IN crystal mode(2)
XT2IN bypass mode(2)
P7.3 (I/O)
X
X
I: 0; O: 1
P7.3/XT2OUT
3
XT2OUT crystal mode(3)
P7.3 (I/O)(3)
X
X
(1) X= Don't care
(2) Setting P7SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P7.2 is configured for crystal
mode or bypass mode.
(3) Setting P7SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P7.3 can be used as
general-purpose I/O.
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9.13.15 Port P7 (P7.4) Input/Output With Schmitt Trigger
Figure 9-18 shows the port diagram. Table 9-30 summarizes the selection of the port function.
Pad Logic
To ADC
INCHx = y
To Comparator_B
From Comparator_B
CBPD.x
OAMx
P7REN.x
DVSS
DVCC
0
1
1
P7DIR.x
P7OUT.x
P7.4/CB8/AD2+/OA1O
P7DS.x
0: Low drive
1: High drive
P7SEL.x
P7IN.x
Bus
Keeper
+
OA1
-
Figure 9-18. Port P7 (P7.4) Diagram
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Table 9-30. Port P7 (P7.4) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P6.x)
P7.4/CB8/AD2+/OA1O
(1) X = Don't care
x
FUNCTION
P6DIR.x
P7SEL.x(3)
CBPD.x(3)
OAMx(3)
0(3)
P7.4 (I/O)
CB8
I: 0; O: 1
0
X
1
0
1
X
X
X
0(3)
4
AD2+ (2)
OA1O
X
X
0(3)
X
1(3)
(2) The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
(3) Setting OAMx = 0 disables the operational amplifier and its output is high impedance. Setting OAMx = 1 enables the operational
amplifier output. Because the operational amplifier output is shared with the ADC channel, selection of the respective ADC channel
allows for direct measurement of the output voltage of the amplifier.
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9.13.16 Port P7 (P7.5) Input/Output With Schmitt Trigger
Figure 9-19 shows the port diagram. Table 9-31 summarizes the selection of the port function.
Pad Logic
To ADC
INCHx = y
To Comparator_B
From Comparator_B
CBPD.x
P7REN.x
DVSS
DVCC
0
1
1
P7DIR.x
P7OUT.x
P7.5/CB9/AD2-/OA1IN0
P7DS.x
0: Low drive
1: High drive
P7SEL.x
P7IN.x
Bus
Keeper
+
OA1
-
Figure 9-19. Port P7 (P7.5) Diagram
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Table 9-31. Port P7 (P7.5) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P7.x)
P7.5/CB9/AD2-/OAIN0
(1) X = Don't care
x
FUNCTION
P7DIR.x
P7SEL.x(3)
CBPD.x(3)
P7.5 (I/O)
CB9
I: 0; O: 1
0
X
1
1
0
1
X
X
X
5
AD2- (2)
OAIN0(3)
X
X
(2) The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
(3) Setting the P7SEL.x bit or the CBPD.x bit disables the output driver and the input Schmitt trigger to prevent parasitic cross currents
when applying analog signals.
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9.13.17 Port P7 (P7.6) Input/Output With Schmitt Trigger
Figure 9-20 shows the port diagram. Table 9-32 summarizes the selection of the port function.
Pad Logic
To ADC
INCHx = y
To Comparator_B
From Comparator_B
CBPD.x
GSW0
P7REN.x
DVSS
DVCC
0
1
1
P7DIR.x
P7OUT.x
P7.6/CB10/AD3+/G1SW0
P7DS.x
0: Low drive
1: High drive
P7SEL.x
P7IN.x
Bus
Keeper
+
OA1
-
GSW0
GSW1
to P7.7
Figure 9-20. Port P7 (P7.6) Diagram
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Table 9-32. Port P7 (P7.6) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P7.x)
P7.6/CB10/AD3+/G1SW0
(1) X = Don't care
x
FUNCTION
P6DIR.x
P7SEL.x(3)
CBPD.x(3)
GSW0(3)
P7.6 (I/O)
CB10
I: 0; O: 1
0
X
1
0
1
0
0
0
1
X
X
X
6
AD3+ (2)
G1SW0(4)
X
X
X
(2) The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
(3) Setting the P7SEL.x bit, the CBPD.x bit, or the GSW0 disables the output driver and the input Schmitt trigger to prevent parasitic cross
currents when applying analog signals.
(4) Setting GSW0 = 1 closes the switch and forces the pin to be switched to ground. All switches are independent of each other, so
different settings can impose different voltages on the pin. Application must ensure there are no conflicts.
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9.13.18 Port P7 (P7.7) Input/Output With Schmitt Trigger
Figure 9-21 shows the port diagram. Table 9-33 summarizes the selection of the port function.
Pad Logic
To ADC
INCHx = y
To Comparator_B
From Comparator_B
CBPD.x
GSW1
P7REN.x
DVSS
DVCC
0
1
1
P7DIR.x
P7OUT.x
P7.7/CB11/AD3-/G1SW1
P7DS.x
0: Low drive
1: High drive
P7SEL.x
P7IN.x
Bus
Keeper
+
OA1
-
GSW0
to P7.6
GSW1
Figure 9-21. Port P7 (P7.7) Diagram
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Table 9-33. Port P7 (P7.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P7.x)
P7.7/CB11/AD3-/G1SW1
(1) X = Don't care
x
FUNCTION
P6DIR.x
P7SEL.x(3)
CBPD.x(3)
GSW1(3)
P7.7 (I/O)
CB11
I: 0; O: 1
0
X
1
0
1
0
0
0
1
X
X
X
7
AD3- (2)
G1SW1(4)
X
X
X
(2) The ADC channel Ax is connected internally to AVSS if not selected by the respective INCHx bits.
(3) Setting the P7SEL.x bit, the CBPD.x bit, or the GSW1 bit disables the output driver and the input Schmitt trigger to prevent parasitic
cross currents when applying analog signals.
(4) Setting GSW1 = 1 closes the switch and forces the pin to be switched to ground. All switches are independent of each other, so
different settings can impose different voltages on the pin. Application must ensure there are no conflicts.
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9.13.19 Port P8 (P8.0 to P8.7) Input/Output With Schmitt Trigger
Figure 9-22 shows the port diagram. Table 9-34 summarizes the selection of the port function.
Pad Logic
S8...S15
LCDS8...LCDS15
P8REN.x
DVSS
DVCC
0
1
1
P8DIR.x
0
1
Direction
0: Input
1: Output
From module
0
1
P8OUT.x
Module X OUT
P8.0/TB0CLK/S15
P8DS.x
0: Low drive
1: High drive
P8.1/UCB1STE/UCA1CLK/S14
P8.2/UCA1TXD/UCA1SIMO/S13
P8.3/UCA1RXD/UCA1SOMI/S12
P8.4/UCB1CLK/UCA1STE/S11
P8.5/UCB1SIMO//UCB1SDA/S10
P8.6/UCB1SOMI/UCB1SCL/S9
P8.7/S8
P8SEL.x
P8IN.x
Bus
Keeper
EN
D
Module X IN
Figure 9-22. Port P8 (P8.0 to P8.7) Diagram
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Table 9-34. Port P8 (P8.0 to P8.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P9.x)
x
FUNCTION
P8DIR.x
P8SEL.x
LCDS8 to 16
P8.0 (I/O)
I: 0; O: 1
0
1
X
0
1
X
0
1
X
0
1
X
0
1
X
0
1
X
0
1
X
0
X
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
1
P8.0/TB0CLK/S15
0
Timer TB0.TB0CLK clock input
0
S15
X
P8.1 (I/O)
I: 0; O: 1
P8.1/UCB1STE/UCA1CLK/S14
P8.2/UCA1TXD/UCA1SIMO/S13
P8.3/UCA1RXD/UCA1SOMI/S12
P8.4/UCB1CLK/UCA1STE/S11
P8.5/UCB1SIMO/UCB1SDA/S10
P8.6/UCB1SOMI/UCB1SCL/S9
1
2
3
4
5
UCB1STE/UCA1CLK
X
S14
X
P8.2 (I/O)
I: 0; O: 1
UCA1TXD/UCA1SIMO
X
S13
X
P8.3 (I/O)
I: 0; O: 1
UCA1RXD/UCA1SOMI
X
S12
X
P8.4 (I/O)
I: 0; O: 1
UCB1CLK/UCA1STE
X
S11
X
P8.5 (I/O)
I: 0; O: 1
UCB1SIMO/UCB1SDA
X
S10
X
P8.6 (I/O)
I: 0; O: 1
6
7
UCB1SOMI/UCB1SCL
X
S9
X
I: 0; O: 1
X
P8.7 (I/O)
S8
P8.7/S8
(1) X= don't care
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9.13.20 Port P9 (P9.0 to P9.7) Input/Output With Schmitt Trigger
Figure 9-23 shows the port diagram. Table 9-35 summarizes the selection of the port function.
Pad Logic
S0...S7
LCDS0...LCDS7
P9REN.x
0
1
DVSS
DVCC
1
Direction
0: Input
1: Output
P9DIR.x
P9OUT.x
P9.0/S7
P9.1/S6
P9.2/S5
P9.3/S4
P9.4/S3
P9.5/S2
P9.6/S1
P9.7/S0
P9DS.x
0: Low drive
1: High drive
P9IN.x
Bus
Keeper
Figure 9-23. Port P9 (P9.0 to P9.7) Diagram
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Table 9-35. Port P9 (P9.0 to P9.7) Pin Functions
CONTROL BITS OR SIGNALS(1)
PIN NAME (P9.x)
x
FUNCTION
LCDS0 to
LCDS7
P9DIR.x
P9SEL.x
P9.0 (I/O)
S7
I: 0; O: 1
0
X
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
P9.0/S7
0
1
2
3
4
5
6
7
X
P9.1 (I/O)
S6
I: 0; O: 1
P9.1/S6
X
X
0
P9.2 (I/O)
S5
I: 0; O: 1
P9.2/S5
X
X
0
P9.3 (I/O)
S4
I: 0; O: 1
P9.3/S4
X
X
0
P9.4 (I/O)
S3
I: 0; O: 1
P9.4/S3
X
X
0
P9.5 (I/O)
S2
I: 0; O: 1
P9.5/S2
X
I: 0; O: 1
X
X
0
P9.6 (I/O)
S1
P9.6/S1
X
0
P9.7 (I/O)
S0
I: 0; O: 1
X
P9.7/S0
X
(1) X= don't care
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9.13.21 Port U (PU.0/DP, PU.1/DM, PUR) USB Ports for MSP430FG662x
Figure 9-24 shows the port diagram. Table 9-36 and Table 9-37 summarize the port function selection.
PUSEL
VUSB
VSSU
Pad Logic
PUOPE
0
1
USB output enable
PUOUT0
0
1
PU.0/DP
USB DP output
PUIN0
USB DP input
PUIPE
PUIN1
USB DM input
PUOUT1
0
1
PU.1/DM
USB DM output
VUSB
VSSU
Pad Logic
PUREN
PUR
“1”
PUSEL
PURIN
Figure 9-24. Port U (PU.0 and PU.1) Diagram
Table 9-36. Port U (PU.0/DP, PU.1/DM) Output Functions for MSP430FG662x
CONTROL BITS
PIN NAME
FUNCTION
PUSEL
PUDIR PUOUT1
PUOUT0
PU.1/DM
PU.0/DP
0
0
0
0
0
1
0
X
X
0
1
0
1
X
Hi-Z
0
Hi-Z
0
Outputs off
Outputs enabled
1
1
1
1
X
0
0
1
1
X
0
1
Outputs enabled
1
0
Outputs enabled
1
1
Outputs enabled
DM
DP
Direction set by USB module
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Table 9-37. Port U (PUR) Input Functions
CONTROL BITS
FUNCTION
PUSEL
PUREN
Input disabled
Pullup disabled
0
0
1
1
0
Input disabled
Pullup enabled
1
0
1
Input enabled
Pullup disabled
Input enabled
Pullup enabled
9.13.22 Port J (J.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
Figure 9-25 shows the port diagram. Table 9-38 summarizes the selection of the port function.
Pad Logic
PJREN.0
0
1
DVSS
DVCC
1
PJDIR.0
DVCC
0
1
PJOUT.0
0
1
From JTAG
PJ.0/TDO
PJDS.0
0: Low drive
1: High drive
From JTAG
PJIN.0
EN
D
Figure 9-25. Port PJ (PJ.0) Diagram
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9.13.23 Port J (J.1 to J.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
Figure 9-26 shows the port diagram. Table 9-38 summarizes the selection of the port function.
Pad Logic
PJREN.x
0
1
DVSS
DVCC
1
PJDIR.x
DVSS
0
1
PJOUT.x
0
1
From JTAG
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
PJDS.x
0: Low drive
1: High drive
From JTAG
PJIN.x
EN
D
To JTAG
Figure 9-26. Port PJ (PJ.1 to PJ.3) Diagram
Table 9-38. Port PJ (PJ.0 to PJ.3) Pin Functions
CONTROL BITS
OR SIGNALS(1)
PIN NAME (PJ.x)
x
FUNCTION
PJDIR.x
I: 0; O: 1
X
PJ.0 (I/O)(2)
TDO(3)
PJ.0/TDO
0
1
2
3
PJ.1 (I/O)(2)
TDI/TCLK(3) (4)
PJ.2 (I/O)(2)
TMS(3) (4)
I: 0; O: 1
X
PJ.1/TDI/TCLK
PJ.2/TMS
I: 0; O: 1
X
PJ.3 (I/O)(2)
TCK(3) (4)
I: 0; O: 1
X
PJ.3/TCK
(1) X= don't care
(2) Default condition
(3) The pin direction is controlled by the JTAG module.
(4) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are don't care.
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9.14 Device Descriptors
Table 9-39 summarizes the contents of the device descriptor tag-length-value (TLV) structure.
Table 9-39. Device Descriptor Table
VALUE
SIZE
(bytes)
DESCRIPTION
Info length
ADDRESS
FG6626
06h
FG6625
FG6426
06h
FG6425
01A00h
01A01h
01A02h
01A04h
01A06h
01A07h
01A08h
01A09h
01A0Ah
01A0Eh
01A10h
01A12h
01A14h
01A15h
01A16h
01A18h
01A1Ah
01A1Ch
1
1
2
2
1
1
1
1
4
2
2
2
1
1
2
2
2
2
06h
06h
CRC length
CRC value
06h
06h
06h
06h
Per unit
8234h
Per unit
Per unit
08h
Per unit
8235h
Per unit
Per unit
08h
Per unit
Per unit
8237h
Per unit
Per unit
08h
Info Block
Device ID
8236h
Per unit
Per unit
08h
Hardware revision
Firmware revision
Die record tag
Die record length
Lot/wafer ID
0Ah
0Ah
0Ah
0Ah
Per unit
Per unit
Per unit
Per unit
1Dh
Per unit
Per unit
Per unit
Per unit
1Dh
Per unit
Per unit
Per unit
Per unit
1Dh
Per unit
Per unit
Per unit
Per unit
1Dh
Die Record
Die X position
Die Y position
Test results
CTSD16 calibration tag
CTSD16 calibration length
CTSD16 gain factor gain = 1
CTSD16 gain factor gain = 16
CTSD16 offset gain = 1
CTSD16 offset gain = 16
0Ch
0Ch
0Ch
0Ch
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
CTSD16 Calibration
CTSD16 internal reference
temperature sensor 30°C
01A1Eh
01A20h
2
2
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
Per unit
CTSD16 internal reference
temperature sensor 85°C
9.15 Memory
Table 9-40 summarizes the memory organization for all devices.
Table 9-40. Memory Organization
VALUE(1) (2)
MSP430FG6626
MSP430FG6625
MSP430FG6426
MSP430FG6425
Memory (flash)
Main: interrupt vector
128KB
00FFFFh to 00FF80h
64KB
128KB
64KB
Total Size
Bank 3
00FFFFh to 00FF80h 00FFFFh to 00FF80h 00FFFFh to 00FF80h
32KB
0243FFh to 01C400h
32KB
0243FFh to 01C400h
NA
NA
NA
NA
32KB
01C3FFh to 014400h
32KB
01C3FFh to 014400h
Bank 2
Main: code memory
32KB
0143FFh to 00C400h
32KB
0143FFh to 00C400h
32KB
0143FFh to 00C400h
32KB
0143FFh to 00C400h
Bank 1
32KB
00C3FFh to 004400h
32KB
00C3FFh to 004400h
32KB
00C3FFh to 004400h
32KB
00C3FFh to 004400h
Bank 0
2KB
2KB
2KB
2KB
Sector 3
Sector 2
Sector 1
0043FFh to 003C00h
0043FFh to 003C00h
0043FFh to 003C00h
0043FFh to 003C00h
2KB
2KB
2KB
2KB
RAM
003BFFh to 003400h
003BFFh to 003400h
003BFFh to 003400h
003BFFh to 003400h
2KB
2KB
2KB
2KB
0033FFh to 002C00h
0033FFh to 002C00h
0033FFh to 002C00h
0033FFh to 002C00h
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Table 9-40. Memory Organization (continued)
VALUE(1) (2)
MSP430FG6626
MSP430FG6625
MSP430FG6426
MSP430FG6425
2KB
2KB
2KB
2KB
Sector 0
Sector 7
Sector 7
A
002BFFh to 002400h
002BFFh to 002400h
002BFFh to 002400h
002BFFh to 002400h
2KB
2KB
RAM(3)
NA
NA
0023FFh to 001C00h
0023FFh to 001C00h
2KB
2KB
USB RAM(4)
NA
NA
0023FFh to 001C00h
0023FFh to 001C00h
128 bytes
001BFFh to 001B80h
128 bytes
128 bytes
128 bytes
001BFFh to 001B80h 001BFFh to 001B80h 001BFFh to 001B80h
128 bytes
001B7Fh to 001B00h
128 bytes
001B7Fh to 001B00h
128 bytes
001B7Fh to 001B00h
128 bytes
001B7Fh to 001B00h
B
TI factory memory
(ROM)
128 bytes
001AFFh to 001A80h
128 bytes
128 bytes
128 bytes
C
001AFFh to 001A80h 001AFFh to 001A80h 001AFFh to 001A80h
128 bytes
001A7Fh to 001A00h
128 bytes
001A7Fh to 001A00h
128 bytes
001A7Fh to 001A00h
128 bytes
001A7Fh to 001A00h
D
128 bytes
0019FFh to 001980h
128 bytes
0019FFh to 001980h
128 bytes
0019FFh to 001980h
128 bytes
0019FFh to 001980h
Info A
Info B
Info C
Info D
BSL 3
BSL 2
BSL 1
BSL 0
Size
128 bytes
00197Fh to 001900h
128 bytes
00197Fh to 001900h
128 bytes
00197Fh to 001900h
128 bytes
00197Fh to 001900h
Information memory
(flash)
128 bytes
0018FFh to 001880h
128 bytes
0018FFh to 001880h
128 bytes
0018FFh to 001880h
128 bytes
0018FFh to 001880h
128 bytes
00187Fh to 001800h
128 bytes
00187Fh to 001800h
128 bytes
00187Fh to 001800h
128 bytes
00187Fh to 001800h
512 bytes
0017FFh to 001600h
512 bytes
0017FFh to 001600h
512 bytes
0017FFh to 001600h
512 bytes
0017FFh to 001600h
512 bytes
0015FFh to 001400h
512 bytes
0015FFh to 001400h
512 bytes
0015FFh to 001400h
512 bytes
0015FFh to 001400h
Bootloader (BSL)
memory (flash)
512 bytes
0013FFh to 001200h
512 bytes
0013FFh to 001200h
512 bytes
0013FFh to 001200h
512 bytes
0013FFh to 001200h
512 bytes
0011FFh to 001000h
512 bytes
0011FFh to 001000h
512 bytes
0011FFh to 001000h
512 bytes
0011FFh to 001000h
4KB
4KB
4KB
4KB
Peripherals
000FFFh to 000000h
000FFFh to 000000h
000FFFh to 000000h
000FFFh to 000000h
(1) N/A = Not available.
(2) Backup RAM is accessed through the control registers BAKMEM0, BAKMEM1, BAKMEM2, and BAKMEM3.
(3) Only available on FG642x.
(4) Only available on FG662x. USB RAM can be used as general-purpose RAM when not used for USB operation.
9.15.1 Peripheral File Map
Table 9-41 lists all of the the available peripherals and their base addresses. Table 9-42 through Table 9-78 list
the registers and their offset addresses for each peripheral.
Table 9-41. Peripherals
MODULE NAME
Special Functions (see Table 9-42)
PMM (see Table 9-43)
BASE ADDRESS
OFFSET ADDRESS RANGE(1)
000h to 01Fh
0100h
0120h
000h to 010h
Flash Control (see Table 9-44)
CRC16 (see Table 9-45)
0140h
000h to 00Fh
0150h
000h to 007h
RAM Control (see Table 9-46)
Watchdog (see Table 9-47)
UCS (see Table 9-48)
0158h
000h to 001h
015Ch
000h to 001h
0160h
000h to 01Fh
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Table 9-41. Peripherals (continued)
MODULE NAME
BASE ADDRESS
OFFSET ADDRESS RANGE(1)
000h to 01Fh
000h to 001h
000h to 003h
000h to 007h
000h to 01Fh
000h to 01Fh
000h to 00Bh
000h to 00Bh
000h to 00Bh
000h to 01Fh
000h to 02Eh
000h to 02Eh
000h to 02Eh
000h to 02Eh
000h to 01Fh
000h to 01Fh
000h to 02Fh
000h to 00Fh
000h to 00Ah
000h to 00Ah
000h to 00Ah
000h to 00Ah
000h to 00Ah
000h to 00Ah
000h to 01Fh
000h to 01Fh
000h to 01Fh
000h to 01Fh
000h to 01Fh
000h to 00Fh
000h to 014h
000h to 01Fh
000h to 014h
000h to 05Fh
000h to 05Fh
000h to 00Fh
000h to 00Fh
SYS (see Table 9-49)
0180h
Shared Reference (see Table 9-50)
Port Mapping Control (see Table 9-51)
Port Mapping Port P2 (see Table 9-51)
Port P1, P2 (see Table 9-52)
01B0h
01C0h
01D0h
0200h
0220h
0240h
0260h
0280h
0320h
0340h
0380h
03C0h
0400h
0480h
04A0h
04C0h
0500h
0510h
0520h
0530h
0540h
0550h
0560h
05C0h
05E0h
0600h
0620h
0780h
08C0h
0900h
0920h
0900h
0A00h
0A80h
0AE0h
0AF0h
Port P3, P4 (see Table 9-53)
Port P5, P6 (see Table 9-54)
Port P7, P8 (see Table 9-55)
Port P9 (see Table 9-56)
Port PJ (see Table 9-57)
Timer TA0 (see Table 9-58)
Timer TA1 (see Table 9-59)
Timer TB0 (see Table 9-60)
Timer TA2 (see Table 9-61)
Battery Backup (see Table 9-62)
RTC_B (see Table 9-63)
32-Bit Hardware Multiplier (see Table 9-64)
DMA General Control (see Table 9-65)
DMA Channel 0 (see Table 9-65)
DMA Channel 1 (see Table 9-65)
DMA Channel 2 (see Table 9-65)
DMA Channel 3 (see Table 9-65)
DMA Channel 4 (see Table 9-65)
DMA Channel 5 (see Table 9-65)
USCI_A0 (see Table 9-66)
USCI_B0 (see Table 9-67)
USCI_A1 (see Table 9-68)
USCI_B1 (see Table 9-69)
DAC12_A (see Table 9-70)
Comparator_B (see Table 9-71)
USB configuration (see Table 9-72)(2)
USB control (see Table 9-73)(2)
LDO-PWR; LDO and Port U configuration (see Table 9-74) (3)
LCD_B control (see Table 9-75)
CTSD16 (see Table 9-76)
OA0 and GSW0 (see Table 9-77)
OA1 and GSW1 (see Table 9-78)
(1) For a detailed description of the individual control register offset addresses, see the MSP430F5xx and MSP430F6xx Family User's
Guide.
(2) Only on devices with peripheral module USB.
(3) Only on devices with peripheral module LDO-PWR.
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Table 9-42. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
SFR interrupt enable
SFR interrupt flag
SFRIE1
SFRIFG1
SFRRPCR
02h
SFR reset pin control
04h
Table 9-43. PMM Registers (Base Address: 0120h)
REGISTER DESCRIPTION
REGISTER
PMMCTL0
PMMCTL1
SVSMHCTL
SVSMLCTL
PMMIFG
OFFSET
00h
PMM control 0
PMM control 1
02h
SVS high-side control
SVS low-side control
PMM interrupt flags
PMM interrupt enable
PMM power mode 5 control
04h
06h
0Ch
0Eh
PMMIE
PM5CTL0
10h
Table 9-44. Flash Control Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
Flash control 1
Flash control 3
Flash control 4
FCTL1
FCTL3
04h
FCTL4
06h
Table 9-45. CRC16 Registers (Base Address: 0150h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
CRC data input
CRC result
CRC16DI
CRC16INIRES
04h
Table 9-46. RAM Control Registers (Base Address: 0158h)
REGISTER DESCRIPTION
REGISTER
OFFSET
RAM control 0
RCCTL0
00h
Table 9-47. Watchdog Registers (Base Address: 015Ch)
REGISTER DESCRIPTION
REGISTER
OFFSET
Watchdog timer control
WDTCTL
00h
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Table 9-48. UCS Registers (Base Address: 0160h)
REGISTER DESCRIPTION
REGISTER
UCSCTL0
UCSCTL1
UCSCTL2
UCSCTL3
UCSCTL4
UCSCTL5
UCSCTL6
UCSCTL7
UCSCTL8
OFFSET
UCS control 0
UCS control 1
UCS control 2
UCS control 3
UCS control 4
UCS control 5
UCS control 6
UCS control 7
UCS control 8
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
Table 9-49. SYS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
System control
SYSCTL
Bootloader configuration area
JTAG mailbox control
SYSBSLC
SYSJMBC
SYSJMBI0
SYSJMBI1
SYSJMBO0
SYSJMBO1
SYSBERRIV
SYSUNIV
02h
06h
JTAG mailbox input 0
08h
JTAG mailbox input 1
0Ah
0Ch
0Eh
18h
JTAG mailbox output 0
JTAG mailbox output 1
Bus error vector generator
User NMI vector generator
System NMI vector generator
Reset vector generator
1Ah
1Ch
1Eh
SYSSNIV
SYSRSTIV
Table 9-50. Shared Reference Registers (Base Address: 01B0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Shared reference control
REFCTL
00h
Table 9-51. Port Mapping Registers
(Base Address of Port Mapping Control: 01C0h, Port P2: 01D0h)
REGISTER DESCRIPTION
REGISTER
PMAPPWD
PMAPCTL
P2MAP0
P2MAP1
P2MAP2
P2MAP3
P2MAP4
P2MAP5
P2MAP6
P2MAP7
OFFSET
00h
Port mapping password
Port mapping control
Port P2.0 mapping
Port P2.1 mapping
Port P2.2 mapping
Port P2.3 mapping
Port P2.4 mapping
Port P2.5 mapping
Port P2.6 mapping
Port P2.7 mapping
02h
00h
01h
02h
03h
04h
05h
06h
07h
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Table 9-52. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
02h
04h
06h
08h
0Ah
0Eh
18h
1Ah
1Ch
01h
03h
05h
07h
09h
0Bh
1Eh
19h
1Bh
1Dh
Port P1 input
P1IN
Port P1 output
P1OUT
P1DIR
P1REN
P1DS
Port P1 direction
Port P1 resistor enable
Port P1 drive strength
Port P1 selection
P1SEL
P1IV
Port P1 interrupt vector word
Port P1 interrupt edge select
Port P1 interrupt enable
Port P1 interrupt flag
Port P2 input
P1IES
P1IE
P1IFG
P2IN
Port P2 output
P2OUT
P2DIR
P2REN
P2DS
Port P2 direction
Port P2 resistor enable
Port P2 drive strength
Port P2 selection
P2SEL
P2IV
Port P2 interrupt vector word
Port P2 interrupt edge select
Port P2 interrupt enable
Port P2 interrupt flag
P2IES
P2IE
P2IFG
Table 9-53. Port P3, P4 Registers (Base Address: 0220h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
02h
04h
06h
08h
0Ah
0Eh
18h
1Ah
1Ch
01h
03h
05h
07h
09h
0Bh
1Eh
19h
1Bh
1Dh
Port P3 input
P3IN
Port P3 output
P3OUT
P3DIR
P3REN
P3DS
Port P3 direction
Port P3 resistor enable
Port P3 drive strength
Port P3 selection
P3SEL
P3IV
Port P3 interrupt vector word
Port P3 interrupt edge select
Port P3 interrupt enable
Port P3 interrupt flag
Port P4 input
P3IES
P3IE
P3IFG
P4IN
Port P4 output
P4OUT
P4DIR
P4REN
P4DS
Port P4 direction
Port P4 resistor enable
Port P4 drive strength
Port P4 selection
P4SEL
P4IV
Port P4 interrupt vector word
Port P4 interrupt edge select
Port P4 interrupt enable
Port P4 interrupt flag
P4IES
P4IE
P4IFG
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Table 9-54. Port P5, P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P5 input
P5IN
00h
02h
04h
06h
08h
0Ah
01h
03h
05h
07h
09h
0Bh
Port P5 output
P5OUT
P5DIR
P5REN
P5DS
Port P5 direction
Port P5 resistor enable
Port P5 drive strength
Port P5 selection
Port P6 input
P5SEL
P6IN
Port P6 output
P6OUT
P6DIR
P6REN
P6DS
Port P6 direction
Port P6 resistor enable
Port P6 drive strength
Port P6 selection
P6SEL
Table 9-55. Port P7, P8 Registers (Base Address: 0260h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
Port P7 input
P7IN
Port P7 output
P7OUT
P7DIR
P7REN
P7DS
02h
Port P7 direction
Port P7 resistor enable
Port P7 drive strength
Port P7 selection
Port P8 input
04h
06h
08h
P7SEL
P8IN
0Ah
01h
Port P8 output
P8OUT
P8DIR
P8REN
P8DS
03h
Port P8 direction
Port P8 resistor enable
Port P8 drive strength
Port P8 selection
05h
07h
09h
P8SEL
0Bh
Table 9-56. Port P9 Register (Base Address: 0280h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
Port P9 input
P9IN
Port P9 output
P9OUT
P9DIR
P9REN
P9DS
02h
Port P9 direction
Port P9 resistor enable
Port P9 drive strength
Port P9 selection
04h
06h
08h
P9SEL
0Ah
Table 9-57. Port J Registers (Base Address: 0320h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
Port PJ input
PJIN
Port PJ output
PJOUT
PJDIR
02h
Port PJ direction
Port PJ resistor enable
Port PJ drive strength
04h
PJREN
PJDS
06h
08h
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Table 9-58. TA0 Registers (Base Address: 0340h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
TA0 control
TA0CTL
TA0CCTL0
TA0CCTL1
TA0CCTL2
TA0CCTL3
TA0CCTL4
TA0R
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
Capture/compare control 3
Capture/compare control 4
TA0 counter
02h
04h
06h
08h
0Ah
10h
Capture/compare 0
Capture/compare 1
Capture/compare 2
Capture/compare 3
Capture/compare 4
TA0 expansion 0
TA0CCR0
TA0CCR1
TA0CCR2
TA0CCR3
TA0CCR4
TA0EX0
12h
14h
16h
18h
1Ah
20h
TA0 interrupt vector
TA0IV
2Eh
Table 9-59. TA1 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
TA1 control
TA1CTL
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TA1 counter
TA1CCTL0
TA1CCTL1
TA1CCTL2
TA1R
02h
04h
06h
10h
Capture/compare 0
Capture/compare 1
Capture/compare 2
TA1 expansion 0
TA1CCR0
TA1CCR1
TA1CCR2
TA1EX0
12h
14h
16h
20h
TA1 interrupt vector
TA1IV
2Eh
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Table 9-60. TB0 Registers (Base Address: 03C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TB0 control
TB0CTL
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
2Eh
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
Capture/compare control 3
Capture/compare control 4
Capture/compare control 5
Capture/compare control 6
TB0 counter
TB0CCTL0
TB0CCTL1
TB0CCTL2
TB0CCTL3
TB0CCTL4
TB0CCTL5
TB0CCTL6
TB0R
Capture/compare 0
TB0CCR0
TB0CCR1
TB0CCR2
TB0CCR3
TB0CCR4
TB0CCR5
TB0CCR6
TB0EX0
Capture/compare 1
Capture/compare 2
Capture/compare 3
Capture/compare 4
Capture/compare 5
Capture/compare 6
TB0 expansion 0
TB0 interrupt vector
TB0IV
Table 9-61. TA2 Registers (Base Address: 0400h)
REGISTER DESCRIPTION
REGISTER
OFFSET
00h
TA2 control
TA2CTL
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TA2 counter
TA2CCTL0
TA2CCTL1
TA2CCTL2
TA2R
02h
04h
06h
10h
Capture/compare 0
Capture/compare 1
Capture/compare 2
TA2 expansion 0
TA2CCR0
TA2CCR1
TA2CCR2
TA2EX0
12h
14h
16h
20h
TA2 interrupt vector
TA2IV
2Eh
Table 9-62. Battery Backup Registers (Base Address: 0480h)
REGISTER DESCRIPTION
REGISTER
BAKMEM0
BAKMEM1
BAKMEM2
BAKMEM3
BAKCTL
OFFSET
00h
Battery backup memory 0
Battery backup memory 1
Battery backup memory 2
Battery backup memory 3
Battery backup control
Battery charger control
02h
04h
06h
1Ch
BAKCHCTL
1Eh
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Table 9-63. Real-Time Clock Registers (Base Address: 04A0h)
REGISTER DESCRIPTION
REGISTER
RTCCTL0
RTCCTL1
RTCCTL2
RTCCTL3
RTCPS0CTL
RTCPS1CTL
RTCPS0
OFFSET
00h
01h
02h
03h
08h
0Ah
0Ch
0Dh
0Eh
10h
11h
RTC control 0
RTC control 1
RTC control 2
RTC control 3
RTC prescaler 0 control
RTC prescaler 1 control
RTC prescaler 0
RTC prescaler 1
RTC interrupt vector word
RTC seconds
RTCPS1
RTCIV
RTCSEC
RTC minutes
RTCMIN
RTC hours
RTCHOUR
RTCDOW
RTCDAY
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Eh
RTC day of week
RTC days
RTC month
RTCMON
RTCYEARL
RTCYEARH
RTCAMIN
RTCAHOUR
RTCADOW
RTCADAY
BIN2BCD
BCD2BIN
RTC year low
RTC year high
RTC alarm minutes
RTC alarm hours
RTC alarm day of week
RTC alarm days
Binary-to-BCD conversion
BCD-to-binary conversion
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Table 9-64. 32-Bit Hardware Multiplier Registers (Base Address: 04C0h)
REGISTER DESCRIPTION
REGISTER
OFFSET
16-bit operand 1 – multiply
MPY
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah
1Ch
1Eh
20h
22h
24h
26h
28h
2Ah
2Ch
16-bit operand 1 – signed multiply
16-bit operand 1 – multiply accumulate
16-bit operand 1 – signed multiply accumulate
16-bit operand 2
MPYS
MAC
MACS
OP2
16 × 16 result low word
RESLO
RESHI
16 × 16 result high word
16 × 16 sum extension register
SUMEXT
MPY32L
MPY32H
MPYS32L
MPYS32H
MAC32L
MAC32H
MACS32L
MACS32H
OP2L
32-bit operand 1 – multiply low word
32-bit operand 1 – multiply high word
32-bit operand 1 – signed multiply low word
32-bit operand 1 – signed multiply high word
32-bit operand 1 – multiply accumulate low word
32-bit operand 1 – multiply accumulate high word
32-bit operand 1 – signed multiply accumulate low word
32-bit operand 1 – signed multiply accumulate high word
32-bit operand 2 – low word
32-bit operand 2 – high word
OP2H
32 × 32 result 0 – least significant word
32 × 32 result 1
RES0
RES1
32 × 32 result 2
RES2
32 × 32 result 3 – most significant word
MPY32 control 0
RES3
MPY32CTL0
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Table 9-65. DMA Registers (Base Address DMA General Control: 0500h,
DMA Channel 0: 0510h, DMA Channel 1: 0520h, DMA Channel 2: 0530h, DMA Channel 3: 0540h, DMA
Channel 4: 0550h, DMA Channel 5: 0560h)
REGISTER DESCRIPTION
REGISTER
DMACTL0
DMACTL1
DMACTL2
DMACTL3
DMACTL4
DMAIV
OFFSET
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
00h
02h
04h
06h
08h
0Ah
DMA general control: DMA module control 0
DMA general control: DMA module control 1
DMA general control: DMA module control 2
DMA general control: DMA module control 3
DMA general control: DMA module control 4
DMA general control: DMA interrupt vector
DMA channel 0 control
DMA0CTL
DMA0SAL
DMA0SAH
DMA0DAL
DMA0DAH
DMA0SZ
DMA channel 0 source address low
DMA channel 0 source address high
DMA channel 0 destination address low
DMA channel 0 destination address high
DMA channel 0 transfer size
DMA channel 1 control
DMA1CTL
DMA1SAL
DMA1SAH
DMA1DAL
DMA1DAH
DMA1SZ
DMA channel 1 source address low
DMA channel 1 source address high
DMA channel 1 destination address low
DMA channel 1 destination address high
DMA channel 1 transfer size
DMA channel 2 control
DMA2CTL
DMA2SAL
DMA2SAH
DMA2DAL
DMA2DAH
DMA2SZ
DMA channel 2 source address low
DMA channel 2 source address high
DMA channel 2 destination address low
DMA channel 2 destination address high
DMA channel 2 transfer size
DMA channel 3 control
DMA3CTL
DMA3SAL
DMA3SAH
DMA3DAL
DMA3DAH
DMA3SZ
DMA channel 3 source address low
DMA channel 3 source address high
DMA channel 3 destination address low
DMA channel 3 destination address high
DMA channel 3 transfer size
DMA channel 4 control
DMA4CTL
DMA4SAL
DMA4SAH
DMA4DAL
DMA4DAH
DMA4SZ
DMA channel 4 source address low
DMA channel 4 source address high
DMA channel 4 destination address low
DMA channel 4 destination address high
DMA channel 4 transfer size
DMA channel 5 control
DMA5CTL
DMA5SAL
DMA5SAH
DMA5DAL
DMA5DAH
DMA5SZ
DMA channel 5 source address low
DMA channel 5 source address high
DMA channel 5 destination address low
DMA channel 5 destination address high
DMA channel 5 transfer size
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Table 9-66. USCI_A0 Registers (Base Address: 05C0h)
REGISTER DESCRIPTION
REGISTER
UCA0CTL0
UCA0CTL1
UCA0BR0
OFFSET
USCI control 0
00h
01h
06h
07h
08h
0Ah
0Ch
0Eh
10h
12h
13h
1Ch
1Dh
1Eh
USCI control 1
USCI baud rate 0
USCI baud rate 1
UCA0BR1
USCI modulation control
USCI status
UCA0MCTL
UCA0STAT
UCA0RXBUF
UCA0TXBUF
UCA0ABCTL
UCA0IRTCTL
UCA0IRRCTL
UCA0IE
USCI receive buffer
USCI transmit buffer
USCI LIN control
USCI IrDA transmit control
USCI IrDA receive control
USCI interrupt enable
USCI interrupt flags
USCI interrupt vector word
UCA0IFG
UCA0IV
Table 9-67. USCI_B0 Registers (Base Address: 05E0h)
REGISTER DESCRIPTION
REGISTER
UCB0CTL0
UCB0CTL1
UCB0BR0
UCB0BR1
UCB0STAT
UCB0RXBUF
UCB0TXBUF
UCB0I2COA
UCB0I2CSA
UCB0IE
OFFSET
00h
USCI synchronous control 0
USCI synchronous control 1
USCI synchronous bit rate 0
USCI synchronous bit rate 1
USCI synchronous status
01h
06h
07h
0Ah
0Ch
0Eh
10h
USCI synchronous receive buffer
USCI synchronous transmit buffer
USCI I2C own address
USCI I2C slave address
USCI interrupt enable
12h
1Ch
1Dh
1Eh
USCI interrupt flags
UCB0IFG
USCI interrupt vector word
UCB0IV
Table 9-68. USCI_A1 Registers (Base Address: 0600h)
REGISTER DESCRIPTION
REGISTER
UCA1CTL0
UCA1CTL1
UCA1BR0
OFFSET
00h
USCI control 0
USCI control 1
01h
USCI baud rate 0
06h
USCI baud rate 1
UCA1BR1
07h
USCI modulation control
USCI status
UCA1MCTL
UCA1STAT
UCA1RXBUF
UCA1TXBUF
UCA1ABCTL
UCA1IRTCTL
UCA1IRRCTL
UCA1IE
08h
0Ah
0Ch
0Eh
10h
USCI receive buffer
USCI transmit buffer
USCI LIN control
USCI IrDA transmit control
USCI IrDA receive control
USCI interrupt enable
USCI interrupt flags
USCI interrupt vector word
12h
13h
1Ch
1Dh
1Eh
UCA1IFG
UCA1IV
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Table 9-69. USCI_B1 Registers (Base Address: 0620h)
REGISTER DESCRIPTION
REGISTER
UCB1CTL0
UCB1CTL1
UCB1BR0
UCB1BR1
UCB1STAT
UCB1RXBUF
UCB1TXBUF
UCB1I2COA
UCB1I2CSA
UCB1IE
OFFSET
00h
USCI synchronous control 0
USCI synchronous control 1
USCI synchronous bit rate 0
USCI synchronous bit rate 1
USCI synchronous status
01h
06h
07h
0Ah
0Ch
0Eh
10h
USCI synchronous receive buffer
USCI synchronous transmit buffer
USCI I2C own address
USCI I2C slave address
USCI interrupt enable
12h
1Ch
1Dh
1Eh
USCI interrupt flags
UCB1IFG
USCI interrupt vector word
UCB1IV
Table 9-70. DAC12_A Registers (Base Address: 0780h)
REGISTER DESCRIPTION
REGISTER
DAC12_0CTL0
DAC12_0CTL1
DAC12_0DAT
OFFSET
00h
DAC12_A channel 0 control 0
DAC12_A channel 0 control 1
DAC12_A channel 0 data
02h
04h
DAC12_A channel 0 calibration control
DAC12_A channel 0 calibration data
DAC12_A channel 1 control 0
DAC12_A channel 1 control 1
DAC12_A channel 1 data
DAC12_0CALCTL
DAC12_0CALDAT
DAC12_1CTL0
DAC12_1CTL1
DAC12_1DAT
06h
08h
10h
12h
14h
DAC12_A channel 1 calibration control
DAC12_A channel 1 calibration data
DAC12_A interrupt vector word
DAC12_1CALCTL
DAC12_1CALDAT
DAC12IV
16h
18h
1Eh
Table 9-71. Comparator_B Registers (Base Address: 08C0h)
REGISTER DESCRIPTION
REGISTER
CBCTL0
CBCTL1
CBCTL2
CBCTL3
CBINT
OFFSET
00h
Comp_B control 0
Comp_B control 1
Comp_B control 2
Comp_B control 3
Comp_B interrupt
02h
04h
06h
0Ch
Comp_B interrupt vector word
CBIV
0Eh
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Table 9-72. USB Configuration Registers (Base Address: 0900h)
REGISTER DESCRIPTION
REGISTER
USBKEYID
USBCNF
OFFSET
USB key/ID
00h
02h
04h
08h
0Ah
10h
12h
14h
USB module configuration
USB PHY control
USBPHYCTL
USBPWRCTL
USBPWRVSR
USBPLLCTL
USBPLLDIV
USBPLLIR
USB power control
USB power voltage setting
USB PLL control
USB PLL divider
USB PLL interrupts
Table 9-73. USB Control Registers (Base Address: 0920h)
REGISTER DESCRIPTION
REGISTER
USBIEPCNF_0
USBIEPBCNT_0
USBOEPCNFG_0
USBOEPBCNT_0
USBIEPIE
OFFSET
00h
Input endpoint_0 configuration
Input endpoint_0 byte count
Output endpoint_0 configuration
Output endpoint_0 byte count
Input endpoint interrupt enables
Output endpoint interrupt enables
Input endpoint interrupt flags
Output endpoint interrupt flags
USB interrupt vector
01h
02h
03h
0Eh
0Fh
10h
USBOEPIE
USBIEPIFG
USBOEPIFG
USBIV
11h
12h
USB maintenance
USBMAINT
USBTSREG
USBFN
16h
Time stamp
18h
USB frame number
1Ah
1Ch
1Dh
1Eh
1Fh
USB control
USBCTL
USB interrupt enables
USB interrupt flags
USBIE
USBIFG
Function address
USBFUNADR
Table 9-74. LDO and Port U Configuration Registers (Base Address: 0900h)
REGISTER DESCRIPTION
REGISTER
LDOKEYPID
PUCTL
OFFSET
00h
LDO key and ID
PU port control
04h
LDO power control
LDOPWRCTL
08h
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Table 9-75. LCD_B Registers (Base Address: 0A00h)
REGISTER DESCRIPTION
REGISTER
OFFSET
000h
002h
004h
006h
008h
00Ah
00Ch
00Eh
012h
01Eh
020h
021h
⋮
LCD_B control 0
LCDBCTL0
LCDBCTL1
LCDBBLKCTL
LCDBMEMCTL
LCDBVCTL
LCDBPCTL0
LCDBPCTL1
LCDBPCTL2
LCDBCTL0
LCDBIV
LCD_B control 1
LCD_B blinking control
LCD_B memory control
LCD_B voltage control
LCD_B port control 0
LCD_B port control 1
LCD_B port control 2
LCD_B charge pump control
LCD_B interrupt vector word
LCD_B memory 1
LCDM1
LCD_B memory 2
LCDM2
⋮
⋮
LCD_B memory 22
LCD_B blinking memory 1
LCD_B blinking memory 2
⋮
LCDM22
035h
040h
041h
⋮
LCDBM1
LCDBM2
⋮
LCD_B blinking memory 22
LCDBM22
055h
Table 9-76. CTSD16 Registers (Base Address: 0A80h)
REGISTER DESCRIPTION
REGISTER
CTSD16CTL
CTSD16CCTL0
CTSD16INCTL0
CTSD16PRE0
CTSD16IFG
CTSD16IE
OFFSET
00h
CTSD16 control
CTSD16 channel 0 control
02h
CTSD16 channel 0 input control
CTSD16 channel 0 preload
CTSD16 interrupt flag
04h
06h
2Ch
2Eh
30h
CTSD16 interrupt enable
CTSD16 interrupt vector
CTSD16IV
CTSD16 channel 0 conversion memory
CTSD16MEM0
32h
Table 9-77. OA0 Registers (Base Address: 0AE0h)
REGISTER DESCRIPTION
REGISTER
OA0CTL0
OA0PSW
OA0NSW
OA0GSW
OFFSET
00h
OA0 control 0
OA0 positive input terminal switches
OA0 negative input terminal switches
OA0 ground switches
02h
04h
0Eh
Table 9-78. OA1 Registers (Base Address: 0AF0h)
REGISTER DESCRIPTION
REGISTER
OA1CTL0
OA1PSW
OA1NSW
OA1GSW
OFFSET
00h
OA1 control 0
OA1 positive input terminal switches
OA1 negative input terminal switches
OA1 ground switches
02h
04h
0Eh
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9.16 Identification
9.16.1 Revision Identification
The device revision information is shown as part of the top-side marking on the device package. The device-
specific errata sheet describes these markings. For links to all of the errata sheets for the devices in this data
sheet, see Section 11.4.
The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For details on
this value, see the "Hardware Revision" entries in Section 9.14.
9.16.2 Device Identification
The device type can be identified from the top-side marking on the device package. The device-specific errata
sheet describes these markings. For links to all of the errata sheets for the devices in this data sheet, see
Section 11.4.
A device identification value is also stored in the Device Descriptor structure in the Info Block section. For details
on this value, see the "Device ID" entries in Section 9.14.
9.16.3 JTAG Identification
Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in detail in
the MSP430 Programming With the JTAG Interface.
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10 Applications, Implementation, and Layout
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
10.1 Device Connection and Layout Fundamentals
This section discusses the recommended guidelines when designing with the MSP430. These guidelines are to
make sure that the device has proper connections for powering, programming, debugging, and optimum analog
performance.
10.1.1 Power Supply Decoupling and Bulk Capacitors
TI recommends connecting a combination of a 1-µF plus a 100-nF low-ESR ceramic decoupling capacitor to
each AVCC and DVCC pin. Higher-value capacitors may be used but can impact supply rail ramp-up time.
Decoupling capacitors must be placed as close as possible to the pins that they decouple (within a few
millimeters). Additionally, separated grounds with a single-point connection are recommend for better noise
isolation from digital to analog circuits on the board and are especially recommended to achieve high analog
accuracy.
DVCC
Digital
Power Supply
Decoupling
+
1 µF
100 nF
100 nF
DVSS
AVCC
Analog
Power Supply
Decoupling
+
1 µF
AVSS
Figure 10-1. Power Supply Decoupling
10.1.2 External Oscillator
Depending on the device variant (see Section 6), the device can support a low-frequency crystal (32 kHz) on the
XT1 pins, a high-frequency crystal on the XT2 pins, or both. External bypass capacitors for the crystal oscillator
pins are required.
It is also possible to apply digital clock signals to the XIN and XT2IN input pins that meet the specifications of the
respective oscillator if the appropriate XT1BYPASS or XT2BYPASS mode is selected. In this case, the
associated XOUT and XT2OUT pins can be used for other purposes. If they are left unused, they must be
terminated according to Table 7-4.
Figure 10-2 shows a typical connection diagram.
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XIN
or
XOUT
or
XT2IN
XT2OUT
CL1
CL2
Figure 10-2. Typical Crystal Connection
See MSP430 32-kHz Crystal Oscillators for more information on selecting, testing, and designing a crystal
oscillator with the MSP430 devices.
10.1.3 JTAG
With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or MSP-
FET430UIF) can be used to program and debug code on the target board. In addition, the connections also
support the MSP-GANG production programmers, thus providing an easy way to program prototype boards, if
desired. Figure 10-3 shows the connections between the 14-pin JTAG connector and the target device required
to support in-system programming and debugging for 4-wire JTAG communication. Figure 10-4 shows the
connections for 2-wire JTAG mode (Spy-Bi-Wire).
The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are identical.
Both can supply VCC to the target board (through pin 2). In addition, the MSP-FET and MSP-FET430UIF
interface modules and MSP-GANG have a VCC sense feature that, if used, requires an alternate connection (pin
4 instead of pin 2). The VCC-sense feature senses the local VCC present on the target board (that is, a battery
or other local power supply) and adjusts the output signals accordingly. Figure 10-3 and Figure 10-4 show a
jumper block that supports both scenarios of supplying VCC to the target board. If this flexibility is not required,
the desired VCC connections may be hard-wired to eliminate the jumper block. Pins 2 and 4 must not be
connected at the same time.
For additional design information regarding the JTAG interface, see the MSP430 Hardware Tools User’s Guide.
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VCC
Important to connect
MSP430FGxxxx
AVCC/DVCC
J1 (see Note A)
J2 (see Note A)
C2
10 µF
C3
0.1 µF
R1
47 kW
JTAG
RST/NMI/SBWTDIO
VCC TOOL
TDO/TDI
TDI
TDO/TDI
TDI
2
1
VCC TARGET
4
3
TMS
TMS
6
5
7
TEST
TCK
8
TCK
GND
RST
10
12
14
9
11
13
TEST/SBWTCK
AVSS/DVSS
C1
2.2 nF
See Note B
A. If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used, make connection
J2.
B. The upper limit for C1 is 2.2 nF when using current TI tools.
Figure 10-3. Signal Connections for 4-Wire JTAG Communication
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VCC
Important to connect
MSP430FGxxxx
J1 (see Note A)
J2 (see Note A)
AVCC/DVCC
C2
10 µF
C3
0.1 µF
R1
47 kΩ
See Note B
JTAG
VCC TOOL
TDO/TDI
2
1
3
5
7
9
RST/NMI/SBWTDIO
VCC TARGET
4
6
TCK
8
GND
10
12
14
11
13
TEST/SBWTCK
AVSS/DVSS
C1
2.2 nF
See Note B
A. Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the debug or
programming adapter.
B. The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during JTAG access, and any
capacitance that is attached to this signal may affect the ability to establish a connection with the device. The upper limit for C1 is 2.2 nF
when using current TI tools.
Figure 10-4. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire)
10.1.4 Reset
The reset pin can be configured as a reset function (default) or as an NMI function in the Special Function
Register (SFR), SFRRPCR.
In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing
specifications generates a BOR-type device reset.
Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is edge
sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the external NMI.
When an external NMI event occurs, the NMIIFG is set.
The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either pullup or
pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not. If the RST/NMI
pin is unused, it is required either to select and enable the internal pullup or to connect an external 47-kΩ pullup
resistor to the RST/NMI pin with a 2.2-nF pulldown capacitor. The pulldown capacitor should not exceed 2.2 nF
when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG mode with TI tools like
FET interfaces or GANG programmers.
See the MSP430F5xx and MSP430F6xx Family User's Guide for more information on the referenced control
registers and bits.
10.1.5 Unused Pins
For details on the connection of unused pins, see Section 7.6.
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10.1.6 General Layout Recommendations
•
Proper grounding and short traces for external crystal to reduce parasitic capacitance. See MSP430 32-kHz
Crystal Oscillators for recommended layout guidelines.
•
•
Proper bypass capacitors on DVCC, AVCC, and reference pins if used.
Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital switching
signals such as PWM or JTAG signals away from the oscillator circuit.
•
Proper ESD level protection should be considered to protect the device from unintended high-voltage
electrostatic discharge. See MSP430 System-Level ESD Considerations for guidelines.
10.1.7 Do's and Don'ts
TI recommends powering AVCC and DVCC pins from the same source. At a minimum, during power up, power
down, and device operation, the voltage difference between AVCC and DVCC must not exceed the limits
specified in Section 8.1. Exceeding the specified limits may cause malfunction of the device including erroneous
writes to RAM and flash.
10.2 Peripheral- and Interface-Specific Design Information
10.2.1 CTSD16 Peripheral
For internal connections between signal chain modules such as CTSD16, OA, and DAC12, see Section 9.12.16.
When internal connections are available, they should be chosen over external connections to reduce noise and
save pins.
Solid decoupling on both the digital and analog supplies is also required (best with two capacitors, one 1 µF and
one 100 nF [see Section 10.1.1]).
VREFBG/VeREF+
(see Note A)
1 nF
CPCAP
(see Note B)
22 nF
AVSS
A. The capacitor reduces noise when using internal VREFBG setting. This pin is also used for the external reference input for the CTSD16 or
DAC, and when doing so the capacitor is not needed. Because of the shared signal path and pin, the internal and external references
(VREFBG and VeREF+, respectively) cannot be used at the same time.
B. The capacitor on CPCAP is required when the charge pump is enabled. The charge pump can be enabled by rail-to-rail operation of the
CTSD16 or by the OA module. See the register settings for each module in the MSP430F5xx and MSP430F6xx Family User's Guide for
enabling this operation.
Figure 10-5. CTSD16 Partial Schematic
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10.2.1.1 Example Measurement Schematic – Differential Input
Vm
<10 kHz
RC filter
R1
(see Note A)
CTSD16
AD0+
R2
Vin
AD0–
R1
A. TI recommends an external RC antialiasing low-pass filter for the CTSD16 to prevent aliasing of the input signal. The cutoff frequency
should be <10 kHz for a 1-MHz modulator clock and OSR = 256. The cutoff frequency may be set to a lower frequency for applications
that have lower bandwidth requirements. It is up to the user to determine the configuration and type of low-pass filter used.
Figure 10-6. CTSD16 Measurement Schematic – Differential Input
10.2.1.2 Example Measurement Schematic – Single-Ended Input
Vm
<10 kHz
RC filter
R1
A0 or
AD0+
(see Note A)
CTSD16
R2
AD0–
VREFBG/VeREF+
A. TI recommends an external RC antialiasing low-pass filter for the CTSD16 to prevent aliasing of the input signal. The cutoff frequency
should be <10 kHz for a 1-MHz modulator clock and OSR = 256. The cutoff frequency may be set to a lower frequency for applications
that have lower bandwidth requirements. It is up to the user to determine the configuration and type of low-pass filter used.
Figure 10-7. CTSD16 Measurement Schematic – Single-Ended Input
10.2.1.3 Design Requirements
As with any high-resolution ADC, appropriate printed circuit board layout and grounding techniques should be
followed to eliminate ground loops, unwanted parasitic effects, and noise.
Ground loops are formed when return current from the ADC flows through paths that are common with other
analog or digital circuitry. If care is not taken, this current can generate small unwanted offset voltages that can
add to or subtract from the reference or input voltages of the ADC. Therefore, solid decoupling on both the digital
and analog supplies is required (best with two capacitors, one 1 µF and one 100 nF [see Section 10.1.1]).
In addition to grounding, ripple and noise spikes on the power-supply lines due to digital switching or switching
power supplies can corrupt the conversion result. TI recommends a noise-free design using separate analog and
digital ground planes with a single-point connection to achieve high accuracy.
If the internal reference is used, the reference voltage should be buffered externally by connecting a small
(approximately 1 nF) capacitor to the VREFBG pin to reduce the noise on the reference.
The CTSD16 has a fixed 1.024-MHz clock (fM). Fault flags for this oscillator are described in the CTSD16 and
UCS section of the MSP430F5xx and MSP430F6xx Family User's Guide.
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Rail-to-rail operation mode is available when the OA module is used to buffer the CTSD16 inputs. For more
information, see the CTSD16 and the OA modules in the MSP430F5xx and MSP430F6xx Family User's Guide.
10.2.1.4 Detailed Design Procedure
10.2.1.4.1 OSR and Sampling Frequency
A simple equation guides the relationship between effective sampling frequency and oversampling ratio (OSR)
for CTSD16.
f
m
f =
s
OSR
(2)
Where
•
•
fs = effective sampling frequency
fm = modulation frequency
For the CTSD16, the modulation frequency is set to 1.024 MHz. Using Equation 2 with an example OSR of 256,
the effective sampling frequency would be 4 kHz. The OSR value also affects the number of bits in the digital
filter output. See the CTSD16 chapter in the MSP430F5xx and MSP430F6xx Family User's Guide for additional
information and available OSR values.
10.2.1.4.2 Differential Input Range Explanation
The following equations can give guidance on the input range for the CTSD16 while using an external reference.
Keep in mind the absolute bounds of an external reference as mentioned in the specifications section of this
module. The external and internal references cannot be used at the same time, because they share the same
signal path and pin. For internal reference ranges, see Section 8.8.11.
+V
R
V
=
FSR+
GAIN
(3)
(4)
–V
R
V
=
FSR–
GAIN
V
R
Full-Scale Range = V
FSR+
– V = 2 ×
FSR–
GAIN
(5)
(6)
V
= 0.8 V
FSR–
to 0.8 V , with externally sourced V
FSR+ R
ID
Where
•
•
•
VFSR is the full-scale range voltage
VID is the differential input voltage
VR is the reference voltage
The differential input voltage range with internal voltage reference at different GAIN settings is given in Section
8.8.11. Using Equation 3 through Equation 6, determine the absolute maximum differential input ranges for the
CTSD16 with a given external voltage reference. Equation 7 corresponds to the example circuit in Figure 10-6
and can be used after a range is chosen to limit differential input voltage to acceptable levels by solving for the
external resistors R1 and R2.
R
1
2
V
= V
×
×
in
m
R
R
+ 2R
1
eff
2
1 +
2R
in
(7)
Where
•
•
•
Reff = (R2 × 2R1) / ((R2 + 2R1)
Vin is the differential voltage input to CTSD16
Vm is the voltage to measure
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•
Rin is the internal resistance of the CTSD16 (see Section 8.8.11)
10.2.1.4.3 Single-Ended Input Mode
The CTSD16 has six single-ended analog inputs and four differential inputs that can be placed in single-ended
mode by the CTSDINCHx bits in the CTSD16INCTLx registers. These single-ended modes use the fully
differential path of the CTSD16 by internally tying the negative input to the VREFBG/VeREF+ signal. This means for
the differential inputs in single-ended mode, the external pin normally tied to the negative input can be used for
its alternate functions. Equation 8 through Equation 11 apply for full-scale range while in single-ended mode.
V
R
V
= V
+
FSR+
R
GAIN
(8)
(9)
V
R
V
= V
–
FSR–
R
GAIN
æ
ç
è
V
ö
÷
ø
æ
ç
è
V
ö
÷
ø
V
R
R
R
Full-Scale Range = V
– V
FSR–
=
V
+
–
V –
R
= 2 ×
FSR+
R
GAIN
GAIN
GAIN
(10)
(11)
æ
ç
è
V
ö
æ
ç
è
V
ö
÷
ø
R
R
V = V – 0.8 ×
R
to V + 0.8 ×
R
÷
I
GAIN
GAIN
ø
Where
•
•
•
VFSR is the full-scale range voltage
VI is the single-ended input voltage range for data-sheet specified performance
VR is the reference voltage
To ensure the measured voltage is within the single-ended voltage range, a simple voltage divider circuit can be
used to condition the desired input signal. In single-ended mode, additional error may be introduced by noise
when compared to a fully differential measurement. Equation 12 corresponds to the example circuit in Figure
10-7 and can be used after a range is chosen to limit differential input voltage to acceptable levels by solving for
the external resistors R1 and R2.
R
2
V
= V
×
in
m
R
+ R
2
1
(12)
Where
•
•
Vin is the single-ended voltage input to CTSD16
Vm is the voltage to measure
10.2.1.4.4 Offset Calibration
In some applications, it is necessary to calibrate the module for offset error. This module allows an easy way to
do this by providing internal connections from input to VREF or DAC0. To short AD4+ and AD4- to VREF or
DAC0, change the CTSD16INCHx setting for each channel to 0x11 for VREF and 0x12 for DAC0. This allows
calibration of the CTSD16 input stage by what is measured from the ideal value. The total signal chain offset
depends on the impedance of the external circuitry; thus, the actual offset seen at any of the analog inputs may
be different.
10.2.1.5 Layout Guidelines
Components that are shown in the partial schematic (see Figure 10-5) should be placed as close as possible to
the respective device pins. Avoid long traces, because they add additional parasitic capacitance, inductance,
and resistance on the signal.
Avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency PWM), because
the high-frequency switching can be coupled into the analog signal.
The analog differential input signals must be routed closely together to minimize the effect of noise on the
resulting signal.
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10.2.2 Operational Amplifier With Ground Switches Peripheral
For internal connections between signal chain modules such as CTSD16, OA, and DAC12, see Section 9.12.16.
When internal connections are available, they should be chosen over external connections to reduce noise and
save pins.
Solid decoupling on both the digital and analog supplies is also required (best with two capacitors, one 1 µF and
one 100 nF [see Section 10.1.1]).
10.2.2.1 Reference Schematic
CPCAP
(see Note A)
22 nF
AVSS
A. The capacitor on CPCAP is required when the charge pump is enabled. The charge pump can be enabled by rail-to-rail operation of the
PGA buffers of the CTSD16 or by the OA module. See the register settings for each module in the MSP430F5xx and MSP430F6xx
Family User's Guide for enabling this operation.
Figure 10-8. Op Amp Partial Schematic
10.2.2.2 Design Requirements
As with any analog signals, appropriate printed-circuit-board layout and grounding techniques should be
followed to eliminate ground loops, unwanted parasitic effects, and noise.
In addition to grounding, ripple and noise spikes on the power-supply lines due to digital switching or switching
power supplies can corrupt the signal. TI recommends a noise-free design using separate analog and digital
ground planes with a single-point connection to achieve high accuracy. For more information about noise and its
effects on op amps, see Noise Analysis in Operational Amplifiers.
Rail-to-rail operation mode is available with the OA module at the cost of increased current. This should be used
when OA input is near the AVCC rail. See the VCM specification (see Section 8.8.14) to see if rail-to-rail
operation is required for your application. For more information, see the OA chapter of the MSP430F5xx and
MSP430F6xx Family User's Guide.
Ground switches are also available for use. See Section 9.12.16 for connections. These ground switches
provide a low-ohmic connection to ground to both internal connections and to the external pin. When a ground
switch is active, the Digital I/O logic for the corresponding pin is ignored.
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10.2.2.3 Detailed Design Procedure
Operational amplifiers are a diverse and useful tool in many applications. Some common configurations that
might prove to be useful to the user are transimpedance amplifiers to convert currents to voltage, voltage-gain
amplifiers, and buffering configurations. For more information about how to design these circuits along with other
common configurations, see the following documents.
•
•
•
•
Op Amps for Everyone (ISBN: 978-0128116487)
Handbook of Operational Amplifier Applications
Understanding Basic Analog – Ideal Op Amps
An Applications Guide for Op Amps
10.2.2.4 Layout Guidelines
Components that are shown in the partial schematic (see Figure 10-8) should be placed as close as possible to
the respective device pins. Avoid long traces, because they add additional parasitic capacitance, inductance,
and resistance on the signal. Avoid routing analog input signals close to a high-frequency pin (for example, a
high-frequency PWM), because the high-frequency switching can be coupled into the analog signal. When
possible, use internal connections to other modules to limit the potential of error introduction.
10.2.3 RTC_B With Battery Backup System
If not using a separate battery backup supply in the system, see Section 7.6 for VBAT and VBAK connections.
10.2.3.1 Partial Schematic
CBAK
VBAK
–
+
VBAT
BAT
(see Note A)
A. BAT can be a battery or super-capacitor. See Section 8.8.8 for specifications.
Figure 10-9. RTC_B With Battery Backup Partial Schematic
10.2.3.2 Retaining an Accurate Real-Time Clock (RTC) Through Main Supply Interrupts
The RTC_B module with Battery Backup System is designed to keep an accurate RTC during main supply
interruptions and during low-power modes. For more details on when the Backup Battery System engages, see
the Battery Backup System chapter in the MSP430F5xx and MSP430F6xx Family User's Guide. See Using the
MSP430 RTC_B Module With Battery Backup Supply for more information and example code on how to keep an
accurate RTC through power loss.
10.2.3.3 Charging Super-Capacitors With Built-In Resistive Charger
In applications that use a super-capacitor instead of a battery for secondary supply, the charging circuit
functionality of the Battery Backup System can be used to charge the super-capacitor. The resistive charger
circuit connects VBAT to DVCC with selectable resistor values found in Section 8.8.8. This means that if DVCC
is not present, you cannot use this feature to charge a super-capacitor connected to VBAT. The CTSD16 module
can be used to sense the voltage level on VBAT divided by a factor of three. Typical values during VBAT sensing
are listed in Section 8.8.8. Channel A8 of the CTSD16 is routed internally for this. See the CTSD16 chapter of
the MSP430F5xx and MSP430F6xx Family User's Guide for more information. The BAKADC bit in the BAKCTL
register must also be enabled for this feature to operate. Additionally, RTC interrupts can be used to wake up
from LPMx.5 states to charge the super-capacitor. While in an LPMx.5 state, the super-capacitor on VBAT
drains. This means that the "wakeup to charge" interrupt interval must be designed so that charging starts before
the leftover charge in the super-capacitor is too small to accommodate the worst-case backup time if the system
were to suddenly lose power. To estimate this time, use Equation 13 for capacitor discharge in an RC circuit.
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–t
V(t) = VOeRC
(13)
Where
•
•
•
•
VO = initial voltage of capacitor
t = time
R = circuit resistance
C = capacitance
Because the operational current is given for when RTC is operating within the specifications section, R can be
replaced with VO/ILPM3.5 by Ohm's law. By setting V(t) to the minimum voltage for RTC operation while in backup
supply, VO as voltage of capacitor when fully charged, and C as the super-capacitor capacitance, the estimated
RTC operation time can be calculated. If periodic wakeups from LPM3.5 are not desirable for a given application,
external means of charging the super-capacitor must be implemented by the user.
For a detailed list of when the secondary supply VBAT powers the backup-supplied subsystem, see the Battery
Backup System chapter in the MSP430F5xx and MSP430F6xx Family User's Guide.
10.2.4 LCD_B Peripheral
10.2.4.1 Partial Schematic
Required LCD connections greatly vary by the type of display that is used (static or multiplexed), whether
external or internal biasing is used, and also whether the on-chip charge pump is employed. For any display
used, there is flexibility as to how the segment (Sx) and common (COMx) signals are connected to the MCU
which (assuming that the correct choices are made) can be advantageous for the PCB layout and for the design
of the application software.
Because LCD connections are application specific, it is difficult to provide a single one-fits-all schematic.
However for an example of a schematic using the LCD_B module with an MSP430F6638, see the Ultra Low
Power Blood Pressure And Heart Rate Monitor Reference Design.
10.2.4.2 Design Requirements
Due to the flexibility of the LCD_B peripheral module to accommodate various segment-based LCDs, selecting
the right display for the application in combination with determining specific design requirements is often an
iterative process. There can be well-defined requirements in terms of how many individually addressable LCD
segments need to be controlled, what the requirements for LCD contrast are, which device pins are available for
LCD use and which are required by other application functions, and what the power budget is, to name just a
few. TI strongly recommends reviewing the LCD_B peripheral module chapter in the MSP430F5xx and
MSP430F6xx Family User's Guide during the initial design requirements and decision process. The following
table provides a brief overview over different choices that can be made and their impact.
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OPTION OR FEATURE
IMPACT OR USE CASE
•
•
•
•
•
Enable displays with more segments
Use fewer device pins
LCD contrast decreases as mux level increases
Power consumption increases with mux level
Requires multiple intermediate bias voltages
Multiplexed LCD
•
•
•
•
Limited number of segments that can be addressed
Use a relatively large number of device pins
Use the least amount of power
Static LCD
Use only VCC and GND to drive LCD signals
•
•
•
Simpler solution – no external circuitry
Independent of VLCD source
Internal Bias Generation
Somewhat higher power consumption
•
•
•
Requires external resistor ladder divider
Resistor size depends on display
Ability to adjust drive strength to optimize tradeoff between power consumption and good drive of large
segments (high capacitive load)
External Bias Generation
Internal Charge Pump
•
•
External resistor ladder divider can be stabilized through capacitors to reduce ripple
Helps ensure a constant level of contrast despite decaying supply voltage conditions (battery-powered
applications)
•
•
•
Programmable voltage levels allow software-driven contrast control
Requires an external capacitor on the LCDCAP pin
Higher current consumption than simply using VCC for the LCD driver
10.2.4.3 Detailed Design Procedure
A major component in designing the LCD solution is determining the exact connections between the LCD_B
peripheral module and the display itself. Two basic design processes can be employed for this step, although in
reality often a balanced co-design approach is necessary:
•
•
PCB layout-driven design
Software-driven design
In the PCB layout-driven design process, the segment Sx and common COMx signals are connected to
respective MSP430 device pins so that the routing of the PCB can be optimized to minimize signal crossings and
to keep signals on one side of the PCB only, typically the top layer. For example, using a multiplexed LCD, it is
possible to arbitrarily connect the Sx and COMx signals between the LCD and the MSP430 device as long as
segment lines are swapped with segment lines and common lines are swapped with common lines. It is also
possible to not contiguously connect all segment lines but rather skip LCD_B module segment connections to
optimize layout or to allow access to other functions that may be multiplexed on a particular device port pin.
Employing a purely layout-driven design approach, however, can result in the LCD_B module control bits that
are responsible for turning on and off segments to appear scattered throughout the memory map of the LCD
controller (LCDMx registers). This approach potentially places a rather large burden on the software design that
may also result in increased energy consumption due to the computational overhead required to work with the
LCD.
The other extreme is a purely software-driven approach that starts with the idea that control bits for LCD
segments that are frequently turned on and off together should be co-located in memory in the same LCDMx
register or in adjacent registers. For example, in case of a 4-mux display that contains several 7‑segment digits,
from a software perspective it can be very desirable to control all 7 segments of each digit though a single byte-
wide access to an LCDMx register. And consecutive segments are mapped to consecutive LCDMx registers.
This allows use of simple look-up tables or software loops to output numbers on an LCD, reducing computational
overhead and optimizing the energy consumption of an application. Establishing the most convenient memory
layout must be performed in conjunction with the specific LCD that is being used to understand its design
constraints in terms of which segment and which common signals are connected to, for example, a digit.
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For design information regarding the LCD controller input voltage selection including internal and external
options, contrast control, and bias generation, refer to the LCD_B controller chapter in the MSP430F5xx and
MSP430F6xx Family User's Guide.
For additional design information, see Designing With MSP430 and Segment LCD.
10.2.4.4 Layout Guidelines
LCD segment (Sx) and common (COMx) signal traces are continuously switching while the LCD is enabled and
should, therefore, be kept away from sensitive analog signals such as ADC inputs to prevent any noise coupling.
TI recommends keeping the LCD signal traces on one side of the PCB grouped together in a bus-like fashion. A
ground plane underneath the LCD traces and guard traces employed alongside the LCD traces can provide
shielding.
If the internal charge pump of the LCD module is used, the externally provided capacitor on the LCDCAP pin
should be located as close as possible to the MCU. The capacitor should be connected to the device using a
short and direct trace and also have a solid connection to the ground plane that is supplying the VSS pins of the
MCU.
For an example layout of the LCD_B module with an MSP430F6638, see the Ultra Low Power Blood Pressure
And Heart Rate Monitor reference design.
10.2.5 DAC12 Peripheral
For internal connections between signal chain modules such as CTSD16, OA, and DAC12, see Section 9.12.16.
When available, internal connections should be chosen over external ones to reduce noise and save pins.
Solid decoupling on both the digital and analog supplies is required (best with two capacitors per supply, one
1 µF and one 100 nF [see Section 10.1.1]).
10.2.5.1 Partial Schematic
VREFBG/VeREF+
(see Note)
1 nF
AVSS
A. The capacitor is used to reduce noise when using internal VREFBG setting. This pin is also used for the external reference input for the
CTSD16 or DAC. When using the external reference, the capacitor is not needed. Because of the shared signal path and pin, the internal
and external references (VREFBG and VeREF+, respectively) cannot be used at the same time.
Figure 10-10. DAC12 Partial Schematic
10.2.5.2 Design Requirements
As with any analog signals, appropriate printed-circuit-board layout and grounding techniques must be followed
to eliminate ground loops, unwanted parasitic effects, and noise.
In addition to grounding, ripple and noise spikes on the power-supply lines due to digital switching or switching
power supplies can corrupt the signal. TI recommends a noise-free design using separate analog and digital
ground planes with a single-point connection to achieve high accuracy.
10.2.5.3 Detailed Design Procedure
Digital-to-analog converters (DACs) can be used in a variety of applications and configurations. This section
provides some resources for the user to help get started in a design. For details on example DAC applications,
see Bridging the Divide: a DAC Applications Tutorial (Precision Signal Path).
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Some DAC applications may need an output buffer to reduce the affect of a load on the DAC output. This buffer
can be an external op amp or, on some MSP430 devices, the integrated op amp can be used. For more
information on how to configure an op amp for this function, see Section 10.2.2.
For more information about DAC applications, see the following application notes:
Digital-to-Analog High-Speed Data Converters Basics
Design for a Wideband Differential Transimpedance DAC Output
10.2.5.4 Layout Guidelines
Application circuits attached to the DAC output should be placed as close as possible to the respective device
pins. Avoid long traces because they add additional parasitic capacitance, inductance, and resistance on the
signal. Avoid routing analog signals close to a high-frequency pin (for example, a high-frequency PWM) because
the high-frequency switching can be coupled into the analog signal. When possible, use internal connections to
other modules to limit the potential of error introduction.
10.2.6 USB Module
See the following resources for help with USB design. The application notes contain hardware, software, and
application guides and implementations.
Starting a USB Design Using MSP430 MCUs
USB Field Firmware Updates on MSP430 MCUs
MSP430 USB Developers Package
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10.2.7 LDO Module
Solid decoupling on both the digital and analog supplies is required (best with two capacitors per supply, one
1 µF and one 100 nF [see Section 10.1.1]).
The LDO module is in its own power domain on chip (separate from DVCC). To use the Port U pins (PU.0 and
PU.1) this domain must be powered. If use of the Port U pins is needed and no voltage is supplied to LDOI, then
a 3.3-V supply to LDOO is needed. LDOO can act as an input only when the 3.3-V LDO is not enabled. When
the 3.3-V LDO is not needed in applications, keep LDOI tied low to make sure that the LDO module does not
draw excessive current when disabled.
10.2.7.1 Partial Schematic
LDOI
5 V
4.7 µF
LDOO
VSSU
220 nF
DVCC
(see Note)
A. Connection between LDOO and DVCC is optional. If connected, the LDO powers the device. LDOO can also supply other subsystems in
the application if the maximum output current for the LDO is not exceeded (see the LDO power system specifications in Section
8.8.18.1).
Figure 10-11. LDO Partial Schematic
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11 Device and Documentation Support
11.1 Getting Started
For more information on the MSP430™ family of devices and the tools and libraries that are available to help with
your development, visit the MSP430 ultra-low-power sensing & measurement MCUs overview.
11.2 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP
MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS. These
prefixes represent evolutionary stages of product development from engineering prototypes (XMS) through fully
qualified production devices (MSP).
XMS – Experimental device that is not necessarily representative of the final device's electrical specifications
MSP – Fully qualified production device
XMS devices are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices have been characterized fully, and the quality and reliability of the device have been demonstrated
fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices.
TI recommends that these devices not be used in any production system because their expected end-use failure
rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature
range, package type, and distribution format. Figure 11-1 provides a legend for reading the complete device
name.
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MSP 430 F 5 438 A I PM T -EP
Processor Family
MCU Platform
Device Type
Series
Feature Set
Optional: Additional Features
Optional: Tape and Reel
Packaging
Optional: Temperature Range
Optional: Revision
Processor Family
CC = Embedded RF Radio
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
MCU Platform
Device Type
430 = MSP430 low-power microcontroller platform
Memory Type
C = ROM
F = Flash
FR = FRAM
G = Flash
L = No nonvolatile memory
Specialized Application
AFE = Analog front end
BQ = Contactless power
CG = ROM medical
FE = Flash energy meter
FG = Flash medical
FW = Flash electronic flow meter
Series
1 = Up to 8 MHz
2 = Up to 16 MHz
3 = Legacy
4 = Up to 16 MHz with LCD driver
5 = Up to 25 MHz
6 = Up to 25 MHz with LCD driver
0 = Low-voltage series
Feature Set
Various levels of integration within a series
Updated version of the base part number
Optional: Revision
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging
http://www.ti.com/packaging
Optional: Tape and Reel
T = Small reel
R = Large reel
No markings = Tube or tray
Optional: Additional Features -EP = Enhanced product (–40°C to 105°C)
-HT = Extreme temperature parts (–55°C to 150°C)
-Q1 = Automotive Q100 qualified
Figure 11-1. Device Nomenclature
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11.3 Tools and Software
All MSP microcontrollers are supported by a wide variety of software and hardware development tools. Tools are
available from TI and various third parties. See them all at MSP430 ultra-low-power MCUs – Tools & software.
Table 11-1 lists the debug features of the MSP430FG662x and MSP430FG642x MCUs. See the Code
Composer Studio IDE for MSP430 MCUs User's Guide for details on the available features.
Table 11-1. Hardware Debug Features
BREAK-
POINTS
(N)
RANGE
BREAK-
POINTS
LPMx.5
DEBUGGING
SUPPORT
MSP430
ARCHITECTURE
4-WIRE
JTAG
2-WIRE
JTAG
CLOCK
CONTROL
STATE
SEQUENCER
TRACE
BUFFER
EnergyTrace++™
TECHNOLOGY
MSP430Xv2
Yes
Yes
8
Yes
Yes
Yes
Yes
No
No
Design Kits and Evaluation Modules
MSP-TS430PZ100AUSB - 100-pin target development board for MSP430FG6x MCUs
The MSP-TS430PZ100AUSB is a stand-alone 100-pin ZIF socket target board used to program and debug the
MSP430 MCU in system through the JTAG interface or the Spy-Bi-Wire (2-wire JTAG) protocol.
Educational BoosterPack MKII
The Educational BoosterPack MKII offers a high level of integration for developers to quickly prototype complete
solutions. Various analog and digital inputs/outputs are at your disposal including an analog joystick,
environmental and motion sensors, RGB LED, microphone, buzzer, color LCD display, and more.
Software
MSP430Ware™ software
MSP430Ware software is a collection of code examples, data sheets, and other design resources for all
MSP430 devices delivered in a convenient package. In addition to providing a complete collection of existing
MSP430 design resources, MSP430Ware software also includes a high-level API called MSP Driver Library. This
library makes it easy to program MSP430 hardware. MSP430Ware software is available as a component of
Code Composer Studio™ IDE or as a stand-alone package.
MSP430FG662x, MSP430FG642x code examples
C code examples are available for every MSP device that configures each of the integrated peripherals for
various application needs.
MSP Driver Library
The abstracted API of MSP Driver Library provides easy-to-use function calls that free you from directly
manipulating the bits and bytes of the MSP430 hardware. Thorough documentation is delivered through a
helpful API Guide, which includes details on each function call and the recognized parameters. Developers can
use Driver Library functions to write complete projects with minimal overhead.
Capacitive Touch Software Library
Free C libraries for enabling capacitive touch capabilities on MSP430 MCUs. The MSP430 MCU version of the
library features several capacitive touch implementations including the RO and RC method.
MSP EnergyTrace™ Technology
EnergyTrace technology for MSP430 microcontrollers is an energy-based code analysis tool that measures and
displays the energy profile of the application and helps to optimize it for ultra-low-power consumption.
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ULP (Ultra-Low Power) Advisor
ULP Advisor™ software is a tool for guiding developers to write more efficient code to fully use the unique ultra-
low-power features of MSP and MSP432 microcontrollers. Aimed at both experienced and new microcontroller
developers, ULP Advisor checks your code against a thorough ULP checklist to help minimize the energy
consumption of your application. At build time, ULP Advisor provides notifications and remarks to highlight areas
of your code that can be further optimized for lower power.
IEC60730 Software Package
The IEC60730 MSP430 software package helps customers comply with IEC 60730-1:2010 (Automatic Electrical
Controls for Household and Similar Use – Part 1: General Requirements) for up to Class B products, which
includes home appliances, arc detectors, power converters, power tools, e-bikes, and many others. The
IEC60730 MSP430 software package can be embedded in customer applications running on MSP430 MCUs to
help simplify the customer’s certification efforts of functional safety-compliant consumer devices to IEC
60730-1:2010 Class B.
Fixed Point Math Library for MSP
The MSP IQmath and Qmath Libraries are a collection of highly optimized and high-precision mathematical
functions for C programmers to seamlessly port a floating-point algorithm into fixed-point code on MSP430 and
MSP432 MCUs. These routines are typically used in computationally intensive real-time applications where
optimal execution speed, high accuracy, and ultra-low energy are critical. By using the IQmath and Qmath
libraries, it is possible to achieve execution speeds considerably faster and energy consumption considerably
lower than equivalent code written using floating-point math.
Floating Point Math Library for MSP430
Continuing to innovate in the low-power and low-cost microcontroller space, TI provides MSPMATHLIB.
Leveraging the intelligent peripherals of our devices, this floating-point math library of scalar functions that are up
to 26 times faster than the standard MSP430 math functions. Mathlib is easy to integrate into your designs. This
library is free and is integrated in both Code Composer Studio IDE and IAR Embedded Workbench IDE.
Development Tools
Code Composer Studio™ Integrated Development Environment for MSP Microcontrollers
Code Composer Studio integrated development environment (IDE) supports all MSP microcontroller devices.
Code Composer Studio IDE comprises a suite of embedded software utilities used to develop and debug
embedded applications. Code Composer Studio IDE includes an optimizing C/C++ compiler, source code editor,
project build environment, debugger, profiler, and many other features.
Command-Line Programmer
MSP Flasher is an open-source shell-based interface for programming MSP microcontrollers through a FET
programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP Flasher can download binary
files (.txt or .hex) directly to the MSP microcontroller without an IDE.
Uniflash Standalone Flash Tool for TI Microcontrollers
CCS Uniflash is a standalone tool used to program on-chip flash memory on TI MCUs and on-board flash
memory for Sitara processors. Uniflash has a GUI, command line, and scripting interface. CCS Uniflash is
available free of charge.
MSP-GANG Production Programmer
The MSP Gang Programmer is an MSP430 or MSP432 device programmer that can program up to eight
identical MSP430 or MSP432 flash or FRAM devices at the same time. The MSP Gang Programmer connects to
a host PC using a standard RS-232 or USB connection and provides flexible programming options that let the
user fully customize the process.
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11.4 Documentation Support
The following documents describe the MSP430FG662x and MSP430FG642x MCUs. Copies of these documents
are available on the Internet at www.ti.com.
Receiving Notification of Document Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for your
device on ti.com (for links to the product folders, see Section 11.5). In the upper right corner, click the "Alert me"
button. This registers you to receive a weekly digest of product information that has changed (if any). For change
details, check the revision history of any revised document.
Errata
MSP430FG6626 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430FG6625 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430FG6426 Device Erratasheet
Describes the known exceptions to the functional specifications.
MSP430FG6425 Device Erratasheet
Describes the known exceptions to the functional specifications.
User's Guides
MSP430F5xx and MSP430F6xx Family User's Guide
Detailed information on the modules and peripherals available in this device family.
MSP430 Flash Device Bootloader (BSL) User's Guide
The MSP430 bootloader (BSL) lets users communicate with embedded memory in the MSP430 microcontroller
during the prototyping phase, final production, and in service. Both the programmable memory (flash memory)
and the data memory (RAM) can be modified as required. Do not confuse the bootloader with the bootstrap
loader programs found in some digital signal processors (DSPs) that automatically load program code (and data)
from external memory to the internal memory of the DSP.
MSP430 Programming With the JTAG Interface
This document describes the functions that are required to erase, program, and verify the memory module of the
MSP430 flash-based and FRAM-based microcontroller families using the JTAG communication port. The
document also describes how to program the JTAG access security fuse that is available on all MSP430
devices. This document describes device access using both the standard 4-wire JTAG interface and the 2-wire
JTAG interface, which is also referred to as Spy-Bi-Wire (SBW).
MSP430 Hardware Tools User's Guide
This manual describes the hardware of the TI MSP-FET430 flash emulation tool (FET). The FET is the program
development tool for the MSP430 ultra-low-power microcontroller.
Application Reports
Designing With MSP430 MCUs and Segment LCDs
Segment liquid crystal displays (LCDs) are needed to provide information to users in a wide variety of
applications from smart meters to electronic shelf labels (ESLs) to medical equipment. This application note
helps explain how segmented LCDs work, the different features of the various LCD modules across the MSP430
MCU family, LCD hardware layout tips, guidance on writing efficient and easy-to-use LCD driver software, and
an overview of the portfolio of MSP430 devices that include different LCD features to aid in device selection.
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MSP430 32-kHz Crystal Oscillators
Selection of the correct crystal, correct load circuit, and proper board layout are important for a stable crystal
oscillator. This application report summarizes crystal oscillator function and explains the parameters to select the
correct crystal for MSP430 ultra-low-power operation. In addition, hints and examples for correct board layout
are given. The document also contains detailed information on the possible oscillator tests to ensure stable
oscillator operation in mass production.
MSP430 System-Level ESD Considerations
System-level ESD has become increasingly demanding with silicon technology scaling towards lower voltages
and the need for designing cost-effective and ultra-low-power components. This application report addresses
different ESD topics to help board designers and OEMs understand and design robust system-level designs.
Using the MSP430 RTC_B Module With Battery Backup Supply
Some applications need to retain an accurate real-time clock (RTC) through battery changes, power outages,
and other events. This application note describes how to use RTC_B with battery backup supply functionality to
retain the time and keep the RTC counting through loss of main power supply and how to reinitialize when the
main power supply is restored.
11.5 Related Links
Table 11-2 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 11-2. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
ORDER NOW
MSP430FG6626
MSP430FG6625
MSP430FG6426
MSP430FG6425
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
11.6 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.7 Trademarks
MSP430Ware™, Microstar Junior™, Code Composer Studio™, TI E2E™, MicroStar Junior™, MSP430™,
EnergyTrace™, ULP Advisor™, are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.8 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.9 Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as
defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled
product restricted by other applicable national regulations, received from disclosing party under nondisclosure
obligations (if any), or any direct product of such technology, to any destination to which such export or re-export
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is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.
Department of Commerce and other competent Government authorities to the extent required by those laws.
11.10 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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MSP430FG6626, MSP430FG6625
MSP430FG6426, MSP430FG6425
SLAS874B – MAY 2015 – REVISED SEPTEMBER 2020
www.ti.com
12 Mechanical, Packaging, and Orderable Information
12.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2020 Texas Instruments Incorporated
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Product Folder Links: MSP430FG6626 MSP430FG6625 MSP430FG6426 MSP430FG6425
PACKAGE OPTION ADDENDUM
www.ti.com
14-Sep-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
1000
2500
(1)
(2)
(3)
(4/5)
(6)
MSP430FG6425IPZR
ACTIVE
LQFP
PZ
100
113
Green (RoHS
& no Sb/Br)
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
FG6425
MSP430FG6425IZQWR
ACTIVE
BGA
ZQW
Green (RoHS
& no Sb/Br)
SNAGCU
FG6425
MICROSTAR
JUNIOR
MSP430FG6426IPZR
ACTIVE
ACTIVE
LQFP
PZ
100
113
1000
2500
Green (RoHS
& no Sb/Br)
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
FG6426
FG6426
MSP430FG6426IZQWR
BGA
MICROSTAR
JUNIOR
ZQW
Green (RoHS
& no Sb/Br)
SNAGCU
MSP430FG6625IPZR
ACTIVE
ACTIVE
LQFP
PZ
100
113
1000
2500
Green (RoHS
& no Sb/Br)
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
FG6625
FG6625
MSP430FG6625IZQWR
BGA
MICROSTAR
JUNIOR
ZQW
Green (RoHS
& no Sb/Br)
SNAGCU
MSP430FG6626IPZ
MSP430FG6626IPZR
ACTIVE
ACTIVE
LQFP
PZ
PZ
100
100
90
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
FG6626
FG6626
LQFP
1000
Green (RoHS
& no Sb/Br)
MSP430FG6626IZCAR
MSP430FG6626IZCAT
MSP430FG6626IZQWR
ACTIVE
ACTIVE
ACTIVE
NFBGA
NFBGA
ZCA
ZCA
ZQW
113
113
113
2500
250
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 85
-40 to 85
-40 to 85
FG6626
FG6626
FG6626
TBD
BGA
MICROSTAR
JUNIOR
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
MSP430FG6626IZQWT
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQW
113
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
FG6626
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Sep-2020
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MSP430FG6425IPZR
LQFP
PZ
100
113
1000
2500
330.0
330.0
24.4
16.4
17.0
7.3
17.0
7.3
2.1
1.5
20.0
12.0
24.0
16.0
Q2
Q1
MSP430FG6425IZQWR BGA MI
ZQW
CROSTA
R JUNI
OR
MSP430FG6426IPZR
LQFP
PZ
100
113
1000
2500
330.0
330.0
24.4
16.4
17.0
7.3
17.0
7.3
2.1
1.5
20.0
12.0
24.0
16.0
Q2
Q1
MSP430FG6426IZQWR BGA MI
ZQW
CROSTA
R JUNI
OR
MSP430FG6625IPZR
LQFP
PZ
100
113
1000
2500
330.0
330.0
24.4
16.4
17.0
7.3
17.0
7.3
2.1
1.5
20.0
12.0
24.0
16.0
Q2
Q1
MSP430FG6625IZQWR BGA MI
ZQW
CROSTA
R JUNI
OR
MSP430FG6626IPZR
LQFP
PZ
100
113
1000
2500
330.0
330.0
24.4
16.4
17.0
7.3
17.0
7.3
2.1
1.5
20.0
12.0
24.0
16.0
Q2
Q1
MSP430FG6626IZQWR BGA MI
ZQW
CROSTA
R JUNI
OR
MSP430FG6626IZQWT BGA MI
CROSTA
ZQW
113
250
180.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Feb-2019
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
R JUNI
OR
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
MSP430FG6425IPZR
LQFP
PZ
100
113
1000
2500
350.0
350.0
350.0
350.0
43.0
43.0
MSP430FG6425IZQWR BGA MICROSTAR
JUNIOR
ZQW
MSP430FG6426IPZR
LQFP
PZ
100
113
1000
2500
350.0
350.0
350.0
350.0
43.0
43.0
MSP430FG6426IZQWR BGA MICROSTAR
JUNIOR
ZQW
MSP430FG6625IPZR
LQFP
PZ
100
113
1000
2500
350.0
350.0
350.0
350.0
43.0
43.0
MSP430FG6625IZQWR BGA MICROSTAR
JUNIOR
ZQW
MSP430FG6626IPZR
LQFP
PZ
100
113
1000
2500
350.0
350.0
350.0
350.0
43.0
43.0
MSP430FG6626IZQWR BGA MICROSTAR
JUNIOR
ZQW
MSP430FG6626IZQWT BGA MICROSTAR
JUNIOR
ZQW
113
250
213.0
191.0
55.0
Pack Materials-Page 2
PACKAGE OUTLINE
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
ZCA0113A
A
7.1
6.9
B
BALL A1 CORNER
7.1
6.9
1 MAX
C
SEATING PLANE
0.08 C
0.25
0.15
BALL TYP
5.5
TYP
(0.75) TYP
SYMM
M
L
K
J
(0.75) TYP
H
G
F
E
D
C
SYMM
5.5
TYP
0.35
0.25
113X Ø
B
A
0.15
0.05
C
C
A B
1
2
3
4
5
6
7
8
9 10 11 12
0.5 TYP
0.5 TYP
4225149/A 08/2019
NanoFree is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
ZCA0113A
(0.5) TYP
(0.5) TYP
1
2
3
4
5
6
7
8
9
10 11 12
A
B
C
D
E
F
113X (Ø0.25)
SYMM
G
H
J
K
L
M
SYMM
LAND PATTERN EXAMPLE
SCALE: 10X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
EXPOSED
METAL
(Ø 0.25)
METAL
(Ø 0.25)
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4225149/A 08/2019
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. Refer to Texas Instruments
Literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
NFBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
ZCA0113A
(0.5) TYP
(0.5) TYP
1
2
3
4
5
6
7
8
9
10 11 12
A
B
C
D
E
F
(R0.05)
SYMM
G
H
J
METAL TYP
113X ( 0.25)
K
L
M
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.100 mm THICK STENCIL
SCALE: 10X
4225149/A 08/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
MECHANICAL DATA
MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996
PZ (S-PQFP-G100)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
75
M
0,08
51
50
76
26
100
0,13 NOM
1
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
0,25
16,20
SQ
0,05 MIN
0°–7°
15,80
1,45
1,35
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040149/B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
1
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相关型号:
MSP430FG6626IPZR
具有 128KB 闪存、10KB SRAM、16 位 Σ-Δ ADC、双通道 DAC、DMA、2 个运算放大器和 160 段 LCD 的 25MHz MCU | PZ | 100 | -40 to 85
TI
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