OPA1612AQDRQ1 [TI]
汽车类 1.1nV/√Hz 噪声、低功耗、精密音频运算放大器 | D | 8 | -40 to 125;
| 型号： | OPA1612AQDRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 1.1nV/√Hz 噪声、低功耗、精密音频运算放大器 | D | 8 | -40 to 125 放大器 光电二极管 运算放大器 |
| 文件： | 总31页 (文件大小：998K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA1612-Q1
ZHCSED7A –NOVEMBER 2015–REVISED NOVEMBER 2015
Burr-Brown Audio
OPA1612-Q1 SoundPlus 高性能、双极输入音频运算放大器
1 特性
3 概述
1
•
符合汽车应用要求
具有符合 AEC-Q100 的下列结果：
OPA1612-Q1 器件是一款双通道、 SoundPlus™双极
输入运算放大器，在 1kHz 频率下可实现很低的噪声密
度 (1.1nV/√Hz) 以及超低失真 (0.000015%)。
OPA1612-Q1 器件可在 2kΩ 负载条件下提供摆幅在
600mV 以内的轨到轨输出，这有助于提高余量并实现
动态范围的最大化。 此外，这些器件还具有 ±30mA
高输出驱动能力。
•
–
器件温度 1 级：-40℃ 至 +125℃ 的环境运行温
度范围
–
–
器件人体放电模式 (HBM) 分类等级 2
器件组件充电模式 (CDM) 分类等级 C6
•
•
•
出色音质
超低噪声：1kHz 时为 1.1nV/√Hz
这些器件支持 ±2.25V 到 ±18V 的宽电源电压范围，每
通道电源电流仅为 3.6mA。 OPA1612-Q1 运算放大器
的单位增益稳定，在宽负载条件范围内可提供出色的动
态性能。
超低失真：
1kHz 时为 0.000015%
•
•
•
•
•
高压摆率：27V/μs
高带宽：40MHz (G = +1)
高开环增益：130dB
单位增益稳定
双通道型号具有完全独立的电路，即使处于过驱或过载
状态也可在通道间实现最低串扰和零交互。
低静态电流：
每通道 3.6mA
OPA1612-Q1 器件采用小外形尺寸集成电路 (SOIC)-8
封装 封装。 该器件的额定工作温度范围为 –40°C 至
+125°C。
•
•
轨到轨输出
宽电源电压范围：±2.25V 至 ±18V
器件信息(1)
2 应用
器件型号
封装
SOIC (8)
封装尺寸（标称值）
•
•
•
•
•
•
专业音频设备
OPA1612-Q1
4.90mm x 3.91mm
麦克风前置放大器
模数混合控制台
播音室设备
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
音频测试和测量
高端 A/V 接收器
THD+N 比与输出幅值间的关系
功能框图
–80
V+
0.01
0.001
1-kHz Signal
BW = 80 kHz
RSOURCE = 0 Ω
–100
–120
–140
–160
0.0001
G = 1, RL = 600 Ω
G = 1, RL = 2 kΩ
G = –1, RL = 600 Ω
Pre-Output
Driver
OUT
0.00001
0.000001
G = –1, RL = 2 kΩ
G = 10, RL = 600 Ω
IN–
IN+
G = 10, RL = 2 kΩ
0.01
0.1
1
10 20
Output Amplitude (VRMS
)
V–
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLOS931
OPA1612-Q1
ZHCSED7A –NOVEMBER 2015–REVISED NOVEMBER 2015
www.ti.com.cn
目录
8.3 Feature Description................................................. 14
8.4 Device Functional Modes........................................ 17
Application and Implementation ........................ 18
9.1 Application Information............................................ 18
9.2 Typical Application .................................................. 18
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
概述.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics: VS = ±2.25 V to ±18 V .... 5
6.6 Typical Characteristics.............................................. 7
Parameter Measurement Information ................ 11
Detailed Description ............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 14
9
10 Power-Supply Recommendations ..................... 22
11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
11.2 Layout Example .................................................... 23
12 器件和文档支持 ..................................................... 24
12.1 文档支持................................................................ 24
12.2 社区资源................................................................ 24
12.3 商标....................................................................... 24
12.4 静电放电警告......................................................... 24
12.5 Glossary................................................................ 24
13 机械、封装和可订购信息....................................... 24
7
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (November 2015) to Revision A
Page
•
已更改 器件状态“产品预览”至“量产数据” ................................................................................................................................ 1
2
Copyright © 2015, Texas Instruments Incorporated
OPA1612-Q1
www.ti.com.cn
ZHCSED7A –NOVEMBER 2015–REVISED NOVEMBER 2015
5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
OUT A
–IN A
+IN A
V–
1
2
3
4
8
7
6
5
V+
A
OUT B
–IN B
+IN B
B
Pin Functions
PIN
I/O
DESCRIPTION
NO.
1
NAME
OUT A
–IN A
+IN A
V–
O
I
Output, channel A
2
Inverting input, channel A
Noninverting input, channel A
Negative (lowest) power supply
Inverting input, channel B
Noninverting input, channel B
Output, channel B
3
I
4
—
I
5
+IN B
–IN B
OUT B
V+
6
I
7
O
—
8
Positive (highest) power supply
Copyright © 2015, Texas Instruments Incorporated
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OPA1612-Q1
ZHCSED7A –NOVEMBER 2015–REVISED NOVEMBER 2015
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
40
UNIT
V
(2)
VS
Supply voltage
Input voltage
(V–) – 0.5
(V+) + 0.5
±10
V
Input current (all pins except power-supply pins)
Output short-circuit(2)
Operating temperature
Junction temperature
Storage temperature
mA
Continuous
TA
–55
–65
125
200
150
°C
°C
°C
TJ
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Short-circuit to VS / 2 (ground in symmetrical dual supply setups), one amplifier per package.
6.2 ESD Ratings
VALUE
±3000
±1000
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5 (±2.25)
–40
NOM
MAX
36 (±18)
85
UNIT
V
Supply voltage (V+ – V–)
Specified temperature
°C
6.4 Thermal Information
OPA1612-Q1
D (SOIC)
8 PINS
111.9
26.5
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
0.8
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
20.9
ψJB
1.6
RθJC(bot)
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
Copyright © 2015, Texas Instruments Incorporated
OPA1612-Q1
www.ti.com.cn
ZHCSED7A –NOVEMBER 2015–REVISED NOVEMBER 2015
6.5 Electrical Characteristics: VS = ±2.25 V to ±18 V
At TA = 25°C and RL = 2 kΩ, unless otherwise noted. VCM = VOUT = midsupply, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AUDIO PERFORMANCE
0.000015%
–136
THD+N
IMD
Total harmonic distortion + noise
Intermodulation distortion
G = +1, f = 1 kHz, VO = 3 VRMS
dB
dB
dB
dB
0.000015%
–136
SMPTE/DIN two-tone, 4:1 (60 Hz and 7 kHz),
G = +1, VO = 3 VRMS
0.000012%
–138
DIM 30 (3-kHz square wave and 15-kHz sine
wave), G = +1, VO = 3 VRMS
0.000008%
–142
CCIF twin-tone (19 kHz and 20 kHz), G = +1,
VO = 3 VRMS
FREQUENCY RESPONSE
G = 100
G = 1
80
40
MHz
MHz
V/μs
MHz
ns
GBW
SR
Gain-bandwidth product
Slew rate
G = –1
27
Full-power bandwidth(1)
Overload recovery time
Channel separation (dual)
VO = 1 VPP
G = –10
f = 1 kHz
4
500
–130
dB
NOISE
Input voltage noise
f = 20 Hz to 20 kHz
f = 10 Hz
1.2
2
μVPP
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
pA/√Hz
en
Input voltage noise density(2)
f = 100 Hz
f = 1 kHz
1.5
1.1
3
1.5
f = 10 Hz
In
Input current noise density
f = 1 kHz
1.7
OFFSET VOLTAGE
VOS
Input offset voltage
VOS over temperature(2)
VS = ±15 V
±100
1
±500
μV
dVOS/dT
PSRR
TA = –40°C to +125°C
VS = ±2.25 V to ±18 V
4
1
μV/°C
μV/V
Power-supply rejection ratio
0.1
INPUT BIAS CURRENT
VCM = 0 V
±60
±60
±250
±300
350
nA
nA
nA
nA
IB
Input bias current
VCM = 0 V, DRG package only
TA = –40°C to +125°C
VCM = 0 V
IB over temperature(2)
Input offset current
IOS
±25
120
±175
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
Common-mode rejection ratio
(V–) + 2
110
(V+) – 2
V
CMRR
(V–) + 2 V ≤ VCM ≤ (V+) – 2 V
dB
INPUT IMPEDANCE
Differential
Common-mode
20k || 8
109 || 2
Ω || pF
Ω || pF
(1) Full-power bandwidth = SR / (2π × VP), where SR = slew rate.
(2) Specified by design and characterization.
Copyright © 2015, Texas Instruments Incorporated
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Electrical Characteristics: VS = ±2.25 V to ±18 V (continued)
At TA = 25°C and RL = 2 kΩ, unless otherwise noted. VCM = VOUT = midsupply, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPEN-LOOP GAIN
(V–) + 0.2 V ≤ VO ≤ (V+) – 0.2 V, RL = 10 kΩ
(V–) + 0.6 V ≤ VO ≤ (V+) – 0.6 V, RL = 2 kΩ
114
110
130
114
dB
dB
AOL
Open-loop voltage gain
Voltage output
OUTPUT
VOUT
RL = 10 kΩ, AOL ≥ 114 dB
RL = 2 kΩ, AOL ≥ 110 dB
(V–) + 0.2
(V–) + 0.6
(V+) – 0.2
(V+) – 0.6
V
V
IOUT
ZO
Output current
See Figure 27
See Figure 28
55
mA
Ω
Open-loop output impedance
Source, VS = ±18 V
Sink, VS = ±18 V
mA
mA
pF
ISC
Short-circuit current
–62
CLOAD
Capacitive load drive
See Typical Characteristics
POWER SUPPLY
VS
IQ
Specified voltage
±2.25
±18
4.5
5.5
V
Quiescent current (per channel)
IQ over Temperature(2)
IOUT = 0 A
3.6
mA
mA
TA = –40°C to +125°C
TEMPERATURE RANGE
Specified range
–40
–55
125
125
°C
°C
Operating range
6
Copyright © 2015, Texas Instruments Incorporated
OPA1612-Q1
www.ti.com.cn
ZHCSED7A –NOVEMBER 2015–REVISED NOVEMBER 2015
6.6 Typical Characteristics
At TA = 25°, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.
100
Current Noise Density
Voltage Noise Density
10
1
0.1
1
10
100
1k
10k
100k
Time (1 s/div)
Frequency (Hz)
Figure 2. 0.1-Hz to 10-Hz Noise
Figure 1. Input Voltage Noise Density and Input Current
Noise Density vs Frequency
30
25
20
15
10
5
10k
VS
VS
VS
=
=
=
15 V
5 V
Total Output Voltage Noise
Resistor Noise
2.25 V
1k
Maximum output
voltage range
without slew-rate
induced distortion
100
10
1
0
100
1k
10k
100k
1M
10k
100k
Frequency (Hz)
1M
10M
Source Resistance, RS (Ω)
EO2 = en2 + (in × RS)2 + 4kRTS
See Figure 29
Figure 3. Voltage Noise vs Source Resistance
Figure 4. Maximum Output Voltage vs Frequency
25
140
120
100
80
180
160
140
120
100
80
G = 10
G = –1
G = 1
Gain
20
15
10
5
Phase
60
0
40
-5
20
60
-10
-15
-20
-25
0
40
-20
-40
20
0
100
1k
10k
100k
1M
10M
100M
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
Figure 5. Gain and Phase vs Frequency
Figure 6. Closed-Loop Gain vs Frequency
Copyright © 2015, Texas Instruments Incorporated
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Typical Characteristics (continued)
At TA = 25°, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.
0.0001
-120
-80
0.01
0.001
G = 1, RL = 600 Ω
G = 1, RL = 2 kΩ
G = –1, RL = 600 Ω
G = –1, RL = 2 kΩ
G = 10, RL = 600 Ω
G = 10, RL = 2 kΩ
RSOURCE = 0 Ω
RSOURCE = 150 Ω
RSOURCE = 300 Ω
RSOURCE = 600 Ω
-100
-120
-140
0.0001
0.00001
0.00001
-140
10
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
BW = 80 KHz
VOUT = 3VRMS
BW = 80 KHz
VOUT = 3VRMS
See Figure 30
Figure 7. THD+N Ratio vs Frequency
Figure 8. THD+N Ratio vs Frequency
-100
-120
-140
0.001
-80
0.01
0.001
G = 1, RL = 600 Ω
G = 1, RL = 2 kΩ
G = –1, RL = 600 Ω
G = –1, RL = 2 kΩ
G = 11, RL = 600 Ω
G = 11, RL = 2 kΩ
RSOURCE = 0 Ω
RSOURCE = 150 Ω
RSOURCE = 300 Ω
RSOURCE = 600 Ω
-100
-120
-140
0.0001
0.0001
0.00001
0.00001
10
100
1k
10k
100k
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
BW > 500 KHz
VOUT = 3VRMS
BW > 500 KHz
VOUT = 3VRMS
See Figure 30
Figure 9. THD+N Ratio vs Frequency
Figure 10. THD+N Ratio vs Frequency
–80
0.01
0.001
-80
0.01
0.001
SMPTE/DIN, Two-Tone, 4:1 (60 Hz and 7 kHz)
DIM30, (3-kHz square wave and 15-kHz
sine wave)
–100
–120
–140
–160
-100
-120
-140
-160
CCIF, Twin-Tone, (19 kHz and 20 kHz)
0.0001
0.0001
G = 1, RL = 600 Ω
G = 1, RL = 2 kΩ
G = –1, RL = 600 Ω
0.00001
0.000001
0.00001
0.000001
G = –1, RL = 2 kΩ
G = 10, RL = 600 Ω
G = 10, RL = 2 kΩ
0.01
0.1
1
10 20
0.1
1
10
20
Output Amplitude (VRMS
)
Output Amplitude (VRMS)
1-kHz Signal
BW = 80 KHz
RSOURCE = 0 Ω
G = 1
Figure 11. THD+N Ratio vs Output Amplitude
Figure 12. Intermodulation Distortion vs Output Amplitude
8
Copyright © 2015, Texas Instruments Incorporated
OPA1612-Q1
www.ti.com.cn
ZHCSED7A –NOVEMBER 2015–REVISED NOVEMBER 2015
Typical Characteristics (continued)
At TA = 25°, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.
-80
RL = 600 Ω
160
140
120
100
80
–PSRR
+PSRR
CMRR
-90
RL = 2 kΩ
-100
RL = 5 kΩ
-110
-120
-130
-140
-150
-160
-170
-180
60
40
20
0
10
100
1k
10k
100k
1
10
100
1k
10k 100k
1M
10M 100M
Frequency (Hz)
VS = ±15 V
Frequency (Hz)
VOUT = 3.5 VRMS
G = 1
Figure 13. Channel Separation vs Frequency
Figure 14. CMRR and PSRR vs Frequency
(Referred to Input)
Time (0.1 µs/div)
Time (0.1 µs/div)
G = –1
CL = 50 pF
See Figure 32
G = 1
CL = 50 pF
See Figure 31
Figure 16. Small-Signal Step Response (100 mV)
Figure 15. Small-Signal Step Response (100 mV)
RF = 75 Ω
RF = 0 Ω
Time (0.5 µs/div)
Time (0.5 µs/div)
G = 1
CL = 50 pF
RL = 2 kΩ
G = –1
CL = 50 pF
RL = 2 kΩ
See the Input Protection section
Figure 17. Large-Signal Step Response
Figure 18. Large-Signal Step Response
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Typical Characteristics (continued)
At TA = 25°, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.
50
RS = 0 Ω
25
20
15
10
5
RS = 0 Ω
RS = 25 Ω
RS = 50 Ω
RS = 25 Ω
40
30
20
10
0
RS = 50 Ω
0
0
100
200
300
400
500
600
0
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
Capacitive Load (pF)
G = 1
See Figure 33
G = –1
See Figure 34
Figure 19. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
Figure 20. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
1.0
120
10 kΩ
–IB
+IB
IOS
0.8
2 kΩ
100
80
60
40
20
0
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
-40
-15
10
35
60
85
-40
-15
10
35
50
85
Temperature (°C)
Temperature (°C)
Figure 21. Open-Loop Gain vs Temperature
Figure 22. IB and IOS vs Temperature
5.0
4.5
4.0
3.5
3.0
2.5
2.0
80
70
60
50
40
30
20
10
0
–IB
+IB
IOS
Common-Mode Range
-10
-20
-18
-12
-6
0
6
12
18
-40
-15
10
35
60
85
Common-Mode Voltage (V)
Temperature (°C)
VS = ±18 V
Figure 23. IB and IOS vs Common-Mode Voltage
Figure 24. Quiescent Current vs Temperature
10
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OPA1612-Q1
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ZHCSED7A –NOVEMBER 2015–REVISED NOVEMBER 2015
Typical Characteristics (continued)
At TA = 25°, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.
4.0
75
70
65
60
55
50
45
40
35
30
–ISC
+ISC
3.9
3.8
3.7
3.6
3.5
3.4
3.3
3,2
Specified Supply-Voltage Range
3.1
3.0
0
4
8
12
16
20
24
28
32
36
-50
-25
0
25
Temperature (°C)
50
75
100
125
Supply Voltage (V)
Figure 25. Quiescent Current vs Supply Voltage
Figure 26. Short-Circuit Current vs Temperature
15
14
13
10k
1k
100
–40°C
25°C
85°C
10
1
-13
-14
-15
0.1
0
10
20
30
40
50
10
100
1k
10k
100k
1M
10M
100M
Output Current (mA)
Frequency (Hz)
VS = ±15 V
Both channels driven simultaneously
Figure 27. Output Voltage vs Output Current
Figure 28. Open-Loop Output Impedance vs Frequency
7 Parameter Measurement Information
EO
RS
Figure 29. Circuit for Figure 3—Voltage Noise vs Source Resistance
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www.ti.com.cn
Parameter Measurement Information (continued)
15 V
Device
–15 V
RSOURCE
RL
Figure 30. Circuit for Figure 8 and Figure 10—THD+N Ratio vs Frequency
15 V
Device
RL
CL
–15 V
Figure 31. Circuit for Figure 15—Small-Signal Step Response (100 mV)
CF = 5.6 pF
RI = 2 kΩ
R
F = 2 kΩ
15 V
Device
–15 V
CL
Figure 32. Circuit for Figure 16—Small-Signal Step Response (100 mV)
15 V
RS
Device
RL
CL
–15 V
Figure 33. Circuit for Figure 19—Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
12
Copyright © 2015, Texas Instruments Incorporated
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ZHCSED7A –NOVEMBER 2015–REVISED NOVEMBER 2015
Parameter Measurement Information (continued)
CF = 5.6 pF
RF = 2 kΩ
15 V
RI = 2 kΩ
RS
Device
CL
–15 V
Figure 34. Circuit for Figure 20—Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
Copyright © 2015, Texas Instruments Incorporated
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8 Detailed Description
8.1 Overview
The OPA1612-Q1 bipolar-input operational amplifierachieves very low 1.1-nV/√Hz noise density with an ultralow
distortion of 0.000015% at 1 kHz. The rail-to-rail output swing, within 600 mV with a 2-kΩ load, increases
headroom and maximizes dynamic range. These devices also have a high output drive capability of ±40 mA. The
wide supply range of ±2.25 V to ±18 V, on only 3.6 mA of supply current per channel, makes them applicable to
both 5-V systems and 36-V audio applications. The OPA1612-Q1 op amp is unity-gain stable and provide
excellent dynamic behavior over a wide range of load conditions.
8.2 Functional Block Diagram
V+
Pre-Output Driver
OUT
IN–
IN+
V–
8.3 Feature Description
8.3.1 Power Dissipation
The OPA1612-Q1 op amp is capable of driving 2-kΩ loads with a power-supply voltage up to ±18 V. Internal
power dissipation increases when operating at high supply voltages. Copper leadframe construction used in the
OPA1612-Q1 op amp improves heat dissipation compared to conventional materials. Circuit board layout can
also help minimize junction temperature rise. Wide copper traces help dissipate the heat by acting as an
additional heat sink. Temperature rise can be further minimized by soldering the devices to the circuit board
rather than using a socket.
8.3.2 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
14
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Feature Description (continued)
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. Figure 35 shows the ESD circuits contained in the OPA1612-Q1 device (indicated by the dashed line
area). The ESD protection circuitry involves several current-steering diodes connected from the input and output
pins and routed back to the internal power-supply lines, where they meet at an absorption device internal to the
operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.
RF
+VS
+V
RI
ESD Current-
–IN
Steering Diodes
OUT
Op-Amp
Core
+IN
Edge-Triggered ESD
Absorption Circuit
RL
ID
(1)
VIN
–V
–VS
(1) VIN = +VS + 500 mV.
Figure 35. Equivalent Internal ESD Circuitry and its Relation to a Typical Circuit Application
An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, high-
current pulse when discharged through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage to the core. The energy absorbed
by the protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more of the amplifier device pins, current flows through one or
more of the steering diodes. Depending on the path that the current takes, the absorption device may activate.
The absorption device internal to the OPA1612-Q1 device triggers when a fast ESD voltage pulse is impressed
across the supply pins. Once triggered, the absorption device quickly activates and clamps the ESD pulse to a
safe voltage level.
When the operational amplifier connects into a circuit such as the one Figure 35 shows, the ESD protection
components are intended to remain inactive and not become involved in the application circuit operation.
However, circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin.
If this condition occurs, some of the internal ESD protection circuits may possibly be biased on, and conduct
current. Any such current flow occurs through steering diode paths and rarely involves the absorption device.
Figure 35 shows a specific example where the input voltage, VIN, exceeds the positive supply voltage (+VS) by
500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If +VS can sink the
current, one of the upper input steering diodes conducts and directs current to +VS. Excessively high current
levels can flow with increasingly higher VIN. As a result, the datasheet specifications recommend that applications
limit the input current to 10 mA.
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Feature Description (continued)
If the supply is not capable of sinking the current, VIN may begin sourcing current to the operational amplifier, and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings. In extreme but rare cases, the absorption
device triggers on while +VS and –VS are applied. If this event happens, a direct current path is established
between the +VS and –VS supplies. The power dissipation of the absorption device is quickly exceeded, and the
extreme internal heating destroys the operational amplifier.
Another common question involves what happens to the amplifier if an input signal is applied to the input while
the power supplies +VS or –VS are at 0 V. Again, the result depends on the supply characteristic while at 0 V, or
at a level below the input signal amplitude. If the supplies appear as high impedance, then the operational
amplifier supply current may be supplied by the input source via the current steering diodes. This state is not a
normal bias condition; the amplifier most likely does not operate normally. If the supplies are low impedance,
then the current through the steering diodes can become quite high. The current level depends on the ability of
the input source to deliver current, and any resistance in the input path.
If there is an uncertainty about the ability of the supply to absorb this current, external zener diodes may be
added to the supply pins; see Figure 35. The zener voltage must be selected such that the diode does not turn
on during normal operation. However, the zener diode voltage must be low enough so that the zener diode
conducts if the supply pin begins to rise above the safe operating supply voltage level.
8.3.3 Operating Voltage
The OPA1612-Q1 op amp operates from ±2.25-V to ±18-V supplies while maintaining excellent performance.
The OPA1612-Q1 device can operate with as little as +4.5 V between the supplies and with up to +36 V between
the supplies. However, some applications do not require equal positive and negative output voltage swing. With
the OPA1612-Q1 device, power-supply voltages do not need to be equal. For example, the positive supply could
be set to +25 V with the negative supply at –5 V.
In all cases, the common-mode voltage must be maintained within the specified range. In addition, key
parameters are assured over the specified temperature range of TA = –40°C to +85°C. Parameters that vary with
operating voltage or temperature are shown in the Typical Characteristics section.
8.3.4 Input Protection
The input terminals of the OPA1612-Q1 device is protected from excessive differential voltage with back-to-back
diodes, as Figure 36 shows. In most circuit applications, the input protection circuitry has no consequence.
However, in low-gain or G = +1 circuits, fast ramping input signals can forward bias these diodes because the
output of the amplifier cannot respond rapidly enough to the input ramp. This effect is illustrated in Figure 17 of
the Typical Characteristics section. If the input signal is fast enough to create this forward bias condition, the
input signal current must be limited to 10 mA or less. If the input signal current is not inherently limited, an input
series resistor (RI) or a feedback resistor (RF) can be used to limit the signal input current. This input series
resistor degrades the low-noise performance of the OPA1612-Q1 device and is examined in the Noise
Performance section. Figure 36 shows an example configuration when both current-limiting input and feedback
resistors are used.
RF
–
Device
Output
RI
+
Input
Figure 36. Pulsed Operation
16
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8.4 Device Functional Modes
The OPA1612-Q1 device has a single functional mode. The device is powered on as long as the power supply
voltage is between 4.5 V (±2.25 V) and 36 V (±18 V).
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The OPA1612-Q1 device is unity-gain stable, precision op amp with very low noise; these devices are also free
from output phase reversal. Applications with noisy or high-impedance power supplies require decoupling
capacitors close to the device power-supply pins. In most cases, 0.1-μF capacitors are adequate.
9.2 Typical Application
Figure 37 shows how to use the OPA1612-Q1 device as an amplifier for professional audio headphones. The
circuit shows the left side stereo channel. An identical circuit is used to drive the right side stereo channel.
820 Ω
2200 pF
0.1 µF
+VA
(15 V)
330 Ω
IOUTL+
Device
2700 pF
–VA
(–15 V)
680 Ω
620 Ω
0.1 µF
+VA
(15 V)
0.1 µF
Audio DAC
with Differential
Current
Outputs
100 Ω
L Ch
Output
820 Ω
Device
8200 pF
2200 pF
–VA
(–15 V)
0.1 µF
0.1 µF
+VA
(15 V)
680 Ω
620 Ω
IOUTL–
Device
2700 pF
330 Ω
–VA
(–15 V)
0.1 µF
Figure 37. Audio DAC Post Filter (I/V Converter and Low-Pass Filter)
18
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Typical Application (continued)
9.2.1 Design Requirements
Use Equation 1 to calculate the total circuit noise.
EO2 = en2 + (inRS)2 + 4kTRS
where
•
•
•
•
•
en = voltage noise
In = current noise
RS = source impedance
k = Boltzmann’s constant = 1.38 × 10–23 J/K
T = temperature in degrees Kelvin (K)
(1)
9.2.2 Detailed Design Procedure
9.2.2.1 Noise Performance
Figure 40 shows the total circuit noise for varying source impedances with the op amp in a unity-gain
configuration (no feedback resistor network, and therefore no additional noise contributions).
The OPA1612-Q1 device (GBW = 40 MHz, G = +1) is shown with total circuit noise calculated. The op amp
contributes both a voltage noise component and a current noise component. The voltage noise is commonly
modeled as a time-varying component of the offset voltage. The current noise is modeled as the time-varying
component of the input bias current and reacts with the source resistance to create a voltage component of
noise. Therefore, the lowest noise op amp for a given application depends on the source impedance. For low
source impedance, current noise is negligible, and voltage noise generally dominates. The low voltage noise of
the OPA1612-Q1 device makes it a good choice for use in applications where the source impedance is less than
1 kΩ.
9.2.2.1.1 Basic Noise Calculations
Design of low-noise op amp circuits requires careful consideration of a variety of possible noise contributors:
noise from the signal source, noise generated in the op amp, and noise from the feedback network resistors. The
total noise of the circuit is the root-sum-square combination of all noise components.
The resistive portion of the source impedance produces thermal noise proportional to the square root of the
resistance. Figure 40 plots this function. The source impedance is usually fixed; consequently, select the op amp
and the feedback resistors to minimize the respective contributions to the total noise.
Figure 38 shows both inverting and noninverting op amp circuit configurations with gain. In circuit configurations
with gain, the feedback network resistors also contribute noise.
The current noise of the op amp reacts with the feedback resistors to create additional noise components. The
feedback resistor values can generally be chosen to make these noise sources negligible. The equations for total
noise are shown for both configurations.
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Typical Application (continued)
Noise in Noninverting Gain Configuration
Noise at the output:
R2
é
ù2
ú
2 é
1+
ù2
ú
R2
R2
2
)
2
2
2
2
EO = 1+
en + e12 + e2 + i R
+ eS + i R
(
(
)
ê
ê
n
2
n
S
R1 û
R1 û
R1
ë
ë
EO
where
é
ù
ú
R2
· eS
=
4kTRS ´ 1+
= thermal noise of R
S
RS
ê
R1 û
ë
é
ê
ë
ù
ú
R2
VS
· e1 = 4kTR ´
= thermal noise of R
1
1
R1 û
· e2 = 4kTR2 = thermal noise of R2
Noise in Inverting Gain Configuration
Noise at the output:
R2
é
ù2
ú
R2
2
)
2
2
2
2
EO = 1+
en + e12 + e2 + i R
+ eS
(
ê
n
2
R1 + RS û
R1
ë
EO
RS
where
é
ê
ë
ù
ú
R2
· eS
=
4kTRS
´
= thermal noise of R
VS
S
R1 + RS û
é
ê
ë
ù
ú
R2
· e1 = 4kTR ´
= thermal noise of R
1
1
R1 + RS û
· e2 = 4kTR2 = thermal noise of R2
At 1 kHz, en = 1.1 nV/√Hz and in = 1.7 pA/√Hz.
Figure 38. Noise Calculation in Gain Configurations
9.2.2.2 Total Harmonic Distortion Measurements
The OPA1612-Q1 op amp has excellent distortion characteristics. THD + noise is below 0.00008% (G = +1, VO =
3 VRMS, BW = 80 kHz) throughout the audio frequency range, 20 Hz to 20 kHz, with a 2-kΩ load (see Figure 7 for
characteristic performance).
The distortion produced by OPA1612-Q1 op amp is below the measurement limit of many commercially available
distortion analyzers. However, a special test circuit (such as Figure 39 shows) can be used to extend the
measurement capabilities.
Op amp distortion can be considered an internal error source that can be referred to the input. Figure 39 shows a
circuit that causes the op amp distortion to be 101 times (or approximately 40 dB) greater than that normally
produced by the op amp. The addition of R3 to the otherwise standard noninverting amplifier configuration alters
the feedback factor or noise gain of the circuit. The closed-loop gain is unchanged, but the feedback available for
error correction is reduced by a factor of 101, thus extending the resolution by 101. Note that the input signal and
load applied to the op amp are the same as with conventional feedback without R3. Keep the value of R3 small to
minimize its effect on the distortion measurements.
20
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Typical Application (continued)
Validity of this technique can be verified by duplicating measurements at high gain and/or high frequency where
the distortion is within the measurement capability of the test equipment. Measurements for this data sheet were
made with an audio precision system two distortion and noise analyzer, which greatly simplifies such repetitive
measurements. The measurement technique can, however, be performed with manual distortion measurement
instruments.
R1
R2
R3
Device
VO = 3 VRMS
R2
R1
Signal Gain = 1+
R2
Distortion Gain = 1+
R1 || R3
Generator
Output
Analyzer
Input
Audio Precision
System Two(1)
Load
with PC Controller
(1) For measurement bandwidth, see Figure 7 through Figure 12.
SIGNAL
GAIN
DISTORTION
GAIN
R1
R2
R3
1
101
101
110
∞
1 kΩ
10 Ω
–1
10
4.99 kΩ
549 Ω
4.99 kΩ
4.99 kΩ
49.9 kΩ
49.9 kΩ
Figure 39. Distortion Test Circuit
9.2.2.3 Capacitive Loads
The dynamic characteristics of the OPA1612-Q1 device is optimized for commonly encountered gains, loads,
and operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the
phase margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads
must be isolated from the output. The simplest way to achieve this isolation is to add a small resistor (RS equal to
50 Ω, for example) in series with the output.
This small series resistor also prevents excess power dissipation if the output of the device becomes shorted.
Figure 19 and Figure 20 illustrate graphs of Small-Signal Overshoot vs Capacitive Load for several values of RS.
For details of analysis techniques and application circuits, refer to Applications Bulletin AB-028, Feedback Plots
Define Op Amp AC Performance (SBOA015).
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Typical Application (continued)
9.2.3 Application Curves
Equation 1 applies to Figure 40 and Figure 41.
10k
Total Output Voltage Noise
Resistor Noise
EO
1k
RS
100
10
1
100
1k
10k
100k
1M
Source Resistance, RS (Ω)
Figure 40. Noise Performance of the OPA1612-Q1
in Unity-Gain Buffer Configuration
Figure 41. Circuit for Figure 40
10 Power-Supply Recommendations
The OPA1612-Q1 device is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications
apply from –40°C to +85°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics section.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings table.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, refer to the Layout
section.
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry.
–
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
Separate grounding for analog and digital portions of the circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds while paying attention to the flow of the ground current. For more detailed information,
refer to the application report, Circuit Board Layout Techniques (SLOA089).
•
In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be keep them separate, crossing the sensitive trace perpendicular as
22
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Layout Guidelines (continued)
opposed to in parallel with the noisy trace is the preferred method.
•
•
•
Place the external components as close to the device as possible. As shown in Figure 42, keeping RF and
RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
11.2 Layout Example
R±N
RG
V±N
+
VOUT
RF
(Schematic Representation)
Place components
close to device and to
each other to reduce
parasitic errors
Run the input traces
as far away from
the supply lines
as possible
VS+
RF
NC
NC
RG
GND
GND
± ±N
+±N
V±
V+
OUT
NC
V±N
R±N
Use low-ESR, ceramic
bypass capacitor
Only needed for
dual-supply
operation
GND
VS±
(or GND for single supply)
VOUT
Ground (GND) plane on another layer
Figure 42. Operational Amplifier Board Layout for a Noninverting Configuration
版权 © 2015, Texas Instruments Incorporated
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OPA1612-Q1
ZHCSED7A –NOVEMBER 2015–REVISED NOVEMBER 2015
www.ti.com.cn
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档ꢀ
相关文档如下：
•
•
《反馈曲线图定义运算放大器交流性能》，SBOA015
《电路板布局布线技巧》，SLOA089
12.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 商标
E2E is a trademark of Texas Instruments.
SoundPlus is a trademark of Texas Instruments, Inc.
All other trademarks are the property of their respective owners.
12.4 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页中包括机械、封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不
对本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
24
版权 © 2015, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA1612AQDRQ1
ACTIVE
SOIC
D
8
2500 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
1612Q1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA1612AQDRQ1
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
OPA1612AQDRQ1
D
8
2500
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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