OPA1679QRUMRQ1 [TI]
汽车类四通道、低噪声 4.5nV/rtHz、低失真 120dB 音频运算放大器 | RUM | 16 | -40 to 125;
| 型号： | OPA1679QRUMRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类四通道、低噪声 4.5nV/rtHz、低失真 120dB 音频运算放大器 | RUM | 16 | -40 to 125 放大器 运算放大器 |
| 文件： | 总52页 (文件大小：3675K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA1677, OPA1678, OPA1679
SBOS855D – JANUARY 2017 – REVISED DECEMBER 2021
OPA167x Low-Distortion Audio Operational Amplifiers
The OPA167x amplifiers achieve a low 4.5-nV/√Hz
noise density and low distortion of 0.0001% at 1 kHz,
which improves audio signal fidelity. These devices
also offer rail-to-rail output swing to within 800 mV
with a 2-kΩ load, which increases headroom and
maximizes dynamic range.
1 Features
•
•
•
•
•
Low noise: 4.5 nV/√Hz at 1 kHz
Low distortion: 0.0001% at 1 kHz
High open-loop gain: 114 dB
High common-mode rejection: 110 dB
Low quiescent current:
To accommodate the power-supply constraints of
many types of audio products, the OPA167x operate
over a very-wide supply range of ±2.25 V to ±18 V
(or 4.5 V to 36 V) on only 2 mA of supply current.
These op amps are unity-gain stable and have
excellent dynamic behavior over a wide range of load
conditions, allowing the OPA167x to be used in many
audio circuits.
– 2 mA per channel
•
•
•
•
•
•
Low input bias current: 10 pA (typical)
Slew rate: 9 V/μs
Wide gain bandwidth: 16 MHz (G = 1)
Unity-gain stable
Rail-to-rail output
Wide supply range:
– ±2.25 V to ±18 V, or 4.5 V to 36 V
Single, dual, and quad-channel versions
Available packages:
The OPA167x amplifiers use completely independent
internal circuitry for lowest crosstalk and freedom from
interactions between channels, even when overdriven
or overloaded.
•
•
– Single: SOIC-8 (preview), SOT-23
– Dual: SOIC-8, small SON-8, VSSOP-8
– Quad: Small QFN-16, SO-14, TSSOP-14
Temperature range: –40°C to +85°C
Device Information
PACKAGE(1)
SOIC (8) - Preview
SOT-23 (5)
SOIC (8)
BODY SIZE (NOM)
4.90 mm × 3.91 mm
2.90 mm × 1.60 mm
4.90 mm × 3.91 mm
3.00 mm × 3.00 mm
3.00 mm × 3.00 mm
8.65 mm × 3.91 mm
5.00 mm × 4.40 mm
4.00 mm × 4.00 mm
•
PART NUMBER
OPA1677
2 Applications
•
•
•
Professional microphones and wireless systems
Professional audio mixer/control surface
Guitar amplifier and other music instrument
amplifier
OPA1678
OPA1679
VSSOP (8)
SON (8)
•
•
A/V receiver
Automotive external amplifier
SOIC (14)
TSSOP (14)
QFN (16)
3 Description
The
single-channel
OPA1677,
dual-channel
(1) For all available packages, see the package option
addendum at the end of the data sheet.
OPA1678, and quad-channel OPA1679 (OPA167x)
op amps offer higher system-level performance over
legacy op amps commonly used in audio circuitry.
V+
0.1
0.01
-60
Gain = 10 V/V
Gain = 1 V/V
Gain = -1 V/V
Tail
Current
V
BIAS1
-80
V
V
+
IN
Class AB
V
Control
O
Circuitry
0.001
-100
-120
-140
-
IN
V
BIAS2
0.0001
0.00001
10
100
1k
Frequency (Hz)
10k
V-
C002
Simplified Internal Schematic
THD+N vs Frequency (2-kΩ Load)
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA1677, OPA1678, OPA1679
SBOS855D – JANUARY 2017 – REVISED DECEMBER 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information: OPA1677.................................. 7
6.5 Thermal Information: OPA1678.................................. 7
6.6 Thermal Information: OPA1679.................................. 7
6.7 Electrical Characteristics.............................................8
6.8 Typical Characteristics................................................9
7 Detailed Description......................................................14
7.1 Overview...................................................................14
7.2 Functional Block Diagram.........................................14
7.3 Feature Description...................................................14
7.4 Device Functional Modes..........................................17
8 Application and Implementation..................................18
8.1 Application Information............................................. 18
8.2 Typical Applications.................................................. 19
9 Power Supply Recommendations................................25
10 Layout...........................................................................25
10.1 Layout Guidelines................................................... 25
10.2 Layout Example...................................................... 26
11 Device and Documentation Support..........................27
11.1 Device Support........................................................27
11.2 Documentation Support.......................................... 28
11.3 Receiving Notification of Documentation Updates..28
11.4 Support Resources................................................. 28
11.5 Trademarks............................................................. 28
11.6 Electrostatic Discharge Caution..............................28
11.7 Glossary..................................................................28
12 Mechanical, Packaging, and Orderable
Information.................................................................... 28
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (April 2019) to Revision D (December 2021)
Page
•
•
Updated the numbering format for tables, figures, and cross-references throughout the document..................1
Added OPA1677 production data (active) device and associated content.........................................................1
Changes from Revision B (June 2018) to Revision C (April 2019)
Page
Changed status of OPA1679 QFN package to production data......................................................................... 1
Updated GPN BUF634A in Figure 8-6 .............................................................................................................24
•
•
Changes from Revision A (May 2018) to Revision B (June 2018)
Page
•
Added content re: preview QFN (RUM) package............................................................................................... 1
Changes from Revision * (February 2017) to Revision A (May 2018)
Page
•
•
•
•
Added DRG (SON) 8-pin package to Device Information table..........................................................................1
Added SON-8 package to Features list.............................................................................................................. 1
Added DRG (SON) 8-pin pinout drawing to Pin Configuration and Functions section....................................... 3
Added thermal pad information to Pin Functions: OPA1678 table......................................................................3
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5 Pin Configuration and Functions
NC
–IN
+IN
V–
1
2
3
4
8
7
6
5
NC
V+
–
+
OUT
NC
Not to scale
Figure 5-1. OPA1677 D (8-Pin SOIC) Preview Package, Top View
OUT
Vœ
1
2
3
5
V+
+IN
4
œIN
Not to scale
Figure 5-2. OPA1677 DBV (5-Pin SOT-23) Package, Top View
Pin Functions: OPA1677
PIN
NO.
TYPE
DESCRIPTION
NAME
D
DBV
(SOIC)
(SOT-23)
–IN
+IN
OUT
V–
2
3
6
4
7
4
3
1
2
5
Input
Input
Inverting input
Noninverting input
Output
Power
Power
Output
Negative (lowest) power supply
Positive (highest) power supply
V+
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OUT A
œIN A
+IN A
Vœ
1
2
3
4
8
7
6
5
V+
OUT B
œIN B
+IN B
Not to scale
Figure 5-3. OPA1678 D (8-Pin SOIC) and DGK (8-Pin VSSOP) Packages, Top View
OUT A
œIN A
+IN A
Vœ
1
2
3
4
8
7
6
5
V+
OUT B
œIN B
+IN B
Thermal
Pad
Not to scale
Figure 5-4. OPA1678 DRG (8-Pin SON With Exposed Thermal Pad) Package, Top View
Pin Functions: OPA1678
PIN
TYPE
DESCRIPTION
NAME
–IN A
+IN A
–IN B
+IN B
OUT A
OUT B
V–
NO.
2
Input
Input
Inverting input, channel A
Noninverting input, channel A
Inverting input, channel B
Noninverting input, channel B
Output, channel A
3
6
Input
5
Input
1
Output
Output
Power
Power
7
Output, channel B
4
Negative (lowest) power supply
Positive (highest) power supply
V+
8
For DRG (SON-8) package. Exposed thermal die pad on underside. Connect thermal
die pad to V–. Solder the thermal pad to improve heat dissipation and provide specified
performance.
Thermal Pad
Thermal pad
—
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OUT A
œIN A
+IN A
V+
1
2
3
4
5
6
7
14
13
12
11
10
9
OUT D
œIN D
+IN D
Vœ
-IN A
+IN A
V+
1
2
3
4
12
11
10
9
-IN D
+IN D
V–
+IN B
œIN B
OUT B
+IN C
œIN C
OUT C
Thermal
Pad
8
+IN B
+IN C
Not to scale
Figure 5-5. OPA1679 D (14-Pin SOIC) and
PW (14-Pin TSSOP) Packages, Top View
Not to scale
Figure 5-6. OPA1679 RUM (16-Pin QFN With
Exposed Thermal Pad) Package, Top View
Pin Functions: OPA1679
PIN
NO.
TYPE
DESCRIPTION
NAME
D (SOIC)
PW (TSSOP)
RUM (QFN)
–IN A
2
3
1
2
Input
Input
Input
Input
Input
Input
Input
Input
—
Inverting input, channel A
+IN A
–IN B
+IN B
–IN C
+IN C
–IN D
+IN D
NC
Noninverting input, channel A
Inverting input, channel B
Noninverting input, channel B
Inverting input, channel C
Noninverting input, channel C
Inverting input, channel D
Noninverting input, channel D
No connect
6
5
5
4
9
8
10
13
12
—
—
1
9
12
11
13
16
15
6
NC
—
No connect
OUT A
OUT B
OUT C
OUT D
V+
Output
Output
Output
Output
Power
Power
Output, channel A
7
Output, channel B
8
7
Output, channel C
14
4
14
3
Output, channel D
Positive (highest) power supply
Negative (lowest) power supply
V–
11
10
Exposed thermal die pad on underside. Connect thermal die pad to V–.
Solder the thermal pad to improve heat dissipation and provide specified
performance.
Thermal Pad
—
Thermal pad
—
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
40
UNIT
V
Supply voltage, VS = (V+) – (V–)
Voltage
Input voltage
(V–) – 0.5
–10
(V+) + 0.5
10
V
Input current (all pins except power-supply pins)
mA
Current
Output short-circuit current(2)
Continuous
TA
Operating temperature
Junction temperature
Storage temperature
–55
–65
125
150
150
°C
°C
°C
TJ
Tstg
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Short-circuit to VS / 2 (groundinsymmetrical dual-supply setups), one amplifier per package.
6.2 ESD Ratings
VALUE
±2000
±1000
±200
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Machine model (MM)(3)
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allowssafemanufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allowssafemanufacturing with a standard ESD control process.
(3) Machine Model was not tested on OPA1679IRUM.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
MAX
36
UNIT
V
Single supply
Dual supply
VS
TA
Supply voltage
±2.25
–40
±18
125
Operating temperature
°C
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6.4 Thermal Information: OPA1677
OPA1677
THERMAL METRIC(1)
DBV (SOT-23)
5 PINS
180.5
78.5
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
47.3
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
20.4
ψJB
47.0
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: OPA1678
OPA1678
DGK
(VSSOP)
DRG
(SON)
THERMAL METRIC(1)
D (SOIC)
UNIT
8 PINS
144
77
8 PINS
219
79
8 PINS
66.9
54.5
40.4
1.9
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
62
104
15
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
28
ψJB
61
102
N/A
40.4
10.8
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information: OPA1679
OPA1679
PW
(TSSOP)
RUM
(QFN)
THERMAL METRIC(1)
D (SOIC)
UNIT
14 PINS
90
14 PINS
127
47
16 PINS
38.5
34.4
17.4
0.6
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
55
44
59
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
20
55
ψJB
44
58
17.4
7.1
RθJC(bot)
N/A
N/A
(1) For more information about traditional and newthermalmetrics, see the Semiconductorand ICPackage Thermal Metrics application
report.
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UNIT
SBOS855D – JANUARY 2017 – REVISED DECEMBER 2021
6.7 Electrical Characteristics
at VS = ±15 V, TA = 25°C, RL = 2 kΩ, and VCM = VOUT = midsupply, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
AUDIO PERFORMANCE
0.0001%
–120
THD+N
Total harmonic distortion + noise
Intermodulation distortion
G = 1, RL = 600 Ω, f = 1 kHz, VO = 3 VRMS
dB
dB
0.0001%
–120
SMPTE/DIN two-tone, 4:1
(60 Hz and 7 kHz)
DIM 30
G = 1
0.0001%
IMD
(3-kHz square wave and 15
VO = 3 VRMS
–120
dB
dB
kHz sine wave)
0.0001%
–120
CCIF twin-tone
(19 kHz and 20 kHz)
FREQUENCY RESPONSE
GBW
SR
Gain-bandwidth product
G = 1
16
9
MHz
V/µs
MHz
µs
Slew rate
G = –1
Full power bandwidth(1)
Overload recovery time
Channel separation (dual and quad)
VO = 1 VP
G = –10
f = 1 kHz
1.4
1
–130
dB
NOISE
f = 20 Hz to 20 kHz
f = 0.1 Hz to 10 Hz
f = 1 kHz
5.4
1.74
4.5
3
en
Input voltage noise
µVPP
Input voltage noise density
Input current noise density
nV/√Hz
fA/√Hz
in
f = 1 kHz
OFFSET VOLTAGE
VS = ±2.25 V to ±18 V
±0.5
2
±2
8
mV
VOS
Input offset voltage
VS = ±2.25 V to ±18 V, TA = –40°C to 125°C(2)
VS = ±2.25 V to ±18 V
µV/°C
µV/V
PSRR
Power-supply rejection ratio
3
INPUT BIAS CURRENT
IB
Input bias current
Input offset current
VCM = 0 V
VCM = 0 V
±10
±10
pA
pA
IOS
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
Common-mode rejection ratio
(V–)+0.5
100
(V+) – 2
V
CMRR
110
dB
INPUT IMPEDANCE
Differential
Common-mode
OPEN-LOOP GAIN
100 || 6
MΩ || pF
GΩ || pF
6000 || 2
AOL
OUTPUT
VO
Open-loop voltage gain
(V–) + 0.8 V ≤ VO ≤ (V+) – 0.8 V
106
114
dB
Output voltage
(V–) + 0.8
(V+) – 0.8
V
IOUT
ZO
Output Current
See Section 6.8
See Section 6.8
±50
mA
Ω
Open-loop output impedance
Short-circuit current(3)
Capacitive load drive
f = 1 MHz
ISC
mA
pF
CL
100
POWER SUPPLY
IO = 0 A
2
2.5
2.8
IQ Quiescent current (per channel)
mA
IO = 0 A, TA = –40°C to 125°C(2)
(1) Full-power bandwidth = SR / (2π ×VP),where SR = slew rate.
(2) Specified by design and characterization.
(3) One channel at a time.
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6.8 Typical Characteristics
at TA = 25°C, VS = ±15 V, and RL = 2 kΩ, (unless otherwise noted)
1000
100
10
1
Time (1s/div)
1
10
100
1k
10k
100k
Frequency (Hz)
C001
C003
Figure 6-1. Input Voltage Noise Density vs Frequency
Figure 6-2. 0.1-Hz to 10-Hz Noise
20
18
16
14
12
10
8
10000
VS = +/- 18 V
VS = +/- 5 V
Resistor Noise Contribution
Voltage Noise Contribution
Current Noise Contribution
Total Noise
VS = +/- 2.25 V
1000
100
10
1
6
4
2
0.1
0
10
100
1k
10k 100k 1M
10M 100M 1000M
10k
100k
1M
10M
Source Resistance (O)
Frequency (Hz)
C001
C015
Figure 6-3. Voltage Noise vs Source Resistance
Figure 6-4. Maximum Output Voltage vs Frequency
30
140
120
100
80
180
135
90
Gain
Phase
20
10
0
60
œ10
40
œ20
20
45
Gain = -1 V/V
œ30
0
Gain = 1 V/V
Gain = 10 V/V
œ20
0
œ40
10
100
1k
10k
100k
1M
10M 100M
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
C006
C002
CL = 10 pF
CL = 10 pF
Figure 6-5. Open-Loop Gain and Phase vs Frequency
Figure 6-6. Closed-Loop Gain vs Frequency
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, and RL = 2 kΩ, (unless otherwise noted)
0.1
0.01
-60
0.1
0.01
-60
Gain = 10 V/V
Gain = 1 V/V
Gain = -1 V/V
Gain = 10 V/V
Gain = 1 V/V
Gain = -1 V/V
-80
-80
0.001
-100
-120
-140
0.001
-100
-120
0.0001
0.00001
0.0001
0.00001
-140
10
100
1k
10k
10
100
1k
10k
Frequency (Hz)
Frequency (Hz)
C002
C002
VOUT = 3 VRMS
RL = 2 kΩ
Bandwidth = 80 kHz
VOUT = 3 VRMS
RL = 600 Ω
Bandwidth = 80 kHz
Figure 6-7. THD+N Ratio vs Frequency
Figure 6-8. THD+N Ratio vs Frequency
0.1
0.01
-60
0.1
0.01
-60
-80
-80
0.001
-100
-120
-140
0.001
-100
-120
-140
0.0001
0.00001
0.0001
0.00001
Gain = 1 V/V
Gain = -1 V/V
Gain = 10 V/V
Gain = 1 V/V
Gain = -1 V/V
Gain = 10 V/V
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
Output Amplitude (VRMS
)
Output Amplitude (VRMS)
C002
C002
f = 1 kHz
RL = 2 kΩ
Bandwidth = 80 kHz
f = 1 kHz
RL = 600 Ω
Bandwidth = 80 kHz
Figure 6-9. THD+N Ratio vs Output Amplitude
Figure 6-10. THD+N Ratio vs Output Amplitude
œ60
140
œ70
œ80
120
100
80
60
40
20
0
œ90
œ100
œ110
œ120
œ130
œ140
œ150
œ160
CMRR
PSRR(+)
PSRR(-)
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
C006
C006
VOUT = 3 VRMS
Gain = 1 V/V
Figure 6-11. Channel Separation vs Frequency
Figure 6-12. CMRR and PSRR vs Frequency (Referred to Input)
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, and RL = 2 kΩ, (unless otherwise noted)
VIN
VIN
VOUT
VOUT
Time (0.2 ꢀs/div)
Time (0.2 ꢀs/div)
C009
C009
Gain = 1 V/V
CL = 100 pF
Gain = –1 V/V
CL = 100 pF
Figure 6-13. Small-Signal Step Response (100 mV)
Figure 6-14. Small-Signal Step Response (100 mV)
VIN
VIN
VOUT
VOUT
Time (1 ꢀs/div)
Time (1 ꢀs/div)
C009
C009
Gain = +1 V/V
RF = 2 kΩ
CL = 100 pF
Gain = –1 V/V
CL = 100 pF
Figure 6-15. Large-Signal Step Response
Figure 6-16. Large-Signal Step Response
145
140
135
130
125
120
115
110
105
100
1000
500
0
-500
-1000
-1500
-2000
IB(N)
IB(P)
I(OS)
10
35
60
85
110
10
35
60
85
110
œ40
œ15
œ40
œ15
Temperature (°C)
Temperature (°C)
C008
C008
Figure 6-17. Open-Loop Gain vs Temperature
Figure 6-18. IB and IOS vs Temperature
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, and RL = 2 kΩ, (unless otherwise noted)
8
6
3
2.8
2.6
2.4
2.2
2
4
2
0
1.8
1.6
1.4
1.2
1
-2
-4
IB(N)
-6
IB(P)
I(OS)
-8
10
35
60
85
110
0
3
6
9
12 15 18
œ40
œ15
œ18 œ15 œ12 œ9 œ6 œ3
Temperature (°C)
Common-Mode Voltage (V)
C008
C008
Figure 6-20. Supply Current vs Temperature
Figure 6-19. IB and IOS vs Common-Mode Voltage
20
3
18
16
14
12
10
8
2.5
2
1.5
1
6
-40°C
0°C
4
0.5
0
25°C
85°C
2
0
0
5
10
15
20
25
30
35
40
0
5
10 15 20 25 30 35 40 45 50 55 60
Supply Voltage (V)
Output Current (mA)
C008
C004
Figure 6-21. Supply Current vs Supply Voltage
Figure 6-22. Output Voltage vs Output Current (Sourcing)
0
80
-40°C
ISC (+)
-2
0°C
60
ISC (-)
-4
-6
25°C
85°C
40
20
-8
-10
-12
-14
-16
-18
-20
0
œ20
œ40
œ60
0
5
10
15
20
25
30
35
40
45
50
10
35
60
85
110
135
œ40
œ15
Output Current (mA)
Temperature (ëC)
C004
C003
Figure 6-23. Output Voltage vs Output Current (Sinking)
Figure 6-24. Short-Circuit Current vs Temperature
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6.8 Typical Characteristics (continued)
at TA = 25°C, VS = ±15 V, and RL = 2 kΩ, (unless otherwise noted)
70
60
50
40
30
20
10
0
60
50
40
30
20
10
0
VS = +/- 18 V
VS = +/- 2.25 V
0
100
200
300
400
500
600
0
100
200
300
400
500
600
Capacitive Load (pF)
Capacitive Load (pF)
C002
C001
G = 1
G = 1
Figure 6-25. Phase Margin vs Capacitive Load
Figure 6-26. Percent Overshoot vs Capacitive Load
10
20
5
0
15
10
5
-5
-10
0
-15
-5
VIN
VOUT
VIN
VOUT
-20
-10
Time (500 ns/div)
Time (500 ns/div)
C004
C004
Gain = –10 V/V
Gain = –10 V/V
Figure 6-27. Negative Overload Recovery
Figure 6-28. Positive Overload Recovery
10000
1000
100
10
20
15
10
5
0
-5
-10
-15
VIN
VOUT
1
-20
Time (125 ꢀs/div)
10
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
C015
C004
Gain = 1 V/V
Figure 6-29. Open-Loop Output Impedance vs Frequency
Figure 6-30. No Phase Reversal
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7 Detailed Description
7.1 Overview
The OPA167x devices are unity-gain stable, dual-channel and quad-channel op amps with low noise and
distortion. Section 7.2 shows a simplified schematic of the OPA167x (one channel shown). These devices
consist of a low-noise input stage with a folded cascode and a rail-to-rail output stage. This topology exhibits
superior noise and distortion performance across a wide range of supply voltages that are not delivered by
legacy commodity audio operational amplifiers.
7.2 Functional Block Diagram
V+
Tail
Current
V
BIAS1
V
V
+
IN
Class AB
Control
V
O
Circuitry
-
IN
V
BIAS2
V-
7.3 Feature Description
7.3.1 Phase Reversal Protection
The OPA167x family has internal phase-reversal protection. Many op amps exhibit phase reversal when the
input is driven beyond the linear common-mode range. This condition is most often encountered in noninverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The input of the OPA167x prevents phase reversal with excessive common-mode
voltage. Instead, the appropriate rail limits the output voltage. This performance is shown in Figure 7-1.
20
15
10
5
0
-5
-10
-15
VIN
VOUT
-20
Time (125 ꢀs/div)
C004
Figure 7-1. Output Waveform Devoid of Phase Reversal During an Input Overdrive Condition
7.3.2 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
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Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
A good understanding of this basic ESD circuitry and the relevance to an electrical overstress event is helpful.
Figure 7-2 illustrates the ESD circuits contained in the OPA167x (indicated by the dashed line area). The ESD
protection circuitry involves several current-steering diodes connected from the input and output pins and routed
back to the internal power-supply lines, where the diodes meet at an absorption device internal to the operational
amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.
TVS
RF
+VS
R1
RS
250 Ω
250 Ω
INœ
IN+
+
Power-Supply
ESD Cell
ID
RL
+
VIN
œ
œVS
TVS
Figure 7-2. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, high-
current pulse when discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or
more steering diodes. Depending on the path that the current takes, the absorption device can activate. The
absorption device has a trigger, or threshold voltage, that is greater than the normal operating voltage of the
OPA167x but less than the device breakdown voltage level. When this threshold is exceeded, the absorption
device quickly activates and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit (see Figure 7-2), the ESD protection components
are intended to remain inactive and do not become involved in the application circuit operation. However,
circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. If this
condition occurs, there is a risk that some internal ESD protection circuits can turn on and conduct current. Any
such current flow occurs through steering-diode paths and rarely involves the absorption device.
Figure 7-2 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (V+)
by 500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If V+ can
sink the current, one of the upper input steering diodes conducts and directs current to V+. Excessively high
current levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
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If the supply is not capable of sinking the current, VIN can begin sourcing current to the operational amplifier and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings.
Another common question involves what happens to the amplifier if an input signal is applied to the input when
the power supplies (V+ or V–) are at 0 V. Again, this question depends on the supply characteristic when at 0
V, or at a level less than the input signal amplitude. If the supplies appear as high impedance, then the input
source supplies the operational amplifier current through the current-steering diodes. This state is not a normal
bias condition; most likely, the amplifier does not operate normally. If the supplies are low impedance, then the
current through the steering diodes can become quite high. The current level depends on the ability of the input
source to deliver current, and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, add external Zener diodes to the
supply pins; see Figure 7-2. Select the Zener voltage so that the diode does not turn on during normal operation.
However, the Zener voltage must be low enough so that the Zener diode conducts if the supply pin begins to rise
above the safe-operating, supply-voltage level.
7.3.3 EMI Rejection Ratio (EMIRR)
The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational
amplifiers. An adverse effect that is common to many operational amplifiers is a change in the offset voltage
as a result of RF signal rectification. An operational amplifier that is more efficient at rejecting this change in
offset as a result of EMI has a higher EMIRR and is quantified by a decibel value. Measuring EMIRR can be
performed in many ways, but this document provides the EMIRR IN+, which specifically describes the EMIRR
performance when the RF signal is applied to the noninverting input pin of the operational amplifier. In general,
only the noninverting input is tested for EMIRR for the following three reasons:
•
•
•
Operational amplifier input pins are known to be the most sensitive to EMI, and typically rectify RF signals
better than the supply or output pins.
The noninverting and inverting operational amplifier inputs have symmetrical physical layouts and exhibit
nearly matching EMIRR performance.
EMIRR is easier to measure on noninverting pins than on other pins because the noninverting input pin can
be isolated on a printed-circuit-board (PCB). This isolation allows the RF signal to be applied directly to the
noninverting input pin with no complex interactions from other components or connecting PCB traces.
A more formal discussion of the EMIRR IN+ definition and test method is shown in the EMI Rejection Ratio of
Operational Amplifiers application report, available for download at www.ti.com.
The EMIRR IN+ of the OPA167x is plotted versus frequency in Figure 7-3. The dual and quad operational
amplifier device versions have approximately identical EMIRR IN+ performance. The OPA167x unity-gain
bandwidth is 16 MHz. EMIRR performance below this frequency denotes interfering signals that fall within the
operational amplifier bandwidth.
100
90
80
70
60
50
40
30
20
10
0
10
100
1000
10000
Frequency (MHz)
C001
Figure 7-3. OPA167x EMIRR vs Frequency
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Table 7-1 lists the EMIRR IN+ values for the OPA167x at particular frequencies commonly encountered in real-
world applications. Applications listed in Table 7-1 can be centered on or operated near the particular frequency
shown. This information can be of special interest to designers working with these types of applications, or
working in other fields likely to encounter RF interference from broad sources, such as the industrial, scientific,
and medical (ISM) radio band.
Table 7-1. OPA167x EMIRR IN+ for Frequencies of Interest
FREQUENCY
400 MHz
900 MHz
1.8 GHz
APPLICATION OR ALLOCATION
Mobile radio, mobile satellite, space operation, weather, radar, UHF
GSM, radio communication and navigation, GPS (to 1.6 GHz), ISM, aeronautical mobile, UHF
GSM, mobile personal comm. broadband, satellite, L-band
EMIRR IN+
36 dB
42 dB
52 dB
2.4 GHz
802.11b/g/n, Bluetooth™, mobile personal comm., ISM, amateur radio and satellite, S-band
Radiolocation, aero comm./nav., satellite, mobile, S-band
64 dB
3.6 GHz
67 dB
802.11a/n, aero communication and navigation, mobile communication, space and satellite operation,
C-band
5 GHz
77 dB
7.3.3.1 EMIRR IN+ Test Configuration
Figure 7-4 shows the circuit configuration for testing the EMIRR IN+. An RF source is connected to the
operational amplifier noninverting input pin using a transmission line. The operational amplifier is configured
in a unity-gain buffer topology with the output connected to a low-pass filter (LPF) and a digital multimeter
(DMM). A large impedance mismatch at the operational amplifier input causes a voltage reflection; however, this
effect is characterized and accounted for when determining the EMIRR IN+. The resulting dc offset voltage is
sampled and measured by the multimeter. The LPF isolates the multimeter from residual RF signals that can
interfere with multimeter accuracy. See the EMI Rejection Ratio of Operational Amplifiers application report for
more details.
Ambient temperature: 25˘C
+VS
œ
50 ꢀ
Low-Pass Filter
+
RF source
DC Bias: 0 V
Modulation: None (CW)
-VS
Sample /
Averaging
Digital Multimeter
Not shown: 0.1 µF and 10 µF
supply decoupling
Frequency Sweep: 201 pt. Log
Figure 7-4. EMIRR IN+ Test Configuration Schematic
7.4 Device Functional Modes
7.4.1 Operating Voltage
The OPA167x series op amps operate from ±2.25 V to ±18 V supplies while maintaining excellent performance.
The OPA167x series can operate with as little as 4.5 V between the supplies and with up to 36 V between the
supplies. However, some applications do not require equal positive and negative output voltage swing. With the
OPA167x series, power-supply voltages are not required to be equal. For example, the positive supply can be
set to 25 V with the negative supply at –5 V.
In all cases, the common-mode voltage must be maintained within the specified range. In addition, key
parameters are specified over the temperature range of TA = –40°C to +85°C. Parameters that vary significantly
with operating voltage or temperature are shown in Section 6.8.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
8.1.1 Capacitive Loads
The dynamic characteristics of the OPA167x series are optimized for commonly encountered gains, loads, and
operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the phase
margin of the amplifier, and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be
isolated from the output. The simplest way to achieve this isolation is to add a small resistor (RS equal to 50 Ω,
for example) in series with the output.
This small series resistor also prevents excess power dissipation if the output of the device short-circuits. For
more details about analysis techniques and application circuits, see the Feedback Plots Define Op Amp AC
Performance application report, available for download from the TI website (www.ti.com).
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8.2 Typical Applications
8.2.1 Phantom-Powered Preamplifier for Piezo Contact Microphones
Contact microphones are useful for amplifying the sound of musical instruments that do not contain electrical
pickups, such as acoustic guitars and violins. Most contact microphones use a piezo element to convert
vibrations in the body of the musical instrument to a voltage which may be amplified or recorded. The low noise
and low input bias current of the OPA1678 make the device an excellent choice for high impedance preamplifiers
for piezo elements. This preamplifier circuit provides high input impedance for the piezo element but has low
output impedance for driving long cable runs. The circuit is also designed to be powered from 48-V phantom
power which is commonly available in professional microphone preamplifiers and recording consoles.
A TINA-TI™ simulation schematic of the circuit below is available in the Tools and Software section of the
OPA1678 or OPA1679 product folder.
R1
1.2 kꢀ
C2
C1
R2
1.2 kꢀ
0.1 ꢁF 22 ꢁF
+
ZD1
24 V
R14
100 ꢀ
½ OPA1678
+
VS+
VOUT
œ
VSœ
C5
22 ꢁF
R10
100 ꢀ
R3
1 Mꢀ
R7 2 kꢀ
R12
100 kꢀ
R5
100 kꢀ
TPD1E1B04
To
Microphone
Preamplifier
Piezo
Contact
Microphone
C3 390 pF
C4 390 pF
R8
442 ꢀ
R6
100 kꢀ
R13
100 kꢀ
R9 2 kꢀ
R4
1 Mꢀ
R11
100 ꢀ
C6
22 ꢁF
R15
100 ꢀ
œ
+
½ OPA1678
Figure 8-1. Phantom-Powered Preamplifier for Piezo Contact Microphones
8.2.1.1 Design Requirements
•
•
•
–3-dB bandwidth: 20 Hz to 20 kHz
Gain: 20 dB (10 V/V)
Piezo element capacitance: 8 nF (9-kHz resonance)
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8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Power Supply
In professional audio systems, phantom power is applied to the two signal lines that carry a differential audio
signal from the microphone. Figure 8-2 is a diagram of the system showing 48-V phantom power applied to
the differential signal lines between the piezo preamplifier output and the input of a professional microphone
preamplifier.
48 V
Phantom
Power
6.8 kꢀ
6.8 kꢀ
R1
R2
+
+
Piezo
Contact
Microphone
Differential
Signal Cable
œ
œ
Microphone
Preamplifier
Piezo
Preamplifier
Figure 8-2. System Diagram Showing the Application of Phantom Power to the Audio Signal Lines
A voltage divider is used to extract the common-mode phantom power from the differential audio signal in this
type of system. The voltage at center point of the voltage divider formed by R1 and R2 does not change when
audio signals are present on the signal lines (assuming R1 and R2 are matched). A Zener diode forces the
voltage at the center point of R1 and R2 to a regulated voltage. The values of R1 and R2 are determined by the
allowable voltage drop across these resistors from the current delivered to both op amp channels and the Zener
diode. There are two power supply current pathways in parallel, each sharing half the total current of the op amp
and Zener diode. Resistors R1 and R2 can be calculated using Equation 1:
R1 = R2 = RPS
VZD
- 6.8 kW = RPS
I
IZD
2
≈
’
OPA
+
∆
«
÷
◊
2
(1)
A 24-V Zener diode is selected for this design, and 1 mA of current flows through the diode at idle conditions
to maintain the reverse-biased condition of the Zener diode. The maximum idle power supply current of both op
amp channels is 5 mA. Inserting these values into Equation 1 gives the values for R1 and R2 shown in Equation
2.
24V
IZD
24V
- 6.8 kW =
- 6.8 kW = 1.2 kW = RPS
I
5.0 mA 1.0 mA
+
≈
’
≈
’
OPA
+
∆
«
÷
◊
∆
«
÷
◊
2
2
2
2
(2)
Using a value of 1.2 kΩ for resistors R1 and R2 establishes a 1-mA current through the Zener diode and
properly regulate the node to 24 V. Capacitor C1 forms a low-pass filter with resistors R1 and R2 to filter the
Zener diode noise and any residual differential audio signals. Mismatch in the values of R1 and R2 causes a
portion of the audio signal to appear at the voltage divider center point. The corner frequency of the low-pass
filter must be set below the audio band, as shown in Equation 3.
1
1
C1 í
í
í 13 mF ç 22 mF
2∂ p∂R1 ||R2 ∂ f-3dB 2∂ p∂600 W ∂20 Hz
(3)
A 22-μF capacitor is selected because the capacitor meets the requirements for power supply filtering and is a
widely available denomination. A 0.1-µF capacitor (C2) is added in parallel with C1 as a high-frequency bypass
capacitor.
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8.2.1.2.2 Input Network
Resistors R3 and R4 provide a pathway for the input bias current of the OPA1678 while maintaining the high
input impedance of the circuit. The contact microphone capacitance and the required
low-frequency response determine the values of R3 and R4. The –3-dB frequency formed by the microphone
capacitance and amplifier input impedance is shown in Equation 4:
1
F-3dB
=
Ç 20 Hz
2∂ p∂(R3 + R4 )∂CMIC
(4)
A piezo element with 8 nF of capacitance was selected for this design because the 9-kHz resonance is towards
the upper end of the audible bandwidth, and is less likely to affect the frequency response of many musical
instruments. The minimum value for resistors R3 and R4 is then calculated with Equation 5:
R3 = R4 = RIN
1
1
RIN
í
í
í 497.4 kW
4∂ p∂F-3dB ∂CMIC 4∂ p∂ 20 Hz∂8 nF
(5)
1-MΩ resistors are selected for R3 and R4 to make sure the circuit meets the design requirements for –3-dB
bandwidth. The center point of resistors R3 and R4 is biased to half the supply voltage through the voltage
divider formed by R5 and R6. This sets the input common-mode voltage of the circuit to a value within the input
voltage range of the OPA1678. Piezo elements can produce very large voltages if the elements are struck with
sufficient force. To prevent damage, the input of the OPA1678 is protected by a transient voltage suppressor
(TVS) diode placed across the preamplifier inputs. The TPD1E1B04 TVS was selected due to low capacitance
and the 6.4-V clamping voltage does not clamp the desired low amplitude vibration signals. Resistors R14 and
R15 limit current flow into the amplifier inputs in the event that the internal protection diodes of the amplifier are
forward-biased.
8.2.1.2.3 Gain
R7, R8, and R9 determines the gain of the preamplifier circuit. The gain of the circuit is shown in Equation 6:
R7 + R9
R8
AV = 1+
= 10 V/V
(6)
Resistors R7 and R9 are selected with a value of 2 kΩ to avoid loading the output of the OPA1678 and
producing distortion. The value of R8 is then calculated in Equation 7:
R7 +R9
AV -1
2 kW + 2 kW
10 -1
R8 =
=
= 444.4 W ç 442 W
(7)
Capacitors C3 and C4 limit the bandwidth of the circuit so that signals outside the audio bandwidth are not
amplified. The corner frequency produced by capacitors C3 and C4 is shown in Equation 8. This corner
frequency must be above the desired –3-dB bandwidth point to avoid attenuating high-frequency audio signals.
C3 = C4 = CFB
1
1
CFB
Ç
Ç
Ç 3.98 nF
2∂ p∂F-3dB ∂R7/9 2∂ p∂20 kHz∂2 kW
(8)
C3 and C4 are 390-pF capacitors, which places the corner frequency approximately 1 decade above the desired
–3-dB bandwidth point . Capacitors C3 and C4 must be NP0 or C0G type ceramic capacitors or film capacitors.
Other ceramic dielectrics, such as X7R, are not suitable for these capacitors and produces distortion.
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8.2.1.2.4 Output Network
The audio signal is ac-coupled onto the microphone signal lines through capacitors C5 and C6. The value of
capacitors C5 and C6 are determined by the low-frequency design requirements and the input impedance of
the microphone preamplifier that connect to the output of the circuit. Equation 9 shows an approximation of the
capacitor value requirements, and neglects the effects of R10, R11, R12, and R13 on the frequency response.
The microphone preamplifier input impedance (RIN_MIC) uses a typical value of 4.4 kΩ for the calculation.
C5 = C6 = COUT
2
2
COUT
í
í
í 3.6 mF
2∂ p∂RIN_MIC ∂ 20 Hz 2∂ p∂ 4.4 kW ∂20 Hz
(9)
For simplicity, the same 22-μF capacitors selected for the power supply filtering are selected for C5 and C6
to satisfy Equation 9. At least 50-V rated capacitors must be used for C5 and C6. If polarized capacitors are
used, the positive terminal must be oriented towards the microphone preamplifier. Resistors R10 and R11 isolate
the op amp outputs from the capacitances of long cables that may cause instability. R12 and R13 discharge
ac-coupling capacitors C4 and C5 when phantom power is removed.
8.2.1.3 Application Curves
The frequency response of the preamplifier circuit is shown in Figure 8-3. The –3-dB frequencies are 15.87 Hz
and 181.1 kHz, which meet the design requirements. The gain within the passband of the circuit is 18.9 dB,
slightly less than the design goal of 20 dB. The reduction in gain is a result of the voltage division between the
output resistors of the piezo preamplifier circuit and the input impedance of the microphone preamplifier. The
A-weighted noise of the circuit (referred to the input) is 842.2 nVRMS or –119.27 dBu.
20
19
18
17
16
15
14
13
12
11
10
10
100
1k
10k
100k
1M
Frequency (Hz)
C001
Figure 8-3. Frequency Response of the Preamplifier Circuit for a 8-nF Piezo Element
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8.2.2 Phono Preamplifier for Moving Magnet Cartridges
The noise and distortion performance of the OPA167x family of amplifiers is exceptional in applications with high
source impedances, which makes these devices a viable choice in preamplifier circuits for moving magnet (MM)
phono cartridges. Figure 8-4 shows a preamplifier circuit for MM cartridges with 40 dB of gain at 1 kHz.
15 V
C5
100 ꢁF
MM Phono Input
R5
100 ꢀ
½ OPA1678
VOUT
+
V+
Vœ
Output
R1
47 kꢀ
C1
150 pF
œ
R6
100 kꢀ
-15 V
R2
118 kꢀ
R3
10 kꢀ
C2
27 nF
C3
7.5 nF
R4
127 ꢀ
C4
100 ꢁF
Figure 8-4. Phono Preamplifier for Moving Magnet Cartridges (Single-Channel Shown)
8.2.3 Single-Supply Electret Microphone Preamplifier
The preamplifier circuit shown in Figure 8-5 operates the OPA1678 as a transimpedance amplifier that converts
the output current from the electret microphone internal JFET into a voltage. Resistor R4 determines the gain of
the circuit. Resistors R2 and R3 bias the input voltage to half the power supply voltage for proper functionality on
a single-supply.
C3
9 V
16 pF
R4
R1
13.7 kꢀ
61.9 kꢀ
9 V
C1
0.1 ꢁF
2.2 ꢁF
9 V
Electret
Microphone
œ
R2
100 kꢀ
Output
+
½ OPA1678
R3
100 kꢀ
C2
2.2 ꢁF
Figure 8-5. Single-Supply Electret Microphone Preamplifier
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8.2.4 Composite Headphone Amplifier
Figure 8-6 shows the BUF634A buffer inside the feedback loop of the OPA1678 to increase the available
output current for low-impedance headphones. If the BUF634A is used in wide-bandwidth mode, no additional
components besides the feedback resistors are required to maintain loop stability.
12 V
100 ꢁF
0.1 ꢁF
0.1 ꢁF
½
OPA1678
+
Input
Output
BUF634A
0.1 ꢁF
œ
100 kꢀ
R1
RBW
0.1 ꢁF
100 ꢁF
-12 V
R3
R2
200 ꢀ
200 ꢀ
Figure 8-6. Composite Headphone Amplifier (Single-Channel Shown)
8.2.5 Differential Line Receiver With AC-Coupled Outputs
Figure 8-7 shows the OPA1678 used as an integrator that drives the reference pin of the INA1650, which forces
the output dc voltage to 0 V. This configuration is an alternative to large ac-coupling capacitors that can distort at
high output levels. The low input bias current and low input offset voltage of the OPA1678 make the device an
excellent choice for integrator applications.
18 V
-18 V
C5 1 ꢀF
C7 1 ꢀF
R7
1 Mꢁ
Input Differential
Audio Signals
C6 0.1 ꢀF
C8 0.1 ꢀF
C1 10 ꢀF
R3 1 Mꢁ
18 V
R1
100 kꢁ
VCC
1
2
3
4
5
6
7
VEE 14
C9
100 nF
2
½
OPA1678
IN+ A
COM A
IN- A
13
OUT A
1
R2
100 kꢁ
-18 V
3
XLR Connector
REF A 12
VMID(IN)
Output Single-Ended
Audio Signals
11
10
9
C2 10 ꢀF
C3 10 ꢀF
IN- B
VMID(OUT)
REF B
R4
100 kꢁ
COM B
IN+ B
3
R6 1 Mꢁ
½
OPA1678
8
OUT B
C10
100 nF
1
R5
100 kꢁ
2
INA1650
XLR Connector
C4 10 ꢀF
R8
1 Mꢁ
Figure 8-7. Differential Line Receiver With AC-Coupled Outputs
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9 Power Supply Recommendations
The OPA167x devices are specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications
apply from –40°C to +85°C. Parameters that can exhibit significant variance with regard to operating voltage
or temperature are shown in Section 6.8. Applications with noisy or high-impedance power supplies require
decoupling capacitors close to the device pins. In most cases, 0.1-µF capacitors are adequate.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed-circuit board (PCB) layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources
local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Physically
separate digital and analog grounds, observing the flow of the ground current.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed
to in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible. As shown in Figure 10-1, keeping RF and
RG close to the inverting input minimizes parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
•
•
Cleaning the PCB following board assembly is recommended for best performance.
Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, bake the PCB assembly to remove moisture
introduced into the device packaging during the cleaning process. A low temperature, post-cleaning bake at
85°C for 30 minutes is sufficient for most circumstances.
10.1.1 Power Dissipation
The OPA167x series op amps are capable of driving 2-kΩ loads with a power-supply voltage up to ±18 V and
full operating temperature range. Internal power dissipation increases when operating at high supply voltages.
Copper leadframe construction used in the OPA167x series op amps improves heat dissipation compared to
conventional materials. Circuit board layout can also help minimize junction temperature rise. Wide copper
traces help dissipate the heat by acting as an additional heat sink. Temperature rise can be further minimized by
soldering the devices to the circuit board rather than using a socket.
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10.2 Layout Example
VIN A
VIN B
+
+
VOUT A
VOUT B
RG
RG
RF
RF
(Schematic Representation)
Place components
Output A
Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible.
close to device and to
each other to reduce
parasitic errors.
VS+
GND
OUTPUT A
RF
V+
Output B
GND
-IN A
+IN A
Vœ
OUTPUT B
-IN B
RF
RG
GND
VIN A
RG
+IN B
VIN B
Keep input traces short
and run the input traces
as far away from
the supply lines
Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible.
GND
VSœ
Ground (GND) plane on another layer
as possible.
Figure 10-1. Operational Amplifier Board Layout for Noninverting Configuration
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 PSpice® for TI
PSpice® for TI is a design and simulation environment that helps evaluate performance of analog circuits. Create
subsystem designs and prototype solutions before committing to layout and fabrication, reducing development
cost and time to market.
11.1.1.2 TINA-TI™ Simulation Software (Free Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™
simulation software is a free, fully-functional version of the TINA software, preloaded with a library of macro
models in addition to a range of both passive and active models. TINA-TI simulation software provides all the
conventional dc, transient, and frequency domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the WEBENCH® Design Center, TINA-TI simulation software offers extensive
post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer
the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic
quick-start tool.
Note
These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed.
Download the free TINA-TI software from the TINA-TI folder.
11.1.1.3 DIP Adapter EVM
The DIP Adapter EVM tool provides an easy, low-cost way to prototype small surface mount devices. The
evaluation tool these TI packages: D or U (SOIC-8), PW (TSSOP-8), DGK (VSSOP-8), DBV (SOT-23-6,
SOT-23-5 and SOT-23-3), DCK (SC70-6 and SC70-5), and DRL (SOT563-6). The DIP Adapter EVM may also
be used with terminal strips or may be wired directly to existing circuits.
11.1.1.4 Universal Operational Amplifier EVM
The Universal Op Amp EVM is a series of general-purpose, blank circuit boards that simplify prototyping circuits
for a variety of device package types. The evaluation module board design allows many different circuits to be
constructed easily and quickly. Five models are offered, with each model intended for a specific package type.
PDIP, SOIC, VSSOP, TSSOP and SOT-23 packages are all supported.
Note
These boards are unpopulated, so users must provide their own devices. TI recommends requesting
several op amp device samples when ordering the Universal Op Amp EVM.
11.1.1.5 TI Precision Designs
TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the
theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials,
and measured performance of many useful circuits. TI Precision Designs are available online at http://
www.ti.com/ww/en/analog/precision-designs/.
11.1.1.6 WEBENCH® Filter Designer
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The
WEBENCH® Filter Designer allows the user to create optimized filter designs using a selection of TI operational
amplifiers and passive components from TI's vendor partners.
Available as a web-based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows the user
to design, optimize, and simulate complete multistage active filter solutions within minutes.
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11.2 Documentation Support
11.2.1 Related Documentation
The following documents are relevant to using the OPA167x, and are recommended for reference. All are
available for download at www.ti.com unless otherwise noted.
•
•
•
•
•
•
•
Texas Instruments, Source resistance and noise considerations in amplifiers technical brief
Burr Brown, Single-Supply Operation of Operational Amplifiers application bulletin
Burr Brown, Op Amp Performance Analysis application bulletin
Texas Instruments, Compensate Transimpedance Amplifiers Intuitively application report
Burr Brown, Tuning in Amplifiers application bulletin
Burr Brown, Feedback Plots Define Op Amp AC Performance application bulletin
Texas Instruments, Active Volume Control for Professional Audio precision design
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TINA™ and DesignSoft™ are trademarks of DesignSoft, Inc.
TINA-TI™ and TI E2E™ are trademarks of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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19-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA1677DBVR
OPA1677DBVT
OPA1678IDGKR
OPA1678IDGKT
OPA1678IDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
VSSOP
VSSOP
SOIC
DBV
DBV
DGK
DGK
D
5
5
3000 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
O1677
NIPDAU
NIPDAUAG
NIPDAUAG
NIPDAU
O1677
8
1AW7
8
1AW7
8
2500 RoHS & Green
3000 RoHS & Green
OP1678
OP1678
OP1678
OPA1679
OPA1679
OPA1678IDRGR
OPA1678IDRGT
OPA1679IDR
SON
DRG
DRG
D
8
NIPDAU
SON
8
250
RoHS & Green
NIPDAU
SOIC
14
14
16
2500 RoHS & Green
2000 RoHS & Green
3000 RoHS & Green
NIPDAU
OPA1679IPWR
OPA1679IRUMR
TSSOP
WQFN
PW
NIPDAU
RUM
NIPDAU
OPA
1679
OPA1679IRUMT
ACTIVE
WQFN
RUM
16
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
OPA
1679
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Dec-2021
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA1679 :
Automotive : OPA1679-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA1677DBVR
OPA1677DBVT
OPA1678IDGKR
OPA1678IDGKT
OPA1678IDR
SOT-23
SOT-23
VSSOP
VSSOP
SOIC
DBV
DBV
DGK
DGK
D
5
5
3000
250
180.0
180.0
330.0
330.0
330.0
330.0
180.0
330.0
330.0
330.0
180.0
8.4
3.2
3.2
5.3
5.3
6.4
3.3
3.3
6.5
6.9
4.25
4.25
3.2
3.2
3.4
3.4
5.2
3.3
3.3
9.0
5.6
4.25
4.25
1.4
1.4
1.4
1.4
2.1
1.1
1.1
2.1
1.6
1.15
1.15
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q1
Q1
Q1
Q2
Q2
Q1
Q1
Q2
Q2
8.4
8.0
8
2500
250
12.4
12.4
12.4
12.4
12.4
16.4
12.4
12.4
12.4
12.0
12.0
12.0
12.0
12.0
16.0
12.0
12.0
12.0
8
8
2500
3000
250
OPA1678IDRGR
OPA1678IDRGT
OPA1679IDR
SON
DRG
DRG
D
8
SON
8
SOIC
14
14
16
16
2500
2000
3000
250
OPA1679IPWR
OPA1679IRUMR
OPA1679IRUMT
TSSOP
WQFN
WQFN
PW
RUM
RUM
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA1677DBVR
OPA1677DBVT
OPA1678IDGKR
OPA1678IDGKT
OPA1678IDR
SOT-23
SOT-23
VSSOP
VSSOP
SOIC
DBV
DBV
DGK
DGK
D
5
5
3000
250
210.0
210.0
366.0
366.0
853.0
367.0
210.0
853.0
853.0
367.0
210.0
185.0
185.0
364.0
364.0
449.0
367.0
185.0
449.0
449.0
367.0
185.0
35.0
35.0
50.0
50.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
8
2500
250
8
8
2500
3000
250
OPA1678IDRGR
OPA1678IDRGT
OPA1679IDR
SON
DRG
DRG
D
8
SON
8
SOIC
14
14
16
16
2500
2000
3000
250
OPA1679IPWR
OPA1679IRUMR
OPA1679IRUMT
TSSOP
WQFN
WQFN
PW
RUM
RUM
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
2X 0.95
1.9
3.05
2.75
1.9
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/F 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
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EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/F 06/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/F 06/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
RUM 16
4 x 4, 0.65 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224843/A
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DRG0008A
WSON - 0.8 mm max height
SCALE 5.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
3.1
2.9
PIN 1 INDEX AREA
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
(0.2) TYP
EXPOSED
THERMAL PAD
1.2 0.1
4
1
5
8
2X
1.5
2 0.1
6X 0.5
0.3
8X
0.2
0.1
0.08
0.6
0.4
PIN 1 ID
8X
C A B
C
4218885/A 03/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.2)
SYMM
8X (0.7)
1
8
8X (0.25)
SYMM
(2)
(0.75)
5
6X (0.5)
4
(R0.05) TYP
(
0.2) VIA
TYP
(0.35)
(2.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
EXPOSED
METAL
METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218885/A 03/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
METAL
TYP
8X (0.7)
8
8X (0.25)
1
SYMM
(1.79)
6X (0.5)
4
5
(R0.05) TYP
(1.13)
(2.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
84% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218885/A 03/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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