OPA211MDGKTEP [TI]
1.1nV/âHz NOISE, LOW POWER, PRECISION OPERATIONAL AMPLIFIER; 1.1nV / A ???? Hz的噪声，低功耗，精密运算放大器
| 型号： | OPA211MDGKTEP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1.1nV/âHz NOISE, LOW POWER, PRECISION OPERATIONAL AMPLIFIER |
| 文件： | 总23页 (文件大小：592K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA211-EP
www.ti.com
SBOS638 –JUNE 2012
1.1nV/√Hz NOISE, LOW POWER, PRECISION
OPERATIONAL AMPLIFIER
Check for Samples: OPA211-EP
1
FEATURES
2
•
LOW VOLTAGE NOISE: 1.1nV/√Hz at 1kHz
APPLICATIONS
•
INPUT VOLTAGE NOISE:
80nVPP (0.1Hz to 10Hz)
•
•
PLL LOOP FILTER
LOW-NOISE, LOW-POWER SIGNAL
PROCESSING
•
•
•
•
•
•
THD+N: –136dB (G = 1, f = 1kHz)
OFFSET VOLTAGE: 180μV (max)
OFFSET VOLTAGE DRIFT: 0.35μV/°C (typ)
LOW SUPPLY CURRENT: 3.6mA/Ch (typ)
UNITY-GAIN STABLE
•
•
•
•
•
•
•
•
•
•
•
16-BIT ADC DRIVERS
DAC OUTPUT AMPLIFIERS
ACTIVE FILTERS
LOW-NOISE INSTRUMENTATION AMPS
ULTRASOUND AMPLIFIERS
PROFESSIONAL AUDIO PREAMPLIFIERS
LOW-NOISE FREQUENCY SYNTHESIZERS
INFRARED DETECTOR AMPLIFIERS
HYDROPHONE AMPLIFIERS
GEOPHONE AMPLIFIERS
GAIN BANDWIDTH PRODUCT:
80MHz (G = 100)
45MHz (G = 1)
•
•
•
SLEW RATE: 27V/μs
16-BIT SETTLING: 700ns
WIDE SUPPLY RANGE:
±2.25V to ±18V, +4.5V to +36V
MEDICAL
•
•
RAIL-TO-RAIL OUTPUT
OUTPUT CURRENT: 30mA
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
CONTROLLED BASELINE
ONE ASSEMBLY/TEST SITE
ONE FABRICATION SITE
AVAILABLE IN MILITARY (–55°C/125°C)
(1)
TEMPERATURE RANGE
•
•
EXTENDED PRODUCT LIFE CYCLE
EXTENDED PRODUCT-CHANGE
NOTIFICATION
•
PRODUCT TRACEABILITY
(1) Additional temperature ranges available - contact factory
DESCRIPTION
The OPA211 series of precision operational amplifiers achieves very low 1.1nV/√Hz noise density with a supply
current of only 3.6mA. This series also offers rail-to-rail output swing, which maximizes dynamic range.
The extremely low voltage and low current noise, high speed, and wide output swing of the OPA211 series make
these devices an excellent choice as a loop filter amplifier in PLL applications.
In precision data acquisition applications, the OPA211 series of op amps provides 700ns settling time to 16-bit
accuracy throughout 10V output swings. This ac performance, combined with only 125μV of offset and
0.35μV/°C of drift over temperature, makes the OPA211 ideal for driving high-precision 16-bit analog-to-digital
converters (ADCs) or buffering the output of high-resolution digital-to-analog converters (DACs).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
OPA211-EP
SBOS638 –JUNE 2012
www.ti.com
The OPA211 is specified over a wide dual-power supply range of ±2.25V to ±18V, or for single-supply operation
from +4.5V to +36V.
The OPA211 is available in a small MSOP-8 package. This op amp is specified from TA = –55°C to +125°C.
INPUT VOLTAGE NOISE DENSITY vs FREQUENCY
100
10
1
0.1
1
10
100
1k
10k
100k
Frequency (Hz)
PACKAGE/ORDERING INFORMATION(1)
ORDERABLE PART
TA
PACKAGE
PACKAGE MARKING
VID NUMBER
NUMBER
-55°C to 125°C
MSOP-8 - DGK
OPA211MDGKTEP
OBCM
V62/12619-01XE
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
PIN CONFIGURATIONS
OPA211
MSOP-8
NC(1)
-IN
1
2
3
4
8
7
6
5
Shutdown(2)
V+
+IN
V-
OUT
NC(1)
(1) NC denotes no internal connection.
(2) Shutdown function:
•
•
Device enabled: (V–) ≤ VSHUTDOWN ≤ (V+) – 3V
Device disabled: VSHUTDOWN ≥ (V+) – 0.35V
2
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SBOS638 –JUNE 2012
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range (unless otherwise noted).
VALUE
UNIT
V
Supply Voltage
VS = (V+) – (V–)
40
(V–) – 0.5 to (V+) + 0.5
±10
Input Voltage
V
Input Current (Any pin except power-supply pins)
Output Short-Circuit(2)
Operating Temperature
Storage Temperature
mA
Continuous
(TA)
(TA)
(TJ)
–55 to +125
–65 to +150
200
°C
°C
°C
V
Junction Temperature
Human Body Model (HBM)
ESD Ratings
3000
Charged Device Model (CDM)
1000
V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
(2) Short-circuit to VS/2 (ground in symmetrical dual supply setups), one amplifier per package.
THERMAL INFORMATION
OPA211
THERMAL METRIC(1)
DGK
8 PINS
184.9
71.2
UNITS
θJA
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
θJCtop
θJB
104.9
11.5
°C/W
ψJT
ψJB
103.4
N/A
θJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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ELECTRICAL CHARACTERISTICS: VS = ±2.25V to ±18V
BOLDFACE limits apply over the specified temperature range, TA = –55°C to +125°C.
At TA = +25°C, RL = 10kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
Input Offset Voltage
Over Temperature
Drift
VOS
VS = ±15V
±20
±100
μV
µV
±180
dVOS/dT
0.35
μV/°C
μV/V
μV/V
vs Power Supply
PSRR
VS = ±2.25V to ±18V
0.1
0.5
Over Temperature
INPUT BIAS CURRENT
Input Bias Current
Offset Current
3
IB
VCM = 0V
VCM = 0V
±50
±20
±200
±150
nA
nA
IOS
NOISE
Input Voltage Noise
Input Voltage Noise Density
en
f = 0.1Hz to 10Hz
f = 10Hz
80
2
nVPP
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
pA/√Hz
f = 100Hz
f = 1kHz
1.4
1.1
3.2
1.7
Input Current Noise Density
In
f = 10Hz
f = 1kHz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range
VCM
V
S ≥ ±5V
(V–) + 1.8
(V–) + 2
114
(V+) – 1.4
(V+) – 1.4
V
V
VS < ±5V
Common-Mode Rejection Ratio
CMRR
V
S ≥ ±5V, (V–) + 2V ≤ VCM ≤ (V+) – 2V
120
120
dB
dB
VS < ±5V, (V–) + 2V ≤ VCM ≤ (V+) – 2V
108
INPUT IMPEDANCE
Differential
20k || 8
109 || 2
Ω || pF
Ω || pF
Common-Mode
OPEN-LOOP GAIN
Open-Loop Voltage Gain
AOL
AOL
AOL
AOL
(V–) + 0.2V ≤ VO ≤ (V+) – 0.2V,
RL = 10kΩ
114
110
110
103
130
dB
dB
dB
dB
(V–) + 0.6V ≤ VO ≤ (V+) – 0.6V,
RL = 600Ω
114
Over Temperature
(V–) + 0.6V ≤ VO ≤ (V+) – 0.6V,
IO ≤ 15mA
(V–) + 0.6V ≤ VO ≤ (V+)–0.6V,
15mA < IO ≤ 30mA
FREQUENCY RESPONSE
Gain-Bandwidth Product
GBW
G = 100
G = 1
80
45
MHz
MHz
V/μs
ns
Slew Rate
SR
tS
27
Settling Time, 0.01%
0.0015% (16-bit)
VS = ±15V, G = –1, 10V Step, CL = 100pF
VS = ±15V, G = –1, 10V Step, CL = 100pF
G = –10
400
700
500
ns
Overload Recovery Time
Total Harmonic Distortion + Noise
ns
THD+N
G = +1, f = 1kHz,
VO = 3VRMS, RL = 600Ω
0.000015
–136
%
dB
4
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SBOS638 –JUNE 2012
ELECTRICAL CHARACTERISTICS: VS = ±2.25V to ±18V (continued)
BOLDFACE limits apply over the specified temperature range, TA = –55°C to +125°C.
At TA = +25°C, RL = 10kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
Voltage Output
VOUT
RL = 10kΩ, AOL ≥ 114dB
RL = 600Ω, AOL ≥ 110dB
IO < 15mA, AOL ≥ 110dB
(V–) + 0.2
(V–) + 0.6
(V–) + 0.6
(V+) – 0.2
(V+) – 0.6
(V+) – 0.6
V
V
V
Short-Circuit Current
Capacitive Load Drive
ISC
CLOAD
ZO
+30/–45
mA
pF
Ω
See Typical Characteristics
5
Open-Loop Output Impedance
SHUTDOWN
f = 1MHz
Shutdown Pin Input Voltage(1)
Device disabled (shutdown)
Device enabled
(V+) – 0.35
V
V
(V+) – 3
Shutdown Pin Leakage Current
Turn-On Time(2)
1
2
3
1
μA
μs
μs
μA
Turn-Off Time(2)
Shutdown Current
POWER SUPPLY
Specified Voltage
Shutdown (disabled)
20
VS
IQ
±2.25
±18
4.5
6
V
Quiescent Current
(per channel)
IOUT = 0A
3.6
mA
mA
Over Temperature
TEMPERATURE RANGE
Operating Range
TA
–55
+125
°C
Thermal Resistance
θ JA
200
°C/W
(1) When disabled, the output assumes a high-impedance state.
(2) See Typical Characteristic curves, Figure 42 through Figure 44.
1000000
100000
10000
1000
125
130
135
140
145
150
Continuous T (°C)
J
A. See datasheet for absolute maximum and minimum recommended operating conditions.
B. Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
Figure 1. OPA211-EP Wirebond Life Derating Chart
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TYPICAL CHARACTERISTICS
At TA = +25°C, VS = ±18V, and RL = 10kΩ, unless otherwise noted.
INPUT VOLTAGE NOISE DENSITY
vs FREQUENCY
INPUT CURRENT NOISE DENSITY
vs FREQUENCY
100
10
1
100
10
1
0.1
1
10
100
1k
10k
100k
0.1
1
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Figure 2.
Figure 3.
THD+N RATIO vs FREQUENCY
THD+N RATIO vs OUTPUT VOLTAGE AMPLITUDE
0.1
-60
-100
0.001
VS
= 15V
VOUT = 3VRMS
0.01
0.001
-80
Measurement BW = 80kHz
G = 11
-100
-120
-140
-160
-120
0.0001
G = 11
RL = 600W
0.0001
VS
=
15V
G = 1
G = 1
RL = 5kW
G = 1
RL = 600W
RL = 600W
1kHz Signal
0.00001
0.000001
Measurement BW = 80kHz
0.01 0.1
G = -1
-140
0.00001
1
10
100
10
100
1k
10k 20k
Output Voltage Amplitude (VRMS
)
Frequency (Hz)
Figure 4.
Figure 5.
THD+N RATIO vs FREQUENCY
CHANNEL SEPARATION vs FREQUENCY
-100
-120
-140
0.001
-80
-90
VS
= 15V
VS
= 15V
VIN = 3.5VRMS
VIN = 3.5VRMS
G = 1
Measurement BW > 500kHz
-100
-110
-120
-130
-140
-150
-160
-170
-180
RL = 600W
G = 11
RL = 600W
0.0001
RL = 2kW
G = 1
RL = 5kW
G = 1
RL = 600W
RL = 5kW
0.00001
10
100
1k
Frequency (Hz)
10k
100k
10
100
1k
10k
100k
Frequency (Hz)
Figure 6.
Figure 7.
6
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±18V, and RL = 10kΩ, unless otherwise noted.
POWER-SUPPLY REJECTION RATIO
0.1Hz TO 10Hz NOISE
vs FREQUENCY (Referred to Input)
160
140
120
100
80
-PSRR
+PSRR
60
40
20
0
Time (1s/div)
1
10
100
1k
10k 100k
1M
10M 100M
Frequency (Hz)
Figure 8.
Figure 9.
COMMON-MODE REJECTION RATIO
OPEN-LOOP OUTPUT IMPEDANCE
vs FREQUENCY
vs FREQUENCY
140
10k
1k
120
100
80
60
40
20
0
100
10
1
0.1
10k
100k
1M
10M
100M
10
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Figure 10.
Frequency (Hz)
Figure 11.
GAIN AND PHASE vs FREQUENCY
NORMALIZED OPEN-LOOP GAIN vs TEMPERATURE
140
120
100
80
180
5
RL = 10kW
4
3
135
90
45
0
Phase
2
300mV Swing From Rails
200mV Swing From Rails
1
60
0
-1
-2
-3
-4
-5
40
Gain
20
0
-20
100
1k
10k
100k
1M
10M
100M
-75 -50 -25
0
25 50 75 100 125 150 175 200
Temperature (°C)
Frequency (Hz)
Figure 12.
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±18V, and RL = 10kΩ, unless otherwise noted.
OFFSET VOLTAGE PRODUCTION DISTRIBUTION
OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
Offset Voltage Drift (mV/°C)
Offset Voltage (mV)
Figure 14.
Figure 15.
IB AND IOS CURRENT
vs
TEMPERATURE
OFFSET VOLTAGE vs COMMON-MODE VOLTAGE
200
150
2000
1500
1000
500
100
+IB
50
IOS
0
0
-50
-500
-1000
-1500
-2000
-IB
-100
-150
-200
-50
-25
0
25
50
75
100
125
150
(V-)+1.0 (V-)+1.5 (V-)+2.0
(V+)-1.5 (V+)-1.0 (V+)-0.5
Ambient Temperature (°C)
VCM (V)
Figure 16.
Figure 17.
VOS WARMUP
INPUT OFFSET CURRENT vs SUPPLY VOLTAGE
12
10
8
100
20 Typical Units Shown
5 Typical Units Shown
80
60
6
40
4
20
2
0
0
-2
-4
-6
-8
-10
-12
-20
-40
-60
-80
-100
0
10
20
30
40
50
60
2.25
4
6
8
10
12
14
16
18
Time (s)
VS (±V)
Figure 18.
Figure 19.
8
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±18V, and RL = 10kΩ, unless otherwise noted.
INPUT OFFSET CURRENT vs COMMON-MODE VOLTAGE
INPUT BIAS CURRENT vs SUPPLY VOLTAGE
100
150
100
50
VS = 36V
3 Typical Units Shown
Unit 1
75
50
3 Typical Units Shown
Unit 2
25
0
0
Unit 3
-25
-50
-75
-100
-50
-100
-150
Common-Mode Range
-IB
+IB
1
5
10
15
20
25
30
35
2.25
4
6
8
10
12
14
16
18
VCM (V)
VS (±V)
Figure 20.
Figure 21.
INPUT BIAS CURRENT vs COMMON-MODE VOLTAGE
QUIESCENT CURRENT vs TEMPERATURE
6
5
4
3
2
1
0
150
-IB
VS = 36V
3 Typical Units Shown
+IB
100
50
Unit 1
Unit 2
0
-50
-100
-150
Unit 3
Common-Mode Range
-75 -50 -25
0
25 50 75 100 125 150 175 200
1
5
10
15
20
25
30
35
Temperature (°C)
VCM (V)
Figure 22.
Figure 23.
QUIESCENT CURRENT vs
SUPPLY VOLTAGE
NORMALIZED QUIESCENT CURRENT
vs TIME
0.05
0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
-0.05
-0.10
-0.15
-0.20
-0.25
-0.30
Average of 10 Typical Units
0
60 120 180 240 300 360 420 480 540 600
Time (s)
0
4
8
12
16
20
24
28
32
36
VS (V)
Figure 24.
Figure 25.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±18V, and RL = 10kΩ, unless otherwise noted.
SHORT-CIRCUIT CURRENT
vs TEMPERATURE
SMALL-SIGNAL STEP RESPONSE
(100mV)
60
50
40
G = -1
CL = 10pF
30
Sourcing
CF
20
10
5.6pF
RI
RF
0
604W
604W
-10
-20
-30
+18V
OPA211
-18V
CL
-40
Sinking
-50
-60
Time (0.1µs/div)
-75 -50 -25
0
25 50 75 100 125 150 175 200
Temperature (°C)
Figure 26.
Figure 27.
SMALL-SIGNAL STEP RESPONSE
(100mV)
SMALL-SIGNAL STEP RESPONSE
(100mV)
G = +1
RL = 600W
G = -1
CL = 100pF
CL = 10pF
CF
5.6pF
+18V
OPA211
-18V
RI
RF
604W
604W
+18V
OPA211
-18V
RL
CL
CL
Time (0.1ms/div)
Time (0.1µs/div)
Figure 28.
Figure 29.
SMALL-SIGNAL STEP RESPONSE
(100mV)
SMALL-SIGNAL OVERSHOOT
vs CAPACITIVE LOAD (100mV Output Step)
60
50
40
30
20
10
0
G = +1
RL = 600W
G = +1
CL = 100pF
G = -1
+18V
OPA211
-18V
G = 10
RL
CL
Time (0.1ms/div)
0
200
400
600
800
1000 1200 1400
Capacitive Load (pF)
Figure 30.
Figure 31.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±18V, and RL = 10kΩ, unless otherwise noted.
LARGE-SIGNAL STEP RESPONSE
LARGE-SIGNAL STEP RESPONSE
G = +1
CL = 100pF
G = -1
CL = 100pF
RL = 600W
RF = 0W
RL = 600W
RF = 100W
Note: See the
Applications Information
section, Input Protection.
Time (0.5ms/div)
Time (0.5ms/div)
Figure 32.
Figure 33.
LARGE-SIGNAL POSITIVE SETTLING TIME
(10VPP, CL = 100pF)
LARGE-SIGNAL POSITIVE SETTLING TIME
(10VPP, CL = 10pF)
1.0
0.8
0.010
0.008
0.006
0.004
0.002
0
1.0
0.8
0.010
0.008
0.006
0.004
0.002
0
0.6
0.6
0.4
0.4
16-Bit Settling
16-Bit Settling
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.002
-0.004
-0.006
-0.008
-0.010
-0.2
-0.4
-0.6
-0.8
-1.0
-0.002
-0.004
-0.006
-0.008
-0.010
(±1/2 LSB = ±0.00075%)
(±1/2 LSB = ±0.00075%)
0
100 200 300 400 500 600 700 800 900 1000
Time (ns)
0
100 200 300 400 500 600 700 800 900 1000
Time (ns)
Figure 34.
Figure 35.
LARGE-SIGNAL NEGATIVE SETTLING TIME
(10VPP, CL = 100pF)
LARGE-SIGNAL NEGATIVE SETTLING TIME
(10VPP, CL = 10pF)
1.0
0.8
1.0
0.8
0.010
0.010
0.008
0.006
0.004
0.002
0
0.008
0.006
0.004
0.002
0
0.6
0.6
0.4
0.4
16-Bit Settling
16-Bit Settling
0.2
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.002
-0.004
-0.006
-0.008
-0.010
-0.2
-0.4
-0.6
-0.8
-1.0
-0.002
-0.004
-0.006
-0.008
-0.010
(±1/2 LSB = ±0.00075%)
(±1/2 LSB = ±0.00075%)
0
100 200 300 400 500 600 700 800 900 1000
Time (ns)
0
100 200 300 400 500 600 700 800 900 1000
Time (ns)
Figure 36.
Figure 37.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±18V, and RL = 10kΩ, unless otherwise noted.
NEGATIVE OVERLOAD RECOVERY
POSITIVE OVERLOAD RECOVERY
G = -10
G = -10
VIN
10kW
VOUT
1kW
0V
10kW
1kW
VOUT
OPA211
VIN
VOUT
OPA211
VIN
0V
VOUT
VIN
Time (0.5ms/div)
Time (0.5ms/div)
Figure 38.
Figure 39.
OUTPUT VOLTAGE vs OUTPUT CURRENT
NO PHASE REVERSAL
20
15
0°C
Output
+85°C
+125°C
-55°C
10
5
+125°C
0
+150°C
0°C
-5
+18V
OPA211
-10
-15
-20
Output
+85°C
37VPP
-18V
(±18.5V)
0.5ms/div
0
10
20
30
40
50
60
70
IOUT (mA)
Figure 40.
Figure 41.
TURN-OFF TRANSIENT
TURN-ON TRANSIENT
20
15
20
15
Shutdown Signal
10
10
Output Signal
5
5
0
0
Output Signal
-5
-5
-10
-15
-20
-10
-15
-20
Shutdown Signal
VS = ±15V
VS = ±15V
Time (2ms/div)
Time (2ms/div)
Figure 42.
Figure 43.
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TYPICAL CHARACTERISTICS (continued)
At TA = +25°C, VS = ±18V, and RL = 10kΩ, unless otherwise noted.
TURN-ON/TURN-OFF TRANSIENT
20
15
1.6
Shutdown Signal
1.2
10
0.8
5
0.4
0
0
Output
-5
-0.4
-0.8
-1.2
-1.6
-10
-15
-20
VS = ±15V
Time (100ms/div)
Figure 44.
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APPLICATION INFORMATION
negative output voltage swing. With the OPA211
series, power-supply voltages do not need to be
equal. For example, the positive supply could be set
to +25V with the negative supply at –5V or vice-
versa.
The OPA211 is a unity-gain stable, precision op amp
with very low noise. Applications with noisy or high-
impedance power supplies require decoupling
capacitors close to the device pins. In most cases,
0.1μF capacitors are adequate. Figure 45 shows a
simplified schematic of the OPA211. This die uses a
SiGe bipolar process and contains 180 transistors.
The common-mode voltage must be maintained
within the specified range. In addition, key
parameters are assured over the specified
temperature range, TA
=
–55°C to +125°C.
OPERATING VOLTAGE
Parameters that vary significantly with operating
voltage or temperature are shown in the Typical
Characteristics.
OPA211 series op amps operate from ±2.25V to
±18V
supplies
while
maintaining
excellent
performance. The OPA211 series can operate with as
little as +4.5V between the supplies and with up to
+36V between the supplies. However, some
applications do not require equal positive and
V+
Pre-Output Driver
OUT
IN+
IN-
V-
Figure 45. OPA211 Simplified Schematic
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INPUT PROTECTION
VOLTAGE NOISE SPECTRAL DENSITY
vs SOURCE RESISTANCE
The input terminals of the OPA211 are protected from
excessive differential voltage with back-to-back
diodes, as shown in Figure 46. In most circuit
applications, the input protection circuitry has no
consequence. However, in low-gain or G = 1 circuits,
fast ramping input signals can forward bias these
diodes because the output of the amplifier cannot
respond rapidly enough to the input ramp. This effect
is illustrated in Figure 33 of the Typical
Characteristics. If the input signal is fast enough to
create this forward bias condition, the input signal
current must be limited to 10mA or less. If the input
signal current is not inherently limited, an input series
resistor can be used to limit the signal input current.
This input series resistor degrades the low-noise
performance of the OPA211, and is discussed in the
Noise Performance section of this data sheet.
Figure 46 shows an example implementing a current-
limiting feedback resistor.
10k
1k
EO
RS
OPA227
OPA211
100
10
1
Resistor Noise
EO2 = en2 + (in RS)2 + 4kTRS
100
1k
10k
100k
1M
Source Resistance, RS (W)
Figure 47. Noise Performance of the OPA211 and
OPA227 in Unity-Gain Buffer Configuration
BASIC NOISE CALCULATIONS
RF
Design of low-noise op amp circuits requires careful
consideration of
a
variety of possible noise
-
contributors: noise from the signal source, noise
generated in the op amp, and noise from the
feedback network resistors. The total noise of the
circuit is the root-sum-square combination of all noise
components.
OPA211
Output
RI
+
Input
The resistive portion of the source impedance
produces thermal noise proportional to the square
root of the resistance. This function is plotted in
Figure 47. The source impedance is usually fixed;
consequently, select the op amp and the feedback
resistors to minimize the respective contributions to
the total noise.
Figure 46. Pulsed Operation
NOISE PERFORMANCE
Figure 47 shows total circuit noise for varying source
impedances with the op amp in unity-gain
Figure 47 depicts total noise for varying source
a
impedances with the op amp in
a unity-gain
configuration (no feedback resistor network, and
therefore no additional noise contributions). Two
different op amps are shown with total circuit noise
calculated. The OPA211 has very low voltage noise,
making it ideal for low source impedances (less than
2kΩ). A similar precision op amp, the OPA227, has
somewhat higher voltage noise but lower current
noise. It provides excellent noise performance at
moderate source impedance (10kΩ to 100kΩ). Above
100kΩ, a FET-input op amp such as the OPA132
(very low current noise) may provide improved
performance. The equation in Figure 47 is shown for
the calculation of the total circuit noise. Note that en =
voltage noise, In = current noise, RS = source
impedance, k = Boltzmann’s constant = 1.38 × 10–23
J/K, and T is temperature in K.
configuration (no feedback resistor network, and
therefore no additional noise contributions). The
operational amplifier itself contributes both a voltage
noise component and a current noise component.
The voltage noise is commonly modeled as a time-
varying component of the offset voltage. The current
noise is modeled as the time-varying component of
the input bias current and reacts with the source
resistance to create a voltage component of noise.
Therefore, the lowest noise op amp for a given
application depends on the source impedance. For
low source impedance, current noise is negligible and
voltage noise generally dominates. For high source
impedance, current noise may dominate.
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Figure 48 illustrates both inverting and noninverting
op amp circuit configurations with gain. In circuit
configurations with gain, the feedback network
resistors also contribute noise. The current noise of
the op amp reacts with the feedback resistors to
create additional noise components. The feedback
resistor values can generally be chosen to make
these noise sources negligible. The equations for
total noise are shown for both configurations.
101, thus extending the resolution by 101. Note that
the input signal and load applied to the op amp are
the same as with conventional feedback without R3.
The value of R3 should be kept small to minimize its
effect on the distortion measurements.
Validity of this technique can be verified by
duplicating measurements at high gain and/or high
frequency where the distortion is within the
measurement capability of the test equipment.
Measurements for this data sheet were made with an
Audio Precision System Two distortion/noise
analyzer, which greatly simplifies such repetitive
measurements. The measurement technique can,
however, be performed with manual distortion
measurement instruments.
TOTAL HARMONIC DISTORTION
MEASUREMENTS
OPA211 series op amps have excellent distortion
characteristics. THD + Noise is below 0.0002% (G =
+1, VOUT = 3VRMS) throughout the audio frequency
range, 20Hz to 20kHz, with a 600Ω load.
SHUTDOWN
The distortion produced by OPA211 series op amps
is below the measurement limit of many commercially
available distortion analyzers. However, a special test
circuit illustrated in Figure 49 can be used to extend
the measurement capabilities.
The shutdown (enable) function of the OPA211 is
referenced to the positive supply voltage of the
operational amplifier. A valid high disables the op
amp. A valid high is defined as (V+) – 0.35V of the
positive supply applied to the shutdown pin. A valid
low is defined as (V+) – 3V below the positive supply
pin. For example, with VCC at ±15V, the device is
enabled at or below 12V. The device is disabled at or
above 14.65V. If dual or split power supplies are
used, care should be taken to ensure the valid high
or valid low input signals are properly referred to the
positive supply voltage. This pin must be connected
to a valid high or low voltage or driven, and not left
open-circuit. The enable and disable times are
provided in the Typical Characteristics section (see
Figure 42 through Figure 44). When disabled, the
output assumes a high-impedance state.
Op amp distortion can be considered an internal error
source that can be referred to the input. Figure 49
shows a circuit that causes the op amp distortion to
be 101 times greater than that normally produced by
the op amp. The addition of R3 to the otherwise
standard noninverting amplifier configuration alters
the feedback factor or noise gain of the circuit. The
closed-loop gain is unchanged, but the feedback
available for error correction is reduced by a factor of
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Noise in Noninverting Gain Configuration
Noise at the output:
R2
2
2
R2
R2
2
EO
R1
=
1 +
en2 + e12 + e22 + (inR2)2 + eS2 + (inRS)2 1 +
R1
R1
EO
R2
R1
Where eS = Ö4kTRS
e1 = Ö4kTR1
´
= thermal noise of RS
1 +
RS
R2
R1
´
= thermal noise of R1
VS
e2 = Ö4kTR2 = thermal noise of R2
Noise in Inverting Gain Configuration
Noise at the output:
R2
2
R2
2
EO
2
=
1 +
en2 + e12 + e22 + (inR2)2 + eS
R1
R1 + RS
EO
RS
R2
Where eS = Ö4kTRS
´
= thermal noise of RS
= thermal noise of R1
R1 + RS
VS
R2
e1 = Ö4kTR1
´
R1 + RS
e2 = Ö4kTR2 = thermal noise of R2
For the OPA211 series op amps at 1kHz, en = 1.1nV/ÖHz and in = 1.7pA/ÖHz.
Figure 48. Noise Calculation in Gain Configurations
R1
R2
SIG. DIST.
GAIN GAIN
R1
R2
1kW
R3
1
101
¥
10W
11W
R3
OPA211
VOUT
11
101 100W 1kW
R2
R1
Signal Gain = 1+
R2
Distortion Gain = 1+
R1 II R3
Generator
Output
Analyzer
Input
Audio Precision
System Two(1)
Load
with PC Controller
(1) For measurement bandwidth, see Figure 4, Figure 5, and Figure 6.
Figure 49. Distortion Test Circuit
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ELECTRICAL OVERSTRESS
An ESD event produces a short duration, high-
voltage pulse that is transformed into
a short
Designers often ask questions about the capability of
an operational amplifier to withstand electrical
overstress. These questions tend to focus on the
device inputs, but may involve the supply voltage pins
or even the output pin. Each of these different pin
functions have electrical stress limits determined by
the voltage breakdown characteristics of the
particular semiconductor fabrication process and
specific circuits connected to the pin. Additionally,
internal electrostatic discharge (ESD) protection is
built into these circuits to protect them from
accidental ESD events both before and during
product assembly.
duration, high-current pulse as it discharges through
a semiconductor device. The ESD protection circuits
are designed to provide a current path around the
operational amplifier core to prevent it from being
damaged. The energy absorbed by the protection
circuitry is then dissipated as heat.
When an ESD voltage develops across two or more
of the amplifier device pins, current flows through one
or more of the steering diodes. Depending on the
path that the current takes, the absorption device
may activate. The absorption device has a trigger, or
threshold voltage, that is above the normal operating
voltage of the OPA211 but below the device
breakdown voltage level. Once this threshold is
exceeded, the absorption device quickly activates
and clamps the voltage across the supply rails to a
safe level.
It is helpful to have a good understanding of this
basic ESD circuitry and its relevance to an electrical
overstress event. Figure 50 illustrates the ESD
circuits contained in the OPA211 (indicated by the
dashed line area). The ESD protection circuitry
involves several current-steering diodes connected
from the input and output pins and routed back to the
internal power-supply lines, where they meet at an
absorption device internal to the operational amplifier.
This protection circuitry is intended to remain inactive
during normal circuit operation.
When the operational amplifier connects into a circuit
such as that illustrated in Figure 50, the ESD
protection components are intended to remain
inactive and not become involved in the application
circuit operation. However, circumstances may arise
where an applied voltage exceeds the operating
voltage range of a given pin. Should this condition
occur, there is a risk that some of the internal ESD
protection circuits may be biased on, and conduct
current. Any such current flow occurs through
steering diode paths and rarely involves the
absorption device.
RF
+VS
+V
OPA211
RI
ESD Current-
Steering Diodes
Out
-In
Op-Amp
Core
+In
Edge-Triggered ESD
Absorption Circuit
RL
ID
(1)
VIN
-V
-VS
(1) VIN = +VS + 500mV.
Figure 50. Equivalent Internal ESD Circuitry and Its Relation to a Typical Circuit Application
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Figure 50 depicts a specific example where the input
voltage, VIN, exceeds the positive supply voltage
(+VS) by 500mV or more. Much of what happens in
the circuit depends on the supply characteristics. If
+VS can sink the current, one of the upper input
steering diodes conducts and directs current to +VS.
Excessively high current levels can flow with
increasingly higher VIN. As a result, the datasheet
specifications recommend that applications limit the
input current to 10mA.
the supplies appear as high impedance, then the
operational amplifier supply current may be supplied
by the input source via the current steering diodes.
This state is not a normal bias condition; the amplifier
most likely will not operate normally. If the supplies
are low impedance, then the current through the
steering diodes can become quite high. The current
level depends on the ability of the input source to
deliver current, and any resistance in the input path.
THERMAL CONSIDERATIONS
If the supply is not capable of sinking the current, VIN
may begin sourcing current to the operational
amplifier, and then take over as the source of positive
supply voltage. The danger in this case is that the
voltage can rise to levels that exceed the operational
amplifier absolute maximum ratings. In extreme but
rare cases, the absorption device triggers on while
+VS and –VS are applied. If this event happens, a
direct current path is established between the +VS
and –VS supplies. The power dissipation of the
absorption device is quickly exceeded, and the
extreme internal heating destroys the operational
amplifier.
The primary issue with all semiconductor devices is
junction temperature (TJ). The most obvious
consideration is assuring that TJ never exceeds the
absolute maximum rating specified for the device.
However, addressing device thermal dissipation has
benefits beyond protecting the device from damage.
Even modest increases in junction temperature can
decrease op amp performance, and temperature-
related errors can accumulate. Understanding the
power generated by the device within the specific
application and assessing the thermal effects on the
error tolerance lead to a better understanding of
system performance and thermal dissipation needs.
Another common question involves what happens to
the amplifier if an input signal is applied to the input
while the power supplies +VS and/or –VS are at 0V.
Again, it depends on the supply characteristic while at
0V, or at a level below the input signal amplitude. If
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PACKAGE OPTION ADDENDUM
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16-Aug-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
OPA211MDGKTEP
V62/12619-01XE
ACTIVE
ACTIVE
VSSOP
VSSOP
DGK
DGK
8
8
250
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF OPA211-EP :
Catalog: OPA211
•
NOTE: Qualified Version Definitions:
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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16-Aug-2012
Catalog - TI's standard catalog product
•
Addendum-Page 2
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