OPA320AQDBVRQ1 [TI]
通过汽车级认证的精密、零交叉、20MHz、0.9pA Ib、RRIO、CMOS 运算放大器 | DBV | 5 | -40 to 125;
| 型号： | OPA320AQDBVRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 通过汽车级认证的精密、零交叉、20MHz、0.9pA Ib、RRIO、CMOS 运算放大器 | DBV | 5 | -40 to 125 放大器 运算放大器 |
| 文件： | 总35页 (文件大小：1772K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA320-Q1, OPA2320-Q1
ZHCSCS6B –SEPTEMBER 2014–REVISED DECEMBER 2018
OPAx320-Q1 高精度 20MHz 0.9pA 低噪声 RRIO
CMOS 运算放大器
1 特性
3 说明
1
•
•
符合汽车应用 标准
具有符合 AEC-Q100 标准的下列结果：
OPA320-Q1 和 OPA2320-Q1 (OPAx320-Q1) 器件是
经过优化的新一代精密低压 CMOS 运算放大器 (op
amps)，具有极低噪声和宽带宽。这些器件可在仅
1.45mA 的低静态电流下运行。
–
器件温度 1 级：–40°C 至 125°C 的环境工作温
度范围
–
–
器件 HBM ESD 分类等级 2
OPAx320-Q1 非常适用于低功耗、单电源类 应用。低
噪声 (7nV/√Hz) 和高速运行特性使这些器件同样非常
适合驱动采样模数转换器 (ADC)。其他 应用 包括信号
调节和传感器放大。
器件 CDM ESD 分类等级 C4B
•
零交叉失真时的精度：
–
–
–
低偏移电压：150µV（最大值）
高共模抑制比 (CMRR)：114dB
轨到轨 I/O
OPAx320-Q1 具有零交叉失真的线性输入级，能够在
整个输入范围内提供 114dB（典型值）的出色共模抑
制比 (CMRR)。共模输入范围将正负电源电压分别扩展
了 100mV。输出电压摆幅通常在 10mV 电源轨内。
•
•
•
•
•
•
•
•
低输入偏置电流：0.9pA（最大值）
低噪声：10kHz 时为 7nV/√Hz
高带宽：20MHz
转换率：10V/μs
此外，OPAx320-Q1 还具有 1.8V 至 5.5V 的宽电源电
压范围，而且在整个电源电压范围内的 PSRR 都极为
出色 (106dB)。这些 特性 使得 OPAx320-Q1 适用于
直接从电池运行， 而无需调节的 高精度、低功耗类应
用。
静态电流：每通道 1.45mA
单电源电压范围：1.8V 到 5.5V
单位增益稳定
小型超薄小外形尺寸 (VSSOP) 封装
OPAx320-Q1 器件采用 8 引脚 VSSOP (DGK) 封装。
2 应用
器件信息(1)
•
•
•
•
•
•
•
•
•
汽车
高阻抗传感器信号调节
互阻抗放大器
器件型号
OPA320-Q1
OPA2320-Q1
封装
封装尺寸（标称值）
2.90mm x 1.60mm
3.00mm × 3.00mm
SOT (5)
VSSOP (8)
测试和测量设备
可编程逻辑控制器 (PLC)
电机控制环路
(1) 要了解所有可用封装，请参见数据表末尾的封装选项附录。
零交叉失真：低偏移电压
通信
100
80
输入和输出 ADC 和 DAC 缓冲器
有源滤波器
60
40
20
0
–20
–40
–60
–80
–100
–3 –2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
3
Common-Mode Voltage (V)
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLOS884
OPA320-Q1, OPA2320-Q1
ZHCSCS6B –SEPTEMBER 2014–REVISED DECEMBER 2018
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics: ........................................ 5
6.6 Typical Characteristics.............................................. 7
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 16
8
9
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Applications ................................................ 17
Power Supply Recommendations...................... 22
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 23
11 器件和文档支持 ..................................................... 24
11.1 器件支持................................................................ 24
11.2 相关链接................................................................ 24
11.3 接收文档更新通知 ................................................. 24
11.4 社区资源................................................................ 24
11.5 商标....................................................................... 24
11.6 静电放电警告......................................................... 24
11.7 术语表 ................................................................... 24
12 机械、封装和可订购信息....................................... 25
7
4 修订历史记录
Changes from Revision A (December 2016) to Revision B
Page
•
•
•
•
•
•
•
•
•
•
Changed Figure 1 x-axis unit from mV to µV (typo)............................................................................................................... 7
Changed Figure 2 x-axis unit from mV/°C to µV/°C (typo)..................................................................................................... 7
Changed Figure 3 y-axis unit from mV to µV (typo)............................................................................................................... 7
Changed Figure 14 y-axis unit from mV to µV (typo)............................................................................................................. 8
Changed Figure 19 y-axis unit from W to Ω (typo)................................................................................................................. 9
Changed Figure 25 y-axis unit from V/ms to V/µs (typo) ..................................................................................................... 10
Changed Figure 26 x-axis unit from ms to µs (typo) ............................................................................................................ 10
Changed Figure 27 x-axis unit from ms to µs (typo) ............................................................................................................ 10
Changed Figure 28 x-axis unit from ms to µs (typo) ............................................................................................................ 10
Changed Figure 35 x-axis unit from ms to µs (typo) ............................................................................................................ 16
Changes from Original (September 2014) to Revision A
Page
•
•
•
•
•
已添加 在文档中添加了 OPA320-Q1 器件.............................................................................................................................. 1
已更改 在同时提及 OPA2320-Q1 和 OPAx320-Q1 器件的文档中，将 OPA2320-Q1 更改为了 OPAx320-Q1...................... 1
已更改 更改了说明部分的 首句 ：添加了 (OPA320-Q1、OPA2320-Q1) ............................................................................... 1
已添加 将 OPA320-Q1 添加到了器件信息 表 ......................................................................................................................... 1
Added OPA320-Q1 device (SOT package) to Pin Configuration and Functions section: added OPA320-Q1 pin out
to section and added relevant rows to Pin Functions table.................................................................................................... 3
•
•
Changed format of ESD Ratings table: updated table to current standards, moved storage temperature parameter to
Absolute Maximum Ratings table........................................................................................................................................... 4
Changed Supply voltage parameter in Recommended Operating Conditions table: split apart single- and dual-
supply values into separate rows ........................................................................................................................................... 4
•
•
•
Added OPA320-Q1 package to Thermal Information table ................................................................................................... 4
Changed Output Voltage Swing vs Output Current figure ..................................................................................................... 8
Changed Operational Amplifier Board Layout for Noninverting Configuration figure........................................................... 23
2
Copyright © 2014–2018, Texas Instruments Incorporated
OPA320-Q1, OPA2320-Q1
www.ti.com.cn
ZHCSCS6B –SEPTEMBER 2014–REVISED DECEMBER 2018
5 Pin Configuration and Functions
OPA320-Q1: DBV Package
5-Pin SOT
OPA2320-Q1: DGK Package
8-Pin VSSOP
Top View
Top View
Pin Functions
PIN
NO.
I/O
DESCRIPTION
NAME
–IN
DBV
4
DGK
—
2
I
I
Inverting input
–IN A
–IN B
+IN
—
—
3
Inverting input (channel A)
Inverting input (channel B)
Noninverting input
6
I
—
3
I
+IN A
+IN B
OUT
OUT A
OUT B
V–
—
—
1
I
Noninverting input (channel A)
Noninverting input (channel B)
Output
5
I
—
1
O
O
O
—
—
—
—
2
Output (channel A)
7
Output (channel B)
4
Negative supply or ground (for single-supply operation)
Positive supply
V+
5
8
Copyright © 2014–2018, Texas Instruments Incorporated
3
OPA320-Q1, OPA2320-Q1
ZHCSCS6B –SEPTEMBER 2014–REVISED DECEMBER 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
Supply voltage
Voltage(2)
V+ and V–
6
V(V+) + 0.5
10
Signal input pins
Signal input pins
Output short-circuit current(3)
Operating, TA
V(V–) – 0.5
–10
V
Current(2)
mA
Continuous
–40
–65
150
150
150
Temperature
Junction, TJ
°C
Storage, Tstg
(1) Stresses beyond those listed as absolute maximum ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated as recommended operating conditions is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails should
be current limited to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
V(ESD)
Electrostatic discharge
All pins
Corner pins (1, 4, 5, and 8)
V
Charged-device model (CDM),
per AEC Q100-011
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.8
NOM
MAX
5.5
UNIT
V
Single-supply
Dual-supply
VS
TA
Supply voltage
±0.9
–40
±2.75
125
Ambient operating temperature
°C
6.4 Thermal Information
OPA320-Q1
OPA2320-Q1
THERMAL METRIC(1)
DBV (SOT)
5 PINS
158.8
60.7
DGK (VSSOP)
UNIT
8 PINS
174.8
43.9
95
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
44.8
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.6
2
ψJB
4.2
93.5
—
RθJC(bot)
—
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2014–2018, Texas Instruments Incorporated
OPA320-Q1, OPA2320-Q1
www.ti.com.cn
ZHCSCS6B –SEPTEMBER 2014–REVISED DECEMBER 2018
6.5 Electrical Characteristics:
VS = 1.8 to 5.5 V or ±0.9 V to ±2.75 V; at TA = 25°C, R(L) = 10 kΩ connected to VS / 2, V(CM) = VS / 2, VO = VS / 2 (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
OFFSET VOLTAGE
VIO
Input offset voltage
40
150
5
µV
Input offset voltage versus
temperature
VS = 5.5 V, TA = –40°C to +125°C
1.5
µV/°C
VS = 1.8 to 5.5 V
5
20
Input offset voltage versus power
supply
µV/V
dB
VS = 1.8 to 5.5 V, TA = –40°C to +125°C
15
Input offset-voltage channel
separation
At 1 kHz
130
INPUT VOLTAGE
V(CM)
Common-mode voltage range
V(V–) – 0.1
100
V(V+) + 0.1
V
CMRR
Common-mode rejection ratio
VS = 5.5 V, V(V–) – 0.1 V < V(CM) < V(V+) + 0.1 V
114
dB
Common-mode rejection ratio,
over temperature
VS = 5.5 V, V(V–) – 0.1 V < V(CM) < V(V+) + 0.1 V,
TA = –40°C to 125°C
96
dB
INPUT BIAS CURRENT
IIB Input bias current
±0.2
±0.2
±0.9
±50
pA
pA
pA
pA
TA = –40°C to 85°C
TA = –40°C to 125°C
Input bias current, over
temperature
±400
±0.9
±50
IIO
Input offset current
TA = –40°C to 85°C
TA = –40°C to 125°C
Input offset current, over
temperature
±400
NOISE
VI(n)
Input voltage noise
f = 0.1 to 10 Hz
f = 1 kHz
2.8
8.5
7
µVPP
nV/√Hz
fA/√Hz
Input voltage noise density
f = 10 kHz
f = 1 kHz
Input current noise density
0.6
INPUT CAPACITANCE
Differential
5
4
pF
pF
Common-mode
OPEN-LOOP GAIN
0.1 V < VO < V(V+) – 0.1 V, R(L) = 10 kΩ
114
100
108
96
132
130
123
130
47
0.1 V < VO < V(V+) – 0.1 V, R(L) = 10 kΩ, TA = –40°C to 125°C
0.2 V < VO < V(V+) – 0.2 V, R(L) = 2 kΩ
A(OL)
Open-loop voltage gain
dB
°
0.2 V < VO < V(V+) – 0.2 V, R(L) = 2 kΩ, TA = –40°C to 125°C
VS = 5 V, C(L) = 50 pF
PM
Phase margin
FREQUENCY RESPONSE (VS = 5 V, C(L) = 50 pF)
GBP
SR
Gain bandwidth product
Slew rate
Unity gain
20
10
MHz
V/µs
G = 1
To 0.1%, 2-V step, G = 1
To 0.01%, 2-V step, G = 1
To 0.0015%, 2-V step, G = 1(1)
VI × G > VS
0.25
ts
Settling time
0.32
µs
ns
0.5
Overload recovery time
100
VO = 4 VPP, G = 1, f = 10 kHz, R(L) = 10 kΩ
VO = 4 VPP, G = 1, f = 10 kHz, R(L) = 600 kΩ
0.0005%
0.0011%
Total harmonic distortion +
noise(2)
THD+N
(1) Based on simulation.
(2) Third-order filter; bandwidth = 80 kHz at –3 dB.
Copyright © 2014–2018, Texas Instruments Incorporated
5
OPA320-Q1, OPA2320-Q1
ZHCSCS6B –SEPTEMBER 2014–REVISED DECEMBER 2018
www.ti.com.cn
Electrical Characteristics: (continued)
VS = 1.8 to 5.5 V or ±0.9 V to ±2.75 V; at TA = 25°C, R(L) = 10 kΩ connected to VS / 2, V(CM) = VS / 2, VO = VS / 2 (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
10
MAX UNIT
OUTPUT
R(L) = 10 kΩ
20
R(L) = 10 kΩ, TA = –40°C to 125°C
R(L) = 2 kΩ
30
35
45
Voltage output swing from both
rails
VO
mV
25
R(L) = 2 kΩ, TA = –40°C to 125°C
VS = 5.5 V
I(SC)
C(L)
Short-circuit current
±65
mA
Capacitive load drive
Open-loop output resistance
See Typical Characteristics
IO = 0 mA, f = 1MHz
90
Ω
POWER SUPPLY
VS
Specified voltage range
1.8
5.5
V
IO = 0 mA, VS = 5.5V
1.45
28
1.6
1.7
IQ
Quiescent current per amplifier
Power-on time
mA
µs
IO = 0 mA, VS = 5.5V, TA = –40°C to 125°C
V(V+) = 0 to 5 V, to 90% IQ level
TEMPERATURE
Specified range
Operating range
–40
–40
125
150
°C
°C
6
Copyright © 2014–2018, Texas Instruments Incorporated
OPA320-Q1, OPA2320-Q1
www.ti.com.cn
ZHCSCS6B –SEPTEMBER 2014–REVISED DECEMBER 2018
6.6 Typical Characteristics
at TA = 25°C, V(CM) = VO = mid-supply, and R(L) = 10 kΩ (unless otherwise noted)
14
12
10
8
25
20
15
10
5
6
4
2
0
0
0.1
0.5
0.9
1.3
1.7
2.1
2.5
2.9
Offset Drift (µV/°C)
Offset Voltage (µV)
Figure 2. Offset Voltage Drift Distribution
Figure 1. Offset Voltage Production Distribution
100
80
160
140
120
100
80
0
Phase
Gain
-20
60
-40
40
-60
20
-80
0
60
-100
-120
-140
-160
-180
–20
–40
–60
–80
–100
40
20
0
-20
–3 –2.5 –2 –1.5 –1 –0.5
0
0.5
1
1.5
2
2.5
3
1
10
100
1k
10k 100k
1M
10M 100M
Common-Mode Voltage (V)
Frequency (Hz)
Representative units, VS = ±2.75 V
VS = ±2.5 V, C(L) = 50 pF
Figure 4. Open-Loop Gain and Phase vs Frequency
Figure 3. Offset Voltage vs Common-Mode Voltage
140
1.5
10-kΩ Load
2-kΩ Load
135
130
125
120
115
110
105
100
1.45
1.4
1.35
1.3
125°C
85°C
25°C
–40°C
1.25
-50
-25
0
25
50
75
100
125
150
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Temperature (°C)
Supply Voltage (V)
Figure 5. Open-Loop Gain vs Temperature
Figure 6. Quiescent Current vs Supply Voltage
Copyright © 2014–2018, Texas Instruments Incorporated
7
OPA320-Q1, OPA2320-Q1
ZHCSCS6B –SEPTEMBER 2014–REVISED DECEMBER 2018
www.ti.com.cn
Typical Characteristics (continued)
at TA = 25°C, V(CM) = VO = mid-supply, and R(L) = 10 kΩ (unless otherwise noted)
1
0.8
0.6
0.4
0.2
0
6
IIB–
IIB+
IIB+
IIB–
IIO
5
4
3
2
1
0
-1
-2
-3
-4
-5
-6
-0.2
-0.4
-0.6
-0.8
-1
0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9
Supply Voltage ( Vꢀ
-3 -2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
2.5
3
Common-Mode Voltage (V)
Figure 7. Input Bias Current vs Supply Voltage
Figure 8. Input Bias Current vs Common-Mode Voltage
40
1300
IIB–
1200
35
30
25
20
15
10
5
IIB+
1100
1000
900
800
700
600
500
400
300
200
100
0
IIO
IIB
IIO
0
-100
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
Input Bias Current (pA)
Figure 10. Input Bias Current vs Temperature
Figure 9. Input Bias Current Distribution
140
130
125
120
115
110
105
100
95
PSRR
CMRR
PSRR
CMRR
120
100
80
60
40
20
0
90
100
1k
10k
100k
1M
10M
-50
-25
0
25
50
75
100
125
150
Frequency (Hz)
Temperature (°C)
VS = 1.8 to 5.5 V
Figure 12. CMRR and PSRR vs Temperature
Figure 11. CMRR and PSRR vs Frequency
8
Copyright © 2014–2018, Texas Instruments Incorporated
OPA320-Q1, OPA2320-Q1
www.ti.com.cn
ZHCSCS6B –SEPTEMBER 2014–REVISED DECEMBER 2018
Typical Characteristics (continued)
at TA = 25°C, V(CM) = VO = mid-supply, and R(L) = 10 kΩ (unless otherwise noted)
6
1000
100
10
5
4
3
2
1
0
–1
–2
–3
–4
1
10
100
1k
10k
100k
1M
0
1
2
3
4
5
6
7
8
9
10
Frequency (Hz)
Time (1 s/div)
VS = 1.8 to 5.5 V
Figure 13. Input Voltage Noise Spectral Density vs
Frequency
Figure 14. 0.1-Hz to 10-Hz Input Voltage Noise
60
40
20
0
60
40
20
0
G = 100 V/V
G = 10 V/V
G = 1 V/V
G = 100 V/V
G = 10 V/V
G = 1 V/V
-20
-20
10k
100k
1M
10M
100M
10k
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
VS = 1.8 V, C(L) = 50 pF, R(L) = 10 kΩ
VS = 5.5 V, C(L) = 50 pF, R(L) = 10 kΩ
Figure 15. Closed-Loop Gain vs Frequency
Figure 16. Closed-Loop Gain vs Frequency
3
2
1
0
6
5
4
3
2
1
0
5.5 VS
–40°C
25°C
3.3 VS
1.8 VS
125°C
-1
-2
-3
10k
100k
Frequency (Hz)
1M
10M
0
10
20
30
40
50
60
70
80
Output Current (mA)
C(L) = 50 pF, R(L) = 10 kΩ
VS = ±2.75 V
Figure 17. Maximum Output Voltage vs Frequency
Figure 18. Output Voltage Swing vs Output Current
Copyright © 2014–2018, Texas Instruments Incorporated
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Typical Characteristics (continued)
at TA = 25°C, V(CM) = VO = mid-supply, and R(L) = 10 kΩ (unless otherwise noted)
1000
100
10
70
60
50
40
30
20
10
0
G = 1 V/V, VS = 1.8 V
G = 1 V/V, VS = 5.5 V
G = 10 V/V, VS = 1.8 V
G = 10 V/V, VS = 5.5 V
1
10
100
1k
10k 100k
1M
10M 100M
0
500
1000
1500
2000
2500
3000
Frequency (Hz)
Capacitive Load (pF)
VS = ±2.75 V
Figure 19. Open-Loop Output Impedance vs Frequency
Figure 20. Small-Signal Overshoot vs Load Capacitance
0.1
0.1
Load = 600 Ω
Load = 10 kΩ
0.01
0.01
0.001
0.001
Load = 600 Ω
Load = 10 kΩ
0.0001
0.0001
0.01
0.1
1
10
10
100
1k
10k
100k
Input Voltage (VPP
)
Frequency (Hz)
VS = ±2.5 V, f = 10 kHz, G = 1 V/V
VS = ±2.5 V, f = 10 kHz, G = 1 V/V, VI = 2 VPP
Figure 21. THD+N vs Amplitude
Figure 22. THD+N vs Frequency
0.1
0.01
0
-20
Load = 600 Ω
Load = 10 kΩ
-40
-60
-80
0.001
0.0001
-100
-120
-140
10
100
1k
10k
100k
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
VS = ±2.5 V, f = 10 kHz, G = 1 V/V, VI = 4 VPP
VS = ±2.75 V
Figure 23. THD+N vs Frequency
Figure 24. Channel Separation vs Frequency
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Typical Characteristics (continued)
at TA = 25°C, V(CM) = VO = mid-supply, and R(L) = 10 kΩ (unless otherwise noted)
12
11.5
11
0.1
0.075
0.05
Rise
Fall
VO
VI
0.025
0
10.5
10
–0.025
–0.05
–0.075
–0.1
9.5
9
1.6
2
2.4 2.8 3.2 3.6
4
4.4 4.8 5.2 5.6
–0.8
–0.4
0
0.4
0.8
1.2
1.6
Supply Voltage (V)
Time (µs)
C(L) = 50 pF
VS = ±2.75 V, G = 1 V/V, VI = 100 mVPP
Figure 25. Slew Rate vs Supply Voltage
Figure 26. Small-Signal Step Response
1.5
1
0.1
VI
VO
VO
VI
0.075
0.05
0.5
0
0.025
0
–0.025
–0.05
–0.075
–0.1
–0.5
–1
–1.5
–1.6
–1.2
–0.8
0
0.4
0.8
–0.4
0
0.4
0.8
1.2
1.6
–0.4
Time (µs)
Time (µs)
VS = ±2.75 V, G = –1 V/V, VI = 100 mVPP
VS = ±2.75 V, G = 1 V/V, VI = 2 VPP
Figure 28. Large-Signal Step Response vs Time
Figure 27. Small-Signal Step Response
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7 Detailed Description
7.1 Overview
The OPA320-Q1 and OPA2320-Q1 (OPAx320-Q1) operational amplifiers (op amps) are unity-gain stable and
operate on a single-supply voltage (1.8 V to 5.5 V), or a split supply voltage (±0.9 V to ±2.75 V), making these
devices highly versatile and easy to use. The OPAx320-Q1 amplifiers are fully specified from 1.8 V to 5.5 V and
over the extended temperature range of –40°C to +125°C. Parameters that can exhibit variance with regard to
operating voltage or temperature are presented in the Typical Characteristics section.
7.2 Functional Block Diagram
V(V+)
Charge Pump
Reference
Current
IN+
INœ
VBIAS1
Class AB
Control
OUT
Circuitry
VBIAS2
E-TrimTM
V(V-)
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7.3 Feature Description
7.3.1 Input and ESD Protection
The OPAx320-Q1 incorporate internal electrostatic discharge (ESD) protection circuits on all pins. In the case of
input and output pins, this protection primarily consists of current-steering diodes connected between the input
and power-supply pins. These ESD protection diodes also provide in-circuit input overdrive protection, provided
that the current is limited to 10 mA, as stated in the Absolute Maximum Ratings. Many input signals are
inherently current-limited to less than 10 mA; therefore, a limiting resistor is not required. Figure 29 shows how a
series input resistor (R(S)) may be added to the driven input to limit the input current. The added resistor
contributes thermal noise at the amplifier input and the value should be kept to the minimum in noise-sensitive
applications.
V(V+)
I(OVERLOAD)
10 mA, Max
VO
OPA320-Q1
VI
R(S)
Figure 29. Input Current Protection
7.3.2 Feedback Capacitor Improves Response
For optimum settling time and stability with high-impedance feedback networks, adding a feedback capacitor
across the feedback resistor, R(FB), as shown in Figure 30 may be necessary. This capacitor compensates for the
zero created by the feedback network impedance and the OPAx320-Q1 input capacitance (and any parasitic
layout capacitance). The effect becomes more significant with higher impedance networks.
C(F)
R(IN)
R(F)
VI
V(V+)
C(IN)
R(IN) × C(IN) = R(F) × C(F)
VO
OPA320-Q1
C(L)
C(IN)
NOTE: Where C(IN) is equal to the OPAx320-Q1 input capacitance (approximately 9 pF) plus any parasitic layout
capacitance.
Figure 30. Feedback Capacitor Improves Dynamic Performance
It is suggested that a variable capacitor be used for the feedback capacitor because input capacitance may vary
between op amps and layout capacitance is difficult to determine. For the circuit shown in Figure 30, the value of
the variable feedback capacitor should be chosen so that the input resistance times the input capacitance of the
OPAx320-Q1 (9 pF, typical) plus the estimated parasitic layout capacitance equals the feedback capacitor times
the feedback resistor:
R(IN) × C(IN) = R(FB) × C(FB)
Where:
•
C(IN) is equal to the OPAx320-Q1 input capacitance (sum of differential and common-mode) plus the layout
capacitance.
(1)
13
The capacitor value can be adjusted until optimum performance is obtained.
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Feature Description (continued)
7.3.3 EMI Susceptibility And Input Filtering
Operational amplifiers vary in susceptibility to electromagnetic interference (EMI). If conducted EMI enters the
operational amplifier, the DC offset observed at the amplifier output may shift from the nominal value while EMI is
present. This shift is a result of signal rectification associated with the internal semiconductor junctions. While all
operational amplifier pin functions can be affected by EMI, the input pins are likely to be the most susceptible.
The OPAx320-Q1 operational amplifier family incorporates an internal input low-pass filter that reduces the
amplifiers response to EMI. Both common-mode and differential mode filtering are provided by the input filter.
The filter is designed for a cut-off frequency of approximately 580 MHz (–3 dB), with a roll-off of 20 dB per
decade.
7.3.4 Output Impedance
The open-loop output impedance of the OPAx320-Q1 common-source output stage is approximately 90 Ω. When
the op amp is connected with feedback, this value is reduced significantly by the loop gain. For example, with
130 dB (typical) of open-loop gain, the output impedance is reduced in unity-gain to less than 0.03 Ω. For each
decade rise in the closed-loop gain, the loop gain is reduced by the same amount, which results in a ten-fold
increase in effective output impedance. While the OPAx320-Q1 output impedance remains very flat over a wide
frequency range, at higher frequencies the output impedance rises as the open-loop gain of the op amp drops.
However, at these frequencies the output also becomes capacitive as a result of parasitic capacitance. This in
turn prevents the output impedance from becoming too high, which can cause stability problems when driving
large capacitive loads. As mentioned previously, the OPAx320-Q1 have excellent capacitive load drive capability
for op amps with the bandwidth.
7.3.5 Capacitive Load and Stability
The OPAx320-Q1 are designed to be used in applications where driving a capacitive load is required. As with all
op amps, there may be specific instances where the OPAx320-Q1 can become unstable. The particular op amp
circuit configuration, layout, gain, and output loading are some of the factors to consider when establishing
whether an amplifier is stable in operation. An op amp in the unity-gain (1 V/V) buffer configuration and driving a
capacitive load exhibits a greater tendency to become unstable than an amplifier operated at a higher noise gain.
The capacitive load, in conjunction with the op amp output resistance, creates a pole within the feedback loop
that degrades the phase margin. The degradation of the phase margin increases as the capacitive loading
increases. When operating in the unity-gain configuration, the OPAx320-Q1 remain stable with a pure capacitive
load up to approximately 1 nF.
The equivalent series resistance (ESR) of some very large capacitors (C(L) > 1 µF) is sufficient to alter the phase
characteristics in the feedback loop such that the amplifier remains stable. Increasing the amplifier closed-loop
gain allows the amplifier to drive increasingly larger capacitance. This increased capability is evident when
observing the overshoot response of the amplifier at higher voltage gains; see Figure 32. One technique for
increasing the capacitive load drive capability of the amplifier operating in unity gain is to insert a small resistor
(R(S)), typically 10 Ω to 20 Ω, in series with the output, as shown in Figure 31.
This resistor significantly reduces the overshoot and ringing associated with large capacitive loads. A possible
problem with this technique is that a voltage divider is created with the added series resistor and any resistor
connected in parallel with the capacitive load. The voltage divider introduces a gain error at the output that
reduces the output swing. The error contributed by the voltage divider may be insignificant. For instance, with a
load resistance, R(L) = 10 kΩ and R(S) = 20 Ω, the gain error is only about 0.2%. However, when R(L) is
decreased to 600 Ω, which the OPAx320-Q1 are able to drive, the error increases to 7.5%.
V(V+)
R(S)
VO
OPA320-Q1
VI
10 Ω to
20 Ω
R(L)
C(L)
Figure 31. Improving Capacitive Load Drive
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Feature Description (continued)
70
60
50
40
30
20
10
0
G = 1 V/V, VS = 1.8 V
G = 1 V/V, VS = 5.5 V
G = 10 V/V, VS = 1.8 V
G = 10 V/V, VS = 5.5 V
0
500
1000
1500
2000
2500
3000
Capacitive Load (pF)
Figure 32. Small-Signal Overshoot versus Capacitive Load (100-mVPP Output Step)
7.3.6 Overload Recovery Time
Overload recovery time is the time it takes the output of the amplifier to come out of saturation and recover to the
linear region. Overload recovery is particularly important in applications where small signals must be amplified in
the presence of large transients. Figure 33 and Figure 34 show the positive and negative overload recovery
times of the OPAx320-Q1, respectively. In both cases, the time elapsed before the OPAx320-Q1 come out of
saturation is less than 100 ns. In addition, the symmetry between the positive and negative recovery times allows
excellent signal rectification without distortion of the output signal.
3
2.5
2
1
0.5
0
Input
Input
Output
Output
1.5
1
-0.5
-1
0.5
0
-1.5
-2
-0.5
-1
-2.5
-3
9.75
10
10.25
10.5
10.75
11
9.75
10
10.25
10.5
10.75
11
Time (250 ns/div)
Time (250 ns/div)
VS = ±2.75 V, G = –10 V/V
Figure 33. Positive Recovery Time
VS = ±2.75 V, G = –10 V/V
Figure 34. Negative Recovery Time
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7.4 Device Functional Modes
7.4.1 Rail-to-Rail Input
The OPAx320-Q1 feature true rail-to-rail input operation, with supply voltages as low as ±0.9 V (1.8 V). The
design of the OPAx320-Q1 amplifiers include an internal charge-pump that powers the amplifier input stage with
an internal supply rail at approximately 1.6 V above the external supply (V+). This internal supply rail allows the
single differential input pair to operate and remain very linear over a very wide input common-mode range. A
unique zero-crossover input topology eliminates the input offset transition region typical of many rail-to-rail,
complementary input stage operational amplifiers. This topology allows the OPAx320-Q1 to provide superior
common-mode performance (CMRR > 110 dB, typical) over the entire common-mode input range, which extends
100 mV beyond both power-supply rails. When driving analog-to-digital converters (ADCs), the highly linear V(CM)
range of the OPAx320-Q1 provides maximum linearity and lowest distortion.
7.4.2 Phase Reversal
The OPAx320-Q1 op amps are designed to be immune to phase reversal when the input pins exceed the supply
voltages, and thus provide further in-system stability and predictability. Figure 35 shows the input voltage
exceeding the supply voltage without any phase reversal.
4
VI
3
2
VO
1
0
–1
–2
–3
–4
–500
–250
0
250
500
750
1000
Time (µs)
VS = ±2.5 V
Figure 35. No Phase Reversal
16
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPAx320-Q1 can be used in a wide range of applications, such as transimpedance amplifiers, high-
impedance sensors, active filters, and driving ADCs.
8.2 Typical Applications
8.2.1 Transimpedance Amplifier
Wide gain bandwidth, low input bias current, low input voltage, and current noise make the OPAx320-Q1 an
excellent wideband photodiode transimpedance amplifier. Low-voltage noise is important because photodiode
capacitance causes the effective noise gain of the circuit to increase at high frequency.
The key elements to a transimpedance design, as shown in Figure 36, are the expected diode capacitance
(C(D)), which should include the parasitic input common-mode and differential-mode input capacitance (4 pF + 5
pF); the desired transimpedance gain (R(FB)); and the gain-bandwidth (GBW) for the OPAx320-Q1 (20 MHz).
With these three variables set, the feedback capacitor value (C(FB)) can be set to control the frequency response.
C(FB) includes the stray capacitance of R(FB), which is 0.2 pF for a typical surface-mount resistor.
(1)
C(F)
< 1 pF
R(F)
10 MΩ
V(V+)
l
VO
C(D)
OPA320-Q1
V(V–)
(1) C(FB) is optional to prevent gain peaking. C(FB) includes the stray capacitance of R(FB)
.
Figure 36. Dual-Supply Transimpedance Amplifier
8.2.1.1 Design Requirements
PARAMETER
VALUE
2.5 V
Supply voltage V(V+)
Supply voltage V(V–)
–2.5 V
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8.2.1.2 Detailed Design Procedure
To achieve a maximally-flat, second-order Butterworth frequency response, the feedback pole should be set to:
1
GBW
=
2 ´ p ´ R(FB) ´ C(FB)
4 ´ p ´ R(FB) ´ C(D)
(2)
Use Equation 3 to calculate the bandwidth.
GBW
ƒ(–3 dB)
=
2 ´ p ´ R(FB) ´ C(D)
(3)
For even higher transimpedance bandwidth, consider the high-speed CMOS OPA380 (90-MHz GBW), OPA354
(100-MHz GBW), OPA300 (180-MHz GBW), OPA355 (200-MHz GBW), and OPA656 or OPA657 (400-MHz
GBW).
For single-supply applications, the +INx input can be biased with a positive dc voltage to allow the output to
reach true zero when the photodiode is not exposed to any light, and respond without the added delay that
results from coming out of the negative rail; this configuration is shown in Figure 37. This bias voltage also
appears across the photodiode, providing a reverse bias for faster operation.
(1)
C(FB)
< 1pF
R(FB)
10 MΩ
V(V+)
l
VO
OPA320-Q1
+V(BIAS)
(1) C(FB) is optional to prevent gain peaking. C(FB) includes the stray capacitance of R(FB)
.
Figure 37. Single-Supply Transimpedance Amplifier
For additional information, refer to the Compensate Transimpedance Amplifiers Intuitively Application Report.
8.2.1.2.1 Optimizing The Transimpedance Circuit
To achieve the best performance, components should be selected according to the following guidelines:
1. For lowest noise, select R(FB) to create the total required gain. Using a lower value for R(FB) and adding gain
after the transimpedance amplifier generally produces poorer noise performance. The noise produced by
R(FB) increases with the square-root of R(FB), whereas the signal increases linearly. Therefore, signal-to-noise
ratio improves when all the required gain is placed in the transimpedance stage.
2. Minimize photodiode capacitance and stray capacitance at the summing junction (inverting input). This
capacitance causes the voltage noise of the op amp to be amplified (increasing amplification at high
frequency). Using a low-noise voltage source to reverse-bias a photodiode can significantly reduce the
capacitance. Smaller photodiodes have lower capacitance. Use optics to concentrate light on a small
photodiode.
3. Noise increases with increased bandwidth. Limit the circuit bandwidth to only that required. Use a capacitor
across the R(FB) to limit bandwidth, even if not required for stability.
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4. Circuit board leakage can degrade the performance of an otherwise well-designed amplifier. Clean the circuit
board carefully. A circuit board guard trace that encircles the summing junction and is driven at the same
voltage can help control leakage.
For additional information, refer to the following documents:
•
•
Texas Instruments, Noise Analysis of FET Transimpedance Amplifiers Application Bulletin
Texas Instruments, Noise Analysis for High-Speed Op Amps Application Report
8.2.1.3 Application Curves
Wide gain bandwidth as shown in Figure 38 and low input voltage noise as shown in Figure 39 make the
OPAx320-Q1 device an excellent wideband photodiode transimpedance amplifier.
160
140
120
100
80
0
1000
100
10
Phase
Gain
-20
-40
-60
-80
60
-100
-120
-140
-160
-180
40
20
0
-20
1
1
10
100
1k
10k 100k
1M
10M 100M
10
100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
VS = ±2.5 V, C(L) = 50 pF
Figure 38. Open-Loop Gain and Phase vs Frequency
VS = 1.8 to 5.5 V
Figure 39. Input Voltage Noise Spectral Density vs
Frequency
8.2.2 High-Impedance Sensor Interface
Many sensors have high source impedances that may range up to 10 MΩ, or even higher. The output signal of
sensors often must be amplified or otherwise conditioned by means of an amplifier. The input bias current of this
amplifier can load the sensor output and cause a voltage drop across the source resistance, as shown in
Figure 40, where (V(+INx) = VS – I(BIAS) × R(S)). The last term, I(BIAS) × R(S), shows the voltage drop across R(S). To
prevent errors introduced to the system as a result of this voltage, an op amp with very low input bias current
must be used with high impedance sensors. This low current keeps the error contribution by I(BIAS) × R(S) less
than the input voltage noise of the amplifier, so that it does not become the dominant noise factor. The
OPAx320-Q1 series of op amps feature very low input bias current (typically 200 fA), and are therefore excellent
choices for such applications.
R(S)
IIB
100 kΩ
V(+INx)
V(V+)
VO
R(F)
OPA320-Q1
V(V–)
R(G)
Figure 40. Noise as a Result of I(BIAS)
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8.2.3 Driving ADCs
The OPAx320-Q1 series op amps are an excellent choice for driving sampling analog-to-digital converters
(ADCs) with sampling speeds up to 1 MSPS. The zero-crossover distortion input stage topology allows the
OPAx320-Q1 to drive ADCs without degradation of differential linearity and THD.
The OPAx320-Q1 can be used to buffer the ADC switched input capacitance and resulting charge injection while
providing signal gain. Figure 42 shows the OPAx320-Q1 configured to drive the ADS8326.
5 V
50 kΩ
(2.5 V)
8
R(G)
REF1004-2.5
R1
100 kΩ
R2
25 kΩ
4
5 V
5 V
R3
25 kΩ
R4
100 kΩ
½
OPA2320-Q1
½
VO
OPA2320-Q1
R(L)
10 kΩ
200 kΩ
G = 5 +
R(G)
Figure 41. Two Op-Amp Instrumentation Amplifier With Improved High-Frequency Common-Mode
Rejection
5 V
C1
100 nF
5 V
R1(1)
100 Ω
V(V+)
+INx
OPA320-Q1
ADS8326
16-Bit
250kSPS
C3(1)
1 nF
V(V–)
–INx
VI
0 to 4.096 V
REF IN
Optional(2)
5 V
R2
50 kΩ
SD1
BAS40
REF3240
4.096V
–5 V
C2
100 nF
C4
100 nF
(1) Suggested value; may require adjustment based on specific application.
(2) Single-supply applications lose a small number of ADC codes near ground as a result of op amp output swing limitation. If a negative
power supply is available, this simple circuit creates a –0.3-V supply to allow output swing to true ground potential.
Figure 42. Driving the ADS8326
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8.2.4 Active Filter
The OPAx320-Q1 is an excellent choice for active filter applications that require a wide bandwidth, fast slew rate,
low-noise, single-supply operational amplifier. Figure 43 shows a 500 kHz, second-order, low-pass filter using the
multiple-feedback (MFB) topology. The components have been selected to provide a maximally-flat Butterworth
response. Beyond the cutoff frequency, roll-off is –40 dB/dec. The Butterworth response is excellent for
applications requiring predictable gain characteristics, such as the antialiasing filter used in front of an ADC.
One point to observe when considering the MFB filter is that the output is inverted, relative to the input. If this
inversion is not required, or not desired, a noninverting output can be achieved through one of the following
options:
1. adding an inverting amplifier
2. adding an additional second-order MFB stage
3. using a noninverting filter topology, such as the Sallen-Key
R3
549 Ω
C2
150 pF
V(V+)
R1
549 Ω
R2
1.24 kΩ
VI
VO
OPA320-Q1
C1
1 nF
V(V–)
Figure 43. Second-Order Butterworth 500-kHz Low-Pass Filter
220 pF
V(V+)
19.5 kΩ
150 kΩ
1.8 kΩ
VI = 1 VRMS
VO
OPA320-Q1
3.3 nF
47 pF
V(V–)
Figure 44. OPAx320-Q1 Configured as a Three-Pole, 20-kHz, Sallen-Key Filter
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9 Power Supply Recommendations
The OPAx320-Q1 are specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications apply
from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics section.
CAUTION
Supply voltages larger than 6 V can permanently damage the device (see the Absolute
Maximum Ratings table).
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-
impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
Guidelines section.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
•
Noise can propagate into analog circuitry through the power pins of the circuit as a whole and operational
amplifier itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance
power sources local to the analog circuitry.
–
Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
•
•
Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically
separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed
information, refer to the Circuit Board Layout Techniques Application Report.
To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace
perpendicular as opposed to in parallel with the noisy trace.
•
•
•
Place the external components as close to the device as possible. As shown in Figure 45, keeping RF
and RG close to the inverting input will minimize parasitic capacitance.
Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
22
版权 © 2014–2018, Texas Instruments Incorporated
OPA320-Q1, OPA2320-Q1
www.ti.com.cn
ZHCSCS6B –SEPTEMBER 2014–REVISED DECEMBER 2018
10.2 Layout Example
Run the input traces
as far away from
the supply lines
VS+
VIN
as possible.
VSœ
+IN
V+
GND
Use a low-ESR,
ceramic bypass
capacitor.
Vœ
Use a low-ESR,
ceramic bypass
capacitor.
RG
OUT
œIN
VOUT
GND
RF
Place components
close to the device
and to each other to
reduce parasitic
errors.
Copyright © 2016, Texas Instruments Incorporated
Figure 45. Operational Amplifier Board Layout for Noninverting Configuration
版权 © 2014–2018, Texas Instruments Incorporated
23
OPA320-Q1, OPA2320-Q1
ZHCSCS6B –SEPTEMBER 2014–REVISED DECEMBER 2018
www.ti.com.cn
11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
相关文档如下：
•
•
•
•
•
•
•
•
德州仪器 (TI)，《ADS8326 16 位、2.7V 至 5.5V 高速微功耗采样模数转换器产品说明书》
德州仪器 (TI)，《用直观方式补偿跨阻放大器的应用报告》
德州仪器 (TI)，《FET 跨阻放大器噪声分析应用简报》
德州仪器 (TI)，《高速运算放大器噪声分析应用报告》
德州仪器 (TI)，《OPAx380 精密高速跨阻放大器产品说明书》
德州仪器 (TI)，《OPAx354 250MHz 轨至轨 I/O CMOS 运算放大器产品说明书》
德州仪器 (TI)，《具有关断功能的 OPAx355 200MHz CMOS 运算放大器产品说明书》
德州仪器 (TI)，《OPA656 宽带单位增益稳定 FET 输入运算放大器产品说明书》
11.2 相关链接
表 1 列出了快速访问链接。类别包括技术文档、支持与社区资源、工具与软件，以及申请样片或购买产品的快速链
接。
表 1. 相关链接
器件
产品文件夹
请单击此处
请单击此处
样片与购买
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
OPA320-Q1
OPA2320-Q1
11.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
24
版权 © 2014–2018, Texas Instruments Incorporated
OPA320-Q1, OPA2320-Q1
www.ti.com.cn
ZHCSCS6B –SEPTEMBER 2014–REVISED DECEMBER 2018
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2014–2018, Texas Instruments Incorporated
25
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA2320AQDGKRQ1
OPA320AQDBVRQ1
OPA320AQDBVTQ1
ACTIVE
ACTIVE
ACTIVE
VSSOP
SOT-23
SOT-23
DGK
DBV
DBV
8
5
5
2500 RoHS & Green
3000 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
ZAEV
15DD
15DD
NIPDAU
NIPDAU
250
RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jul-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2320AQDGKRQ1
OPA320AQDBVRQ1
OPA320AQDBVTQ1
VSSOP
SOT-23
SOT-23
DGK
DBV
DBV
8
5
5
2500
3000
250
330.0
178.0
178.0
12.4
9.0
5.3
3.3
3.4
3.2
1.4
1.4
8.0
4.0
4.0
12.0
8.0
Q1
Q3
Q3
9.0
3.23
3.17
1.37
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Jul-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA2320AQDGKRQ1
OPA320AQDBVRQ1
OPA320AQDBVTQ1
VSSOP
SOT-23
SOT-23
DGK
DBV
DBV
8
5
5
2500
3000
250
366.0
180.0
180.0
364.0
180.0
180.0
50.0
18.0
18.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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