OPA569AIDWPRG4 [TI]
Power Op Amp, Output Signal Swings Within 200mV of Rails at 2A Output Current 20-SO PowerPAD -55 to 125;
| 型号： | OPA569AIDWPRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Power Op Amp, Output Signal Swings Within 200mV of Rails at 2A Output Current 20-SO PowerPAD -55 to 125 放大器 光电二极管 |
| 文件： | 总28页 (文件大小：1105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
OPA569
O
P
A
5
6
9
SBOS264A – DECEMBER 2002 – REVISED DECEMBER 2003
Rail-to-Rail I/O, 2A
POWER AMPLIFIER
DESCRIPTION
FEATURES
The OPA569 is a low-cost, high-current, operational amplifier
designed for driving a wide variety of loads while operating on
low-voltage supplies. It operates from either single or dual
supplies for design flexibility and has rail-to-rail swing on the
input and output. Typical output swing is within 150mV of the
supply rails, with output current of 2A. Output swing closer to
the rails is achievable with lighter loads.
● HIGH OUTPUT CURRENT: 2A
● OUTPUT SWINGS TO: 150mV of Rails with IO = 2A
● THERMAL PROTECTION
● ADJUSTABLE CURRENT LIMIT
● TWO FLAGS: Current Limit and Temperature
Warning
The OPA569 is unity-gain stable, has low dc errors, is easy
to use, and free from the phase inversion problems found in
some power amplifiers. High performance is maintained at
voltage swings near the output rails.
● LOW SUPPLY VOLTAGE OPERATION: 2.7V to 5.5V
● SHUTDOWN FUNCTION WITH OUTPUT DISABLE
● SMALL POWER PACKAGE: SO-20 PowerPAD™
The OPA569 provides an accurate user-selected current
limit that is set with an external resistor, or digitally adjusted
via a Digital-to-Analog Converter.
APPLICATIONS
● THERMOELECTRIC COOLER DRIVER
● LASER DIODE PUMP DRIVER
● VALVE, ACTUATOR DRIVER
● SYNCHRO, SERVO DRIVER
● TRANSDUCER EXCITATION
The OPA569 output can be independently disabled using the
Enable pin, saving power and protecting the load.
The IMONITOR pin provides a 1:475 bidirectional copy of the
output current. This eliminates the need for a series current
shunt resistor, allowing more voltage to be applied to the
load. This pin can be used for simple monitoring, or feedback
control to establish constant output current.
● GENERAL LINEAR POWER BOOSTER FOR
OP AMPS
Two flags are provided: one for warning of thermal over-
stress, and one for current limit condition. The Thermal Flag
pin can be connected to the Enable pin to provide a thermal
shutdown solution.
● PARALLELING OPTION FOR HIGHER
CURRENT APPLICATIONS
Current
Limit
Flag
Thermal
Flag
V+
12,13
Enable
Packaged in the Texas Instruments PowerPAD™ package,
it is small and easy to heat-sink. The OPA569 is specified for
operation over the industrial temperature range, –40°C to
+85°C.
(1)
7
5
–In
4
8
Parallel Out 1
VO
2
14, 15
OPA569
9
Parallel Out 2
19
6
3
+In
I = IO/475
Current
Limit
Set
17, 18
NOTE: (1) Connect
for thermal protection.
RSET
V–
IMONITOR
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2002-2003, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
Supply Voltage ................................................................................. +7.5V
Output Current ............................................................... See SOA Curves
Signal Input Terminals (pins 2, 5, 6, and 9):
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper han-
dling and installation procedures can cause damage.
Voltage(2) ............................................... (V–) – 0.5V to (V+) + 0.5V
Current(2) ................................................................................ ±10mA
Output Short-Circuit(3) ........ Continuous when thermal protection enabled
Current Monitor (pin 19) Short-Circuit..................................... Continuous
Enable Pin (pin 8) .......................................... (V–) – 0.5V to (V–) + 7.5V
PowerPAD (pins 1, 10, 11, 20, and pad) ...... (V–) – 0.5V to (V–) + 0.5V
Current Limit Set (pin 3)................................. (V–) – 0.5V to (V+) + 0.5V
Operating Temperature ..................................................–55°C to +125°C
Storage Temperature .....................................................–65°C to +150°C
Junction Temperature .................................................................... +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may de-
grade device reliability. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those specified is
not implied. (2) Input terminals are diode-clamped to the power-supply rails.
Input signals that can swing more than 0.5V beyond the supply rails should
be current limited to 10mA or less. (3) Short-circuit to ground.
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see
the Package Option Addendum located at the end of this
data sheet.
PIN CONFIGURATION
PIN DESCRIPTIONS
PIN #
1, 10, 11, 20
2
NAME
DESCRIPTION
Top View
SO
PowerPAD
Parallel Out 1
PowerPAD Connection Pins
Connection for Paralleling Multiple
Amplifiers
OPA569
3
4
Current Limit Set
Current Limit Flag
Current Limit Set Pin
Indicates When Part is in Current
Limit (Active LOW).
PowerPAD(1)
1
2
3
4
5
6
7
8
9
20 PowerPAD(1)
19 IMONITOR
18 V–(3)
5
6
7
–In
+In
Inverting Input
Parallel Out 1
Current Limit Set
Current Limit Flag
–In
Noninverting Input
Thermal Flag
Indicates Thermal Stress (Active
LOW)
17 V–(3)
Metal
PowerPAD
Heat Sink
(Located
on
8
9
Enable
Enabled HIGH. Shut down LOW.
16 NC(2)
Parallel Out 2
Connection for Paralleling Multiple
Amplifiers
(3)
+In
15 VO
12, 13
14, 15
16
V+
VO
Positive Power-Supply Voltage
Output
bottom
side)
(3)
Thermal Flag
Enable
14 VO
13 V+(3)
NC
No Internal Connection
Negative Power-Supply Voltage
17, 18
19
V–
Parallel Out 2
12 V+(3)
IMONITOR
Provides 1:475 Bidirectional Copy
of Output Current.
PowerPAD(1) 10
11 PowerPAD(1)
NOTES: (1) PowerPAD pins 1, 10, 11, and 20 and the
PowerPAD should be connected to the most negative
supply (V–) in either single or split supply configurations.
(2) NC means no internal connection.
(3) The following pin pairs must be connected together:
12 and 13; 14 and 15; 17 and 18.
OPA569
SBOS264A
2
www.ti.com
ELECTRICAL CHARACTERISTICS: VS = +2.7V to +5.5V
Boldface limits apply over the specified temperature range, TA = –40°C to +85°C.
At TCASE = +25°C, RL = 1kΩ, and connected to VS/2, unless otherwise noted.
OPA569
PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
OFFSET VOLTAGE
Input Offset Voltage
vs Temperature
vs Power Supply
VOS
dVOS /dT
IO = 0V, VS = +5V
TA = –40°C to +85°C
±0.5
±1.3
12
±2
mV
µV/°C
µV/V
PSRR VS = +2.7V to +5.5V, VCM = (V–) +0.55V
60
INPUT BIAS CURRENT
Input Bias Current
vs Temperature
IB
±1
±10
±10
pA
pA
(doubles every 10°C)
±2
Input Offset Current
IOS
NOISE
Input Voltage Noise Density, f = 1kHz
f = 0.1Hz to 10Hz
Current Noise Density, f = 1kHz
en
in
12
8
0.6
nV/√Hz
µVp-p
fA/√Hz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range
Common-Mode Rejection Ratio
VCM
CMRR
Linear Operation
VS = +5V, –0.1V < VCM < 3.2V
VS = +5V, –0.1V < VCM < 5.1V
(V–) – 0.1
(V+) + 0.1
V
dB
dB
80
60
100
80
INPUT IMPEDANCE
Differential
Common-Mode
1013 || 4.5
1013 || 9
Ω || pF
Ω || pF
OPEN-LOOP GAIN
Open-Loop Voltage Gain
AOL
0.2V< VO < 4.8V, RL = 1kΩ, VS = +5V
0.3V< VO < 4.7V, RL = 1.15Ω, VS = +5V
100
126
90
dB
dB
FREQUENCY RESPONSE
Gain Bandwidth Product
Slew Rate
GBW
SR
1.2
1.2
MHz
V/µs
G = +1, VO = 4.0V Step
Full-Power Bandwidth(1)
Settling Time: ±0.1%
See Typical Characteristics
5
See Typical Characteristics
G = –1, VO = 4.0V Step
µs
Total Harmonic Distortion + Noise(2)
THD+N
VO
OUTPUT
Voltage Output Swing from Rail
RL = 1kΩ, AOL > 100dB
IO = ±2A, VS = +5V, AOL > 80dB(3)
(V–) + 0.2
(V–) + 0.3
(VS) ± 0.02
(VS) ± 0.15
(V+) – 0.2
(V+) – 0.3
2.4
V
V
A
Maximum Continuous Current Output: dc(4)
Capacitive Load Drive(5)
Output Disabled
CLOAD
See Typical Characteristics
12M || 570
Output Impedance
Ω || pF
CURRENT LIMIT
Output Current Limit(6)
Current Limit Equation
RSET Equation
Externally Adjustable
±0.2 to ±2.2
ILIMIT = ISET • 9800
RSET = 9800 (1.18V/ILIMIT
A
A
Ω
%
%
V
)
Current Limit Tolerance(7), Positive
Negative
ILIMIT = 1A
ILIMIT = 1A
±3
±3
±10
±15
(V–) + 1.3
Voltage on Current Limit Set Pin Tolerance(8)
(V–) + 1.05
(V–) + 1.18
OUTPUT CURRENT MONITOR (Pin 19)
Output Current Monitor
IM
IM = IO /475
A
%
%
Output Current Monitor Tolerance(9), Positive
Negative
IO = +1A, RMONITOR = 400Ω
IO = –1A, RMONITOR = 400Ω
Linear Operation
±3
±3
±10
±15
Compliance Voltage Range
See Discussion on Current Monitor Section
NOTES: (1) See typical characteristic “Maximum Output Voltage vs Frequency.” (2) See the typical characteristic “Total Harmonic Distortion + Noise vs Frequency.”
(3) Swing to the rail is measured in final test. Under those conditions, the AOL is derived from characterization. (4) See Safe Operating Area (SOA) plots. (5) See typical
characteristic, “Overshoot vs Load Capacitance.” (6) External current limit setting resistor is required. See Figure 1. (7) ILIMIT is the value of the desired current limit
and is equal to 9800 (ISET), where ISET is the current through the Current Limit Set pin (pin 3). Errors from this parameter can be calibrated out—see Applications
Information section. (8) VSET is a voltage reference that equals the difference between the voltage of the Current Limit Set pin and V–, and is referenced to the negative
rail. Errors from this parameter can be calibrated out—see Applications Information section. (9) % Tolerance = [(IOUT/475) – IMONITOR] • 100/IMONITOR
.
OPA569
SBOS264A
3
www.ti.com
ELECTRICAL CHARACTERISTICS: VS = +2.7V to +5.5V (Cont.)
Boldface limits apply over the specified temperature range, TA = –40°C to +85°C.
At TCASE = +25°C, RL = 1kΩ, and connected to VS/2, unless otherwise noted.
OPA569
PARAMETER
CONDITION
MIN
TYP
MAX
UNITS
ENABLE/SHUTDOWN INPUT (Pin 8)
Enable Pin Bias Current
HIGH (Output enabled)
LOW (Output disabled)
Output Disable Time
VSD = 0V
Pin Open or Forced HIGH
Pin Forced LOW
RL = 1Ω
0.2
µA
V
V
µs
µs
VSD
VSD
(V–) + 2.5
(V–) + 0.8
0.5
15
Output Enable Time
RL = 1Ω
THERMAL FLAG PIN (Pin 7)
Junction Temperature:
TJ
Alarm (Thermal Flag pin LOW)
Return to Normal Operation (Thermal Flag pin HIGH)
Thermal Flag Pin Voltage
Thermal Overstress
Normal Operation
Normal Operation Ipin 7 = +25µA
During Thermal Overstress, Ipin 7 = –25µA
+147
+130
V+
°C
°C
V
(V+) – 0.8V
(V+) – 0.8V
V–
(V–) + 0.8
(V–) + 0.8
V
CURRENT LIMIT FLAG PIN (Pin 4)
Current Limit Flag Pin Voltage
Normal Operation, Ipin 4 = +25µA
During Current Limit, Ipin 4 = –25µA
V+
V–
V
V
POWER SUPPLY
Specified Voltage Range
Operating Voltage Range
Quiescent Current(10)
VS
IQ
+2.7
+2.7
+5.5
+5.5
+6
V
V
mA
mA
mA
IO = 0, ILIMIT = 200mA, VS = 5V
IO = 0, ILIMIT = 2A, VS = 5V
IO = 0, VSD = 0.8V, VS = 5V
+3.4
+9
+0.01
+11
Quiescent Current in Shutdown Mode
TEMPERATURE RANGE
Specified Range
Operating Range
Junction Temperature
Junction Temperature
–40
–55
–65
+85
+125
+150
°C
°C
°C
Storage Range
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
θJC
θJA
0.37
21.5
°C/W
°C/W
2oz Trace and 9in2 Copper Pad
with Solder
NOTE: (10) Quiescent current is a function of the current limit setting. See application section, “Adjustable Current Limit and Current Limit Flag Pin.”
OPA569
SBOS264A
4
www.ti.com
TYPICAL CHARACTERISTICS
At TA = +25°C, VS = +5V, unless otherwise noted.
POWER-SUPPLY AND COMMON-MODE
REJECTION RATIO vs FREQUENCY
OPEN-LOOP GAIN AND PHASE vs FREQUENCY
180
0
120
100
80
60
40
20
0
160
140
120
100
80
–20
CMRR
–40
–60
–80
–100
–120
–140
–160
–180
–200
PSRR
60
40
20
0
–20
1
10
100
1k
10k
100k
0.1
1
10
100
1k
10k 100k
1M
10M
Frequency (Hz)
Frequency (Hz)
OUTPUT SWING TO POSITIVE RAIL
vs SUPPLY VOLTAGE
OUTPUT SWING TO NEGATIVE RAIL
vs SUPPLY VOLTAGE
300
250
200
150
100
50
300
250
200
150
100
50
IOUT = –2A
IOUT = 2A
I
OUT = –1A
I
OUT = 1A
IOUT = 200mA
IOUT = –200mA
0
0
2.7 3.0
3.5
4.0
4.5
5.0
5.5
2.7 3.0
3.5
4.0
4.5
5.0
5.5
Supply Voltage (V)
Supply Voltage (V)
OUTPUT SWING TO POSITIVE RAIL
vs TEMPERATURE
OUTPUT SWING TO NEGATIVE RAIL
vs TEMPERATURE
300
250
200
150
100
50
300
250
200
150
100
50
VS = 2.7V, IO = 2A
VS = 5V, IO = 2A
VS = 2.7V, IO = 2A
VS = 5V, IO = 2A
VS = 5V, IO = 1A
VS = 2.7V, IO = 1A
VS = 2.7V, IO = 1A
VS = 5V, IO = 1A
VS = 2.7V, IO = 200mA
VS = 5V, IO = 200mA
VS = 5V, IO = 200mA
VS = 2.7V, IO = 200mA
0
0
–55
–35
–15
5
25
45
65
85
–55
–35
–15
5
25
45
65
85
Temperature (°C)
Temperature (°C)
OPA569
SBOS264A
5
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, unless otherwise noted.
INPUT VOLTAGE NOISE SPECTRAL DENSITY
vs FREQUENCY
1000
0.1Hz TO 10Hz INPUT VOLTAGE NOISE
100
10
1
1s/div
10
100
1k
10k
100k
Frequency (Hz)
TOTAL HARMONIC DISTORTION+NOISE
vs FREQUENCY
MAXIMUM OUTPUT VOLTAGE vs FREQUENCY
10
1
6
5
4
3
2
1
0
VS = 5V
RL = 1kΩ
RL = 2Ω
RL = 8Ω
RL = 1kΩ
RL = 1Ω
0.1
RL = 1kΩ
0.01
0.001
VS = 2.7V
RL = 1Ω
100
1k
10k
Frequency (Hz)
100k
1M
20
100
1k
10k 20k
Frequency (Hz)
QUIESCENT CURRENT vs SUPPLY VOLTAGE
Current Limit = 2A
QUIESCENT CURRENT vs TEMPERATURE
10
8
10
8
IQ (ILIMIT = 2A)
Current Limit = 1A
6
6
Current Limit = 200mA
4
4
IQ (ILIMIT = 200mA)
2
2
0
0
2.7
3
3.5
4
4.5
5
5.5
–55 –35 –15
5
25
45
65
85
105 125
Supply Voltage (V)
Temperature (°C)
OPA569
SBOS264A
6
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, unless otherwise noted.
SHUTDOWN CURRENT vs TEMPERATURE
SHUTDOWN CURRENT vs SUPPLY VOLTAGE
12
12
10
8
10
8
ILIMIT = 200mA, 1A, and 2A
6
4
2
0
6
4
2
0
2.7
3
3.5
4
4.5
5
5.5
–55 –35 –15
5
25
45
65
85
105 125
Temperature (°C)
Supply Voltage (V)
INPUT BIAS CURRENT vs TEMPERATURE
QUIESCENT CURRENT vs CURRENT LIMIT SETTING
10
8
10000
1000
100
10
6
4
1
2
0.1
0
0.01
0
0.5
1
1.5
2
2.5
–55 –35 –15
5
25
45
65
85
105 125
Current Limit Setting (A)
Temperature (°C)
SLEW RATE vs LOAD RESISTANCE
SLEW RATE vs TEMPERATURE
2
2
1.8
1.6
1.4
1.2
1
SR+
1.8
1.6
1.4
1.2
1
SR–
SR–
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
SR+
1
10
100
1000
–55 –35 –15
5
25
45
65
85
105 125
Load Resistance (Ω)
Temperature (°C)
OPA569
SBOS264A
7
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, unless otherwise noted.
VOLTAGE ON CURRENT LIMIT SET PIN
vs TEMPERATURE
1.2
VOLTAGE ON CURRENT LIMIT SET PIN
vs SUPPLY VOLTAGE
1.25
1.2
Current Limit = 200mA
1.19
1.18
1.17
1.16
Current Limit = 1A
Current Limit = 2A
1.15
1.1
1.05
–55 –35 –15
5
25
45
65
85
105 125
2.7
3
3.5
4
4.5
5
5.5
Temperature (°C)
Supply Voltage (V)
OFFSET VOLTAGE
PRODUCTION DISTRIBUTION
OFFSET VOLTAGE DRIFT
PRODUCTION DISTRIBUTION
Typical Production
Distribution of
Typical Production
Distribution of
Packaged Units.
Packaged Units.
Offset Voltage (mV)
Drift (µV/°C)
SMALL-SIGNAL STEP RESPONSE
LARGE-SIGNAL STEP RESPONSE
(G = +1, RL = 1kΩ)
(G = +1, RL = 1kΩ)
10µs/div
20µs/div
OPA569
SBOS264A
8
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, unless otherwise noted.
SMALL-SIGNAL STEP RESPONSE
LARGE-SIGNAL STEP RESPONSE
(G = +1, RL = 10Ω)
(G = +1, RL = 10Ω)
10µs/div
20µs/div
LARGE-SIGNAL STEP RESPONSE
SMALL-SIGNAL STEP RESPONSE
(G = +1, RL = 1Ω)
(G = +1, RL = 1Ω)
20µs/div
20µs/div
ENABLE
ENABLE
(10Ω Load)
(1Ω Load)
Enable/Disable 0.8 to 2.5V
Above Negative Supply
Enable/Disable 0.8 to 2.5V
Above Negative Supply
Output Driven to +2V
Output Driven to +2V
4µs/div
10µs/div
OPA569
SBOS264A
9
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, unless otherwise noted.
DISABLE
DISABLE
(10Ω Load)
(1Ω Load)
Enable/Disable 0.8 to 2.5V
Above Negative Supply
Enable/Disable 0.8 to 2.5V
Above Negative Supply
Output Driven
to +2V
Output Driven to +2V
200ns/div
200ns/div
POWER ON
POWER OFF
(1Ω Load)
(1Ω Load)
Supply 5V to 0V
Supply 0V to 5V
Output Driven to +2V
Output Driven to +2V
1ms/div
1ms/div
IN AND OUT OF CURRENT LIMIT TRANSIENT
IN AND OUT OF CURRENT LIMIT TRANSIENT
(RL = 0.75Ω, Current Limit = 2A)
(RL = 7.5Ω, Current Limit = 200mA)
200µs/div
200µs/div
OPA569
SBOS264A
10
www.ti.com
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, unless otherwise noted.
NO PHASE INVERSION WITH INPUTS
LARGER THAN SUPPLY VOLTAGE
(G = +1, RL = 10Ω)
OVERLOAD RECOVERY
(G = +1)
VIN
VOUT
VOUT
VIN
40µs/div
1ms/div
CURRENT MONITOR AND CURRENT LIMIT ERROR
vs SUPPLY VOLTAGE
15
CURRENT MONITOR AND CURRENT
LIMIT ERROR vs TEMPERATURE
15
10
5
10
IMONITOR
+
IMONITOR
–
ILIMIT
–
ILIMIT
+
5
0
0
IMONITOR
–
ILIMIT+
IMONITOR
+
ILIMIT–
–5
–5
–10
–15
–10
–15
2.7
3
3.5
4
4.5
5
5.5
–55
–35
–15
5
25
45
65
85
Supply Voltage (V)
Temperature (°C)
CURRENT MONITOR AND CURRENT LIMIT ERROR
vs OUTPUT CURRENT
OVERSHOOT vs LOAD CAPACITANCE
(G = +1, RL = 1kΩ)
15
10
5
50
40
30
20
10
0
ILIMIT
–
IMONITOR
–
0
IMONITOR
+
ILIMIT
+
–5
–10
–15
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
10
100
1k
10k
Output Current (A)
Load Capacitance (pF)
OPA569
SBOS264A
11
www.ti.com
R1
R2
APPLICATIONS INFORMATION
BASIC CONFIGURATION
V+
47µF
0.1µF
Figure 1 shows the OPA569 connected as a basic non-
inverting amplifier; however, the OPA569 can be used in
virtually any op amp configuration. A current limit setting
resistor (RSET, in Figure 1) is essential to the OPA569’s
operation, and cannot be omitted.
12,
13
5
6
14,
15
Power-supply terminals should be bypassed with low series
impedance capacitors. Using a larger tantalum and smaller
ceramic type in parallel is recommended. Power-supply
wiring should have low series impedance.
OPA569
VO
3
VIN
19
IMONITOR
17,
18
47µF
Current
Limit Set
8
(1)
RSET
Enable(2)
POWER SUPPLIES
RSET (Ω)
ILIMIT (A)
0.1µF
The OPA569 operates with excellent performance from a
single (+2.7V to +5.5V) supply or from dual supplies. Power
supply voltages do not need to be equal as long as the total
voltage remains below 5.5V. Parameters that vary signifi-
cantly with operating voltage are shown in the typical charac-
teristics section.
23.2k
11.5k
7.68k
5.76k
0.5
1.0
1.5
2.0
47µF
NOTES: (1) RSET sets the current
limit value from 0.2A to 2.2A.
R
SET can be a potentiometer to
V–
easily adjust current limit and
calibrate out errors at the current
limit node. (2) Enable—pull LOW
to disable output.
ADJUSTABLE CURRENT LIMIT AND CURRENT
LIMIT FLAG PIN
FIGURE 1. Basic Connections.
The OPA569 provides over-current protection to the load
through its accurate, user-adjustable current limit (pin 3). The
current limit value, ILIMIT, can be set from 0.2A to 2.2A by
controlling the current through the Current Limit Set pin. The
current limit, ILIMIT, will be 9800 ISET; where ISET is the current
through the Current Limit Set pin. Setting the current limit
requires no special power resistors. The output current does
not flow through this pin.
the current limit set pin and V–, the negative supply, accord-
ing to the formula:
ILIMIT = 9800 • (1.18V/RSET
)
Alternatively, the output current limit can be set by applying
a voltage source in series with a resistance using the equa-
tion:
Setting the current limit
ILIMIT = 9800 • [(1.18V – VADJUST)/RSET
]
As illustrated in Figure 2, the simplest method of setting the
current limit is to connect a resistor or potentiometer between
The voltage source will be referenced to V–.
5
5
14,
15
14,
15
1.18V
1.18V
6
6
ILIMIT = 9800 (1.18V/RSET
)
ILIMIT = 9800 (1.18V – VADJUST)
3
3
RSET
RSET
VADJUST
17,
18
17,
18
(1)
RPOT
V–
V–
(a) Resistor or Potentiometer Method
(b) Resistor/Voltage Source Method
NOTE: (1) This voltage source must be able to
sink the current from the Current Limit Set pin,
which is ILIMIT/9800.
Putting a set resistor in series with the potentiometer
will prevent potential short-circuit on pin.
FIGURE 2. Setting the Current Limit—Resistor Method.
OPA569
SBOS264A
12
www.ti.com
Current Limit Accuracy
CURRENT MONITOR
Internally separate circuits monitor the positive and negative
current limits. Each circuit output is compared to a single
internal reference that is set by the user with an external
resistor or a resistor/voltage source combination. The OPA569
employs a patented circuit technique to achieve an accurate
and stable current limit throughout the full output range. The
initial accuracy of the current limit is typically within 3%;
however, due to internal matching limitations, the error can
be as much as 15%. The variation of the current limit with
factors such as output current level, output voltage and
temperature is shown in the Typical Characteristics section.
The OPA569 features an accurate output current monitor
(IMONITOR) without requiring the use of series resistance with
the load. This increases efficiency significantly and provides
better overall swing-to-supply performance.
An internal circuit creates a 1:475 copy of the output current.
This copy of the output current can be monitored indepen-
dently or it can be used in applications such as current
control drive, setting non-symmetric positive and negative
current limits or paralleling two or more devices for increased
output current drive. When not being used, the Current
Monitor pin may be left floating.
When the accuracy of one current limit (sourcing or sinking)
is more important than the other, it is possible to set its
accuracy to better than 1% by adjusting the external resistor
or the applied voltage. The accuracy of the other current limit
will still be affected by internal matching.
Some restrictions apply when using the current monitor
function. When the main amplifier is sourcing current, the
current monitor circuit must be sourcing current. Likewise,
when the main amplifier is sinking current, the current moni-
tor circuit must also be sinking current. Additionally, the
swing on the IMONITOR pin is smaller than the output swing.
When the amplifier is sourcing current, the voltage of the
Current Monitor pin must be at least two hundred millivolts
less than the output voltage of the amplifier. Conversely,
when the amplifier is sinking current, the voltage of the
Current Monitor pin must be at least two hundred millivolts
greater than the output voltage of the amplifier. Resistive
loads are able to meet these restrictions. Other types of
loads may cause invalid current monitor values.
Current Limit Flag Pin
The OPA569 features a Current Limit Flag pin (pin 4) that
can be monitored to determine when the part is in current
limit. The output signal of the current limit flag pin is compat-
ible to standard logic in single supply applications. The
output signal is a CMOS logic gate that switches from V+ to
V– to indicate that the amplifier is in current limit. This flag
output pin can source and sink up to 25µA. Additional
parasitic capacitance between pins 3 and 4 can cause
instability at the edge of the current limit. Avoid routing these
traces in parallel close to each other.
A simple way to monitor the load current and meet these
requirements is to connect a resistor (with resistance less
than 400 • RL) from the IMONITOR pin to the same potential to
which the other side of the load is connected. Another
method is to use a transimpedance amplifier, as shown in
Figure 4. This circuit must assure that the potential of the
Quiescent Current Dependence on the
Current Limit Setting
The OPA569 is a low power amplifier, with a typical 3.4mA
quiescent current (with the current limit configured for 200mA).
The quiescent current varies with the current limit setting—
it increases 0.5mA for each additional 200mA increase in
the current limit, as shown in Figure 3.
I
MONITOR pin remains in the valid voltage range by connecting
it to the same potential to which the load is connected—most
likely ground for dual supply or mid-supply for single-supply
applications.
+2.5V
QUIESCENT CURRENT vs CURRENT LIMIT SETTING
10
12,
13
5
–In
14,
15
IO
8
6
4
2
0
VO
OPA569
6
+In
RL
19
IMONITOR
17,
18
–2.5V
VO = –1V
at IO = 1A
OPA348
IO/475
R = 475Ω
0
0.5
1
1.5
2
2.5
Current Limit Setting (A)
C
FIGURE 3. Quiescent Current vs Current Limit Setting.
FIGURE 4. Transimpedance Amplifier to Monitor Load
Current.
OPA569
SBOS264A
13
www.ti.com
The accuracy of the current copy is reduced with small output
currents. An internal circuit monitors the direction of the
output current and enables the positive or the negative
current monitoring circuitry accordingly. There is an approxi-
mate 20µs delay in the change of current direction. The
switching point is near quiescent conditions and may cause
current monitor inaccuracy with small output currents.
V+
(b) HCT or TTL In
(a) +5V
12,
13
5
6
14,
15
OPA569
VO
Enable
8
(1)
17,
18
ENABLE PIN—OUTPUT DISABLE
The Enable pin can disable the OPA569 within microsec-
onds. When disabled, the amplifier draws less than 10µA and
its output enters a high-impedance state that allows multi-
plexing. It is important to note that when the amplifier is
disabled, the Thermal Flag pin circuitry continues to operate.
This feature allows use of the Thermal Flag pin output to
implement thermal protection strategies. For more details,
please see the section on thermal protection.
4N38
Optocoupler
V–
NOTE: (1) Optional—may be required
to limit leakage current of optocoupler
at high temperatures.
(a) HCT or
TTL In
(b)
FIGURE 5. OPA569 Shutdown Configuration for Dual
Supplies.
The OPA569 Enable pin has an internal pull-up circuit, so it
does not have to be connected to the positive supply for
normal operation. To disable the amplifier, the Enable pin
must be connected to no more than (V–) + 0.8V. To enable
the amplifier, either allow the Enable pin to float or connect
it to at least (V–) + 2.5V.
ENSURING MICROCONTROLLER COMPATIBILITY
Not all microcontrollers output the same logic state after
power-up or reset. 8051-type microcontrollers, for example,
output logic HIGH levels on their ports while other models
power up with logic LOW levels after reset.
The Enable pin is referenced to the negative supply (V–).
Therefore, shutdown operation is slightly different in single-
supply and dual-supply applications.
In configuration (a) shown in Figure 5, the enable/disable
signal is applied on the cathode side of the photodiode within
the optocoupler. A logic HIGH level causes the OPA569 to
be enabled, and a logic LOW level disables the OPA569. In
configuration (b) of Figure 5, with the logic signal applied on
the anode side, a high level disables the OPA569 and a low
level enables the op amp.
In single-supply operation, V– typically equals common
ground, thus the enable/disable logic signal and the OPA569
Enable pin are referenced to the same potential. In this
configuration, the logic level and the OPA569 Enable pin can
simply be tied together. Disable occurs for voltage levels of
less than 0.8V. The OPA569 is enabled at logic levels
greater than 2.5V.
RAIL TO RAIL OUTPUT RANGE
In dual-supply operation, the logic level is referenced to a
logic ground. However, the OPA569 Enable pin is still refer-
enced to V–. To disable the OPA569, the voltage level of the
logic signal needs to be level-shifted. This can be done using
an optocoupler, as shown in Figure 5.
The OPA569 has a class AB output stage with common
source transistors that are used to achieve rail-to-rail output
swing. It was designed to be able to swing closer to the rail
than other existing linear amplifiers, even with high output
current levels. A quick way to estimate the output swing with
various output current requirements is by using the equation:
Examples of output behavior during disabled and enabled
conditions with various load impedances are shown in the
typical characteristics section. Please note that this behavior
is a function of board layout, load impedances and bypass
strategies. For sensitive loads, the use of a low-pass filter or
other protection strategy is recommended.
VSWING [typical] = 0.1 • IO
Plots of the Output Swing vs Output Current, Supply Voltage,
and Temperature are provided in the typical characteristics
section.
OPA569
SBOS264A
14
www.ti.com
RAIL TO RAIL INPUT RANGE
though the junction temperature exceeds 150°C. This allows
maximum usable operation in very harsh conditions but
degrades reliability. The Thermal Flag pin can be used to
provide for orderly system shutdown before failure occurs. It
can be also used to evaluate the thermal environment to
determine need for and appropriate design of a shutdown
mechanism.
The input common-mode voltage range of the OPA569
extends 100mV beyond the supply rails. This is achieved by
a complementary input stage with an N-channel input differ-
ential pair in parallel with a P-channel differential pair. The
N-channel input pair is active for input voltages close to the
positive rail while the P-channel input pair is active for input
voltages close to the negative rail. The transition point is
typically at (V+) – 1.3V, and there is a small transition region
around the switching point where both transistors are on. It
is important to note that the two input pairs can have offsets
of different signs and magnitudes. Therefore, as the transi-
tion point is crossed, the offset of the amplifier changes. This
offset shift accounts for the reduced common-mode rejection
ratio over the full input common-mode range.
The thermal flag output signal is from a CMOS logic gate that
switches from V+ to V– to indicate that the amplifier is in
thermal limit. This flag output pin can source and sink up to
25µA. The Thermal Flag pin is HIGH during normal opera-
tion. Power dissipated in the amplifier will cause the junction
temperature to rise. When the junction temperature exceeds
150°C, the Thermal Flag pin will go LOW, and remain LOW
until the amplifier has cooled to 130°C. Despite this hyster-
esis, with a method of orderly shutdown, the Thermal Flag
pin can cycle on and off, depending on load and signal
conditions. This limits the dissipation of the amplifier but may
have an undesirable effect on the load. This temperature
range exceeds the absolute maximum temperature rating
and is intended to protect the device from excessive tem-
peratures that can cause damage. Brief and infrequent
excursions in this temperature range are likely to be toler-
ated, but are not recommended.
OUTPUT PROTECTION
Reactive and EMF-generating loads can return load current
to the amplifier, causing the output voltage to exceed the
power-supply voltage. This damaging condition can be
avoided with clamp diodes from the output terminal to the
power supplies, as shown in Figure 6. Schottky rectifier
diodes with a 3A or greater continuous rating are recom-
mended.
It is possible to connect the Thermal Flag pin directly to the
Enable pin for automatic shutdown protection. When both
thermal shutdown and the amplifier enable/disable functions
are desired, the externally generated control signal and the
Thermal Flag pin outputs should be combined with an AND
gate, as shown on Figure 7. The temperature protection was
designed to protect against overload conditions. It was not
intended to replace proper heatsinking. Continuously running
the OPA569 in and out of thermal shutdown will degrade
reliability.
THERMAL FLAG PIN
The OPA569 has thermal sensing circuitry that provides a
warning signal when the die temperature exceeds safe limits.
Unless the Thermal Flag is connected to the Enable pin,
when this flag is triggered, the part continues to operate even
+V
12,
13
On
Output Protection Diode
–In
14,
15
Disable
AND
VO
OPA569
+In
Current
Limit
Set
3
Thermal
17,
18
Flag Pin
Output Protection Diode
Enable Pin
7
RSET
8
5
14,
15
OPA569
6
–V
FIGURE 7. Enable/Shutdown Control Using Thermal Flag Pin
and External Control Signal.
FIGURE 6. Output Protection Diode.
OPA569
SBOS264A
15
www.ti.com
Any tendency to activate the thermal protection circuit indi-
cates excessive power dissipation or an inadequate heat
sink. For reliable, long term, continuous operation, the junc-
tion temperature should be limited to 125°C maximum. To
estimate the margin of safety in a complete design (including
heat sink), increase the ambient temperature until the ther-
mal protection is triggered. Use worst-case loading and
signal conditions. For good, long-term reliability, thermal
protection should trigger more than 25°C above the maxi-
mum expected ambient conditions of your application. This
produces a junction temperature of 125°C at the maximum
expected ambient condition.
SAFE OPERATING AREA AT ROOM TEMPERATURE
Current is limited by the
10
Copper—soldered,
maximum output current.
with 500lfm airflow.
Copper—soldered,
with 250lfm airflow.
1
Copper—soldered,
Copper—soldered,
Fast transients of large output current swings (for example
switching quickly from sourcing 2A to sinking 2A) may cause
a glitch on the Thermal Flag pin. When switching large
currents is expected, the use of extra bypass between the
supplies or a low-pass filter on the Thermal Flag pin is
recommended.
without forced air.
with 150lfm airflow.
0.1
0
1
2
3
4
5
6
VS – VOUT (V)
FIGURE 8. Safe Operating Area at Room Temperature.
POWER DISSIPATION AND
SAFE OPERATING AREA
Power dissipation depends on power supply, signal and load
conditions. It is dominated by the power dissipation of the
output transistors. For DC signals, power dissipation is equal
to the product of output current, IOUT and the output voltage
across the conducting output transistor (VS-VOUT). Dissipa-
tion with AC signals is lower. Application Bulletin AB-039
(SBOA022) explains how to calculate or measure power
dissipation with unusual signals and loads and can be found
at the TI web site (www.ti.com).
SAFE OPERATING AREA AT VARIOUS
AMBIENT TEMPERATURES
10
Current is limited by
the maximum output
current.
TA = 0°C
TA = –40°C
1
Output short-circuits are particularly demanding for the am-
plifier because the full supply voltage is seen across the
conducting transistor. It is very important to note that the
temperature protection will not shut the part down in over-
temperature conditions, unless the Thermal Flag pin is con-
nected to the Enable pin; see the section on Thermal Flag.
TA = +125°C
TA = +85°C
TA = +25°C
0.1
0
1
2
3
4
5
6
VS – VOUT (V)
Figure 8 shows the safe operating area at room temperature
with various heatsinking efforts. Note that the safe output
current decreases as (VS – VOUT) increases. Figure 9 shows
the safe operating area at various temperatures with the
PowerPAD being soldered to a 2 oz copper pad.
FIGURE 9. Safe Operating Area at Various Ambient Tempera-
tures. PowerPAD soldered to a 2oz copper pad.
The power that can be safely dissipated in the package is
related to the ambient temperature and the heatsink design.
The PowerPAD package was specifically designed to pro-
vide excellent power dissipation, but board layout greatly
influences the heat dissipation of the package. Refer to
the “PowerPAD Thermally Enhanced Package” section for
further details.
HEATSINKING METHOD
θJA
The part is soldered to a 2 oz copper pad under the
exposed pad.
21.6
Soldered to copper pad with forced airflow (150lfm).
Soldered to copper pad with forced airflow (250lfm).
Soldered to copper pad with forced airflow (500lfm).
15.1
13.2
12.0
The OPA569 has a junction-to-ambient thermal resistance
(θJA) value of 21.6°C/W when soldered to 2oz copper plane.
This value can be further decreased to 12°C/W by the
addition of forced air. Figure 10 shows the junction-to-
ambient thermal resistance of the DWP-20 package.
FIGURE 10. Junction-to-Ambient Thermal Resistance with
Various Heatsinking Efforts.
OPA569
SBOS264A
16
www.ti.com
Junction temperature should be kept below 125°C for reliable
operation. The junction temperature can be calculated by:
THERMAL RESISTANCE vs COPPER AREA
35
30
25
20
15
10
TJ = TA + PDθJA
where θJA = θJC + θCA
TJ = Junction Temperature (°C)
TA = Ambient Temperature (°C)
PD = Power Dissipated (W)
θJA = Junction-to-Ambient Thermal Resistance
θJC = Junction-to-Case Thermal Resistance
θCA = Case-to-Air Thermal Resistance
OPA569
Surface-Mount Package
The Maximum Power Dissipation vs Temperature for the
heatsinking methods listed in Figure 10 is shown in Figure 11.
0
1
2
3
4
5
Copper Area (inches2)
To appropriately determine required heatsink area, required
power dissipation should be calculated and the relationship
between power dissipation and thermal resistance should be
considered to minimize shutdown conditions and allow for
proper long-term operation (junction temperature of 125°C).
Once the heatsink area has been selected, worst-case load
conditions should be tested to ensure proper thermal protec-
tion.
FIGURE 12. Thermal Resistance vs Circuit Board Copper
Area.
FEEDBACK CAPACITOR IMPROVES RESPONSE
For optimum settling time and stability with higher impedance
feedback networks (RF > 50kΩ), it may be necessary to add
a feedback capacitor across the feedback resistor, RF, as
shown in Figure 13. This capacitor compensates for the zero
created by the feedback network impedance and the OPA569
input capacitance (and any parasitic layout capacitance).
The effect becomes more significant with higher impedance
networks.
For applications with limited board size, refer to Figure 12 for
the approximate thermal resistance relative to heatsink area.
Increasing the heatsink area beyond 2in2 provides little
improvement in thermal resistance. To achieve the 21.5°C/W
stated in the Electrical Characteristics, a copper plane size of
9in2 was used. The SO-20 PowerPAD package is well suited
for continuous power levels, as shown in Figure 11. Higher
power levels may be achieved in applications with a low
on/off duty cycle.
The size of the capacitor needed is estimated using the
equation:
RIN • CIN = RF • CF
where CIN is the sum of the input capacitance of the OPA569
plus the parasitic layout capacitance.
MAXIMUM POWER DISSIPATION
vs TEMPERATURE
14
CF
TJ = 150°C
With 250lfm Airlow
12
10
8
RIN
RF
V+
With 150lfm Airlow
VIN
With 500lfm Airlow
12,
13
6
Without Forced Air
5
6
CIN
OPA569
CIN
14,
15
4
RIN • CIN = RF • CF
VOUT
2
CL
0
–55
–30
–5
20
45
70
95
120
17,
18
Temperature (°C)
V–
FIGURE 11. Maximum Power Dissipation vs Temperature.
Where CIN is equal to the OPA569’s input
capacitance (approximately 9pF) plus any
parasitic layout capacitance.
FIGURE 13. Feedback Capacitor for use with Higher Imped-
ance Networks.
OPA569
SBOS264A
17
www.ti.com
PowerPAD THERMALLY ENHANCED PACKAGE
PARALLEL OPERATION
The OPA569 uses the SO-20 PowerPAD package, a ther-
mally enhanced, standard size IC package designed to
eliminate the use of bulky heatsinks and slugs traditionally
used in thermal packages. This package can be easily
mounted using standard PCB assembly techniques.
The OPA569 allows parallel operation of multiple op amps to
extend output current capability or improve the output volt-
age swing to the rail. Special internal circuitry causes the
load current to be shared equally between two (or more) op
amps.
The PowerPAD package is designed so that the leadframe
die pad (or thermal pad) is exposed on the bottom of the IC,
as shown in Figure 15. This provides an extremely low
thermal resistance (θJC) path between the die and the
exterior of the package. The thermal pad on the bottom of
the IC can then be soldered directly to the PCB, using the
PCB as a heatsink. In addition, plated-through holes (vias)
provide a low thermal resistance heat flow path to the back
side of the PCB.
Figure 14 shows two ways to connect the input terminals.
When the amplifier inputs are connected in parallel, the
effective offset voltage is averaged and the bandwidth and
slew rate performance are the same as that of a single
amplifier. It is also possible to use one amplifier to be the
“master” and connect the other inputs to a voltage within the
common-mode input range of the amplifier; however, slew
rate and bandwidth performance will be degraded.
For best performance, keep additional capacitance at the
Parallel Out pins to a minimum and avoid routing these lines
close to other lines that might see large voltage swings.
Soldering the PowerPAD to the PCB ia always recom-
mended, even with applications that have low power dissipa-
tion. This provides the necessary thermal and mechanical
connection between the leadframe die pad and the PCB.
V+
Leadframe (Copper Alloy)
12,
13
Parallel Out 1
IC (Silicon)
5
6
2
14,
15
Die Attach (Epoxy)
OPA569
(A1)
VIN
9
Parallel Out 2
17,
18
V–
V+
12,
13
Parallel Out 1
Leadframe Die Pad
Exposed at Base of the Package
5
6
2
14,
15
OPA569
(A2)
Mold Compound (Epoxy)
9
RL
Parallel Out 2
17,
18
FIGURE 15. Section View of a PowerPAD Package.
PowerPAD Assembly Process
V–
(a) Inputs connected in parallel.
1. The PowerPAD must be connected to the most negative
supply voltage of the device, which will be ground in single-
supply applications and V– in split-supply applications.
V+
12,
13
Parallel Out 1
5
6
2. Prepare the PCB with a top-side etch pattern, as shown in
Figure 16. There should be etch for the leads as well as
etch for the thermal land.
2
14,
15
OPA569
(A1)
VIN
9
Parallel Out 2
Parallel Out 1
3. Place the recommended number of plated-through holes
(or thermal vias) in the area of the thermal pad. These
holes should be 13 mils in diameter. They are kept small
so that solder wicking through the holes is not a problem
during reflow. The minimum recommended number of
holes for the SO-20 PowerPAD package is 24, as shown
in Figure 16.
17,
18
V–
V+
12,
13
5
6
2
14,
15
OPA569
(A2)
4. It is recommended, but not required, to place a small
number of additional holes under the package and outside
the thermal pad area. These holes provide an additional
heat path between the copper land and the ground plane.
They may be larger because they are not in the area to be
soldered, so wicking is not a problem. This is illustrated in
Figure 16.
9
RL
Parallel Out 2
17,
18
V–
(b) Amplifier A1 as “master”, A2 as “slave”.
FIGURE 14. Parallel Operation.
OPA569
SBOS264A
18
www.ti.com
9. With these preparatory steps in place, the PowerPAD IC
is simply placed in position and run through the solder
reflow operation as any standard surface-mount compo-
nent. This results in a part that is properly installed.
Thermal Land
299 mils x 510 mils
Minimum Area (7.59mm x 12.95mm)
(Copper)
OPTIONAL:
Additional 4 vias outside of
thermal pad area but under
the package
For detailed information on the PowerPAD package including
thermal modeling considerations and repair procedures,
please see Technical Brief SLMA002, “PowerPAD Thermally
Enhanced Package,” located at www.ti.com.
(Via diameter = 25 mils)
REQUIRED:
LAYOUT GUIDELINES
The OPA569 is a power amplifier that requires proper layout
for best performance. Figure 18 shows an example layout.
Refinements to this example layout may be required based
on assembly process requirements.
Thermal pad area: 140 mils x 176 mils
(3.56mm x 4.47mm) with 24 vias
(Via diameter = 13 mils)
Keep power-supply leads as short as possible. This will keep
inductance low and resistive losses at a minimum. A mini-
mum of 18 gauge wire thickness is recommended for power-
supply leads. The wire length should be less than 8 inches.
FIGURE16.20-PinDWPPowerPADPCBEtchandViaPattern.
5. Connect all holes, including those within the thermal pad
area and outside the pad area, to the internal ground
plane or other internal copper plane for single supply
applications, and V– for split-supply applications.
Proper power-supply bypassing with low ESR capacitors is
essential to achieve good performance. A parallel combina-
tion of 100nF ceramic and 47µF tantalum bypass capacitors
will provide low impedance over a wide frequency range.
Bypass capacitors should be placed as close as practical to
the power-supply pins of the OPA569.
6. When laying out these holes to the ground plane, do not
use the typical web or spoke via connection methodology,
as shown in Figure 17. Web connections have a high
thermal resistance connection that is useful for slowing
the heat transfer during soldering operations. This makes
soldering the vias that have ground plane connections
easier. However, in this application, low thermal resis-
tance is desired for the most efficient heat transfer.
Therefore, the holes under the PowerPAD package should
make their connection to the internal ground plane with a
complete connection around the entire circumference of
the plated-through hole.
PCB traces conducting high currents, such as from output to
load or from the power-supply connector to the power-supply
pins of the OPA569 should be kept as wide and short as
possible.
The twenty-four holes in the landing pattern for the OPA569
are for the thermal vias that connect the PowerPAD of the
OPA569 to the heatsink area on the PCB. The additional four
larger vias further enhance the heat conduction into the
heatsink area. All traces conducting high currents are very
wide for lowest inductance and minimal resistive losses. Note
that the negative supply (–V) pin on the OPA569 can be
connected through the PowerPAD to allow for maximum
trace width for high current paths.
Parellel
Out 1
IMONITOR
Current
Limit Set
V–
Pin 1
Solid Via
Web or Spoke Via
V–
RECOMMENDED
NOT RECOMMENDED
Current Limit Flag
–In
VOUT
+In
Thermal Flag
Enable
V+
Parallel Out 2
FIGURE 17. Via Connection.
NOTE: Avoid routing Current
Limit Set and Current Limit
Flag traces closely in parallel.
7. The top-side solder mask should leave the terminals of the
pad connections and the thermal pad area exposed. The
thermal pad area should leave the 13 mil holes exposed.
The larger holes outside the thermal pad area should be
covered with solder mask.
FIGURE 18. 20-Pin DWP PowerPAD PCB Etch and Via
Pattern.
8. Apply solder paste to the exposed thermal pad area and
all of the package terminals.
OPA569
SBOS264A
19
www.ti.com
APPLICATION CIRCUITS
R2
4.99kΩ
fO = 10kHz
0.0033µF
0mA
–100mA
RSHUNT
1Ω
R1
49.9kΩ
12,
13
+1V
0V
5
6
14,
15
IO
VIN
VO
OPA569
3
(1)
RSET
R3
49.9kΩ
17,
18
0V
–2.5V
Luxeon Star-0
High-Power LED
–5V
4.99kΩ
Feedback for Constant Current,
1V Input per 100mA Output as Shown.
NOTE: (1) Bypass as recommended.
FIGURE 19. Grounded Anode LED Driver.
1kΩ
1kΩ
5V
5V
(1)
12,
13
12,
13
(1)
5
5
14,
15
14,
TEC
15
OPA569
OPA569
6
6
19
Current
Limit
Set
VIN
IMONITOR
VSET
3
Current
Limit
Set
+
VTEC
–
3
17,
18
17,
18
ITEC
RSET
IM = +
Heat/Cool
RSET
475
VTEC = 2 (VIN – VSET
)
RM
Optional to
monitor the
load current.
VM
NOTE: (1) Bypass as recommended.
FIGURE 20. Bridge Tied Load Driver.
NOTE: Total Supply Must
be < 5.5V Cooling/Heating.
+3.3V
(1)
12,
13
5
6
IL
14,
15
OPA569
VIN
19
17,
18
TEC
IMONITOR
RMONITOR
NOTE: (1) Bypass as recommended.
–1.2V
FIGURE 21. Single Power Amplifier Driving Bidirectional Current through a TEC using Asymmetrical Bipolar Power Supplies.
OPA569
SBOS264A
20
www.ti.com
1kΩ
1kΩ
+5V(1)
12,
+5V(1)
13
5
6
2A max
14,
15
2
3
7
OPA335
4
OPA569
6
RL
VIN
17,
18
NOTE: (1) Bypass as recommended.
FIGURE 22. Power Booster for Precision Op Amp.
C1
3.3nF
+5V
2
1
3pF
1MΩ
(1)
4
5
+5V
R1
10kΩ
12,
13
8pF
5
6
1
14,
15
R2
10kΩ
OPA569
+2.5V
2
+0.5V
REF3025
19
3
LED
PD
17,
18
3
(3)
RMONITOR
C2
0.01µF
VB
R3
2.5kΩ
Luxeon
Star –0
High
Power
LED
(2)
RSET
OPT101(4)
8
3
NOTE: (1) Bypass as recommended.
(2) RSET establishes current limit.
Glass Microscope Slide
(3) RMONITOR used to measure LED current.
(4) OPT101 Pin Numbers for DIP Package.
Approximately
92% light
available for application.
LED
≈ 8%
Optical Calibration
OPT101
FIGURE 23. LED Output Regulation Circuit for Constant Optical Power.
OPA569
SBOS264A
21
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
OPA569AIDWP
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE SO PowerPAD DWP
ACTIVE SO PowerPAD DWP
ACTIVE SO PowerPAD DWP
ACTIVE SO PowerPAD DWP
20
20
20
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
OPA569A
OPA569AIDWPG4
OPA569AIDWPR
OPA569AIDWPRG4
25
Green (RoHS
& no Sb/Br)
OPA569A
OPA569A
OPA569A
1000
1000
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA569AIDWPR
SO
Power
PAD
DWP
20
1000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jul-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SO PowerPAD DWP 20
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
OPA569AIDWPR
1000
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Automotive and Transportation www.ti.com/automotive
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/industrial
www.ti.com/medical
Medical
Logic
Security
www.ti.com/security
Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense
Video and Imaging
www.ti.com/space-avionics-defense
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/omap
OMAP Applications Processors
Wireless Connectivity
TI E2E Community
e2e.ti.com
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明