OPA859IDSGT [TI]
具有 1.8GHz 单位增益带宽、3.3nV/√Hz 电压噪声的 FET 输入放大器 | DSG | 8 | -40 to 125;
| 型号： | OPA859IDSGT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 1.8GHz 单位增益带宽、3.3nV/√Hz 电压噪声的 FET 输入放大器 | DSG | 8 | -40 to 125 放大器 信息通信管理 光电二极管 |
| 文件： | 总34页 (文件大小：2756K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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OPA859
ZHCSIQ9 –SEPTEMBER 2018
OPA859 1.8GHz 单位增益带宽、3.3nV/√Hz、FET输入放大器
1 特性
3 说明
1
•
高单位增益带宽：1.8GHz
增益带宽积：900MHz
OPA859 是一款具有 CMOS 输入的宽带低噪声运算放
大器，适用于宽带跨阻和电压放大器 应用。将该器件
配置为跨阻放大器 (TIA) 时，0.9GHz 增益带宽积
(GBWP) 能够在低电容光电二极管应用中实现高闭环
带宽。
•
•
•
•
•
超低偏置电流 MOSFET 输入：10pA
低输入电压噪声：3.3nV/√Hz
压摆率：1150V/µs
低输入电容：
下图展示了在将 OPA859 设置为 TIA 时该放大器的带
宽和噪声性能与光电二极管电容的函数关系。计算总噪
声时的带宽范围为从直流到左轴上计算得出的频率 f。
OPA859 封装具有一个反馈引脚 (FB)，可简化输入和
输出之间的反馈网络连接。
–
–
共模：0.6pF
差动：0.2pF
•
宽输入共模范围：
–
–
与正电源相差 1.4V
包括负电源
OPA859 经过优化，可在光学飞行时间 (ToF) 系统中
运行，在该系统中 OPA859 与时数转换器（如
TDC7201）配合使用。可在具有差分输出放大器（如
THS4541 或 LMH5401）的高分辨率激光雷达系统中
使用 OPA859 来驱动高速模数转换器 (ADC)。
•
•
•
•
•
TIA 配置下的输出摆幅为 2.5VPP
电源电压范围：3.3V 至 5.25V
静态电流：20.5mA
封装：8 引脚 WSON
温度范围：–40 至 +125°C
器件信息(1)
2 应用
器件编号
OPA859
封装
WSON (8)
封装尺寸（标称值）
•
•
•
•
•
•
•
•
•
高速跨阻放大器
2.00mm × 2.00mm
激光测距
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
CCD 输出缓冲器
高速缓冲器
光学时域反射法 (OTDR)
高速有源滤波器
3D 扫描仪
硅光电倍增器 (SiPM) 缓冲放大器
光电倍增管后置放大器
高速飞行时间接收器
光电二极管电容与带宽和噪声间的关系
CF
225
200
175
150
125
100
75
150
135
120
105
90
f-3dB, RF = 2 kW
f-3dB, RF = 5 kW
IRN, RF = 2 kW
IRN, RF = 5 kW
RF
VBIAS
Rx
5 V
TLV3501
+
Lens
œ
3.5 V
+
OPA859
Stop 2
Start 2
VREF
œ
CF
RF
75
TDC7201
(Time-to-
Digital
VBIAS
60
5 V
Converter)
TLV3501
+
œ
50
45
3.5 V
+
OPA859
Stop 1
Start 1
VREF
œ
25
30
0
15
0
2
4
6
8
10
12
14
16
18
20
Photodiode capacitance (pF)
Tx
Lens
D409
MSP430
ꢀController
Pulsed Laser
Diode
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS852
OPA859
ZHCSIQ9 –SEPTEMBER 2018
www.ti.com.cn
目录
9.3 Feature Description................................................. 16
9.4 Device Functional Modes........................................ 19
10 Application and Implementation........................ 20
10.1 Application Information.......................................... 20
10.2 Typical Application ............................................... 21
11 Power Supply Recommendations ..................... 23
12 Layout................................................................... 24
12.1 Layout Guidelines ................................................. 24
12.2 Layout Example .................................................... 24
13 器件和文档支持 ..................................................... 25
13.1 器件支持................................................................ 25
13.2 文档支持................................................................ 25
13.3 接收文档更新通知 ................................................. 25
13.4 社区资源................................................................ 25
13.5 商标....................................................................... 25
13.6 静电放电警告......................................................... 25
13.7 术语表 ................................................................... 25
14 机械、封装和可订购信息....................................... 25
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics .......................................... 5
7.6 Typical Characteristics.............................................. 7
Parameter Measurement Information ................ 14
8.1 Parameter Measurement Information ..................... 14
Detailed Description ............................................ 15
9.1 Overview ................................................................. 15
9.2 Functional Block Diagram ....................................... 15
8
9
4 修订历史记录
日期
修订版本
说明
2018 年 9 月
*
初始发行版。
2
Copyright © 2018, Texas Instruments Incorporated
OPA859
www.ti.com.cn
ZHCSIQ9 –SEPTEMBER 2018
5 Device Comparison Table
MINIMUM STABLE
GAIN
VOLTAGE NOISE
INPUT
CAPACITANCE (pF)
GAIN BANDWIDTH
(GHz)
DEVICE
INPUT TYPE
(nV/√Hz)
OPA859
OPA858
OPA855
LMH6629
CMOS
CMOS
Bipolar
Bipolar
1 V/V
7 V/V
7 V/V
10 V/V
3.3
2.5
0.8
0.8
0.8
5.7
0.9
5.5
8
0.98
0.69
4
6 Pin Configuration and Functions
DSG Package
8-Pin WSON With Exposed Thermal Pad
Top View
FB
NC
INœ
IN+
1
2
3
4
8
7
6
5
PD
VS+
OUT
VSœ
Thermal pad
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
FB
NO.
1
I
I
Feedback connection to output of amplifier
Inverting input
IN–
3
IN+
4
I
Noninverting input
NC
2
—
O
I
Do not connect
OUT
PD
6
Amplifier output
8
Power down connection. PD = logic low = power off mode; PD = logic high = normal operation.
VS–
VS+
5
—
—
—
Negative voltage supply
7
Positive voltage supply
Thermal pad
Connect the thermal pad to VS–
Copyright © 2018, Texas Instruments Incorporated
3
OPA859
ZHCSIQ9 –SEPTEMBER 2018
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
VS
Total supply voltage (VS+ – VS–
)
5.5
VIN+, VIN–
VID
Input voltage
(VS–) – 0.5
(VS–) – 0.5
(VS+) + 0.5
1
V
Differential input voltage
Output voltage
V
VOUT
IIN
IOUT
TJ
(VS+) + 0.5
±10
V
Continuous input current
Continuous output current(2)
Junction temperature
Operating free-air temperature
Storage temperature
mA
mA
°C
°C
°C
±100
150
TA
–40
–65
125
Tstg
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Long-term continuous output current for electromigration limits.
7.2 ESD Ratings
VALUE
±1000
±1500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3.3
NOM
MAX
5.25
125
UNIT
VS
TA
Total supply voltage (VS+ – VS–
)
5
V
Operating free-air temperature
–40
°C
7.4 Thermal Information
OPA859
THERMAL METRIC(1)
DSG (WSON)
8 PINS
80.1
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
100
45
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
6.8
ψJB
45.2
RθJC(bot)
22.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2018, Texas Instruments Incorporated
OPA859
www.ti.com.cn
ZHCSIQ9 –SEPTEMBER 2018
7.5 Electrical Characteristics
VS+ = 5 V, VS- = 0 V, input common-mode biased at midsupply, unity gain configuration, RL = 200 Ω, output load is referenced
to midsupply, and TA ≈ +25℃ (unless otherwise noted)
PARAMETER
AC PERFORMANCE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SSBW
LSBW
GBWP
Small-signal bandwidth
Large-signal bandwidth
Gain-bandwidth product
Bandwidth for 0.1dB flatness
Slew rate (10% - 90%)
Rise time
VOUT = 100 mVPP
1.8
400
900
140
1150
0.3
0.3
8
GHz
MHz
MHz
MHz
V/µs
ns
VOUT = 2 VPP
SR
tr
VOUT = 2-V step
VOUT = 100-mV step
VOUT = 100-mV step
VOUT = 2-V step
tf
Fall time
ns
Settling time to 0.1%
Settling time to 0.001%
Overshoot/undershoot
ns
VOUT = 2-V step
3000
7%
90
ns
VOUT = 2-V step
f = 10 MHz, VOUT = 2 VPP
f = 100 MHz, VOUT = 2 VPP
f = 10 MHz, VOUT = 2 VPP
f = 100 MHz, VOUT = 2 VPP
f = 1 MHz
HD2
HD3
Second-order harmonic distortion
Third-order harmonic distortion
dBc
60
86
dBc
dBc
64
en
Input-referred voltage noise
3.3
0.15
nV/√Hz
Ω
ZOUT
Closed-loop output impedance
f = 1 MHz
DC PERFORMANCE
AOL
Open-loop voltage gain
60
–5
65
±0.9
–2
dB
mV
µV/°C
pA
VOS
Input offset voltage
TA = 25°C
5
ΔVOS/ΔT
IBN, IBI
IBOS
Input offset voltage drift
Input bias current
TA = –40°C to +125°C
TA = 25°C
–5
–5
70
±0.5
±0.1
84
5
5
Input offset current
TA = 25°C
pA
CMRR
INPUT
Common-mode rejection ratio
VCM = ±0.5 V
dB
Common-mode input resistance
Common-mode input capacitance
Differential input resistance
1
0.62
1
GΩ
pF
GΩ
pF
V
CCM
CDIFF
VIH
Differential input capacitance
Common-mode input range (high)
Common-mode input range (low)
0.2
1.9
0
VS+ = 3.3 V, CMRR > 66 dB
VS+ = 3.3 V, CMRR > 66 dB
CMRR > 66 dB
1.7
3.4
VIL
0.4
V
3.6
3.4
0
VIH
VIL
Common-mode input range (high)
Common-mode input range (low)
V
V
TA = –40°C to +125°C, CMRR > 66 dB
CMRR > 66 dB
0.4
TA = –40°C to +125°C, CMRR > 66 dB
0.35
0.45
OUTPUT
VOH
Output voltage (high)
Output voltage (high)
Output voltage (low)
Output voltage (low)
VS+ = 3.3 V, TA = 25°C
TA = 25°C
2.3
2.4
4.1
3.9
1.05
1.1
1.2
76
V
V
V
V
3.95
VOH
VOL
VOL
TA = –40°C to +125°C
VS+ = 3.3 V, TA = 25°C
TA = 25°C
1.15
1.15
TA = –40°C to +125°C
RL = 10 Ω, AOL > 52 dB
65
85
IO_LIN
ISC
Linear output drive (sink and source)
Output short-circuit current
mA
mA
TA = –40°C to +125°C, RL = 10 Ω,
AOL > 52 dB
64
105
Copyright © 2018, Texas Instruments Incorporated
5
OPA859
ZHCSIQ9 –SEPTEMBER 2018
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Electrical Characteristics (continued)
VS+ = 5 V, VS- = 0 V, input common-mode biased at midsupply, unity gain configuration, RL = 200 Ω, output load is referenced
to midsupply, and TA ≈ +25℃ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
VS+ = 5 V
18
17.5
18
20.5
20
24
23.5
24
VS+ = 3.3 V
VS+ = 5.25 V
TA = 125°C
TA = –40°C
IQ
Quiescent current
21
mA
dB
24.5
18.5
74
PSRR+
PSRR–
Positive power-supply rejection ratio
Negative power-supply rejection ratio
66
64
72
POWER DOWN
Disable voltage threshold
Amplifier OFF below this voltage
Amplifier ON above this voltage
0.65
1
1.5
70
V
V
Enable voltage threshold
Power-down quiescent current
PD bias current
1.8
140
200
µA
µA
ns
ns
70
Turnon time delay
Time to VOUT = 90% of final value
25
Turnoff time delay
120
6
版权 © 2018, Texas Instruments Incorporated
OPA859
www.ti.com.cn
ZHCSIQ9 –SEPTEMBER 2018
7.6 Typical Characteristics
at TA = 25°C, VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, Gain = 1 V/V, RF = 0 Ω, RL = 200 Ω, and output load referenced to
midsupply (unless otherwise noted)
3
0
3
0
-3
-3
-6
-6
Gain = +1 V/V
Gain = -1 V/V
Gain = +2 V/V
Gain = +5 V/V
Gain = +20 V/V
-9
-9
VS = 3.3 V
VS = 5 V
-12
1M
10M
100M
Frequency (Hz)
1G
5G
-12
1M
10M
100M
1G
5G
D300
Frequency (Hz)
VOUT = 100 mVPP; see Parameter Measurement Information for
circuit configuration
D302
VOUT = 100 mVPP
图 1. Small-Signal Frequency Response vs Gain
图 2. Small-Signal Frequency Response vs Supply Voltage
3
2
1
0
0
-3
-6
-1
-2
-3
-4
-5
-6
-7
-8
TA = 125èC
TA = 85èC
TA = 25èC
TA = 0èC
-9
RL = 100 W
RL = 200 W
RL = 400 W
-12
TA = -40èC
1M
10M
100M
1G
5G
1M
10M
100M
1G
5G
Frequency (Hz)
Frequency (Hz)
D303
D304
VOUT = 100 mVPP
VOUT = 100 mVPP
图 3. Small-Signal Frequency Response vs Output Load
图 4. Small-Signal Frequency Response vs Ambient
Temperature
4
3
0
2
0
-3
-6
-9
-2
-4
-6
-8
RS = 18 W, CL = 10 pF
RS = 9.1 W, CL = 47 pF
RS = 6.2 W, CL = 100 pF
RS = 2 W, CL = 1 nF
VS = ê1.65 V, VOUT = 100 mVPP, VCM = 0 V
VS = ê2.5 V, VOUT = 100 mVPP, VCM = 0.9 V
VS = ê2.5 V, VOUT = 2 VPP, VCM = 0 V
-12
-10
-12
-15
1M
10M
Frequency (Hz)
100M
1M
10M
100M
Frequency (Hz)
1G
D301
D305
Gain = 20 V/V
RF = 453 Ω
VOUT = 100 mVPP, See 图 46 for circuit configuration
图 6. Small-Signal Frequency Response vs Capacitive Load
图 5. Frequency Response at Gain = 20 V/V
版权 © 2018, Texas Instruments Incorporated
7
OPA859
ZHCSIQ9 –SEPTEMBER 2018
www.ti.com.cn
Typical Characteristics (接下页)
at TA = 25°C, VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, Gain = 1 V/V, RF = 0 Ω, RL = 200 Ω, and output load referenced to
midsupply (unless otherwise noted)
3
0.2
0.1
0
0
-3
-0.1
-0.2
-0.3
-0.4
-0.5
-6
Gain = +1 V/V
Gain = -1 V/V
Gain = +2 V/V
Gain = +5 V/V
Gain = +20 V/V
-9
-12
1M
10M
100M
Frequency (Hz)
1G
1M
10M
Frequency (Hz)
100M
D306
D307
VOUT = 2 VPP
图 7. Large-Signal Frequency Response vs Gain
VOUT = 2 VPP
图 8. Large-Signal Response for 0.1-dB Gain Flatness
100
10
75
60
45
30
15
0
45
AOL Magnitude (dB)
AOL Phase (è)
0
-45
1
-90
-135
-180
-225
0.1
0.01
-15
100k
1M
10M
100M
10k
100k
1M
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
D309
D310
Small-Signal Response
图 9. Closed-Loop Output Impedance vs Frequency
Small-Signal Response
图 10. Open-Loop Magnitude and Phase vs Frequency
4
100
10
1
3.8
3.6
3.4
3.2
3
2.8
2.6
1k
10k
100k
1M
10M
100M
-40
-20
0
20
40
60
80
100 120 140
Frequency (Hz)
Ambient Temperature (èC)
D311
D312
Frequency 10 MHz
图 11. Voltage Noise Density vs Frequency
图 12. Voltage Noise Density vs Ambient Temperature
8
版权 © 2018, Texas Instruments Incorporated
OPA859
www.ti.com.cn
ZHCSIQ9 –SEPTEMBER 2018
Typical Characteristics (接下页)
at TA = 25°C, VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, Gain = 1 V/V, RF = 0 Ω, RL = 200 Ω, and output load referenced to
midsupply (unless otherwise noted)
-40
-40
-50
HD2, VOUT = 0.5 VPP
HD2, VOUT = 1 VPP
HD2, VOUT = 2 VPP
HD2, VOUT = 2.5 VPP
HD3, VOUT = 0.5 VPP
HD3, VOUT = 1 VPP
HD3, VOUT = 2 VPP
HD3, VOUT = 2.5 VPP
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
1M
10M
Frequency (Hz)
100M
1M
10M
Frequency (Hz)
100M
D313
D314
图 13. Harmonic Distortion (HD2) vs Output Swing
图 14. Harmonic Distortion (HD3) vs Output Swing
-40
-50
-40
-50
HD2, RL = 100 W
HD2, RL = 200 W
HD2, RL = 400 W
HD3, RL = 100 W
HD3, RL = 200 W
HD3, RL = 400 W
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
1M
10M
100M
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
D315
D316
VOUT = 2 VPP
VOUT = 2 VPP
图 15. Harmonic Distortion (HD2) vs Output Load
图 16. Harmonic Distortion (HD3) vs Output Load
-40
-50
-40
-50
HD2, Gain = 1 V/V, RF = 0 W
HD2, Gain = -1 V/V, RF = 150 W
HD2, Gain = 2 V/V, RF = 150 W
HD2, Gain = 5 V/V, RF = 453 W
HD3, Gain = 1 V/V, RF = 0 W
HD3, Gain = -1 V/V, RF = 150 W
HD3, Gain = 2 V/V, RF = 150 W
HD3, Gain = 5 V/V, RF = 453 W
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-100
-110
-120
1M
10M
100M
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
D317
D318
VOUT = 2 VPP
VOUT = 2 VPP
图 17. Harmonic Distortion (HD2) vs Gain
图 18. Harmonic Distortion (HD3) vs Gain
版权 © 2018, Texas Instruments Incorporated
9
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ZHCSIQ9 –SEPTEMBER 2018
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Typical Characteristics (接下页)
at TA = 25°C, VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, Gain = 1 V/V, RF = 0 Ω, RL = 200 Ω, and output load referenced to
midsupply (unless otherwise noted)
60
1.25
1
Input
Output
Input
Output
40
0.75
0.5
20
0.25
0
0
-0.25
-0.5
-0.75
-1
-20
-40
-60
-1.25
Time (5 ns/div)
Time (5 ns/div)
D319
D320
Average Rise and Fall Time (10% - 90%) = 450 ps
Slew Rate: Falling = 1160 V/µs, Rising = 1400 V/µs
图 19. Small-Signal Transient Response
图 20. Large-Signal Transient Response
4
3
0.075
0.05
2
0.025
0
1
0
-1
-2
-3
-4
-0.025
-0.05
-0.075
RS = 18 W, CL = 10 pF
RS = 9.1 W, CL = 47 pF
RS = 6.2 W, CL = 100 pF
RS = 2 W, CL = 1 nF
Ideal Output
Measured Output
Time (10 ns/div)
Time (5 ns/div)
D321
D322
See 图 46 for circuit configuration
Gain = 5 V/V, RF = 453 Ω, 2x Output Overdrive
图 22. Output Overload Response
图 21. Small-Signal Transient Response vs Capacitive Load
3
2
3
Power Down (PD)
Output
2
1
1
0
0
-1
-2
-3
-1
-2
Power Down (PD)
Output
-3
Time (5 ns/div)
Time (5 ns/div)
D323
D324
图 23. Turnon Transient Response
图 24. Turnoff Transient Response
10
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ZHCSIQ9 –SEPTEMBER 2018
Typical Characteristics (接下页)
at TA = 25°C, VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, Gain = 1 V/V, RF = 0 Ω, RL = 200 Ω, and output load referenced to
midsupply (unless otherwise noted)
100
80
60
40
20
0
80
60
40
20
0
CMRR
PSRR+
PSRR-
-20
10k
100k
1M
10M
100M
1G
10k
100k
1M
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
D325
D326
Small-Signal Response
Small-Signal Response
图 25. Common-Mode Rejection Ratio vs Frequency
图 26. Power Supply Rejection Ratio vs Frequency
24
23
22
21
20
19
18
21.5
21.25
21
20.75
20.5
20.25
20
19.75
19.5
19.25
19
Unit 1
Unit 2
Unit 1
Unit 2
3
3.25 3.5 3.75
4
4.25 4.5 4.75
5
5.25
-40
-20
0
20
40
60
80
100 120 140
Total Supply Voltage (V)
Ambient Temperature (èC)
D360
D361
2 Typical Units
VS = 5 V
2 Typical Units
图 27. Quiescent Current vs Supply Voltage
图 28. Quiescent Current vs Ambient Temperature
1
80
78
76
74
72
70
68
66
64
Unit 1
Unit 2
Unit 3
0.75
0.5
0.25
0
-0.25
-0.5
-0.75
-1
-40
-20
0
20
40
60
80
100 120 140
3
3.25 3.5 3.75
4
4.25 4.5 4.75
5
5.25
Ambient Temperature (èC)
Total Supply Voltage (V)
D362
D363
32 Units Tested
3 Typical Units
图 29. Quiescent Current (Amplifier Disabled) vs Ambient
图 30. Offset Voltage vs Supply Voltage
Temperature
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Typical Characteristics (接下页)
at TA = 25°C, VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, Gain = 1 V/V, RF = 0 Ω, RL = 200 Ω, and output load referenced to
midsupply (unless otherwise noted)
0.8
0.6
0.4
0.2
0
2
1.5
1
Unit 1
Unit 2
Unit 3
0.5
0
-0.2
-0.4
-0.6
-0.8
-0.5
-1
-40
-20
0
20
40
60
80
100 120 140
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
Ambient Temperature (èC)
Common-Mode Voltage (V)
D364
D366
µ = –2.1 µV/°C
σ = 2 µV/°C
32 Units Tested
VS = 5 V
3 Typical Units
图 31. Offset Voltage vs Ambient Temperature
图 32. Offset Voltage vs Input Common-Mode Voltage
1.5
1
5
4
TA = -40èC
TA = +25èC
TA = +125èC
3
2
1
0.5
0
0
-1
-2
-3
-4
-5
Unit 1
Unit 2
Unit 3
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
1
1.5
2
2.5
3
3.5
4
4.5
Common-Mode Voltage
Output Voltage (V)
D367
D369
VS = 5 V
VS = 5 V
3 Typical Units
图 33. Offset Voltage vs Input Common-Mode Voltage vs
图 34. Offset Voltage vs Output Swing
Ambient Temperature
10n
4
3
1n
100p
10p
2
1
0
-1
-2
1p
TA = -40èC
Unit 1
Unit 2
Unit 3
-3
-4
TA = +25èC
TA = +125èC
0.1p
1
1.5
2
2.5
3
3.5
4
4.5
-40
-20
0
20
40
60
80
100 120 140
Output Voltage (V)
Ambient Temperature (èC)
D370
D371
VS = 5 V
3 Typical Units
图 35. Offset Voltage vs Output Swing vs Ambient
图 36. Input Bias Current vs Ambient Temperature
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Temperature
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Typical Characteristics (接下页)
at TA = 25°C, VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, Gain = 1 V/V, RF = 0 Ω, RL = 200 Ω, and output load referenced to
midsupply (unless otherwise noted)
5
2.4
2.2
2
TA = -40èC
TA = +25èC
TA = +125èC
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
1.8
1.6
1.4
1.2
1
0
0.5
1
1.5
2
2.5
3
3.5
4
-120
-100
-80
-60
-40
-20
0
Common-Mode Voltage (V)
Output Current (mA)
D372
D373
VS = 5 V
VS = 5 V
图 37. Input Bias Current vs Input Common-Mode Voltage
图 38. Output Swing vs Sinking Current
4.5
7000
6000
5000
4000
3000
2000
1000
0
4
3.5
3
2.5
2
1.5
1
TA = -40èC
TA = +25èC
0.5
0
TA = +125èC
0
20
40
60
80
100
120
Output Current (mA)
D374
D340
Quiescent Current (mA)
VS = 5 V
µ = 20.8 mA
σ = 0.25 mA
9150 Units Tested
图 39. Output Swing vs Sourcing Current
图 40. Quiescent Current Distribution
2000
1750
1500
1250
1000
750
4500
4000
3500
3000
2500
2000
1500
1000
500
500
250
0
0
D342
D341
Offset Voltage (mV)
Input Bias Current (pA)
µ = –0.38 mV
σ = 0.97 mV
9150 Units Tested
µ = –0.55 pA
σ = 0.23 pA
9150 Units Tested
图 41. Offset Voltage Distribution
图 42. Input Bias Current Distribution
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8 Parameter Measurement Information
8.1 Parameter Measurement Information
The various test setup configurations for the OPA859 are shown in the figures below. When configuring the
OPA859 as a noninverting amplifier in gains less 3 V/V, set RF = 150 Ω. When configuring the OPA859 as a
noninverting amplifier in gains of 4 V/V and greater, set RF = 453 Ω.
GND
50 ꢀ
2.5 V
50 ꢀ
50-ꢀ
Source
169 ꢀ
+
50-ꢀ
Measurement
System
œ
50 ꢀ
Þ2.5 V
71.5 ꢀ
GND
GND
图 43. Unity-Gain Buffer Configuration
2.5 V
50 ꢀ
50-ꢀ
Source
169 ꢀ
+
50-ꢀ
Measurement
System
œ
50 ꢀ
Þ2.5 V
71.5 ꢀ
GND
RG
RF
GND
GND
RG values depend on gain configuration
图 44. Noninverting Configuration
2.5 V
169 ꢀ
+
50-ꢀ
Measurement
System
GND
œ
50 ꢀ
Þ2.5 V
71.5 ꢀ
50 ꢀ
50-ꢀ
Source
GND
150 ꢀ
150 ꢀ
GND
75 ꢀ
GND
图 45. Inverting Configuration (Gain = –1 V/V)
GND
50 ꢀ
2.5 V
50 ꢀ
50-ꢀ
Source
RS
169 ꢀ
75 ꢀ
+
50-ꢀ
Measurement
System
œ
50 ꢀ
CL
Þ2.5 V
GND
GND
GND
图 46. Capacitive Load Driver Configuration
14
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9 Detailed Description
9.1 Overview
The ultra-wide, 900-MHz gain bandwidth product (GBWP) of the OPA859, combined with the broadband voltage
noise of 3.3 nV/√Hz, produces a viable amplifier for wideband transimpedance applications, high-speed data
acquisition systems, and applications with weak signal inputs that require low-noise and high-gain front ends.
The OPA859 combines multiple features to optimize dynamic performance. In addition to the wide small-signal
bandwidth, the OPA859 has 400 MHz of large-signal bandwidth (VOUT = 2 VPP), and a slew rate of 1150 V/µs.
The OPA859 is offered in a 2-mm × 2-mm, 8-pin WSON package that features a feedback (FB) pin for a simple
feedback network connection between the amplifiers output and inverting input. Excess capacitance on an
amplifiers input pin can reduce phase margin causing instability. This problem is exacerbated in the case of very
wideband amplifiers like the OPA859. To reduce the effects of stray capacitance on the input node, the OPA859
pinout features an isolation pin (NC) between the feedback and inverting input pins that increases the physical
spacing between them thereby reducing parasitic coupling at high frequencies. The OPA859 also features a very
low capacitance input stage with only 0.8-pF of total input capacitance.
9.2 Functional Block Diagram
The OPA859 is a classic, voltage feedback operational amplifier (op amp) with two high-impedance inputs and a
low-impedance output. Standard application circuits are supported, like the two basic options shown in 图 47 and
图 48. The DC operating point for each configuration is level-shifted by the reference voltage (VREF), which is
typically set to midsupply in single-supply operation. VREF is typically connected to ground in split-supply
applications.
VSIG
VS+
(1 + RF / RG) × VSIG
VREF
VIN
+
VOUT
VREF
œ
RG
VSœ
RF
VREF
图 47. Noninverting Amplifier
VS+
œ(RF / RG) × VSIG
VREF
+
VSIG
VOUT
VREF
VREF
VIN
œ
RG
VSœ
RF
图 48. Inverting Amplifier
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9.3 Feature Description
9.3.1 Input and ESD Protection
The OPA859 is fabricated on a low-voltage, high-speed, BiCMOS process. The internal, junction breakdown
voltages are low for these small geometry devices, and as a result, all device pins are protected with internal
ESD protection diodes to the power supplies as 图 49 shows. There are two antiparallel diodes between the
inputs of the amplifier that clamp the inputs during an overrange or fault condition.
VS+
Power Supply
ESD Cell
VIN+
+
VOUT
œ
VINÞ
FB
VSÞ
图 49. Internal ESD Structure
9.3.2 Feedback Pin
The OPA859 pin layout is optimized to minimize parasitic inductance and capacitance, which is critical in high-
speed analog design. The FB pin (pin 1) is internally connected to the output of the amplifier. The FB pin is
separated from the inverting input of the amplifier (pin 3) by a no connect (NC) pin (pin 2). The NC pin must be
left floating. There are two advantages to this pin layout:
1. A feedback resistor (RF) can connect between the FB and IN– pin on the same side of the package (see 图
50) rather than going around the package.
2. The isolation created by the NC pin minimizes the capacitive coupling between the FB and IN– pins by
increasing the physical separation between the pins.
FB
NC
INœ
IN+
PD
1
2
3
4
8
7
6
5
VS+
OUT
VSœ
RF
œ
+
图 50. RF Connection Between FB and IN– Pins
16
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ZHCSIQ9 –SEPTEMBER 2018
Feature Description (接下页)
9.3.3 Wide Gain-Bandwidth Product
图 10 shows the open-loop magnitude and phase response of the OPA859. Calculate the gain bandwidth product
of any op amp by determining the frequency at which the AOL is 40 dB and multiplying that frequency by a factor
of 100. The open-loop response shows the OPA859 to have approximately 63° of phase-margin when configured
as a unity-gain buffer.
图 51 shows the open-loop magnitude (AOL) of the OPA859 as a function of temperature. The results show
approximately 5° of phase-margin variation over the entire temperature range. Semiconductor process variation
is the naturally occurring variation in the attributes of a transistor (Early-voltage, β, channel-length and width) and
other passive elements (resistors and capacitors) when fabricated into an integrated circuit. The process
variation can occur across devices on a single wafer, or, across devices over multiple wafer lots over time.
Typically the variation across a single wafer is tightly controlled. 图 52 shows the AOL magnitude of the OPA859
as a function of process variation over time. The results show the AOL curve for the nominal process corner and
the variation one standard deviation from the nominal. The simulated results show less than 2° of phase-margin
difference within a standard deviation of process variation when the amplifier is configured as a unity-gain bufffer.
75
60
45
30
15
0
75
60
45
30
15
0
AOL at -40èC
AOL at 25èC
AOL at +125èC
AOL (-1 s)
AOL (Typ.)
AOL (+1 s)
-15
-15
100k
1M
10M
100M
1G
100k
1M
10M
100M
1G
Frequency (Hz)
Frequency (Hz)
D404
D405
图 51. Open-Loop Gain vs Temperature
图 52. Open-Loop Gain vs Process Variation
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Feature Description (接下页)
9.3.4 Slew Rate and Output Stage
In addition to wide bandwidth, the OPA859 features a high slew rate of 1150 V/µs. The slew rate is a critical
parameter in high-speed pulse applications with narrow sub-10-ns pulses, such as optical time-domain
reflectometry (OTDR) and LIDAR. The high slew rate of the OPA859 implies that the device accurately
reproduces a 2-V, sub-ns pulse edge, as seen in 图 20. The wide bandwidth and slew rate of the OPA859 make
it an excellent amplifier for high-speed signal-chain front ends.
图 53 shows the open-loop output impedance of the OPA859 as a function of frequency. To achieve high slew
rates and low output impedance across frequency, the output swing of the OPA859 is limited to approximately 3
V. The OPA859 is typically used in conjunction with high-speed pipeline ADCs and flash ADCs that have limited
input ranges. Therefore, the OPA859 output swing range coupled with the class-leading voltage noise
specification for a CMOS amplifier maximizes the overall dynamic range of the signal chain.
20
18
16
14
12
10
8
6
4
2
0
10k
100k
1M
10M
100M
1G
10G
Frequency (Hz)
D601
图 53. Open-Loop Output Impedance (ZOL) vs Frequency
9.3.5 Current Noise
The input impedance of CMOS and JFET input amplifiers at low frequencies exceed several GΩs. However, at
higher frequencies, the transistors parasitic capacitance to the drain, source, and substrate reduces the
impedance. The high impedance at low frequencies eliminates any bias current and the associated shot noise. At
higher frequencies, the input current noise increases (see 图 54) as a result of capacitive coupling between the
CMOS gate oxide and the underlying transistor channel. This phenomenon is a natural artifact of the construction
of the transistor and is unavoidable.
100p
10p
1p
100f
10f
1f
1k
10k
100k
1M
10M
100M
1G
Frequency (Hz)
D607
图 54. Input Current Noise (IBN and IBI) vs Frequency
18
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ZHCSIQ9 –SEPTEMBER 2018
9.4 Device Functional Modes
9.4.1 Split-Supply and Single-Supply Operation
The OPA859 can be configured with single-sided supplies or split-supplies as shown in 图 60. Split-supply
operation using balanced supplies with the input common-mode set to ground eases lab testing because most
signal generators, network analyzers, spectrum analyzers, and other lab equipment typically reference inputs and
outputs to ground. Split-supply operation is preferred in systems where the signals swing around ground.
However, the system requires two supply rails. In split-supply operation, the thermal pad must be connected to
the negative supply.
Newer systems use a single power supply to improve efficiency and reduce the cost of the extra power supply.
The OPA859 can be used with a single positive supply (negative supply at ground) with no change in
performance if the input common-mode and output swing are biased within the linear operation of the device. In
single-supply operation, level shift the dc input and output reference voltages by half the difference between the
power supply rails. This configuration maintains the input common-mode and output load reference at midsupply.
To eliminate gain errors, the source driving the reference input common-mode voltage must have low output
impedance across the frequency range of interest . In this case, the thermal pad must be connected to ground.
9.4.2 Power-Down Mode
The OPA859 features a power-down mode to reduce the quiescent current to conserve power. 图 23 and 图 24
show the transient response of the OPA859 as the PD pin toggles between the disabled and enabled states.
The PD disable and enable threshold voltages are with reference to the negative supply. If the amplifier is
configured with the positive supply at 3.3 V and the negative supply at ground, then the disable and enable
threshold voltages are 0.65 V and 1.8 V, respectively. If the amplifier is configured with ±1.65-V supplies, then
the disable and enable threshold voltages are at –1 V and 0.15 V, respectively. If the amplifier is configured with
±2.5-V supplies, then the threshold voltages are at –1.85 V and –0.7 V.
图 55 shows the switching behavior of a typical amplifier as the PD pin is swept down from the enabled state to
the disabled state. Similarly, 图 56 shows the switching behavior of a typical amplifier as the PD pin is swept up
from the disabled state to the enabled state. The small difference in the switching thresholds between the down
sweep and the up sweep is caused by the hysteresis designed into the amplifier to increase immunity to noise on
the PD pin.
25
20
15
10
5
25
20
15
10
5
TA = -40èC
TA = 25èC
TA = 125èC
TA = -40èC
TA = 25èC
TA = 125èC
0
0
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
Power Down Voltage (V)
Power Down Voltage (V)
D200
D201
图 55. Switching Threshold (PD Pin Swept from High to
图 56. Switching Threshold (PD Pin Swept from Low to
Low)
High)
Connecting the PD pin low disables the amplifier and places the output in a high-impedance state. When the
amplifier is configured as a noninverting amplifier, the feedback (RF) and gain (RG) resistor network form a
parallel load to the output of the amplifier. To protect the input stage of the amplifier, the OPA859 uses internal,
back-to-back protection diodes between the inverting and noninverting input pins as 图 49 shows. In the power-
down state, if the differential voltage between the input pins of the amplifier exceeds a diode voltage drop, an
additional low-impedance path is created between the noninverting input pin and the output pin.
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10 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The OPA859 offers high input impedance, very high-bandwidth, high slew-rate, low noise, and better than –60
dBc of distortion performance at frequencies up to 100 MHz. These features make this device an excellent front-
end buffer in high-speed data acquisition systems. The wide bandwidth also makes this amplifier an excellent
choice for high-gain active filter systems.
20
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ZHCSIQ9 –SEPTEMBER 2018
10.2 Typical Application
图 57 shows the OPA859 configured as a transimpedance amplifier (U1) in a wide-bandwidth, optical front-end
system. A second OPA859 configured as a unity-gain buffer (U2) sets a dc offset voltage to the THS4520. The
THS4520 is used to convert the single-ended transimpedance output of the OPA859 into a differential output
signal. The THS4520 drives the input of the ADS54J64, 14-bit, 1-GSPS analog-to-digital converter (ADC) that
digitizes the analog signal.
CF
RF
VBIAS
5 V
œ
499 ꢀ
499 ꢀ
U1
+
3.5 V
OPA859
5 V
+
œ
Low-pass
filter
VOCM = 1.3 V
ADS54J64
+
œ
5 V
œ
U2
+
2.95 V
OPA859
499 ꢀ
499 ꢀ
图 57. OPA859 as Both a TIA and a Buffer in an Optical Front-End System
10.2.1 Design Requirements
The objective is to design a low noise, wideband optical front-end system using the OPA859 as a
transimpedance amplifier. The design requirements are:
•
•
•
•
•
Amplifier supply voltage: 5 V
TIA common-mode voltage: 3.5 V
THS4520 gain: 1 V/V
ADC input common-mode voltage: 1.3 V
ADC analog differential input range: 1.1 VPP
10.2.2 Detailed Design Procedure
The OPA859 meets the growing demand for wideband, low-noise photodiode amplifiers. The closed-loop
bandwidth of a transimpedance amplifier is a function of the following:
1. The total input capacitance (CIN). This total includes the photodiode capacitance, the input capacitance of the
amplifier (common-mode and differential capacitance) and any stray capacitance from the PCB.
2. The op amp gain bandwidth product (GBWP).
3. The transimpedance gain (RF).
图 57 shows the OPA859 configured as a TIA, with the avalanche photodiode (APD) reverse biased so that the
APD cathode is tied to a large positive bias voltage. In this configuration, the APD sources current into the op
amp feedback loop so that the output swings in a negative direction relative to the input common-mode voltage.
To maximize the output swing in the negative direction, the OPA859 common-mode voltage is set close to the
positive limit; only 1.5 V from the positive supply rail. The feedback resistance (RF) and the input capacitance
(CIN) form a zero in the noise gain that results in instability if left unchecked. To counteract the effect of the zero,
a pole is inserted into the noise gain transfer function by adding the feedback capacitor (CF).
The Transimpedance Considerations for High-Speed Amplifiers Application Report discusses theories and
equations that show how to compensate a transimpedance amplifier for a particular transimpedance gain and
input capacitance. The bandwidth and compensation equations from the application report are available in an
Excel™ calculator. What You Need To Know About Transimpedance Amplifiers – Part 1 provides a link to the
calculator.
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Typical Application (接下页)
The equations and calculators in the referenced application report and blog posts are used to model the
bandwidth (f–3dB) and noise (IRN) performance of the OPA859 configured as a TIA. The resultant performance is
shown in 图 58 and 图 59. The left-side Y-axis shows the closed-loop bandwidth performance, whereas the right
side of the graph shows the integrated input-referred noise. The noise bandwidth to calculate IRN for a fixed RF
and CPD is set equal to the f–3dB frequency. 图 58 shows the amplifier performance as a function of photodiode
capacitance (CPD) for RF = 10 kΩ and 20 kΩ. Increasing CPD decreases the closed-loop bandwidth. To maximize
bandwidth, make sure to reduce any stray parasitic capacitance from the PCB. The OPA859 is designed with 0.8
pF of total input capacitance to minimize the effect of stray capacitance on system performance. 图 59 shows the
amplifier performance as a function of RF for CPD = 1 pF and 2 pF. Increasing RF results in lower bandwidth. To
maximize the signal-to-noise ratio (SNR) in an optical front-end system, maximize the gain in the TIA stage.
Increasing RF by a factor of X increases the signal level by X, but only increases the resistor noise contribution
by √X, thereby improving SNR.
The OPA859 configured as a unity-gain buffer drives a dc offset voltage of 2.95 V into the lower half of the
THS4520. To maximize the dynamic range of the ADC, the two OPA859 amplifiers drive a differential common-
mode of 3.5 V and 2.95 V into the THS4520. The dc offset voltage of the buffer amplifier can be derived using 公
式 1.
≈
∆
∆
∆
∆
∆
«
’
÷
÷
÷
÷
÷
◊
VADC _DIFF _IN
1
2
VBUF _DC = VTIA _ CM
-
ì
≈
∆
«
’
÷
RF
RG ◊
where
•
•
•
VTIA_CM is the common-mode voltage of the TIA (3.5 V)
VADC_DIFF_IN is the differential input voltage range of the ADC (1.1 VPP
)
RF and RG are the feedback resistance (499 Ω) and gain resistance (499 Ω) of the THS4520 differential
amplifier
(1)
The low-pass filter between the THS4520 and the ADC54J64 minimizes high-frequency noise and maximizes
SNR. The ADC54J64 has an internal buffer that isolates the output of the THS4520 from the ADC sampling-
capacitor input, so a traditional charge bucket filter is not required.
10.2.3 Application Curves
225
200
175
150
125
100
75
150
135
120
105
90
350
300
250
200
150
100
50
140
120
100
80
f-3dB, RF = 2 kW
f-3dB, RF = 5 kW
IRN, RF = 2 kW
IRN, RF = 5 kW
f-3dB, CF = 0.5 pF
f-3dB, CF = 1 pF
IRN, CF = 0.5 pF
IRN, RF = 1 pF
75
60
60
40
50
45
20
25
30
0
15
0
0
0
2
4
6
8
10
12
14
16
18
20
1
10
100
Photodiode capacitance (pF)
Feedback Resistance (kW)
D409
D410
图 58. Bandwidth and Noise vs Photodiode Capacitance
图 59. Bandwidth and Noise vs Feedback Resistance
22
版权 © 2018, Texas Instruments Incorporated
OPA859
www.ti.com.cn
ZHCSIQ9 –SEPTEMBER 2018
11 Power Supply Recommendations
The OPA859 operates on supplies from 3.3 V to 5.25 V. The OPA859 operates on single-sided supplies, split
and balanced bipolar supplies, and unbalanced bipolar supplies. Because the OPA859 does not feature rail-to-
rail inputs or outputs, the input common-mode and output swing ranges are limited at 3.3-V supplies.
a) Single supply configuration
VS+
VS+
+
2
0.1 …F
6.8 …F
RG
75 ꢀ
RF
453 ꢀ
œ
50-Ω Source
+
VI
200 ꢀ
RT
49.9 ꢀ
VS+
2
VS+
2
b) Split supply configuration
VS+
+
0.1 …F
6.8 …F
RG
RF
75 ꢀ
453 ꢀ
œ
50-Ω Source
+
VI
200 ꢀ
+
RT
49.9 ꢀ
0.1 …F
6.8 …F
VSœ
图 60. Split and Single Supply Circuit Configuration , Gain = 7 V/V
版权 © 2018, Texas Instruments Incorporated
23
OPA859
ZHCSIQ9 –SEPTEMBER 2018
www.ti.com.cn
12 Layout
12.1 Layout Guidelines
Achieving optimum performance with a high-frequency amplifier like the OPA859 requires careful attention to
board layout parasitics and external component types. Recommendations that optimize performance include:
•
Minimize parasitic capacitance from the signal I/O pins to ac ground. Parasitic capacitance on the output
and inverting input pins can cause instability. To reduce unwanted capacitance, cut out the power and ground
traces under the signal input and output pins. Otherwise, ground and power planes must be unbroken
elsewhere on the board. When configuring the amplifier as a TIA, if the required feedback capacitor is less
than 0.15 pF, consider using two series resistors, each of half the value of a single resistor in the feedback
loop to minimize the parasitic capacitance from the resistor.
•
Minimize the distance (less than 0.25") from the power-supply pins to high-frequency bypass
capacitors. Use high-quality, 100-pF to 0.1-µF, C0G and NPO-type decoupling capacitors with voltage
ratings at least three times greater than the amplifiers maximum power supplies. This configuration makes
sure that there is a low-impedance path to the amplifiers power-supply pins across the amplifiers gain
bandwidth specification. At the device pins, do not allow the ground and power plane layout to be in close
proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the
pins and the decoupling capacitors. The power-supply connections must always be decoupled with these
capacitors. Larger (2.2-µF to 6.8-µF) decoupling capacitors that are effective at lower frequency must be used
on the supply pins. Place these decoupling capacitors further from the device. Share the decoupling
capacitors among several devices in the same area of the printed circuit board (PCB).
•
Careful selection and placement of external components preserves the high-frequency performance
of the OPA859. Use low-reactance resistors. Surface-mount resistors work best and allow a tighter overall
layout. Never use wirewound resistors in a high-frequency application. Because the output pin and inverting
input pin are the most sensitive to parasitic capacitance, always position the feedback and series output
resistor, if any, as close to the output pin as possible. Place other network components (such as noninverting
input termination resistors) close to the package. Even with a low parasitic capacitance shunting the external
resistors, high resistor values create significant time constants that can degrade performance. When
configuring the OPA859 as a voltage amplifier, keep resistor values as low as possible and consistent with
load driving considerations. Decreasing the resistor values keeps the resistor noise terms low and minimizes
the effect of the parasitic capacitance. However, lower resistor values increase the dynamic power
consumption because RF and RG become part of the output load network of the amplifier.
12.2 Layout Example
Representative schematic
Connect PD to VS+ to enable the
amplifier
VS+
1
2
8
7
CBYP
RS
+
NC (Pin 2) isolates the IN- and FB
pins thereby reducing capacitive
coupling
œ
Thermal
Pad
CBYP
RF
CBYP
Place gain and feedback resistors
close to pins to minimize stray
capacitance
VS-
RF
3
4
6
5
RS
RG
RG
CBYP
Connect the thermal pad to the
negative supply pin
Ground and power plane exist on
inner layers.
Ground and power plane removed
from inner layers. Ground fill on
outer layers also removed
Place bypass capacitor
close to power pins
图 61. Layout Recommendation
24
版权 © 2018, Texas Instruments Incorporated
OPA859
www.ti.com.cn
ZHCSIQ9 –SEPTEMBER 2018
13 器件和文档支持
13.1 器件支持
13.1.1 开发支持
•
•
•
宽带宽光学前端参考设计
使用高速数据转换器的激光雷达脉冲飞行时间参考设计
激光雷达脉冲飞行时间参考设计
13.2 文档支持
13.2.1 相关文档
请参阅如下相关文档：
•
•
•
•
•
•
•
《OPA858EVM 用户指南》
《高速运算放大器跨阻注意事项应用报告》
《跨阻放大器须知 – 第 1 部分》
《跨阻放大器须知 – 第 2 部分》
培训视频：如何设计跨阻放大器电路
培训视频：高速跨阻放大器设计流程
培训视频：如何将 TINA-TI 模型转换为通用 SPICE 模型
13.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
13.5 商标
E2E is a trademark of Texas Instruments.
Excel is a trademark of Microsoft Corporation.
All other trademarks are the property of their respective owners.
13.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2018, Texas Instruments Incorporated
25
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
OPA859IDSGR
OPA859IDSGT
ACTIVE
ACTIVE
WSON
WSON
DSG
DSG
8
8
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
859
859
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
28-Sep-2021
OTHER QUALIFIED VERSIONS OF OPA859 :
Automotive : OPA859-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Sep-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA859IDSGR
OPA859IDSGT
WSON
WSON
DSG
DSG
8
8
3000
250
180.0
180.0
8.4
8.4
2.3
2.3
2.3
2.3
1.15
1.15
4.0
4.0
8.0
8.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Sep-2018
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
OPA859IDSGR
OPA859IDSGT
WSON
WSON
DSG
DSG
8
8
3000
250
210.0
210.0
185.0
185.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DSG 8
2 x 2, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
www.ti.com
PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
0.32
0.18
PIN 1 INDEX AREA
2.1
1.9
0.4
0.2
ALTERNATIVE TERMINAL SHAPE
TYPICAL
0.8
0.7
C
SEATING PLANE
0.05
0.00
SIDE WALL
0.08 C
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
EXPOSED
THERMAL PAD
(DIM A) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
9
1.6 0.1
8
1
0.32
0.18
PIN 1 ID
(45 X 0.25)
8X
0.4
0.2
8X
0.1
C A B
C
0.05
4218900/E 08/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
(
0.2) VIA
8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(1.9)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/E 08/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
METAL
8
SYMM
1
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/E 08/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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