PCA9544A_07 [TI]
4-CHANNEL I2C AND SMBus MULTIPLEXER WITH INTERRUPT LOGIC; 与中断逻辑的4通道I2C和SMBus多路复用器
| 型号： | PCA9544A_07 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4-CHANNEL I2C AND SMBus MULTIPLEXER WITH INTERRUPT LOGIC |
| 文件： | 总27页 (文件大小：824K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCA9544A
4-CHANNEL I2C AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
www.ti.com
SCPS146C–OCTOBER 2005–REVISED OCTOBER 2006
FEATURES
•
•
•
•
•
1-of-4 Bidirectional Translating Switches
I2C Bus and SMBus Compatible
Four Active-Low Interrupt Inputs
Active-Low Interrupt Output
•
•
Low Standby Current
Operating Power-Supply Voltage Range of
2.3 V to 5.5 V
•
•
•
5.5-V Tolerant Inputs
0 to 400-kHz Clock Frequency
Three Address Pins, Allowing up to Eight
Devices on the I2C Bus
Channel Selection Via I2C Bus
Latch-Up Performance Exceeds 100 mA Per
JESD 78
•
•
•
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
Power Up With All Switch Channels
Deselected
•
•
Low RON Switches
Allows Voltage-Level Translation Between
1.8-V, 2.5-V, 3.3-V, and 5-V Buses
– 1000-V Charged-Device Model (C101)
•
•
No Glitch on Power Up
Supports Hot Insertion
DESCRIPTION/ORDERING INFORMATION
The PCA9544A is a quad bidirectional translating switch controlled via the I2C bus. The SCL/SDA upstream pair
fans out to four downstream pairs, or channels. One SCL/SDA pair can be selected at a time, and this is
determined by the contents of the programmable control register. Four interrupt inputs (INT3–INT0), one for
each of the downstream pairs, are provided. One interrupt output (INT) acts as an AND of the four interrupt
inputs.
A power-on reset function puts the registers in their default state and initializes the I2C state machine, with no
channel selected.
The pass gates of the switches are constructed such that the VCC pin can be used to limit the maximum high
voltage, which will be passed by the PCA9544A. This allows the use of different bus voltages on each pair, so
that 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts, without any additional protection. External
pullup resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5-V tolerant.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
PCA9544ARGWR
PCA9544ARGYR
PCA9544ADW
TOP-SIDE MARKING
PREVIEW
QFN – RGW
QFN – RGY
Reel of 3000
Reel of 1000
Tube of 25
PD544A
PCA9544A
PREVIEW
SOIC – DW
Reel of 2000
Reel of 250
Tube of 70
PCA9544ADWR
PCA9544ADWT
PCA9544APW
–40°C to 85°C
TSSOP – PW
TVSOP – DGV
Reel of 2000
Reel of 250
Reel of 2000
Reel of 250
Reel of 1000
Reel of 1000
PCA9544APWR
PCA9544APWT
PD544A
PCA9544ADGVR
PCA9544ADGVT
PCA9544AGQNR
PCA9544AZQNR
PD544A
PREVIEW
PD544A
PD544A
VFBGA – GQN
VFBGA – ZQN (Pb-free)
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
PCA9544A
4-CHANNEL I2C AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
www.ti.com
SCPS146C–OCTOBER 2005–REVISED OCTOBER 2006
DGV, DW, OR PW PACKAGE
(TOP VIEW)
RGW PACKAGE
(TOP VIEW)
RGY PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
A0
A1
VCC
1
20
20 19 18 17 16
SDA
SCL
INT
SC3
SD3
INT3
SC2
SD2
INT2
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
A1
A2
SDA
INT
A2
INT0
SD0
SC0
INT1
1
2
3
4
5
15
14
13
12
11
SCL
INT
A2
INT0
SD0
SC0
INT1
SD1
SC1
SC3
SD3
INT3
SC2
INT0
SD0
SC0
INT1
SD1
SC1
GND
SC3
SD3
INT3
SC2
SD2
10 11
6
7
8 9 10
TERMINAL FUNCTIONS
NO.
NAME
FUNCTION
DGV, DW, PW,
AND RGY
RGW
1
2
3
19
20
1
A0
A1
A2
Address input 0. Connect directly to VCC or ground.
Address input 1. Connect directly to VCC or ground.
Address input 2. Connect directly to VCC or ground.
Active-low interrupt input 0. Connect to VCC through a pullup
resistor.
4
2
INT0
5
6
3
4
SD0
SC0
Serial data 0. Connect to VCC through a pullup resistor.
Serial clock 0. Connect to VCC through a pullup resistor.
Active-low interrupt input 1. Connect to VCC through a pullup
resistor.
7
5
INT1
8
9
6
7
8
SD1
SC1
GND
Serial data 1. Connect to VCC through a pullup resistor.
Serial clock 1. Connect to VCC through a pullup resistor.
Ground
10
Active-low interrupt input 2. Connect to VCC through a pullup
resistor.
11
9
INT2
12
13
10
11
SD2
SC2
Serial data 2. Connect to VCC through a pullup resistor.
Serial clock 2. Connect to VCC through a pullup resistor.
Active-low interrupt input 3. Connect to VCC through a pullup
resistor.
14
12
INT3
15
16
13
14
SD3
SC3
Serial data 3. Connect to VCC through a pullup resistor.
Serial clock 3. Connect to VCC through a pullup resistor.
Active-low interrupt output. Connect to VCC through a pullup
resistor.
17
15
INT
18
19
20
16
17
18
SCL
SDA
VCC
Serial clock line. Connect to VCC through a pullup resistor.
Serial data line. Connect to VCC through a pullup resistor.
Supply power
2
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PCA9544A
4-CHANNEL I2C AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
www.ti.com
SCPS146C–OCTOBER 2005–REVISED OCTOBER 2006
GQN OR ZQN PACKAGE
(TOP VIEW)
TERMINAL ASSIGNMENTS
1
2
3
4
1
2
3
4
A
B
C
D
E
A1
A0
VCC
A2
SDA
SCL
SC3
INT3
SD2
INT0
SC0
SD1
GND
INT
SD0
SC2
SC1
A
B
C
D
E
SD3
INT1
INT2
3
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PCA9544A
4-CHANNEL I2C AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
www.ti.com
SCPS146C–OCTOBER 2005–REVISED OCTOBER 2006
BLOCK DIAGRAM
PCA9544A
6
SC0
SC1
SC2
9
13
16
SC3
SD0
SD1
SD2
SD3
5
8
12
15
Switch Control Logic
10
20
GND
Power-on Reset
V
CC
18
19
1
SCL
SDA
A0
2
3
A1
A2
Input Filter
2
I C Bus Control
4
7
11
14
INT0
INT1
INT2
INT3
17
Output
Filter
INT
Interrupt Logic
Pin numbers shown are for DGV, DW, PW, and RGY packages.
4
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PCA9544A
4-CHANNEL I2C AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
www.ti.com
SCPS146C–OCTOBER 2005–REVISED OCTOBER 2006
Device Address
Following a start condition, the bus master must output the address of the slave it is accessing. The address of
the PCA9544A is shown in Figure 1. To conserve power, no internal pullup resistors are incorporated on the
hardware-selectable address pins, and they must be pulled high or low.
Slave Address
0
1
1
1
A2 A1
R/W
A0
Hardware
Selectable
Fixed
Figure 1. PCA9544A Address
The last bit of the slave address defines the operation to be performed. When set to a logic 1, a read is selected,
while a logic 0 selects a write operation.
Control Register
Following the successful acknowledgment of the slave address, the bus master sends a byte to the PCA9544A,
which is stored in the control register. If multiple bytes are received by the PCA9544A, it saves the last byte
received. This register can be written and read via the I2C bus.
Channel-Selection Bits
(Read/Write)
Interrupt Bits
(Read Only)
7
6
4
3
2
1
0
5
INT3 INT2 INT1 INT0
X
B2
B1
B0
Enable Bit
INT0
INT1
INT2
INT3
Figure 2. Control Register
Control Register Definition
One or several SCn/SDn downstream pairs, or channels, are selected by the contents of the control register
(see Table 1). This register is written after the PCA9544A has been addressed. The three LSBs of the control
byte are used to determine which channel (or channels) is to be selected. When a channel is selected, the
channel becomes active after a stop condition has been placed on the I2C bus. This ensures that all SCn/SDn
lines are in a high state when the channel is made active, so that no false conditions are generated at the time
of connection. A stop condition always must occur right after the acknowledge cycle.
5
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PCA9544A
4-CHANNEL I2C AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
www.ti.com
SCPS146C–OCTOBER 2005–REVISED OCTOBER 2006
Table 1. Control Register Write (Channel Selection), Control Register Read (Channel Status)(1)
INT3
X
INT2
X
INT1
X
INT0
X
D3
X
B2
0
B1
X
0
B0
X
0
COMMAND
No channel selected
Channel 0 enabled
Channel 1 enabled
Channel 2 enabled
Channel 3 enabled
X
X
X
X
X
1
X
X
X
X
X
1
0
1
X
X
X
X
X
1
1
0
X
X
X
X
X
1
1
1
No channel selected,
power-up default state
0
0
0
0
0
0
0
0
(1) Only one channel may be selected at a time.
Interrupt Handling
The PCA9544A provides four interrupt inputs (one for each channel) and one open-drain interrupt output. When
an interrupt is generated by any device, it is detected by the PCA9544A, and the interrupt output is driven low.
The channel does not need to be active for detection of the interrupt. A bit also is set in the control register (see
Table 2).
Bits 4–7 of the control register correspond to channels 0–3 of the PCA9544A, respectively. Therefore, if an
interrupt is generated by any device connected to channel 1, the state of the interrupt inputs is loaded into the
control register when a read is accomplished. Likewise, an interrupt on any device connected to channel 0
causes bit 4 of the control register to be set on the read. The master then can address the PCA9544A and read
the contents of the control register to determine which channel contains the device generating the interrupt. The
master can reconfigure the PCA9544A to select this channel and locate the device generating the interrupt and
clear it. Once the device responsible for the interrupt clears, the interrupt clears.
It should be noted that more than one device can provide an interrupt on a channel, so it is up to the master to
ensure that all devices on a channel are interrogated for an interrupt.
The interrupt inputs can be used as general-purpose inputs if the interrupt function is not required.
If unused, interrupt input(s) must be connected to VCC
.
Table 2. Control Register Read (Interrupt)(1)
INT3
INT2
INT1
INT0
D3
B2
B1
B0
COMMAND
0
1
No interrupt on channel 0
Interrupt on channel 0
No interrupt on channel 1
Interrupt on channel 1
No interrupt on channel 2
Interrupt on channel 2
No interrupt on channel 3
Interrupt on channel 3
X
X
X
X
X
X
X
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
X
X
0
1
X
(1) Several interrupts can be active at the same time. For example, INT3 = 0, INT2 = 1, INT1 = 1, INT0 = 0 means that there is no interrupt
on channels 0 and 3, and there is interrupt on channels 1 and 2.
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PCA9544A
4-CHANNEL I2C AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
www.ti.com
SCPS146C–OCTOBER 2005–REVISED OCTOBER 2006
Power-On Reset
When power is applied to VCC, an internal power-on reset holds the PCA9544A in a reset condition until VCC has
reached VPOR. At this point, the reset condition is released, and the PCA9544A registers and I2C state machine
are initialized to their default states, all zeroes, causing all the channels to be deselected. Thereafter, VCC must
be lowered below 0.2 V to reset the device.
Voltage Translation
The pass-gate transistors of the PCA9544A are constructed such that the VCC voltage can be used to limit the
maximum voltage that is passed from one I2C bus to another.
Figure 3 shows the voltage characteristics of the pass-gate transistors (note that the graph was generated using
data specified in the electrical characteristics section of this data sheet). In order for the PCA9544A to act as a
voltage translator, the Vpass voltage must be equal to or lower than the lowest bus voltage. For example, if the
main bus is running at 5 V and the downstream buses are 3.3 V and 2.7 V, Vpass must be equal to or below 2.7
V to effectively clamp the downstream bus voltages. As shown in Figure 3, Vpass (max) is at 2.7 V when the
PCA9544A supply voltage is 3.5 V or lower, so the PCA9544A supply voltage could be set to 3.3 V. Pullup
resistors then can be used to bring the bus voltages to their appropriate levels (see Figure 12).
5
4.5
Maximum
4
Typical
3.5
3
2.5
2
Minimum
1.5
1
2
2.5
3
3.5
4
4.5
5
5.5
V
CC
(V)
Figure 3. Vpass Voltage vs VCC
I2C Interface
The I2C bus is for two-way two-line communication between different ICs or modules. The two lines are a serial
data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pullup
resistor when connected to the output stages of a device. Data transfer can be initiated only when the bus is not
busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high
period of the clock pulse, as changes in the data line at this time are interpreted as control signals (see
Figure 4).
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PCA9544A
4-CHANNEL I2C AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
www.ti.com
SCPS146C–OCTOBER 2005–REVISED OCTOBER 2006
SDA
SCL
Data Line
Stable;
Data Valid
Change
of Data
Allowed
Figure 4. Bit Transfer
Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while
the clock is high is defined as the start condition (S). A low-to-high transition of the data line while the clock is
high is defined as the stop condition (P) (see Figure 5).
SDA
S
P
SCL
Start Condition
Stop Condition
Figure 5. Definition of Start and Stop Conditions
A device generating a message is a transmitter; a device receiving a message is the receiver. The device that
controls the message is the master, and the devices that are controlled by the master are the slaves (see
Figure 6).
SDA
SCL
2
I C
Master
Transmitter/
Receiver
Master
Transmitter/
Receiver
Slave
Transmitter/
Receiver
Master
Transmitter
Slave
Receiver
Multiplexer
Slave
Figure 6. System Configuration
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is
not limited. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit.
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PCA9544A
4-CHANNEL I2C AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
www.ti.com
SCPS146C–OCTOBER 2005–REVISED OCTOBER 2006
When a slave receiver is addressed, it must generate an acknowledge (ACK) after the reception of each byte.
Also, a master must generate an ACK after the reception of each byte that has been clocked out of the slave
transmitter. The device that acknowledges must pull down the SDA line during the ACK clock pulse so that the
SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 7). Setup and hold
times must be taken into account.
Data Output
by Transmitter
NACK
Data Output
by Receiver
ACK
SCL From
1
2
8
9
Master
S
Start
Clock Pulse for ACK
Condition
Figure 7. Acknowledgment on the I2C Bus
A master receiver must signal an end of data to the transmitter by not generating an acknowledge (NACK) after
the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line
high. In this event, the transmitter must release the data line to enable the master to generate a stop condition.
Data is transmitted to the PCA9544A control register using the write mode shown in Figure 8.
Slave Address
Control Register
SDA
S
1
1
1
0
A1 A0
0
A
X
X
X
X
X
B2 B1 B0
A
A2
P
Start Condition
R/W ACK From Slave
ACK From Slave Stop Condition
Figure 8. Write Control Register
Data is read from the PCA9544A control register using the read mode shown in Figure 9.
Slave Address
Control Register
INT3 INT2 INT1 INT0
B2 B1 B0 NA
P
SDA
S
1
1
1
0
A1 A0
1
A
0
A2
Start Condition
R/W ACK From Slave
NACK From Master Stop Condition
Figure 9. Read Control Register
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PCA9544A
4-CHANNEL I2C AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
www.ti.com
SCPS146C–OCTOBER 2005–REVISED OCTOBER 2006
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
MAX UNIT
VCC
VI
Supply voltage range
Input voltage range(2)
Input current
7
7
V
V
II
±20
±25
±100
±100
92
mA
mA
mA
mA
IO
Output current
Continuous current through VCC
Continuous current through GND
DGV package(3)
DW package(3)
GQN package(3)
PW package(3)
RGW package(4)
RGY package(4)
58
78
θJA
Package thermal impedance
°C/W
83
TBD
37
Ptot
Tstg
TA
Total power dissipation
400
150
85
mW
°C
Storage temperature range
Operating free-air temperature range
–65
–40
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
(4) The package thermal impedance is calculated in accordance with JESD 51-5.
Recommended Operating Conditions(1)
MIN
2.3
MAX UNIT
VCC
VIH
Supply voltage
5.5
6
V
SCL, SDA
0.7 × VCC
0.7 × VCC
–0.5
High-level input voltage
V
A2–A0, INT3–INT0
SCL, SDA
VCC + 0.5
0.3 × VCC
0.3 × VCC
85
VIL
TA
Low-level input voltage
V
A2–A0, INT3–INT0
–0.5
Operating free-air temperature
–40
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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PCA9544A
4-CHANNEL I2C AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
www.ti.com
SCPS146C–OCTOBER 2005–REVISED OCTOBER 2006
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
Power-on reset voltage(2)
TEST CONDITIONS
VI = VCC or GND
VCC
VPOR
MIN TYP(1)
MAX UNIT
VPOR
No load,
1.7
2.1
4.5
2.8
V
5 V
3.6
4.5 V to 5.5 V
3.3 V
2.6
1.9
1.6
1.5
1.1
Vpass
Switch output voltage
VSWin = VCC
,
ISWout = –100 µA
V
3 V to 3.6 V
2.5 V
2.3 V to 2.7 V
2.3 V to 5.5 V
2
IOH
INT
VO = VCC
10
µA
VOL = 0.4 V
VOL = 0.6 V
VOL = 0.4 V
3
6
3
7
10
7
SCL, SDA
IOL
2.3 V to 5.5 V
mA
INT
SCL, SDA
SC3–SC0, SD3–SD0
A2–A0
±1
±1
±1
±1
12
11
10
1
II
VI = VCC or GND
2.3 V to 5.5 V
µA
INT3–INT0
5.5 V
3.6 V
2.7 V
5.5 V
3.6 V
2.7 V
5.5 V
3.6 V
2.7 V
3
3
Operating mode fSCL = 100 kHz
VI = VCC or GND, IO = 0
3
0.3
0.1
0.1
0.3
0.1
0.1
ICC
Low inputs
Standby mode
VI = GND,
IO = 0
IO = 0
1
µA
1
1
High inputs
VI = VCC
,
1
1
One INT3–INT0 input at 0.6 V,
Other inputs at VCC or GND
8
8
8
8
15
15
15
15
INT3–INT0
One INT3–INT0 input at VCC – 0.6 V,
Other inputs at VCC or GND
Supply-current
change
∆ICC
2.3 V to 5.5 V
µA
SCL or SDA input at 0.6 V,
Other inputs at VCC or GND
SCL, SDA
SCL or SDA inputs at VCC – 0.6 V,
Other inputs at VCC or GND
A2–A0
4.5
4.5
15
6
6
6
Ci
VI = VCC or GND
2.3 V to 5.5 V
2.3 V to 5.5 V
pF
pF
INT3–INT0
SCL, SDA
19
8
(3)
Cio(OFF)
VI = VCC or GND, Switch OFF
SC3–SC0, SD3–SD0
4.5 V to 5.5 V
3 V to 3.6 V
4
5
7
9
16
20
45
VO = 0.4 V,
VO = 0.4 V,
IO = 15 mA
IO = 10 mA
RON
Switch-on resistance
11
16
Ω
2.3 V to 2.7 V
(1) All typical values are at nominal supply voltage (2.5-V, 3.3-V, or 5-V VCC), TA = 25°C.
(2) The power-on reset circuit resets the I2C bus logic with VCC < VPOR. VCC must be lowered to 0.2 V to reset the device.
(3) Cio(ON) depends on internal capacitance and external capacitance added to the SCn lines when channels(s) are ON.
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PCA9544A
4-CHANNEL I2C AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
www.ti.com
SCPS146C–OCTOBER 2005–REVISED OCTOBER 2006
I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 12)
STANDARD-MODE
I2C BUS
FAST-MODE
I2C BUS
UNIT
MIN
0
MAX
MIN
0
MAX
fscl
I2C clock frequency
I2C clock high time
I2C clock low time
I2C spike time
I2C serial-data setup time
I2C serial-data hold time
I2C input rise time
100
400
kHz
µs
µs
ns
ns
µs
ns
ns
ns
µs
µs
µs
µs
µs
µs
tsch
tscl
4
0.6
1.3
4.7
tsp
50
50
tsds
tsdh
ticr
250
0(1)
100
0(1)
(2)
1000 20 + 0.1Cb
300 20 + 0.1Cb
300 20 + 0.1Cb
300
300
300
(2)
(2)
ticf
I2C input fall time
tocf
I2C output fall time (10-pF to 400-pF bus)
I2C bus free time between stop and start
I2C start or repeated start condition setup
I2C start or repeated start condition hold
I2C stop condition setup
tbuf
4.7
4.7
4
1.3
0.6
0.6
0.6
tsts
tsth
tsps
tvdL(Data)
tvdH(Data)
4
Valid-data time (high to low)(3)
Valid-data time (low to high)(3)
SCL low to SDA output low valid
1
1
SCL low to SDA output high valid
0.6
0.6
ACK signal from SCL low
to SDA output low
tvd(ack)
Cb
Valid-data time of ACK condition
I2C bus capacitive load
1
1
µs
400
400
pF
(1) A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to as the VIH min of the SCL signal), in order
to bridge the undefined region of the falling edge of SCL.
(2) Cb = total bus capacitance of one bus line in pF
(3) Data taken using a 1-kΩ pullup resistor and 50-pF load (see Figure 10).
Switching Characteristics
over recommended operating free-air temperature range, CL ≤ 100 pF (unless otherwise noted) (see Figure 10)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
MIN
MAX UNIT
RON = 20 Ω, CL = 15 pF
RON = 20 Ω, CL = 50 pF
0.3
µs
1
(1)
tpd
Propagation delay time
SDA or SCL
SDn or SCn
tiv
tir
Interrupt valid time(2)
Interrupt reset delay time(2)
INTn
INTn
INT
INT
4
2
µs
µs
(1) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
(2) Data taken using a 4.7-kΩ pullup resistor and 100-pF load (see Figure 11).
Interrupt Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
Low-level pulse duration rejection of INTn inputs(1)
High-level pulse duration rejection of INTn inputs(1)
MIN
1
MAX UNIT
tPWRL
tPWRH
µs
µs
0.5
(1) Data taken using a 4.7-kΩ pullup resistor and 100-pF load (see Figure 11).
12
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PCA9544A
4-CHANNEL I2C AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
www.ti.com
SCPS146C–OCTOBER 2005–REVISED OCTOBER 2006
PARAMETER MEASUREMENT INFORMATION
V
CC
R
L
= 1 kΩ
SDn, SCn
DUT
C
L
= 50 pF
(See Note A)
2
I C-PORT LOAD CONFIGURATION
Two Bytes for Complete
Device Programming
Stop
Start
Address
Bit 7
(MSB)
R/W
Bit 0
(LSB)
Data
Bit 7
(MSB)
Data
Bit 0
(LSB)
Stop
Condition
(P)
ACK
(A)
Address
Bit 6
Address
Bit 1
ACK
(A)
Condition Condition
(P) (S)
BYTE
DESCRIPTION
2
1
I C address + R/W
2
Control register data
t
scl
t
sch
0.7 × V
0.3 × V
CC
SCL
SDA
CC
t
vd(ACK)
t
icr
t
sts
or t
vdL
t
icf
t
buf
t
sp
t
vdH
0.7 × V
0.3 × V
CC
CC
t
icf
t
icr
t
sdh
t
sps
t
sth
t
Repeat
sds
Stop
Condition
Start
Condition
Start or Repeat
Start Condition
VOLTAGE WAVEFORMS
NOTES: A. C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t t ≤ 30 ns.
O
r/ f
C. The outputs are measured one at a time, with one transition per measurement.
Figure 10. I2C Interface Load Circuit, Byte Descriptions, and Voltage Waveforms
13
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PCA9544A
4-CHANNEL I2C AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
www.ti.com
SCPS146C–OCTOBER 2005–REVISED OCTOBER 2006
PARAMETER MEASUREMENT INFORMATION (continued)
V
CC
R
L
= 4.7 kΩ
INT
DUT
C
L
= 100 pF
(See Note A)
INTERRUPT LOAD CONFIGURATION
INTn
INTn
(input)
0.5 × V
(input)
0.5 × V
CC
CC
t
ir
t
iv
INT
(output)
INT
(output)
0.5 × V
CC
0.5 × V
CC
VOLTAGE WAVEFORMS (t )
VOLTAGE WAVEFORMS (t )
iv
ir
NOTES: A. C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t t ≤ 30 ns.
O
r/ f
Figure 11. Interrupt Load Circuit and Voltage Waveforms
14
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PCA9544A
4-CHANNEL I2C AND SMBus MULTIPLEXER
WITH INTERRUPT LOGIC
www.ti.com
SCPS146C–OCTOBER 2005–REVISED OCTOBER 2006
APPLICATION INFORMATION
V
CC
= 2.7 V to 5.5 V
V
CC
= 3.3 V
20
V
CC
= 2.7 V to 5.5 V
See Note A
Channel 0
5
19
18
17
SD0
SC0
SDA
SDA
2
I C/SMBus
Master
6
4
SCL
SCL
INT
INT0
V
CC
= 2.7 V to 5.5 V
See Note A
Channel 1
8
SD1
9
7
SC1
INT1
V
CC
= 2.7 V to 5.5 V
PCA9544A
See Note A
Channel 2
12
13
11
SD2
SC2
INT2
V
CC
= 2.7 V to 5.5 V
3
2
A2
See Note A
Channel 3
A1
15
16
14
1
SD3
SC3
INT3
A0
GND
10
NOTES: A. If the device generating the interrupt has an open-drain output structure or can be 3-stated, a pullup resistor is required.
If the device generating the interrupt has a totem-pole output structure and cannot be 3-stated, a pullup resistor is not required.
The interrupt inputs should not be left floating.
B. Pin numbers shown are for DGV, DW, PW, and RGY packages.
Figure 12. Typical Application
15
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
PCA9544ADGVR
ACTIVE
TVSOP
DGV
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9544ADGVT
PCA9544ADW
PREVIEW
ACTIVE
TVSOP
SOIC
DGV
DW
20
20
250
TBD
Call TI
Call TI
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9544ADWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9544ADWT
PREVIEW
NRND
SOIC
DW
20
20
250
TBD
TBD
Call TI
SNPB
Call TI
PCA9544AGQNR
BGA MI
CROSTA
R JUNI
OR
GQN
1000
Level-1-240C-UNLIM
PCA9544APW
PCA9544APWE4
PCA9544APWR
PCA9544APWRE4
PCA9544APWT
PCA9544APWTE4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
PW
PW
20
20
20
20
20
20
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PCA9544ARGWR
PCA9544ARGYR
PREVIEW
ACTIVE
QFN
QFN
RGW
RGY
20
20
3000
TBD
Call TI
Call TI
1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
PCA9544ARGYRG4
PCA9544AZQNR
ACTIVE
ACTIVE
QFN
RGY
ZQN
20
20
1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
BGA MI
CROSTA
R JUNI
OR
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2007
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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enhancements, improvements, and other changes to its products and services at any time and to
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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TI deems necessary to support this warranty. Except where mandated by government requirements, testing
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TI assumes no liability for applications assistance or customer product design. Customers are responsible
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