PCI2030PGF [TI]
32-Bit PCI-to-PCI Bridge 176-LQFP;
| 型号： | PCI2030PGF |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 32-Bit PCI-to-PCI Bridge 176-LQFP 时钟 PC 外围集成电路 |
| 文件： | 总14页 (文件大小：208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PCI2030
PCI-TO-PCI BRIDGE
XCPS012 – DECEMBER 1997
Supports PCI Local Bus Specification 2.1
and PCI-to-PCI Bridge Specification 1.0
Secondary Positive Decode
Predictable Latency: Compliant With PCI
Local Bus Specification 2.1
3.3-V Core Logic With Universal PCI
Interfaces Compatible With 3.3-V and 5-V
PCI Signaling Environments
External Arbiter Option
Provides Concurrent Operation
Serial IRQ Bridging
Supports Two 32-Bit, 33-MHz PCI Buses
Provides Internal Arbitration for Up to Six
Secondary Bus Masters With
Programmable Control
Propagates Bus Locking
Supports PCI Clock Run
Secondary Bus Driven Low During Reset
Docking Connect Detects
Provides Six Secondary PCI Bus Clock
Outputs
Supports Burst Transfers to Maximize Data
Throughput on Both PCI Buses
PCI Local Bus Specification 2.0-Compliant
Device Optimization
Provides Two Extension Windows
Advanced Submicron, Low-Power CMOS
Technology
EEPROM Interface for Loading Texas
Instruments (TI ) Subsystem ID and
Subsystem Vendor ID
Provides VGA/Palette Memory and I/O, and
Subtractive Decoding Options
Four Primary and Four Secondary
General-Purpose I/Os
Packaged in 176-Pin Plastic Quad Flatpack
Independent Read and Write Buffers for
Each Direction
Table of Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 PCI Clock/Reset Timing Requirements . . . . . . . . . . . . . . . . . . . . . . 10
Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 PCI Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . 11
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 PCI Bus Parameter Measurement Information . . . . . . . . . . . . . . . . 12
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . 9 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Recommended Operating Conditions for PCI Interface . . . . . . 9
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI is a trademark of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI2030
PCI-TO-PCI BRIDGE
XCPS012 – DECEMBER 1997
description
The TI PCI2030 PCI-to-PCI bridge provides a high-performance connection path between two peripheral
component interconnect (PCI) buses. Transactions can occur between a master on one PCI bus and a target
on another PCI bus. The bridge supports burst-mode transfers to maximize data throughput, and the two bus
traffic paths through the bridge act independently.
The PCI2030 bridge is compliant with the PCI Local Bus Specification 2.1, and can be used to overcome the
electrical loading limit of ten devices per PCI bus by creating hierarchical buses. Furthermore, add-in cards
requiring multiple PCI devices can use the bridge to overcome the electrical loading limit of one PCI device
per slot.
The PCI2030 bridge is also compliant with the PCI-to-PCI Bridge Specification 1.0, and implements many
additional features that make it an ideal solution for bridging two PCI buses. It can be configured for subtractive
decoding, and negative decoding can be disabled on the secondary interface. Two extension windows are also
included for special decoding purposes. The serial- and parallel-port addresses can also be programmed for
positive decoding on the primary interface. The bridge implements many other features, listed above, that add
performance and flexibility.
An advanced CMOS process is utilized to achieve low system-power consumption while operating at PCI clock
rates up to 33 MHz.
system block diagram
Primary PCI Bus
Video Controller
South Bridge
IDE Controller
PCI2030
PCI-To-PCI Bridge
Secondary PCI Bus
Add-In Card
Add-In Card
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI2030
PCI-TO-PCI BRIDGE
XCPS012 – DECEMBER 1997
terminal assignments
PGF PACKAGE
(TOP VIEW)
S_GPIO1
S_GPIO2
S_GPIO3
GND
S_PCLK0
S_PCLK1
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
S_AD16
S_C/BE2
GND
S_FRAME
V
CC
S_IRDY
V
S_TRDY
S_DEVSEL
S_STOP
CC
S_PCLK2
S_V
CCP
S_PCLK3
S_PCLK4
S_V
S_LOCK
GND
CCP
V
CC
S_PCLK5
GND
S_PERR
S_SERR
S_PAR
S_C/BE1
S_AD15
S_AD14
RST_MODE
P_CLKRUN
P_V
P_RST
GND
CCP
V
CC
P_CLK
S_AD13
S_AD12
S_AD11
V
CC
P_GNT
P_REQ
V
CC
P_V
P_AD31
S_AD10
S_AD9
GND
CCP
V
CC
P_AD30
P_AD29
S_AD8
S_C/BE0
S_AD7
V
CC
P_AD28
P_AD27
P_AD26
GND
S_V
S_AD6
S_AD5
CCP
V
CC
P_AD25
P_AD24
P_C/BE3
GND
P_IDSEL
P_AD23
S_AD4
S_AD3
GND
S_AD2
S_AD1
S_AD0
GND
P_GPIO0
P_GPIO1
P_GPIO2
P_GPIO3
V
CC
P_AD22
P_V
CCP
P_AD21
P_AD20
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI2030
PCI-TO-PCI BRIDGE
XCPS012 – DECEMBER 1997
Terminal Functions
primary PCI system
TERMINAL
I/O
TYPE
FUNCTION
NAME
NO.
Primary PCI bus clock. P_CLK provides timing for all transactions on the primary PCI bus. All primary PCI signals
are sampled at rising edge of P_CLK.
P_CLK
152
I
I
PCI reset. When the primary PCI bus reset is asserted, P_RST causes the bridge to 3-state all output buffers
and reset all internal registers. When asserted, the device is completely nonfunctional. During P_RST, the
secondary interface is driven low. After P_RST is deasserted, the bridge is in its default state.
150
R_RST
primary PCI address and data
TERMINAL
NAME
I/O
TYPE
FUNCTION
NO.
P_AD31
P_AD30
P_AD29
P_AD28
P_AD27
P_AD26
P_AD25
P_AD24
P_AD23
P_AD22
P_AD21
P_AD20
P_AD19
P_AD18
P_AD17
P_AD16
P_AD15
P_AD14
P_AD13
P_AD12
P_AD11
P_AD10
P_AD9
157
159
160
162
163
164
166
167
171
173
175
176
1
2
3
4
20
21
23
24
25
Primaryaddress/data bus. These signals make up the multiplexed PCI address and data bus on theprimary
interface. During the address phase of a primary bus PCI cycle, P_AD31–P_AD0 contain a 32-bit address
or other destination information. During the data phase, P_AD31–P_AD0 contain data.
I/O
27
29
P_AD8
31
P_AD7
34
P_AD6
35
P_AD5
37
P_AD4
38
P_AD3
39
P_AD2
41
P_AD1
43
P_AD0
44
Primarybuscommandsandbyteenables. ThesesignalsaremultiplexedonthesamePCIterminals. During
the address phase of a primary bus PCI cycle, P_C/BE3–P_C/BE0 define the bus command. During the
data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full
32-bit data bus carry meaningful data. P_C/BE0 applies to byte 0 (P_AD7–P_AD0), P_C/BE1 applies to
byte 1 (P_AD15–P_AD8), P_C/BE2 applies to byte 2 (P_AD23–P_AD16), and P_C/BE3 applies to byte 3
(P_AD31–P_AD24).
168
6
18
32
P_C/BE3
P_C/BE2
P_C/BE1
P_C/BE0
I/O
I/O
Primary PCI bus clock run. P_CLKRUN is used by the central resource to request permission to stop the
PCI clock or to slow it down.
P_CLKRUN
148
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI2030
PCI-TO-PCI BRIDGE
XCPS012 – DECEMBER 1997
Terminal Functions (Continued)
primary PCI interface control
TERMINAL
I/O
TYPE
FUNCTION
NAME
NO.
Primary device select. The bridge asserts P_DEVSEL to claim a PCI cycle as the target device. As a PCI
initiator on the primary bus, the bridge monitors P_DEVSEL until a target responds. If no target responds
before time-out occurs, then the bridge terminates the cycle with an initiator abort.
P_DEVSEL
P_FRAME
P_GNT
10
I/O
I/O
I
Primary cycle frame. P_FRAME is driven by the initiator of a primary bus cycle. P_FRAME is asserted to
indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When
P_FRAME is deasserted, the primary bus transaction is in the final data phase.
7
Primary bus grant to bridge. P_GNT is driven by the primary PCI bus arbiter to grant the bridge access to the
primary PCI bus after the current data transaction has completed. P_GNT may or may not follow a primary
bus request, depending on the primary bus parking algorithm.
154
P_GPIO3
P_GPIO2
P_GPIO1
P_GPIO0
45
46
47
48
Primary bus general-purpose I/O terminals. These terminals are provided for general input/output use in
system design.
I/O
I
Initialization device select. P_IDSEL selects the bridge during configuration space accesses. P_IDSEL can
be connected to one of the upper 24 PCI address lines on the primary PCI bus.
P_IDSEL
170
Note: There is no IDSEL signal interfacing the secondary PCI bus; thus, the entire configuration space of the
bridge can only be accessed from the primary bus.
Primary initiator ready. P_IRDY indicates the primary bus initiator’s ability to complete the current data phase
of the transaction. A data phase is completed on a rising edge of P_CLK where both P_IRDY and P_TRDY
are asserted. Until P_IRDY and P_TRDY are both sampled asserted, wait states are inserted.
P_IRDY
P_LOCK
8
I/O
I/O
13
Primary PCI bus lock. P_LOCK is used to lock the primary bus and gain exclusive access as an initiator.
Primary parity. In all primary bus read and write cycles, the bridge calculates even parity across the P_AD
and P_C/BE buses. As an initiator during PCI write cycles, the bridge outputs this parity indicator with a
one-P_CLKdelay. As a target during PCI read cycles, the calculated parity is compared to the initiator’s parity
indicator; a misdemeanor can result in a parity error assertion (P_PERR).
P_PAR
17
I/O
Primary parity error indicator. P_PERR is driven by a primary bus PCI device to indicate that calculated parity
does not match P_PAR when P_PERR is enabled through bit 6 of the command register.
15
I/O
O
P_PERR
P_REQ
Primary PCI bus request. P_REQ is asserted by the bridge to request access to the primary PCI bus as an
initiator.
155
Primary system error. Output pulsed from the bridge when enabled through the command register indicating
a system error has occurred. The bridge need not be the target of the primary PCI cycle to assert P_SERR.
When bit 6 is enabled in the bridge control register, P_SERR will also pulse, indicating that a system error
has occurred on one of the subordinate buses downstream from the bridge.
P_SERR
P_STOP
16
O
Primary cycle stop signal. P_STOP is driven by a PCI target to request the initiator to stop the current primary
bus transaction. P_STOP is used for target disconnects and is commonly asserted by target devices that do
not support burst data transfers.
11
147
9
I/O
I
If RST_MODE is asserted during P_RST, it causes S_RST to be asserted and the secondary clocks to be
turned off.
RST_MODE
P_TRDY
Primary target ready. P_TRDY indicates the primary bus target’s ability to complete the current data phase
of the transaction. A data phase is completed on a rising edge of P_CLK where both P_IRDY and P_TRDY
are asserted. Until both P_IRDY and P_TRDY are asserted, wait states are inserted.
I/O
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI2030
PCI-TO-PCI BRIDGE
XCPS012 – DECEMBER 1997
Terminal Functions (Continued)
secondary PCI system
TERMINAL
I/O
TYPE
FUNCTION
NAME
NO.
145
143
142
140
138
137
S_PCLK5
S_PCLK4
S_PCLK3
S_PCLK2
S_PCLK1
S_PCLK0
Secondary PCI bus clock. Provides timing for all transactions on the secondary PCI bus. All secondary PCI
signals are sampled at the rising edge of S_CLK5–S_CLK0.
O
Secondary PCI bus clock run. S_CLKRUN is output by the bridge to indicate that S_CLK will be stopped.
S_CLKRUN is driven by secondary bus PCI devices to request that S_CLK be stopped.
127
129
I/O
I
S_CLKRUN
S_EXTARB
Secondary external arbiter enable. When S_EXTARB is asserted, the secondary external arbiter is enabled.
When the external arbiter is enabled, S_REQ0 is reconfigured as a secondary bus grant input to the bridge
and S_GNT0 is reconfigured as a secondary bus master request to the external arbiter on the secondary bus.
Secondary PCI reset. S_RST is a logical OR of P_RST and the state of the secondary bus reset bit of the
bridge control register. S_RST is asynchronous with respect to the state of the secondary interface CLK
signal.
S_RST
126
O
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI2030
PCI-TO-PCI BRIDGE
XCPS012 – DECEMBER 1997
Terminal Functions (Continued)
secondary PCI address and data
TERMINAL
I/O
TYPE
FUNCTION
NAME
NO.
110
109
108
106
105
104
102
101
97
96
95
94
92
91
90
88
72
71
69
68
67
S_AD31
S_AD30
S_AD29
S_AD28
S_AD27
S_AD26
S_AD25
S_AD24
S_AD23
S_AD22
S_AD21
S_AD20
S_AD19
S_AD18
S_AD17
S_AD16
S_AD15
S_AD14
S_AD13
S_AD12
S_AD11
S_AD10
S_AD9
Secondary address/data bus. These signals make up the multiplexed PCI address and data bus on the
secondary interface. During the address phase of a secondary bus PCI cycle, S_AD31–S_AD0 contain a
32-bit address or other destination information. During the data phase, S_AD31–S_AD0 contain data.
I/O
65
64
62
S_AD8
60
S_AD7
58
S_AD6
57
S_AD5
55
S_AD4
54
S_AD3
52
S_AD2
51
S_AD1
50
S_AD0
Secondary bus commands and byte enables. These signals are multiplexed on the same PCI terminals.
During the address phase of a secondary bus PCI cycle, S_C/BE3–S_C/BE0 define the bus command.
During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths
of the full 32-bit data bus carry meaningful data. S_C/BE0 applies to byte 0 (S_AD7–S_AD0), S_C/BE1
applies to byte 1 (S_AD15–S_AD8), S_C/BE2 applies to byte 2 (S_AD23–S_AD16), and S_C/BE3 applies
to byte 3 (S_AD31–S_AD24).
S_C/BE3
S_C/BE2
S_C/BE1
S_C/BE0
99
87
73
61
I/O
Secondary device select. The bridge asserts S_DEVSEL to claim a PCI cycle as the target device. As a PCI
initiator on the secondary bus, the bridge monitors S_DEVSEL until a target responds. If no target responds
before timeout occurs, then the bridge terminates the cycle with an initiator abort.
S_DEVSEL
S_FRAME
81
85
I/O
I/O
Secondary cycle frame. S_FRAME is driven by the initiator of a secondary bus cycle. S_FRAME is asserted
to indicate that a bus transaction is beginning and data transfers continue while S_FRAME is asserted. When
S_FRAME is deasserted, the secondary bus transaction is in the final data phase.
S_GNT5
S_GNT4
S_GNT3
S_GNT2
S_GNT1
S_GNT0
125
124
123
122
120
119
Secondarybus grant to thebridge. Thebridgeprovidesinternalarbitrationandthesesignalsareusedtogrant
potential secondary PCI bus masters access to the bus. Seven potential initiators (including the bridge) can
be located on the secondary PCI bus.
O
When the internal arbiter is disabled, S_GNT0 is reconfigured as an external secondary bus request signal
for the bridge.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI2030
PCI-TO-PCI BRIDGE
XCPS012 – DECEMBER 1997
Terminal Functions (Continued)
secondary PCI interface control
TERMINAL
NAME
I/O
TYPE
FUNCTION
NO.
135
134
133
132
S_GPIO3
S_GPIO2
S_GPIO1
S_GPIO0
Secondary general-purpose I/O terminals. These terminals are provided for general-purpose input/output
use in system design.
I/O
Secondaryinitiatorready. S_IRDYindicatesthesecondarybusinitiator’sabilitytocompletethecurrentdata
phase of the transaction. A data phase is completed on a rising edge of S_CLK where both S_IRDY and
S_TRDY are asserted; until S_IRDY and S_TRDY are asserted, wait states are inserted.
S_IRDY
S_LOCK
83
78
I/O
I/O
Secondary lock S_LOCK is used to lock the secondary bus and gain exclusive access as an initiator.
Secondary parity. In all secondary bus read and write cycles, the bridge calculates even parity across the
S_AD and S_C/BE buses. As an initiator during PCI write cycles, the bridge outputs this parity indicator with
a one-S_CLK delay. As a target during PCI read cycles, the calculated parity is compared to the initiator’s
parity indicator. A miscompare can result in a parity error assertion (S_PERR).
S_PAR
74
I/O
I/O
Secondary parity error indicator. S_PERR is driven by a secondary bus PCI device to indicate that
calculated parity does not match S_PAR when enabled through the command register.
76
S_PERR
S_REQ5
S_REQ4
S_REQ3
S_REQ2
S_REQ1
S_REQ0
118
116
115
113
112
111
Secondary PCI bus request signals. The bridge provides internal arbitration, and these signals are used as
inputs from secondary PCI bus initiators requesting the bus. Seven potential initiators (including the bridge)
can be located on the secondary PCI bus.
I
When the internal arbiter is disabled, S_REQ0 is reconfigured as an external secondary bus grant for the
bridge.
Secondary system error. S_SERR is passed through the primary interface by the bridge if enabled through
the bridge control register. S_SERR is never asserted by the bridge.
75
80
I
S_SERR
S_STOP
Secondary cycle stop signal. S_STOP is driven by a PCI target to request the initiator to stop the current
secondary bus transaction. S_STOP is used for target disconnects and is commonly asserted by target
devices that do not support burst data transfers.
I/O
Secondary target ready. S_TRDY indicates the secondary bus target’s ability to complete the current data
phase of the transaction. A data phase is completed on a rising edge of S_CLK where both S_IRDY and
S_TRDY are asserted; until S_IRDY and S_TRDY are asserted, wait states are inserted.
S_TRDY
82
I/O
Flush request. When S_FLSHREQ is asserted, it signals a request to the PCI2030 to suspend internal write
posting. When the bridge is ready to suspend internal write posting, it responds by asserting S_FLSHACK.
S_FLSHACK remains asserted until the write posting buffers are empty.
S_FLSHREQ
S_FLSHACK
131
130
I
Flush acknowledge. S_FLSHACK is asserted by the PCI2030 to indicate that the internal write posting is
suspended. S_FLSHACK remains asserted until the write posting buffers are empty.
O
power supply
TERMINAL
FUNCTION
NAME
NO.
5, 19, 22. 30, 33, 49, 53, 63, 77, 86, 93, 103,
107, 121, 136, 146, 151, 161, 165, 169
GND
Device ground terminals
12, 26, 36, 40, 56, 66, 70, 84, 89, 100, 114,
128, 139, 144, 153, 158, 172
V
CC
Power-supply terminal for core logic (3.3 V)
Primarybus-signalingenvironmentsupply. P_V
on primary bus I/O signals.
isusedinprotectioncircuitry
CCP
P_V
14, 28, 42, 149, 156, 174
59, 79, 98, 117, 141
CCP
CCP
Secondary bus-signaling environment supply. S_V
circuitry on primary bus I/O signals.
is used in protection
CCP
S_V
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI2030
PCI-TO-PCI BRIDGE
XCPS012 – DECEMBER 1997
†
absolute maximum ratings over operating temperature ranges (unless otherwise noted)
Supply voltage range: V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
CC
CCP
Input voltage range, V : Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V : Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
Storage temperature range, T
(V < 0 or V > V ) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Virtual junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
J
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Applies to external input and bidirectional buffers. V > V
does not apply to fail-safe terminals.
CC
CC
I
2. Applies to external output and bidirectional buffers. V > V
O
does not apply to fail-safe terminals.
recommended operating conditions
MIN NOM
MAX
4
UNIT
ns
t
Input transition (rise and fall) time
Operating ambient temperature range
Virtual junction temperature
CMOS compatible
Commercial
1
0
0
t
T
25
25
70
°C
A
‡
T
Commercial
115
°C
J
‡
These junction temperatures reflect simulation conditions. The customer is responsible for verifying junction temperature.
recommended operating conditions for PCI interface
OPERATION
3.3 V
3.3 V
5 V
MIN NOM
MAX
3.6
UNIT
V
V
Core voltage
Commercial
Commercial
3
3.3
3.3
5
V
CC
3
4.75
0
3.6
PCI supply voltage
V
V
V
V
V
CCP
5.25
3.3 V
5 V
V
CCP
CCP
CCP
CCP
V
I
Input voltage
0
V
V
V
3.3 V
5 V
0
§
Output voltage
V
V
V
O
0
3.3 V
5 V
0.5 V
CCP
2
¶
CMOS compatible
CMOS compatible
High-level input voltage
Low-level input voltage
IH
3.3 V
5 V
0.3 V
CCP
0.8
¶
IL
§
¶
Applies to external output buffers
Applies to external input and bidirectional buffers without hysteresis
9
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XCPS012 – DECEMBER 1997
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
SIDE
TEST CONDITIONS
OPERATION
3.3 V
MIN
MAX
UNIT
I
I
I
I
= –0.5 mA
0.9 V
OH
CC
2.4
V
V
V
High-level output voltage
OH
= –2 mA
= 1.5 mA
= 6 mA
5 V
OH
OL
OL
0.1 V
3.3 V
CC
V
Low-level output voltage
High-level input current
OL
0.55
5 V
3.6 V
10
20
†
Input pins
V = V
I
CC
5.25 V
I
IH
µA
3.6 V
20
‡
†
I/O pins
V = V
I
CC
5.25 V
25
Input pins
V = GND
I
3.6 V to 5.25 V
3.6 V to 5.25 V
–1
I
I
Low-level input current
µA
µA
IL
‡
V = GND
I
–20
±20
I/O pins
High-impedance output current
V
O
= V
or GND
CCP
OZ
†
‡
For PCI pins, V
CC
= V
.
CCP
For I/O pins, the input leakage current includes the off-state output current I
.
OZ
PCI clock/reset timing requirements over recommended ranges of supply voltage and operating
free-air temperature (see Figure 1, Figure 2, and Figure 3)
ALTERNATE
SYMBOL
MIN
MAX
UNIT
t
t
t
Cycle time, PCLK
t
30
11
11
1
∞
ns
ns
c
cyc
Pulse duration, PCLK high
Pulse duration, PCLK low
Slew rate, PCLK
t
high
wH
wL
t
ns
low
t , t
∆v/∆t
4
V/ns
ms
s
r f
t
t
Pulse duration, RSTIN
t
1
w
rst
Setup time, PCLK active at end of RSTIN (see Note 3)
t
100
su
rst-clk
NOTE 3: The setup and hold times for the secondary are identical to those for the primary; however, the times are relative to the secondary PCI
close.
PCI timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Note 4 and Figure 1 and Figure 4)
ALTERNATE
SYMBOL
TEST CONDITIONS
MIN
MAX
UNIT
PCLK to shared signal
valid delay time
t
11
val
inv
t
Propagation delay time
Enable time,
C
= 50 pF, See Note 5
L
ns
pd
PCLK to shared signal
invalid delay time
t
2
2
t
t
t
ns
ns
en
on
off
high-impedance-to-active delay time from PCLK
Disable time,
t
28
dis
active-to-high-impedance delay time from PCLK
t
t
Setup time before PCLK valid
Hold time after PCLK high
t
, See Note 6
7
0
ns
ns
su
su
t , See Note 6
h
h
NOTES: 4. This data sheet uses the following conventions to describe time (t) intervals. The format is: t , where subscript A indicates the type
A
ofdynamicparameterbeingrepresented. Oneofthefollowingisused:t =propagationdelaytime, t = delay time, t = setup time,
pd su
d
and t = hold time.
h
5. PCI shared signals are AD31–AD0, C/BE3–C/BE0, FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL, and PAR.
6. The setup and hold times for the secondary are identical to those for the primary; however, the times are relative to the secondary
PCI close.
10
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PARAMETER MEASUREMENT INFORMATION
LOAD CIRCUIT PARAMETERS
I
†
OL
TIMING
PARAMETER
C
I
I
V
LOAD
(pF)
OL
OH
LOAD
(V)
(mA)
(mA)
t
0
3
PZH
Test
Point
t
50
8
–8
en
t
t
t
PZL
PHZ
PLZ
From Output
Under Test
V
LOAD
t
t
50
50
8
8
–8
–8
1.5
‡
dis
pd
C
LOAD
†
‡
C
V
includes the typical load-circuit distributed capacitance.
LOAD
LOAD
I
OH
– V
OL
= 50 Ω, where V
= 0.6 V, I
= 8 mA
OL
OL
I
OL
LOAD CIRCUIT
V
Timing
Input
(see Note A)
CC
V
CC
50% V
High-Level
Input
CC
50% V
50% V
CC
CC
0 V
0 V
t
t
h
su
t
w
Data
Input
V
CC
90% V
CC
V
CC
50% V
50% V
10% V
CC
CC
CC
t
Low-Level
Input
0 V
50% V
50% V
CC
CC
0 V
t
f
r
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
INPUT RISE AND FALL TIMES
V
CC
Output
Control
(low-level
enabling)
50% V
50% V
CC
CC
V
0 V
CC
Input
(see Note A)
t
50% V
50% V
CC
PZL
CC
t
PLZ
0 V
t
pd
V
t
CC
pd
≈ 50% V
V
Waveform 1
(see Note B)
CC
CC
OH
50% V
CC
In-Phase
Output
V
+ 0.3 V
OL
50% V
50% V
CC
CC
V
OL
V
OL
t
PHZ
t
pd
t
PZH
t
pd
V
OH
V
OH
V
– 0.3 V
OH
Out-of-Phase
Output
Waveform 2
(see Note B)
50% V
CC
50% V
50% V
CC
CC
≈ 50% V
0 V
V
OL
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by pulse generators having the
following characteristics: PRR = 1 MHz, Z = 50 Ω, t ≤ 6 ns, t ≤ 6 ns.
O
r
f
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. For t
and t
, V
PHZ OL
and V
are measured values.
OH
PLZ
Figure 1. Load Circuit and Voltage Waveforms
11
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PCI2030
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XCPS012 – DECEMBER 1997
PCI BUS PARAMETER MEASUREMENT INFORMATION
t
wH
t
wL
2 V
2 V MIN Peak to Peak
0.8 V
t
t
f
r
t
c
Figure 2. PCLK Timing Waveform
PCLK
t
w
RSTIN
t
su
Figure 3. RSTIN Timing Waveforms
PCLK
1.5 V
t
t
pd
1.5 V
pd
t
Valid
PCI Output
PCI Input
t
on
off
Valid
t
su
t
h
Figure 4. Shared-Signals Timing Waveforms
12
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PCI2030
PCI-TO-PCI BRIDGE
XCPS012 – DECEMBER 1997
MECHANICAL DATA
PGF (S-PQFP-G176)
PLASTIC QUAD FLATPACK
132
89
133
88
0,27
0,17
M
0,08
0,50
0,13 NOM
176
45
1
44
Gage Plane
21,50 SQ
24,20
SQ
23,80
26,20
25,80
0,25
0,05 MIN
0°–7°
SQ
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040134/B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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